303 lines
6.6 KiB
C
303 lines
6.6 KiB
C
/*
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* Copyright (c) 2020-2021, Bluetrum Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-01-22 greedyhao first version
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*/
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#include "board.h"
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#ifdef BSP_USING_TIM
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#include "tim_config.h"
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//#define DRV_DEBUG
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#define LOG_TAG "drv.hwtimer"
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#include <drv_log.h>
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#ifdef RT_USING_HWTIMER
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enum
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{
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#ifdef BSP_USING_TIM1
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TIM1_INDEX,
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#endif
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#ifdef BSP_USING_TIM2
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TIM2_INDEX,
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#endif
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#ifdef BSP_USING_TIM3
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TIM3_INDEX,
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#endif
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#ifdef BSP_USING_TIM4
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TIM4_INDEX,
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#endif
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#ifdef BSP_USING_TIM5
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TIM5_INDEX,
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#endif
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};
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struct ab32_hwtimer
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{
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rt_hwtimer_t time_device;
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hal_sfr_t tim_handle;
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char *name;
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irq_type tim_irqn;
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};
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static struct ab32_hwtimer ab32_hwtimer_obj[] =
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{
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#ifdef BSP_USING_TIM1
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TIM1_CONFIG,
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#endif
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#ifdef BSP_USING_TIM2
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TIM2_CONFIG,
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#endif
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#ifdef BSP_USING_TIM3
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TIM3_CONFIG,
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#endif
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#ifdef BSP_USING_TIM4
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TIM4_CONFIG,
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#endif
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#ifdef BSP_USING_TIM5
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TIM5_CONFIG,
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#endif
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};
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RT_SECTION(".irq.timer")
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static void _rt_device_hwtimer_isr(rt_hwtimer_t *timer)
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{
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RT_ASSERT(timer != RT_NULL);
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timer->overflow ++;
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if (timer->cycles != 0)
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{
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timer->cycles --;
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}
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if (timer->cycles == 0)
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{
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timer->cycles = timer->reload;
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if (timer->mode == HWTIMER_MODE_ONESHOT)
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{
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if (timer->ops->stop != RT_NULL)
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{
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timer->ops->stop(timer);
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}
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}
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if (timer->parent.rx_indicate != RT_NULL)
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{
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timer->parent.rx_indicate(&timer->parent, sizeof(struct rt_hwtimerval));
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}
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}
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}
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static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
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{
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uint32_t prescaler_value = 0;
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hal_sfr_t tim = RT_NULL;
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struct ab32_hwtimer *tim_device = RT_NULL;
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RT_ASSERT(timer != RT_NULL);
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tim = (hal_sfr_t)timer->parent.user_data;
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if (state)
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{
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tim_device = (struct ab32_hwtimer *)timer;
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if (timer->info->cntmode != HWTIMER_CNTMODE_UP)
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{
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LOG_E("Only support HWTIMER_CNTMODE_UP!");
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}
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/* set tim int */
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tim[TMRxCON] = BIT(7);
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LOG_D("%s init success", tim_device->name);
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} else {
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/* stop timer */
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tim[TMRxCON] = 0;
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}
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}
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static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode)
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{
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rt_err_t result = RT_EOK;
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hal_sfr_t tim = RT_NULL;
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RT_ASSERT(timer != RT_NULL);
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tim = (hal_sfr_t)timer->parent.user_data;
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/* set tim cnt */
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tim[TMRxCNT] = 0;
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tim[TMRxPR] = t * (get_sysclk_nhz() / timer->freq) - 1;
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if (opmode != HWTIMER_MODE_PERIOD)
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{
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LOG_E("Opmode only support HWTIMER_MODE_PERIOD!");
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return -RT_EINVAL;
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}
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/* start timer */
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tim[TMRxCON] |= BIT(0);
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return result;
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}
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static void timer_stop(rt_hwtimer_t *timer)
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{
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hal_sfr_t tim = RT_NULL;
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RT_ASSERT(timer != RT_NULL);
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tim = (hal_sfr_t)timer->parent.user_data;
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/* stop timer */
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tim[TMRxCON] &= ~BIT(0);
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/* set tim cnt */
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tim[TMRxCNT] = 0;
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}
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static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
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{
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hal_sfr_t tim = RT_NULL;
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rt_err_t result = RT_EOK;
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RT_ASSERT(timer != RT_NULL);
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RT_ASSERT(arg != RT_NULL);
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tim = (hal_sfr_t)timer->parent.user_data;
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switch (cmd)
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{
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case HWTIMER_CTRL_FREQ_SET:
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{
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}
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break;
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default:
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{
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result = -RT_ENOSYS;
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}
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break;
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}
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return result;
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}
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static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer)
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{
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hal_sfr_t tim = RT_NULL;
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RT_ASSERT(timer != RT_NULL);
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tim = (hal_sfr_t)timer->parent.user_data;
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return tim[TMRxCNT] / (get_sysclk_nhz() / timer->freq);
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}
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static const struct rt_hwtimer_info _info = TIM_DEV_INFO_CONFIG;
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static const struct rt_hwtimer_ops _ops =
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{
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.init = timer_init,
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.start = timer_start,
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.stop = timer_stop,
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.count_get = timer_counter_get,
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.control = timer_ctrl,
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};
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#if defined(BSP_USING_TIM2) || defined(BSP_USING_TIM4) || defined(BSP_USING_TIM5)
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RT_SECTION(".irq.timer")
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void timer2_4_5_isr(int vector, void *param)
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{
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rt_interrupt_enter();
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#ifdef BSP_USING_TIM2
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if (ab32_hwtimer_obj[TIM2_INDEX].tim_handle[TMRxCON] != 0) {
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ab32_hwtimer_obj[TIM2_INDEX].tim_handle[TMRxCPND] = BIT(9);
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_rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM2_INDEX].time_device);
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}
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#endif
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#ifdef BSP_USING_TIM4
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if (ab32_hwtimer_obj[TIM4_INDEX].tim_handle[TMRxCON] != 0) {
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ab32_hwtimer_obj[TIM4_INDEX].tim_handle[TMRxCPND] = BIT(9);
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_rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM4_INDEX].time_device);
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}
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#endif
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#ifdef BSP_USING_TIM5
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if (ab32_hwtimer_obj[TIM5_INDEX].tim_handle[TMRxCON] != 0) {
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ab32_hwtimer_obj[TIM5_INDEX].tim_handle[TMRxCPND] = BIT(9);
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_rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM5_INDEX].time_device);
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}
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#endif
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rt_interrupt_leave();
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}
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#endif
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#ifdef BSP_USING_TIM3
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RT_SECTION(".irq.timer")
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void timer3_isr(int vector, void *param)
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{
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rt_interrupt_enter();
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ab32_hwtimer_obj[TIM3_INDEX].tim_handle[TMRxCPND] = BIT(9);
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_rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM3_INDEX].time_device);
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rt_interrupt_leave();
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}
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#endif
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#ifdef BSP_USING_TIM1
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RT_SECTION(".irq.timer")
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void timer1_isr(int vector, void *param)
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{
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rt_interrupt_enter();
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ab32_hwtimer_obj[TIM1_INDEX].tim_handle[TMRxCPND] = BIT(9);
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_rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM1_INDEX].time_device);
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rt_interrupt_leave();
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}
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#endif
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static int ab32_hwtimer_init(void)
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{
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int i = 0;
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int result = RT_EOK;
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for (i = 0; i < sizeof(ab32_hwtimer_obj) / sizeof(ab32_hwtimer_obj[0]); i++)
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{
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ab32_hwtimer_obj[i].time_device.info = &_info;
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ab32_hwtimer_obj[i].time_device.ops = &_ops;
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if (rt_device_hwtimer_register(&ab32_hwtimer_obj[i].time_device, ab32_hwtimer_obj[i].name, (void *)ab32_hwtimer_obj[i].tim_handle) == RT_EOK)
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{
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LOG_D("%s register success", ab32_hwtimer_obj[i].name);
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}
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else
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{
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LOG_E("%s register failed", ab32_hwtimer_obj[i].name);
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result = -RT_ERROR;
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}
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}
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#ifdef BSP_USING_TIM1
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rt_hw_interrupt_install(IRQ_TMR1_VECTOR, timer1_isr, RT_NULL, "t1_isr");
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#endif
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#if defined(BSP_USING_TIM2) || defined(BSP_USING_TIM4) || defined(BSP_USING_TIM5)
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rt_hw_interrupt_install(IRQ_TMR2_4_5_VECTOR, timer2_4_5_isr, RT_NULL, "t245_isr");
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#endif
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#ifdef BSP_USING_TIM3
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rt_hw_interrupt_install(IRQ_IRRX_VECTOR, timer3_isr, RT_NULL, "t3_isr");
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#endif
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return result;
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}
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INIT_BOARD_EXPORT(ab32_hwtimer_init);
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#endif /* RT_USING_HWTIMER */
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#endif /* BSP_USING_TIM */
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