699 lines
18 KiB
C
699 lines
18 KiB
C
/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2012-01-10 bernard porting to AM1808
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*/
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#include <board.h>
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#include <rthw.h>
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#include <rtthread.h>
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#include <stddef.h>
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#include <stdint.h>
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#include <string.h>
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#include "mm_aspace.h"
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#include "mm_page.h"
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#include "mmu.h"
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#include "tlb.h"
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#ifdef RT_USING_SMART
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#include "ioremap.h"
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#include <lwp_mm.h>
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#endif
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#define DBG_TAG "hw.mmu"
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#define DBG_LVL DBG_LOG
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#include <rtdbg.h>
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#define MMU_LEVEL_MASK 0x1ffUL
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#define MMU_LEVEL_SHIFT 9
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#define MMU_ADDRESS_BITS 39
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#define MMU_ADDRESS_MASK 0x0000fffffffff000UL
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#define MMU_ATTRIB_MASK 0xfff0000000000ffcUL
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#define MMU_TYPE_MASK 3UL
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#define MMU_TYPE_USED 1UL
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#define MMU_TYPE_BLOCK 1UL
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#define MMU_TYPE_TABLE 3UL
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#define MMU_TYPE_PAGE 3UL
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#define MMU_TBL_BLOCK_2M_LEVEL 2
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#define MMU_TBL_PAGE_4k_LEVEL 3
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#define MMU_TBL_LEVEL_NR 4
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volatile unsigned long MMUTable[512] __attribute__((aligned(4 * 1024)));
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struct mmu_level_info
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{
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unsigned long *pos;
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void *page;
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};
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static void _kenrel_unmap_4K(unsigned long *lv0_tbl, void *v_addr)
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{
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int level;
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unsigned long va = (unsigned long)v_addr;
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unsigned long *cur_lv_tbl = lv0_tbl;
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unsigned long page;
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unsigned long off;
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struct mmu_level_info level_info[4];
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int ref;
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int level_shift = MMU_ADDRESS_BITS;
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unsigned long *pos;
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rt_memset(level_info, 0, sizeof level_info);
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for (level = 0; level < MMU_TBL_LEVEL_NR; level++)
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{
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off = (va >> level_shift);
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off &= MMU_LEVEL_MASK;
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page = cur_lv_tbl[off];
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if (!(page & MMU_TYPE_USED))
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{
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break;
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}
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if ((page & MMU_TYPE_MASK) == MMU_TYPE_BLOCK)
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{
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break;
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}
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level_info[level].pos = cur_lv_tbl + off;
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cur_lv_tbl = (unsigned long *)(page & MMU_ADDRESS_MASK);
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cur_lv_tbl = (unsigned long *)((unsigned long)cur_lv_tbl - PV_OFFSET);
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level_info[level].page = cur_lv_tbl;
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level_shift -= MMU_LEVEL_SHIFT;
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}
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level = MMU_TBL_PAGE_4k_LEVEL;
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pos = level_info[level].pos;
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if (pos)
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{
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*pos = (unsigned long)RT_NULL;
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rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, pos, sizeof(void *));
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}
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level--;
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while (level >= 0)
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{
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pos = level_info[level].pos;
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if (pos)
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{
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void *cur_page = level_info[level].page;
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ref = rt_page_ref_get(cur_page, 0);
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if (ref == 1)
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{
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*pos = (unsigned long)RT_NULL;
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rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, pos, sizeof(void *));
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}
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rt_pages_free(cur_page, 0);
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}
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level--;
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}
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return;
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}
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static int _kenrel_map_4K(unsigned long *lv0_tbl, void *vaddr, void *paddr,
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unsigned long attr)
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{
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int ret = 0;
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int level;
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unsigned long *cur_lv_tbl = lv0_tbl;
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unsigned long page;
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unsigned long off;
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intptr_t va = (intptr_t)vaddr;
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intptr_t pa = (intptr_t)paddr;
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int level_shift = MMU_ADDRESS_BITS;
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if (va & ARCH_PAGE_MASK)
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{
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return MMU_MAP_ERROR_VANOTALIGN;
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}
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if (pa & ARCH_PAGE_MASK)
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{
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return MMU_MAP_ERROR_PANOTALIGN;
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}
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for (level = 0; level < MMU_TBL_PAGE_4k_LEVEL; level++)
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{
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off = (va >> level_shift);
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off &= MMU_LEVEL_MASK;
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if (!(cur_lv_tbl[off] & MMU_TYPE_USED))
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{
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page = (unsigned long)rt_pages_alloc(0);
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if (!page)
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{
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ret = MMU_MAP_ERROR_NOPAGE;
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goto err;
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}
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rt_memset((void *)page, 0, ARCH_PAGE_SIZE);
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rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, (void *)page, ARCH_PAGE_SIZE);
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cur_lv_tbl[off] = (page + PV_OFFSET) | MMU_TYPE_TABLE;
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rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, cur_lv_tbl + off, sizeof(void *));
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}
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else
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{
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page = cur_lv_tbl[off];
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page &= MMU_ADDRESS_MASK;
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/* page to va */
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page -= PV_OFFSET;
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rt_page_ref_inc((void *)page, 0);
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}
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page = cur_lv_tbl[off];
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if ((page & MMU_TYPE_MASK) == MMU_TYPE_BLOCK)
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{
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/* is block! error! */
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ret = MMU_MAP_ERROR_CONFLICT;
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goto err;
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}
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cur_lv_tbl = (unsigned long *)(page & MMU_ADDRESS_MASK);
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cur_lv_tbl = (unsigned long *)((unsigned long)cur_lv_tbl - PV_OFFSET);
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level_shift -= MMU_LEVEL_SHIFT;
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}
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/* now is level page */
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attr &= MMU_ATTRIB_MASK;
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pa |= (attr | MMU_TYPE_PAGE); /* page */
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off = (va >> ARCH_PAGE_SHIFT);
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off &= MMU_LEVEL_MASK;
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cur_lv_tbl[off] = pa; /* page */
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rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, cur_lv_tbl + off, sizeof(void *));
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return ret;
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err:
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_kenrel_unmap_4K(lv0_tbl, (void *)va);
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return ret;
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}
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void *rt_hw_mmu_map(rt_aspace_t aspace, void *v_addr, void *p_addr, size_t size,
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size_t attr)
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{
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int ret = -1;
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void *unmap_va = v_addr;
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size_t npages = size >> ARCH_PAGE_SHIFT;
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// TODO trying with HUGEPAGE here
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while (npages--)
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{
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MM_PGTBL_LOCK(aspace);
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ret = _kenrel_map_4K(aspace->page_table, v_addr, p_addr, attr);
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MM_PGTBL_UNLOCK(aspace);
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if (ret != 0)
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{
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/* error, undo map */
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while (unmap_va != v_addr)
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{
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MM_PGTBL_LOCK(aspace);
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_kenrel_unmap_4K(aspace->page_table, (void *)unmap_va);
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MM_PGTBL_UNLOCK(aspace);
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unmap_va += ARCH_PAGE_SIZE;
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}
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break;
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}
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v_addr += ARCH_PAGE_SIZE;
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p_addr += ARCH_PAGE_SIZE;
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}
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if (ret == 0)
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{
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return unmap_va;
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}
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return NULL;
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}
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void rt_hw_mmu_unmap(rt_aspace_t aspace, void *v_addr, size_t size)
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{
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// caller guarantee that v_addr & size are page aligned
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size_t npages = size >> ARCH_PAGE_SHIFT;
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if (!aspace->page_table)
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{
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return;
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}
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while (npages--)
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{
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MM_PGTBL_LOCK(aspace);
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_kenrel_unmap_4K(aspace->page_table, v_addr);
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MM_PGTBL_UNLOCK(aspace);
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v_addr += ARCH_PAGE_SIZE;
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}
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}
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void rt_hw_aspace_switch(rt_aspace_t aspace)
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{
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if (aspace != &rt_kernel_space)
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{
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void *pgtbl = aspace->page_table;
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pgtbl = rt_kmem_v2p(pgtbl);
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uintptr_t tcr;
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__asm__ volatile("msr ttbr0_el1, %0" ::"r"(pgtbl) : "memory");
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__asm__ volatile("mrs %0, tcr_el1" : "=r"(tcr));
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tcr &= ~(1ul << 7);
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__asm__ volatile("msr tcr_el1, %0\n"
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"isb" ::"r"(tcr)
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: "memory");
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rt_hw_tlb_invalidate_all_local();
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}
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}
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void rt_hw_mmu_ktbl_set(unsigned long tbl)
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{
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#ifdef RT_USING_SMART
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tbl += PV_OFFSET;
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__asm__ volatile("msr TTBR1_EL1, %0\n dsb sy\nisb" ::"r"(tbl) : "memory");
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#else
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__asm__ volatile("msr TTBR0_EL1, %0\n dsb sy\nisb" ::"r"(tbl) : "memory");
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#endif
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__asm__ volatile("tlbi vmalle1\n dsb sy\nisb" ::: "memory");
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__asm__ volatile("ic ialluis\n dsb sy\nisb" ::: "memory");
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}
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/**
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* @brief setup Page Table for kernel space. It's a fixed map
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* and all mappings cannot be changed after initialization.
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*
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* Memory region in struct mem_desc must be page aligned,
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* otherwise is a failure and no report will be
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* returned.
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*
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* @param mmu_info
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* @param mdesc
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* @param desc_nr
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*/
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void rt_hw_mmu_setup(rt_aspace_t aspace, struct mem_desc *mdesc, int desc_nr)
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{
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void *err;
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for (size_t i = 0; i < desc_nr; i++)
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{
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size_t attr;
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switch (mdesc->attr)
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{
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case NORMAL_MEM:
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attr = MMU_MAP_K_RWCB;
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break;
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case NORMAL_NOCACHE_MEM:
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attr = MMU_MAP_K_RWCB;
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break;
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case DEVICE_MEM:
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attr = MMU_MAP_K_DEVICE;
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break;
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default:
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attr = MMU_MAP_K_DEVICE;
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}
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struct rt_mm_va_hint hint = {.flags = MMF_MAP_FIXED,
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.limit_start = aspace->start,
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.limit_range_size = aspace->size,
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.map_size = mdesc->vaddr_end -
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mdesc->vaddr_start + 1,
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.prefer = (void *)mdesc->vaddr_start};
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if (mdesc->paddr_start == (rt_size_t)ARCH_MAP_FAILED)
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mdesc->paddr_start = mdesc->vaddr_start + PV_OFFSET;
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int retval;
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retval = rt_aspace_map_phy_static(aspace, &mdesc->varea, &hint, attr,
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mdesc->paddr_start >> MM_PAGE_SHIFT, &err);
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if (retval)
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{
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LOG_E("%s: map failed with code %d", retval);
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RT_ASSERT(0);
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}
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mdesc++;
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}
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rt_hw_mmu_ktbl_set((unsigned long)rt_kernel_space.page_table);
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rt_page_cleanup();
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}
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#ifdef RT_USING_SMART
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static inline void _init_region(void *vaddr, size_t size)
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{
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rt_ioremap_start = vaddr;
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rt_ioremap_size = size;
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rt_mpr_start = rt_ioremap_start - rt_mpr_size;
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}
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#else
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#define RTOS_VEND ((void *)0xfffffffff000UL)
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static inline void _init_region(void *vaddr, size_t size)
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{
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rt_mpr_start = RTOS_VEND - rt_mpr_size;
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}
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#endif
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/**
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* This function will initialize rt_mmu_info structure.
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*
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* @param mmu_info rt_mmu_info structure
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* @param v_address virtual address
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* @param size map size
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* @param vtable mmu table
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* @param pv_off pv offset in kernel space
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*
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* @return 0 on successful and -1 for fail
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*/
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int rt_hw_mmu_map_init(rt_aspace_t aspace, void *v_address, size_t size,
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size_t *vtable, size_t pv_off)
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{
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size_t va_s, va_e;
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if (!aspace || !vtable)
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{
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return -1;
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}
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va_s = (size_t)v_address;
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va_e = (size_t)v_address + size - 1;
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if (va_e < va_s)
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{
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return -1;
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}
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va_s >>= ARCH_SECTION_SHIFT;
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va_e >>= ARCH_SECTION_SHIFT;
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if (va_s == 0)
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{
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return -1;
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}
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#ifdef RT_USING_SMART
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rt_aspace_init(aspace, (void *)KERNEL_VADDR_START, 0 - KERNEL_VADDR_START,
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vtable);
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#else
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rt_aspace_init(aspace, (void *)0x1000, RTOS_VEND - (void *)0x1000, vtable);
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#endif
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_init_region(v_address, size);
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return 0;
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}
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/************ setting el1 mmu register**************
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MAIR_EL1
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index 0 : memory outer writeback, write/read alloc
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index 1 : memory nocache
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index 2 : device nGnRnE
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*****************************************************/
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void mmu_tcr_init(void)
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{
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unsigned long val64;
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val64 = 0x00447fUL;
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__asm__ volatile("msr MAIR_EL1, %0\n dsb sy\n" ::"r"(val64));
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/* TCR_EL1 */
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val64 = (16UL << 0) /* t0sz 48bit */
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| (0x0UL << 6) /* reserved */
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| (0x0UL << 7) /* epd0 */
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| (0x3UL << 8) /* t0 wb cacheable */
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| (0x3UL << 10) /* inner shareable */
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| (0x2UL << 12) /* t0 outer shareable */
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| (0x0UL << 14) /* t0 4K */
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| (16UL << 16) /* t1sz 48bit */
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| (0x0UL << 22) /* define asid use ttbr0.asid */
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| (0x0UL << 23) /* epd1 */
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| (0x3UL << 24) /* t1 inner wb cacheable */
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| (0x3UL << 26) /* t1 outer wb cacheable */
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| (0x2UL << 28) /* t1 outer shareable */
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| (0x2UL << 30) /* t1 4k */
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| (0x1UL << 32) /* 001b 64GB PA */
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| (0x0UL << 35) /* reserved */
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| (0x1UL << 36) /* as: 0:8bit 1:16bit */
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| (0x0UL << 37) /* tbi0 */
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| (0x0UL << 38); /* tbi1 */
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__asm__ volatile("msr TCR_EL1, %0\n" ::"r"(val64));
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}
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struct page_table
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{
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unsigned long page[512];
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};
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static struct page_table *__init_page_array;
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static unsigned long __page_off = 0UL;
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unsigned long get_free_page(void)
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{
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if (!__init_page_array)
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{
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unsigned long temp_page_start;
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asm volatile("mov %0, sp" : "=r"(temp_page_start));
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__init_page_array =
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(struct page_table *)(temp_page_start & ~(ARCH_SECTION_MASK));
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__page_off = 2; /* 0, 1 for ttbr0, ttrb1 */
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}
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__page_off++;
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return (unsigned long)(__init_page_array[__page_off - 1].page);
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}
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static int _map_single_page_2M(unsigned long *lv0_tbl, unsigned long va,
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unsigned long pa, unsigned long attr)
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{
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int level;
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unsigned long *cur_lv_tbl = lv0_tbl;
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unsigned long page;
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unsigned long off;
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int level_shift = MMU_ADDRESS_BITS;
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if (va & ARCH_SECTION_MASK)
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{
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return MMU_MAP_ERROR_VANOTALIGN;
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}
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if (pa & ARCH_SECTION_MASK)
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{
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return MMU_MAP_ERROR_PANOTALIGN;
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}
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for (level = 0; level < MMU_TBL_BLOCK_2M_LEVEL; level++)
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{
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off = (va >> level_shift);
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off &= MMU_LEVEL_MASK;
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if (!(cur_lv_tbl[off] & MMU_TYPE_USED))
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{
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page = get_free_page();
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if (!page)
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{
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return MMU_MAP_ERROR_NOPAGE;
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}
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rt_memset((char *)page, 0, ARCH_PAGE_SIZE);
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cur_lv_tbl[off] = page | MMU_TYPE_TABLE;
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}
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page = cur_lv_tbl[off];
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if ((page & MMU_TYPE_MASK) == MMU_TYPE_BLOCK)
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{
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/* is block! error! */
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return MMU_MAP_ERROR_CONFLICT;
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}
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cur_lv_tbl = (unsigned long *)(page & MMU_ADDRESS_MASK);
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level_shift -= MMU_LEVEL_SHIFT;
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}
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attr &= MMU_ATTRIB_MASK;
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pa |= (attr | MMU_TYPE_BLOCK); /* block */
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off = (va >> ARCH_SECTION_SHIFT);
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off &= MMU_LEVEL_MASK;
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cur_lv_tbl[off] = pa;
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return 0;
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}
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static int _init_map_2M(unsigned long *lv0_tbl, unsigned long va,
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unsigned long pa, unsigned long count,
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unsigned long attr)
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{
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unsigned long i;
|
|
int ret;
|
|
|
|
if (va & ARCH_SECTION_MASK)
|
|
{
|
|
return -1;
|
|
}
|
|
if (pa & ARCH_SECTION_MASK)
|
|
{
|
|
return -1;
|
|
}
|
|
for (i = 0; i < count; i++)
|
|
{
|
|
ret = _map_single_page_2M(lv0_tbl, va, pa, attr);
|
|
va += ARCH_SECTION_SIZE;
|
|
pa += ARCH_SECTION_SIZE;
|
|
if (ret != 0)
|
|
{
|
|
return ret;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static unsigned long *_query(rt_aspace_t aspace, void *vaddr, int *plvl_shf)
|
|
{
|
|
int level;
|
|
unsigned long va = (unsigned long)vaddr;
|
|
unsigned long *cur_lv_tbl;
|
|
unsigned long page;
|
|
unsigned long off;
|
|
int level_shift = MMU_ADDRESS_BITS;
|
|
|
|
cur_lv_tbl = aspace->page_table;
|
|
RT_ASSERT(cur_lv_tbl);
|
|
|
|
for (level = 0; level < MMU_TBL_PAGE_4k_LEVEL; level++)
|
|
{
|
|
off = (va >> level_shift);
|
|
off &= MMU_LEVEL_MASK;
|
|
|
|
if (!(cur_lv_tbl[off] & MMU_TYPE_USED))
|
|
{
|
|
return (void *)0;
|
|
}
|
|
|
|
page = cur_lv_tbl[off];
|
|
if ((page & MMU_TYPE_MASK) == MMU_TYPE_BLOCK)
|
|
{
|
|
*plvl_shf = level_shift;
|
|
return &cur_lv_tbl[off];
|
|
}
|
|
|
|
cur_lv_tbl = (unsigned long *)(page & MMU_ADDRESS_MASK);
|
|
cur_lv_tbl = (unsigned long *)((unsigned long)cur_lv_tbl - PV_OFFSET);
|
|
level_shift -= MMU_LEVEL_SHIFT;
|
|
}
|
|
/* now is level MMU_TBL_PAGE_4k_LEVEL */
|
|
off = (va >> ARCH_PAGE_SHIFT);
|
|
off &= MMU_LEVEL_MASK;
|
|
page = cur_lv_tbl[off];
|
|
|
|
if (!(page & MMU_TYPE_USED))
|
|
{
|
|
return (void *)0;
|
|
}
|
|
*plvl_shf = level_shift;
|
|
return &cur_lv_tbl[off];
|
|
}
|
|
|
|
void *rt_hw_mmu_v2p(rt_aspace_t aspace, void *v_addr)
|
|
{
|
|
int level_shift;
|
|
unsigned long paddr;
|
|
unsigned long *pte = _query(aspace, v_addr, &level_shift);
|
|
|
|
if (pte)
|
|
{
|
|
paddr = *pte & MMU_ADDRESS_MASK;
|
|
paddr |= (uintptr_t)v_addr & ((1ul << level_shift) - 1);
|
|
}
|
|
else
|
|
{
|
|
paddr = (unsigned long)ARCH_MAP_FAILED;
|
|
}
|
|
return (void *)paddr;
|
|
}
|
|
|
|
static int _noncache(uintptr_t *pte)
|
|
{
|
|
int err = 0;
|
|
const uintptr_t idx_shift = 2;
|
|
const uintptr_t idx_mask = 0x7 << idx_shift;
|
|
uintptr_t entry = *pte;
|
|
if ((entry & idx_mask) == (NORMAL_MEM << idx_shift))
|
|
{
|
|
*pte = (entry & ~idx_mask) | (NORMAL_NOCACHE_MEM << idx_shift);
|
|
}
|
|
else
|
|
{
|
|
// do not support other type to be noncache
|
|
err = RT_ENOSYS;
|
|
}
|
|
return err;
|
|
}
|
|
|
|
static int _cache(uintptr_t *pte)
|
|
{
|
|
int err = 0;
|
|
const uintptr_t idx_shift = 2;
|
|
const uintptr_t idx_mask = 0x7 << idx_shift;
|
|
uintptr_t entry = *pte;
|
|
if ((entry & idx_mask) == (NORMAL_NOCACHE_MEM << idx_shift))
|
|
{
|
|
*pte = (entry & ~idx_mask) | (NORMAL_MEM << idx_shift);
|
|
}
|
|
else
|
|
{
|
|
// do not support other type to be cache
|
|
err = -RT_ENOSYS;
|
|
}
|
|
return err;
|
|
}
|
|
|
|
static int (*control_handler[MMU_CNTL_DUMMY_END])(uintptr_t *pte) = {
|
|
[MMU_CNTL_CACHE] = _cache,
|
|
[MMU_CNTL_NONCACHE] = _noncache,
|
|
};
|
|
|
|
int rt_hw_mmu_control(struct rt_aspace *aspace, void *vaddr, size_t size,
|
|
enum rt_mmu_cntl cmd)
|
|
{
|
|
int level_shift;
|
|
int err = -RT_EINVAL;
|
|
void *vend = vaddr + size;
|
|
|
|
int (*handler)(uintptr_t * pte);
|
|
if (cmd >= 0 && cmd < MMU_CNTL_DUMMY_END)
|
|
{
|
|
handler = control_handler[cmd];
|
|
|
|
while (vaddr < vend)
|
|
{
|
|
uintptr_t *pte = _query(aspace, vaddr, &level_shift);
|
|
void *range_end = vaddr + (1ul << level_shift);
|
|
RT_ASSERT(range_end <= vend);
|
|
|
|
if (pte)
|
|
{
|
|
err = handler(pte);
|
|
RT_ASSERT(err == RT_EOK);
|
|
}
|
|
vaddr = range_end;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
err = -RT_ENOSYS;
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
void rt_hw_mem_setup_early(unsigned long *tbl0, unsigned long *tbl1,
|
|
unsigned long size, unsigned long pv_off)
|
|
{
|
|
int ret;
|
|
|
|
/* setup pv off */
|
|
rt_kmem_pvoff_set(pv_off);
|
|
|
|
unsigned long va = KERNEL_VADDR_START;
|
|
unsigned long count = (size + ARCH_SECTION_MASK) >> ARCH_SECTION_SHIFT;
|
|
unsigned long normal_attr = MMU_MAP_CUSTOM(MMU_AP_KAUN, NORMAL_MEM);
|
|
|
|
/* clean the first two pages */
|
|
rt_memset((char *)tbl0, 0, ARCH_PAGE_SIZE);
|
|
rt_memset((char *)tbl1, 0, ARCH_PAGE_SIZE);
|
|
|
|
ret = _init_map_2M(tbl1, va, va + pv_off, count, normal_attr);
|
|
if (ret != 0)
|
|
{
|
|
while (1);
|
|
}
|
|
ret = _init_map_2M(tbl0, va + pv_off, va + pv_off, count, normal_attr);
|
|
if (ret != 0)
|
|
{
|
|
while (1);
|
|
}
|
|
}
|