332 lines
11 KiB
C
332 lines
11 KiB
C
/*
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* Copyright (C) Cvitek Co., Ltd. 2019-2022. All rights reserved.
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*/
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#ifndef _DW_GMAC_182x_H_
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#define _DW_GMAC_182x_H_
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#include "cvi_eth_phy.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef void *eth_mac_handle_t;
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#define CSI_ETH_MAC_CONFIGURE (0x01) ///< Configure MAC; arg = configuration
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#define CSI_ETH_MAC_CONTROL_TX (0x02) ///< Transmitter; arg: 0=disabled (default), 1=enabled
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#define CSI_ETH_MAC_CONTROL_RX (0x03) ///< Receiver; arg: 0=disabled (default), 1=enabled
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#define CSI_ETH_MAC_FLUSH (0x04) ///< Flush buffer; arg = CSI_ETH_MAC_FLUSH_...
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#define CSI_ETH_MAC_SLEEP (0x05) ///< Sleep mode; arg: 1=enter and wait for Magic packet, 0=exit
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#define CSI_ETH_MAC_VLAN_FILTER (0x06) ///< VLAN Filter for received frames; arg15..0: VLAN Tag; arg16: optional CSI_ETH_MAC_VLAN_FILTER_ID_ONLY; 0=disabled (default)
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#define DRV_ETH_MAC_ADJUST_LINK (0x07) ///< Adjust MAC link state according to phy state; arg: phy handle
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#define DRV_ETH_MAC_CONTROL_IRQ (0x08) ///< Interrupt request; arg: 0=disable, 1=enable
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#define DW_GMAC_DMA_ALIGN 128
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#ifndef _DW_ETH_H
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#define _DW_ETH_H
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#define GMAC_NULL_PARAM_CHK(para) CSI_PARAM_CHK(para, -1)
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#define GMAC_NULL_PARAM_CHK_NORETVAL(para) CSI_PARAM_CHK_NORETVAL(para)
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#define CVI_CONFIG_SYS_HZ 1000
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#define CVI_CONFIG_TX_DESCR_NUM 16
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#define CVI_CONFIG_RX_DESCR_NUM 16
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#define CVI_CONFIG_ETH_BUFSIZE 2048
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#define CVI_TX_TOTAL_BUFSIZE (CVI_CONFIG_ETH_BUFSIZE * CVI_CONFIG_TX_DESCR_NUM)
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#define CVI_RX_TOTAL_BUFSIZE (CVI_CONFIG_ETH_BUFSIZE * CVI_CONFIG_RX_DESCR_NUM)
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#define CVI_CONFIG_MACRESET_TIMEOUT (3 * CVI_CONFIG_SYS_HZ)
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#define CVI_CONFIG_MDIO_TIMEOUT (3 * CVI_CONFIG_SYS_HZ)
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struct dw_gmac_mac_regs {
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volatile uint32_t conf; /* 0x00 */
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volatile uint32_t framefilt; /* 0x04 */
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volatile uint32_t hashtablehigh; /* 0x08 */
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volatile uint32_t hashtablelow; /* 0x0c */
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volatile uint32_t miiaddr; /* 0x10 */
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volatile uint32_t miidata; /* 0x14 */
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volatile uint32_t flowcontrol; /* 0x18 */
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volatile uint32_t vlantag; /* 0x1c */
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volatile uint32_t version; /* 0x20 */
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volatile uint32_t reserved_1[5];
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volatile uint32_t intreg; /* 0x38 */
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volatile uint32_t intmask; /* 0x3c */
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volatile uint32_t macaddr0hi; /* 0x40 */
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volatile uint32_t macaddr0lo; /* 0x44 */
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};
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/* MAC configuration register definitions */
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#define CVI_FRAMEBURSTENABLE (1 << 21)
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#define CVI_MII_PORTSELECT (1 << 15)
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#define CVI_FES_100 (1 << 14)
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#define CVI_DISABLERXOWN (1 << 13)
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#define CVI_FULLDPLXMODE (1 << 11)
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#define CVI_RXENABLE (1 << 2)
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#define CVI_TXENABLE (1 << 3)
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/* MII address register definitions */
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#define CVI_MII_BUSY (1 << 0)
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#define CVI_MII_WRITE (1 << 1)
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#define CVI_MII_CLKRANGE_60_100M (0)
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#define CVI_MII_CLKRANGE_100_150M (0x4)
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#define CVI_MII_CLKRANGE_20_35M (0x8)
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#define CVI_MII_CLKRANGE_35_60M (0xC)
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#define CVI_MII_CLKRANGE_150_250M (0x10)
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#define CVI_MII_CLKRANGE_250_300M (0x14)
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#define CVI_MIIADDRSHIFT (11)
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#define CVI_MIIREGSHIFT (6)
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#define CVI_MII_REGMSK (0x1F << 6)
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#define CVI_MII_ADDRMSK (0x1F << 11)
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typedef uint32_t reg_type;
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struct dw_gmac_dma_regs {
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volatile reg_type busmode; /* 0x00 */
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volatile reg_type txpolldemand; /* 0x04 */
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volatile reg_type rxpolldemand; /* 0x08 */
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volatile reg_type rxdesclistaddr; /* 0x0c */
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volatile reg_type txdesclistaddr; /* 0x10 */
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volatile reg_type status; /* 0x14 */
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volatile reg_type opmode; /* 0x18 */
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volatile reg_type intenable; /* 0x1c */
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volatile reg_type discardedcount; /* 0x20 */
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volatile reg_type wdtforri; /* 0x24 */
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//volatile reg_type reserved1[2];
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volatile reg_type axibus; /* 0x28 */
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volatile reg_type reserved2[7];
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volatile reg_type currhosttxdesc; /* 0x48 */
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volatile reg_type currhostrxdesc; /* 0x4c */
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volatile reg_type currhosttxbuffaddr; /* 0x50 */
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volatile reg_type currhostrxbuffaddr; /* 0x54 */
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};
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/* Operation mode definitions */
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#define CVI_RXSTART (1 << 1)
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#define CVI_TXSECONDFRAME (1 << 2)
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#define CVI_TXSTART (1 << 13)
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#define CVI_FLUSHTXFIFO (1 << 20)
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#define CVI_STOREFORWARD (1 << 21)
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#define CVI_DW_DMA_BASE_OFFSET (0x1000)
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/* Default DMA Burst length */
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#ifndef CONFIG_DW_GMAC_DEFAULT_DMA_PBL
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#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL 8
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#endif
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/* Status definitions */
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#define CVI_DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */
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#define CVI_DMA_STATUS_RI 0x00000040 /* Receive Interrupt */
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#define CVI_DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */
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/* Bus mode register definitions */
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#define CVI_DMAMAC_SRST (1 << 0)
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#define CVI_RXHIGHPRIO (1 << 1)
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#define CVI_FIXEDBURST (1 << 16)
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#define CVI_PRIORXTX_11 (0 << 14)
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#define CVI_PRIORXTX_21 (1 << 14)
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#define CVI_PRIORXTX_31 (2 << 14)
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#define CVI_PRIORXTX_41 (3 << 14)
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#define CVI_DMA_PBL (CONFIG_DW_GMAC_DEFAULT_DMA_PBL<<8)
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/* Poll demand definitions */
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#define CVI_POLL_DATA (0xFFFFFFFF)
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/* Descriptior related definitions */
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#define CVI_MAC_MAX_FRAME_SZ (1600)
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struct dmamacdescr {
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unsigned int txrx_status;
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unsigned int dmamac_cntl;
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unsigned int dmamac_addr;
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unsigned int dmamac_next;
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} __attribute__((aligned(DW_GMAC_DMA_ALIGN)));
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/*
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* txrx_status definitions
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*/
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/* tx status bits definitions */
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#if defined(CONFIG_DW_ALTDESCRIPTOR)
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#define CVI_DESC_TXSTS_OWNBYDMA (1 << 31)
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#define CVI_DESC_TXSTS_TXINT (1 << 30)
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#define CVI_DESC_TXSTS_TXLAST (1 << 29)
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#define CVI_DESC_TXSTS_TXFIRST (1 << 28)
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#define CVI_DESC_TXSTS_TXCRCDIS (1 << 27)
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#define CVI_DESC_TXSTS_TXPADDIS (1 << 26)
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#define CVI_DESC_TXSTS_TXCHECKINSCTRL (3 << 22)
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#define CVI_DESC_TXSTS_TXRINGEND (1 << 21)
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#define CVI_DESC_TXSTS_TXCHAIN (1 << 20)
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#define CVI_DESC_TXSTS_MSK (0x1FFFF << 0)
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#else
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#define CVI_DESC_TXSTS_OWNBYDMA (1 << 31)
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#define CVI_DESC_TXSTS_MSK (0x1FFFF << 0)
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#endif
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/* rx status bits definitions */
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#define CVI_DESC_RXSTS_OWNBYDMA (1 << 31)
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#define CVI_DESC_RXSTS_DAFILTERFAIL (1 << 30)
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#define CVI_DESC_RXSTS_FRMLENMSK (0x3FFF << 16)
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#define CVI_DESC_RXSTS_FRMLENSHFT (16)
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#define CVI_DESC_RXSTS_ERROR (1 << 15)
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#define CVI_DESC_RXSTS_RXTRUNCATED (1 << 14)
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#define CVI_DESC_RXSTS_SAFILTERFAIL (1 << 13)
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#define CVI_DESC_RXSTS_RXIPC_GIANTFRAME (1 << 12)
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#define CVI_DESC_RXSTS_RXDAMAGED (1 << 11)
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#define CVI_DESC_RXSTS_RXVLANTAG (1 << 10)
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#define CVI_DESC_RXSTS_RXFIRST (1 << 9)
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#define CVI_DESC_RXSTS_RXLAST (1 << 8)
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#define CVI_DESC_RXSTS_RXIPC_GIANT (1 << 7)
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#define CVI_DESC_RXSTS_RXCOLLISION (1 << 6)
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#define CVI_DESC_RXSTS_RXFRAMEETHER (1 << 5)
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#define CVI_DESC_RXSTS_RXWATCHDOG (1 << 4)
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#define CVI_DESC_RXSTS_RXMIIERROR (1 << 3)
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#define CVI_DESC_RXSTS_RXDRIBBLING (1 << 2)
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#define CVI_DESC_RXSTS_RXCRC (1 << 1)
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/*
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* dmamac_cntl definitions
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*/
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/* tx control bits definitions */
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#if defined(CONFIG_DW_ALTDESCRIPTOR)
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#define CVI_DESC_TXCTRL_SIZE1MASK (0x1FFF << 0)
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#define CVI_DESC_TXCTRL_SIZE1SHFT (0)
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#define CVI_DESC_TXCTRL_SIZE2MASK (0x1FFF << 16)
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#define CVI_DESC_TXCTRL_SIZE2SHFT (16)
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#else
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#define CVI_DESC_TXCTRL_TXINT (1 << 31)
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#define CVI_DESC_TXCTRL_TXLAST (1 << 30)
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#define CVI_DESC_TXCTRL_TXFIRST (1 << 29)
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#define CVI_DESC_TXCTRL_TXCHECKINSCTRL (3 << 27)
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#define CVI_DESC_TXCTRL_TXCRCDIS (1 << 26)
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#define CVI_DESC_TXCTRL_TXRINGEND (1 << 25)
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#define CVI_DESC_TXCTRL_TXCHAIN (1 << 24)
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#define CVI_DESC_TXCTRL_SIZE1MASK (0x7FF << 0)
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#define CVI_DESC_TXCTRL_SIZE1SHFT (0)
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#define CVI_DESC_TXCTRL_SIZE2MASK (0x7FF << 11)
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#define CVI_DESC_TXCTRL_SIZE2SHFT (11)
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#endif
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/* rx control bits definitions */
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#if defined(CONFIG_DW_ALTDESCRIPTOR)
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#define CVI_DESC_RXCTRL_RXINTDIS (1 << 31)
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#define CVI_DESC_RXCTRL_RXRINGEND (1 << 15)
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#define CVI_DESC_RXCTRL_RXCHAIN (1 << 14)
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#define CVI_DESC_RXCTRL_SIZE1MASK (0x1FFF << 0)
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#define CVI_DESC_RXCTRL_SIZE1SHFT (0)
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#define CVI_DESC_RXCTRL_SIZE2MASK (0x1FFF << 16)
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#define CVI_DESC_RXCTRL_SIZE2SHFT (16)
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#else
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#define CVI_DESC_RXCTRL_RXINTDIS (1 << 31)
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#define CVI_DESC_RXCTRL_RXRINGEND (1 << 25)
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#define CVI_DESC_RXCTRL_RXCHAIN (1 << 24)
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#define CVI_DESC_RXCTRL_SIZE1MASK (0x7FF << 0)
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#define CVI_DESC_RXCTRL_SIZE1SHFT (0)
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#define CVI_DESC_RXCTRL_SIZE2MASK (0x7FF << 11)
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#define CVI_DESC_RXCTRL_SIZE2SHFT (11)
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#endif
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struct dw_gmac_priv {
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struct dmamacdescr tx_mac_descrtable[CVI_CONFIG_TX_DESCR_NUM] __aligned(DW_GMAC_DMA_ALIGN);
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struct dmamacdescr rx_mac_descrtable[CVI_CONFIG_RX_DESCR_NUM] __aligned(DW_GMAC_DMA_ALIGN);
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char txbuffs[CVI_TX_TOTAL_BUFSIZE] __aligned(DW_GMAC_DMA_ALIGN);
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char rxbuffs[CVI_RX_TOTAL_BUFSIZE] __aligned(DW_GMAC_DMA_ALIGN);
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uint32_t interface;
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uint32_t max_speed;
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uint32_t tx_currdescnum;
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uint32_t rx_currdescnum;
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struct dw_gmac_mac_regs *mac_regs_p;
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struct dw_gmac_dma_regs *dma_regs_p;
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//struct gpio_desc reset_gpio;
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};
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#ifdef CONFIG_DM_ETH
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int designware_eth_ofdata_to_platdata(struct udevice *dev);
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int designware_eth_probe(struct udevice *dev);
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extern const struct eth_ops designware_eth_ops;
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struct dw_eth_pdata {
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struct eth_pdata eth_pdata;
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u32 reset_delays[3];
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};
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int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr);
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int designware_eth_enable(struct dw_eth_dev *priv);
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int designware_eth_send(struct udevice *dev, void *packet, int length);
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int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp);
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int designware_eth_free_pkt(struct udevice *dev, uchar *packet,
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int length);
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void designware_eth_stop(struct udevice *dev);
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int designware_eth_write_hwaddr(struct udevice *dev);
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#endif
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#endif
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typedef struct {
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// csi_dev_t dev;
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eth_phy_dev_t *phy_dev;
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unsigned long base;
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uint8_t irq;
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// eth_event_cb_t cb_event;
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uint8_t mac_addr[6];
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struct dw_gmac_priv *priv_unalign;
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struct dw_gmac_priv *priv;
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} gmac_dev_t;
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/**
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\brief Ethernet MAC Address
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*/
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typedef struct eth_mac_addr {
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uint8_t b[6]; ///< MAC Address (6 bytes), MSB first
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} eth_mac_addr_t;
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static inline void *memalign(uint32_t align, uint32_t size, void **mem_unalign)
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{
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void *mem;
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uint32_t offset;
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*mem_unalign = (void *)rt_malloc(size + align);
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if (!*mem_unalign) {
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return NULL;
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}
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offset = *(uint32_t *)mem_unalign % align;
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if (offset == 0) {
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mem = (struct eqos_priv *)*mem_unalign;
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} else {
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mem = (struct eqos_priv *)(*mem_unalign + (align - offset));
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}
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return mem;
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* _DW_GMAC_182x_H_ */
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