268 lines
13 KiB
C
268 lines
13 KiB
C
//*****************************************************************************
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//
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// Copyright (C) 2012 - 2017 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// MSP432 Family CMSIS Definitions
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//
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//****************************************************************************
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#ifndef CMSIS_CCS_H_
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#define CMSIS_CCS_H_
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#ifndef __TI_ARM__
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#error This file should only be compiled by TI compiler (minimum version 15.12.x)
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#endif
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/** CMSIS compiler control architecture macros */
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#if defined ( __TI_ARM_V6M0__ )
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#define __ARM_ARCH_6M__ 1
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#endif
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#if defined ( __TI_ARM_V7M3__ )
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#define __ARM_ARCH_7M__ 1
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#endif
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#if defined ( __TI_ARM_V7M4__ )
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#define __ARM_ARCH_7EM__ 1
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#endif
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/* ########################### Core Function Access ########################### */
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/** \ingroup CMSIS_Core_FunctionInterface
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* \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
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* @{
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*/
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/**
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* \brief Enable IRQ Interrupts
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* \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
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* Can only be executed in Privileged modes.
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*/
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#define __enable_irq _enable_IRQ
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/**
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* \brief Disable IRQ Interrupts
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* \details Disables IRQ interrupts by setting the I-bit in the CPSR.
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* Can only be executed in Privileged modes.
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*/
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#define __disable_irq _disable_IRQ
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/** @} */ /* end of CMSIS_Core_RegAccFunctions */
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/* ########################## Core Instruction Access ######################### */
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/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
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* Access to dedicated instructions
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* @{
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*/
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/**
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* \brief Count leading zeros
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* \details Counts the number of leading zeros of a data value.
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* \param [in] VAL Value to count the leading zeros
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* \return number of leading zeros in value
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*/
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#define __CLZ(VAL) ((unsigned char)__clz(VAL))
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/**
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* \brief Signed Saturate
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* \details Saturates a signed value.
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* \param [in] VAL Value to be saturated
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* \param [in] BITPOS Bit position to saturate to (1..32)
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* \return Saturated value
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*/
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#define __SSAT(VAL, BITPOS) _ssatl(VAL, 0, BITPOS)
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/**
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* \brief No Operation
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* \details No Operation does nothing. This instruction can be used for code alignment purposes.
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*/
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#define __NOP __nop
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/**
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* \brief Wait For Interrupt
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* \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
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*/
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#define __WFI __wfi
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/**
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* \brief Wait For Event
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* \details Wait For Event is a hint instruction that permits the processor to enter
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* a low-power state until one of a number of events occurs.
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*/
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#define __WFE __wfe
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/**
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* \brief Data Synchronization Barrier
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* \details Acts as a special kind of Data Memory Barrier.
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* It completes when all explicit memory accesses before this instruction complete.
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*/
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#define __DSB _dsb
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/**
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* \brief Instruction Synchronization Barrier
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* \details Instruction Synchronization Barrier flushes the pipeline in the processor,
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* so that all instructions following the ISB are fetched from cache or memory,
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* after the instruction has been completed.
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*/
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#define __ISB _isb
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/**
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\brief Data Memory Barrier
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\details Ensures the apparent order of the explicit memory operations before
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and after the instruction, without ensuring their completion.
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*/
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#define __DMB _dmb
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/**
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* \brief Rotate Right in unsigned value (32 bit)
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* \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
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* \param [in] VAL Value to rotate
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* \param [in] SHIFT Number of Bits to rotate
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* \return Rotated value
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*/
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#define __ROR(VAL, SHIFT) ((unsigned int)__ror(VAL, SHIFT))
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/** @} */ /* end of group CMSIS_Core_InstructionInterface */
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/* ################### Compiler specific Intrinsics ########################### */
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/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
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* Access to dedicated SIMD instructions
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* @{
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*/
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#if (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))
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#define __SADD8(VAL1, VAL2) ((unsigned int)_sadd8(VAL1, VAL2))
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#define __QADD8(VAL1, VAL2) ((unsigned int)_qadd8(VAL1, VAL2))
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#define __SHADD8(VAL1, VAL2) ((unsigned int)_shadd8(VAL1, VAL2))
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#define __UADD8(VAL1, VAL2) ((unsigned int)_uadd8(VAL1, VAL2))
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#define __UQADD8(VAL1, VAL2) ((unsigned int)_uqadd8(VAL1, VAL2))
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#define __UHADD8(VAL1, VAL2) ((unsigned int)_uhadd8(VAL1, VAL2))
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#define __SSUB8(VAL1, VAL2) ((unsigned int)_ssub8(VAL1, VAL2))
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#define __QSUB8(VAL1, VAL2) ((unsigned int)_qsub8(VAL1, VAL2))
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#define __SHSUB8(VAL1, VAL2) ((unsigned int)_shsub8(VAL1, VAL2))
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#define __USUB8(VAL1, VAL2) ((unsigned int)_usub8(VAL1, VAL2))
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#define __UQSUB8(VAL1, VAL2) ((unsigned int)_uqsub8(VAL1, VAL2))
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#define __UHSUB8(VAL1, VAL2) ((unsigned int)_uhsub8(VAL1, VAL2))
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#define __SADD16(VAL1, VAL2) ((unsigned int)_sadd16(VAL1, VAL2))
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#define __QADD16(VAL1, VAL2) ((unsigned int)_qadd16(VAL1, VAL2))
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#define __SHADD16(VAL1, VAL2) ((unsigned int)_shadd16(VAL1, VAL2))
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#define __UADD16(VAL1, VAL2) ((unsigned int)_uadd16(VAL1, VAL2))
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#define __UQADD16(VAL1, VAL2) ((unsigned int)_uqadd16(VAL1, VAL2))
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#define __UHADD16(VAL1, VAL2) ((unsigned int)_uhadd16(VAL1, VAL2))
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#define __SSUB16(VAL1, VAL2) ((unsigned int)_ssub16(VAL1, VAL2))
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#define __QSUB16(VAL1, VAL2) ((unsigned int)_qsub16(VAL1, VAL2))
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#define __SHSUB16(VAL1, VAL2) ((unsigned int)_shsub16(VAL1, VAL2))
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#define __USUB16(VAL1, VAL2) ((unsigned int)_usub16(VAL1, VAL2))
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#define __UQSUB16(VAL1, VAL2) ((unsigned int)_uqsub16(VAL1, VAL2))
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#define __UHSUB16(VAL1, VAL2) ((unsigned int)_uhsub16(VAL1, VAL2))
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#define __SASX(VAL1, VAL2) ((unsigned int)_saddsubx(VAL1, VAL2))
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#define __QASX(VAL1, VAL2) ((unsigned int)_qaddsubx(VAL1, VAL2))
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#define __SHASX(VAL1, VAL2) ((unsigned int)_shaddsubx(VAL1, VAL2))
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#define __UASX(VAL1, VAL2) ((unsigned int)_uaddsubx(VAL1, VAL2))
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#define __UQASX(VAL1, VAL2) ((unsigned int)_uqaddsubx(VAL1, VAL2))
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#define __UHASX(VAL1, VAL2) ((unsigned int)_uhaddsubx(VAL1, VAL2)))
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#define __SSAX(VAL1, VAL2) ((unsigned int)_ssubaddx(VAL1, VAL2))
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#define __QSAX(VAL1, VAL2) ((unsigned int)_qsubaddx(VAL1, VAL2))
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#define __SHSAX(VAL1, VAL2) ((unsigned int)_shsubaddx(VAL1, VAL2))
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#define __USAX(VAL1, VAL2) ((unsigned int)_usubaddx(VAL1, VAL2))
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#define __UQSAX(VAL1, VAL2) ((unsigned int)_uqsubaddx(VAL1, VAL2))
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#define __UHSAX(VAL1, VAL2) ((unsigned int)_uhsubaddx(VAL1, VAL2))
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#define __USAD8(VAL1, VAL2) ((unsigned int)_usad8(VAL1, VAL2))
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#define __USADA8(VAL1, VAL2, VAL3) ((unsigned int)_usada8(VAL1, VAL2, VAL3))
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#define __SSAT16(VAL, BITPOS) ((unsigned int)_ssat16(VAL, BITPOS))
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#define __USAT16(VAL, BITPOS) ((unsigned int)_usat16(VAL, BITPOS))
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#define __UXTB16(VAL) ((unsigned int)_uxtb16(VAL, 0))
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#define __UXTAB16(VAL1, VAL2) ((unsigned int)_uxtab16(VAL1, VAL2, 0))
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#define __SXTB16(VAL) ((unsigned int)_sxtb16(VAL, 0))
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#define __SXTAB16(VAL1, VAL2) ((unsigned int)_sxtab16(VAL1, VAL2, 0))
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#define __SMUAD(VAL1, VAL2) ((unsigned int)_smuad(VAL1, VAL2))
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#define __SMUADX(VAL1, VAL2) ((unsigned int)_smuadx(VAL1, VAL2))
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#define __SMLAD(VAL1, VAL2, ACCUMULATOR) ((unsigned int)_smlad(VAL1, VAL2, ACCUMULATOR))
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#define __SMLADX(VAL1, VAL2, ACCUMULATOR) ((unsigned int)_smladx(VAL1, VAL2, ACCUMULATOR))
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#define __SMLALD(VAL1, VAL2, ACCUMULATOR) ((unsigned long long)_smlald(ACCUMULATOR, VAL1, VAL2))
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#define __SMLALDX(VAL1, VAL2, ACCUMULATOR) ((unsigned long long)_smlaldx(ACCUMULATOR, VAL1, VAL2))
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#define __SMUSD(VAL1, VAL2) ((unsigned int)_smusd(VAL1, VAL2))
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#define __SMUSDX(VAL1, VAL2) ((unsigned int)_smusdx(VAL1, VAL2))
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#define __SMLSD(VAL1, VAL2, ACCUMULATOR) ((unsigned int)_smlsd(VAL1, VAL2, ACCUMULATOR))
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#define __SMLSDX(VAL1, VAL2, ACCUMULATOR) ((unsigned int)_smlsdx(VAL1, VAL2, ACCUMULATOR))
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#define __SMLSLD(VAL1, VAL2, ACCUMULATOR) ((unsigned long long)_smlsld(ACCUMULATOR, VAL1, VAL2))
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#define __SMLSLDX(VAL1, VAL2, ACCUMULATOR) ((unsigned long long)_smlsldx(ACCUMULATOR, VAL1, VAL2))
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#define __SEL(VAL1, VAL2) ((unsigned int)_sel(VAL1, VAL2))
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#define __QADD _sadd
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#define __QSUB _ssub
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#define __PKHBT _pkhbt
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#define __PKHTB _pkhtb
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#define __SMMLA _smmla
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#define __QDADD _sdadd
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#define __QDSUB _sdsub
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#define __SMLABB _smlabb
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#define __SMLABT _smlabt
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#define __SMLALBB _smlalbb
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#define __SMLALBT _smlalbt
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#define __SMLALTB _smlaltb
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#define __SMLALTT _smlaltt
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#define __SMLATB _smlatb
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#define __SMLATT _smlatt
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#define __SMLAWB _smlawb
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#define __SMLAWT _smlawt
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#define __SMULBB _smulbb
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#define __SMULBT _smulbt
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#define __SMULTB _smultb
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#define __SMULTT _smultt
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#define __SMULWB _smulwb
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#define __SMULWT _smulwt
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#define __SMMLAR _smmlar
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#define __SMMLS _smmls
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#define __SMMLSR _smmlsr
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#define __SMMUL _smmul
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#define __SMMULR _smmulr
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#define __SXTAB _sxtab
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#define __SXTAH _sxtah
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#define __UMAAL _umaal
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#define __UXTAB _uxtab
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#define __UXTAH _uxtah
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#define __SUBC _subc
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#endif /* (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) */
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#if (defined (__ARM_ARCH_6M__) && (__ARM_ARCH_6M__ == 1))
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#define __SXTB _sxtb
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#define __SXTH _sxth
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#define __UXTB _uxtb
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#define __UXTH _uxth
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#endif /* (defined (__ARM_ARCH_6M__) && (__ARM_ARCH_6M__ == 1)) */
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/** @} */ /* end of group CMSIS_SIMD_intrinsics */
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#endif /* CMSIS_CCS_H_ */
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