498 lines
23 KiB
C
498 lines
23 KiB
C
/*
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* Copyright (c) 2022 OpenLuat & AirM2M
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __AIR105_SPI_H
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#define __AIR105_SPI_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "air105.h"
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#define SPI_DMACR_RDMAE_Pos (0)
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#define SPI_DMACR_RDMAE_Mask (0x01U << SPI_DMACR_RDMAE_Pos)
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#define SPI_DMACR_TDMAE_Pos (1)
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#define SPI_DMACR_TDMAE_Mask (0x01U << SPI_DMACR_TDMAE_Pos)
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/** @defgroup SPI_Exported_Types
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* @{
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*/
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/**
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* @brief SPI Init structure definition
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*/
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typedef struct
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{
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uint32_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.
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This parameter can be a value of @ref SPI_data_direction */
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uint32_t SPI_Mode; /*!< Specifies the SPI operating mode.
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This parameter can be a value of @ref SPI_mode */
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uint32_t SPI_DataSize; /*!< Specifies the SPI data size.
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This parameter can be a value of @ref SPI_data_size */
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uint32_t SPI_CPOL; /*!< Specifies the serial clock steady state.
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This parameter can be a value of @ref SPI_Clock_Polarity */
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uint32_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.
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This parameter can be a value of @ref SPI_Clock_Phase */
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uint32_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by
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hardware (NSS pin) or by software using the SSI bit.
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This parameter can be a value of @ref SPI_Slave_Select_management */
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uint32_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
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used to configure the transmit and receive SCK clock.
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This parameter can be a value of @ref SPI_BaudRate_Prescaler.
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@note The communication clock is derived from the master
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clock. The slave clock does not need to be set. */
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uint32_t SPI_RXFIFOFullThreshold;
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uint32_t SPI_TXFIFOEmptyThreshold;
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}SPI_InitTypeDef;
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/**
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* @brief Texas Instruments Synchronous Serial Protocol (SSP) Init structure definition
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*/
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typedef struct
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{
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uint32_t SSP_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.
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This parameter can be a value of @ref SPI_data_direction */
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uint32_t SSP_DataSize; /*!< Specifies the SPI data size.
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This parameter can be a value of @ref SPI_data_size */
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uint32_t SSP_NSS; /*!< Specifies whether the NSS signal is managed by
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hardware (NSS pin) or by software using the SSI bit.
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This parameter can be a value of @ref SPI_Slave_Select_management */
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uint32_t SSP_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
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used to configure the transmit and receive SCK clock.
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This parameter can be a value of @ref SPI_BaudRate_Prescaler.
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@note The communication clock is derived from the master
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clock. The slave clock does not need to be set. */
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uint32_t SSP_RXFIFOFullThreshold;
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uint32_t SSP_TXFIFOEmptyThreshold;
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}SSP_InitTypeDef;
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/**
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* @brief National Semiconductor Microwire (NSM) Init structure definition
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*/
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typedef struct
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{
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uint32_t NSM_Direction;
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uint32_t NSM_TransferMode;
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uint32_t NSM_DataSize; /*!< Specifies the SPI data size.
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This parameter can be a value of @ref SPI_data_size */
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uint32_t NSM_ControlDataSize;
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uint32_t NSM_NSS; /*!< Specifies whether the NSS signal is managed by
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hardware (NSS pin) or by software using the SSI bit.
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This parameter can be a value of @ref SPI_Slave_Select_management */
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uint32_t NSM_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
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used to configure the transmit and receive SCK clock.
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This parameter can be a value of @ref SPI_BaudRate_Prescaler.
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@note The communication clock is derived from the master
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clock. The slave clock does not need to be set. */
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FunctionalState NSM_HandShakingCmd;
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uint32_t NSM_RXFIFOFullThreshold;
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uint32_t NSM_TXFIFOEmptyThreshold;
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}NSM_InitTypeDef;
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/**
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* @brief SPI DMA Init structure definition
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*/
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typedef struct
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{
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uint32_t SPI_DMAReq;
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uint32_t SPI_DMAReceiveLevel;
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uint32_t SPI_DMATransmitLevel;
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FunctionalState SPI_DMAEnCmd;
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}SPI_DMAInitTypeDef;
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/** @defgroup SPI_data_direction
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* @{
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*/
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#define SPI_Direction_2Lines_FullDuplex ((uint32_t)0x0000)
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#define SPI_Direction_1Line_Tx ((uint32_t)0x0100)
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#define SPI_Direction_1Line_Rx ((uint32_t)0x0200)
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#define SPI_Direction_EEPROM_Read ((uint32_t)0x0300)
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#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
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((MODE) == SPI_Direction_1Line_Tx) || \
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((MODE) == SPI_Direction_1Line_Rx) || \
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((MODE) == SPI_Direction_EEPROM_Read))
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/**
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* @}
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*/
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#define SPI_Mode_Master ((uint32_t)0x0001)
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#define SPI_Mode_Slave ((uint32_t)0x0000)
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#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
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((MODE) == SPI_Mode_Slave))
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/** @defgroup SPI_data_size
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* @{
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*/
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#define SPI_DataSize_8b ((uint32_t)0x0007)
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#define SPI_DataSize_16b ((uint32_t)0x000F)
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#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \
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((DATASIZE) == SPI_DataSize_8b))
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/**
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* @}
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*/
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/** @defgroup SPI_Clock_Polarity
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* @{
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*/
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#define SPI_CPOL_Low ((uint32_t)0x0000)
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#define SPI_CPOL_High ((uint32_t)0x0080)
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#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
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((CPOL) == SPI_CPOL_High))
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/**
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* @}
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*/
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/** @defgroup SPI_Clock_Phase
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* @{
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*/
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#define SPI_CPHA_1Edge ((uint32_t)0x0000)
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#define SPI_CPHA_2Edge ((uint32_t)0x0040)
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#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
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((CPHA) == SPI_CPHA_2Edge))
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/**
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* @}
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*/
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#define SPI_NSS_0 ((uint32_t)0x0001)
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#define SPI_NSS_Null ((uint32_t)0x0000)
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#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_0) || \
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((NSS) == SPI_NSS_Null))
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/** @defgroup SPI_BaudRate_Prescaler
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* @{
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*/
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#define SPI_BaudRatePrescaler_2 ((uint32_t)0x0002)
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#define SPI_BaudRatePrescaler_4 ((uint32_t)0x0004)
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#define SPI_BaudRatePrescaler_8 ((uint32_t)0x0008)
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#define SPI_BaudRatePrescaler_16 ((uint32_t)0x0010)
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#define SPI_BaudRatePrescaler_32 ((uint32_t)0x0020)
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#define SPI_BaudRatePrescaler_64 ((uint32_t)0x0040)
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#define SPI_BaudRatePrescaler_128 ((uint32_t)0x0080)
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#define SPI_BaudRatePrescaler_256 ((uint32_t)0x0100)
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#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
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((PRESCALER) == SPI_BaudRatePrescaler_4) || \
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((PRESCALER) == SPI_BaudRatePrescaler_8) || \
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((PRESCALER) == SPI_BaudRatePrescaler_16) || \
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((PRESCALER) == SPI_BaudRatePrescaler_32) || \
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((PRESCALER) == SPI_BaudRatePrescaler_64) || \
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((PRESCALER) == SPI_BaudRatePrescaler_128) || \
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((PRESCALER) == SPI_BaudRatePrescaler_256))
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/**
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* @}
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*/
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/** @defgroup SPI_RXFIFOFullThreshold
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* @{
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*/
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#define SPI_RXFIFOFullThreshold_1 ((uint32_t)0x0000)
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#define SPI_RXFIFOFullThreshold_2 ((uint32_t)0x0001)
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#define SPI_RXFIFOFullThreshold_3 ((uint32_t)0x0002)
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#define SPI_RXFIFOFullThreshold_4 ((uint32_t)0x0003)
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#define SPI_RXFIFOFullThreshold_5 ((uint32_t)0x0004)
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#define SPI_RXFIFOFullThreshold_6 ((uint32_t)0x0005)
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#define SPI_RXFIFOFullThreshold_7 ((uint32_t)0x0006)
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#define SPI_RXFIFOFullThreshold_8 ((uint32_t)0x0007)
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#define SPI_RXFIFOFullThreshold_9 ((uint32_t)0x0008)
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#define SPI_RXFIFOFullThreshold_10 ((uint32_t)0x0009)
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#define SPI_RXFIFOFullThreshold_11 ((uint32_t)0x000A)
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#define SPI_RXFIFOFullThreshold_12 ((uint32_t)0x000B)
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#define SPI_RXFIFOFullThreshold_13 ((uint32_t)0x000C)
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#define SPI_RXFIFOFullThreshold_14 ((uint32_t)0x000D)
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#define SPI_RXFIFOFullThreshold_15 ((uint32_t)0x000E)
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#define SPI_RXFIFOFullThreshold_16 ((uint32_t)0x000F)
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#define IS_SPI_RX_FIFO_FULL_THRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_RXFIFOFullThreshold_1) || \
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((THRESHOLD) == SPI_RXFIFOFullThreshold_2) || \
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((THRESHOLD) == SPI_RXFIFOFullThreshold_3) || \
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((THRESHOLD) == SPI_RXFIFOFullThreshold_4) || \
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((THRESHOLD) == SPI_RXFIFOFullThreshold_5) || \
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((THRESHOLD) == SPI_RXFIFOFullThreshold_6) || \
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((THRESHOLD) == SPI_RXFIFOFullThreshold_7) || \
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((THRESHOLD) == SPI_RXFIFOFullThreshold_8) || \
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((THRESHOLD) == SPI_RXFIFOFullThreshold_9) || \
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((THRESHOLD) == SPI_RXFIFOFullThreshold_10) || \
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((THRESHOLD) == SPI_RXFIFOFullThreshold_11) || \
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((THRESHOLD) == SPI_RXFIFOFullThreshold_12) || \
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((THRESHOLD) == SPI_RXFIFOFullThreshold_13) || \
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((THRESHOLD) == SPI_RXFIFOFullThreshold_14) || \
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((THRESHOLD) == SPI_RXFIFOFullThreshold_15) || \
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((THRESHOLD) == SPI_RXFIFOFullThreshold_16))
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/**
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* @}
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*/
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/** @defgroup SPI_TXFIFOEmptyThreshold
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* @{
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*/
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#define SPI_TXFIFOEmptyThreshold_0 ((uint32_t)0x0000)
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#define SPI_TXFIFOEmptyThreshold_1 ((uint32_t)0x0001)
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#define SPI_TXFIFOEmptyThreshold_2 ((uint32_t)0x0002)
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#define SPI_TXFIFOEmptyThreshold_3 ((uint32_t)0x0003)
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#define SPI_TXFIFOEmptyThreshold_4 ((uint32_t)0x0004)
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#define SPI_TXFIFOEmptyThreshold_5 ((uint32_t)0x0005)
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#define SPI_TXFIFOEmptyThreshold_6 ((uint32_t)0x0006)
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#define SPI_TXFIFOEmptyThreshold_7 ((uint32_t)0x0007)
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#define SPI_TXFIFOEmptyThreshold_8 ((uint32_t)0x0008)
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#define SPI_TXFIFOEmptyThreshold_9 ((uint32_t)0x0009)
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#define SPI_TXFIFOEmptyThreshold_10 ((uint32_t)0x000A)
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#define SPI_TXFIFOEmptyThreshold_11 ((uint32_t)0x000B)
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#define SPI_TXFIFOEmptyThreshold_12 ((uint32_t)0x000C)
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#define SPI_TXFIFOEmptyThreshold_13 ((uint32_t)0x000D)
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#define SPI_TXFIFOEmptyThreshold_14 ((uint32_t)0x000E)
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#define SPI_TXFIFOEmptyThreshold_15 ((uint32_t)0x000F)
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#define IS_SPI_TX_FIFO_EMPTY_THRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_TXFIFOEmptyThreshold_0) || \
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((THRESHOLD) == SPI_TXFIFOEmptyThreshold_1) || \
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((THRESHOLD) == SPI_TXFIFOEmptyThreshold_2) || \
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((THRESHOLD) == SPI_TXFIFOEmptyThreshold_3) || \
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((THRESHOLD) == SPI_TXFIFOEmptyThreshold_4) || \
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((THRESHOLD) == SPI_TXFIFOEmptyThreshold_5) || \
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((THRESHOLD) == SPI_TXFIFOEmptyThreshold_6) || \
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((THRESHOLD) == SPI_TXFIFOEmptyThreshold_7) || \
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((THRESHOLD) == SPI_TXFIFOEmptyThreshold_8) || \
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((THRESHOLD) == SPI_TXFIFOEmptyThreshold_9) || \
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((THRESHOLD) == SPI_TXFIFOEmptyThreshold_10) || \
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((THRESHOLD) == SPI_TXFIFOEmptyThreshold_11) || \
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((THRESHOLD) == SPI_TXFIFOEmptyThreshold_12) || \
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((THRESHOLD) == SPI_TXFIFOEmptyThreshold_13) || \
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((THRESHOLD) == SPI_TXFIFOEmptyThreshold_14) || \
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((THRESHOLD) <= SPI_TXFIFOEmptyThreshold_15))
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/**
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* @}
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*/
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/** @defgroup SPI_DMAReceiveLevel
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* @{
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*/
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#define SPI_DMAReceiveLevel_1 ((uint32_t)0x0000)
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#define SPI_DMAReceiveLevel_2 ((uint32_t)0x0001)
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#define SPI_DMAReceiveLevel_3 ((uint32_t)0x0002)
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#define SPI_DMAReceiveLevel_4 ((uint32_t)0x0003)
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#define SPI_DMAReceiveLevel_5 ((uint32_t)0x0004)
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#define SPI_DMAReceiveLevel_6 ((uint32_t)0x0005)
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#define SPI_DMAReceiveLevel_7 ((uint32_t)0x0006)
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#define SPI_DMAReceiveLevel_8 ((uint32_t)0x0007)
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#define SPI_DMAReceiveLevel_9 ((uint32_t)0x0008)
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#define SPI_DMAReceiveLevel_10 ((uint32_t)0x0009)
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#define SPI_DMAReceiveLevel_11 ((uint32_t)0x000A)
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#define SPI_DMAReceiveLevel_12 ((uint32_t)0x000B)
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#define SPI_DMAReceiveLevel_13 ((uint32_t)0x000C)
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#define SPI_DMAReceiveLevel_14 ((uint32_t)0x000D)
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#define SPI_DMAReceiveLevel_15 ((uint32_t)0x000E)
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#define SPI_DMAReceiveLevel_16 ((uint32_t)0x000F)
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#define IS_SPI_DMA_RECEIVE_LEVEL(LEVEL) ((((int32_t)(LEVEL)) >= SPI_DMAReceiveLevel_1) && \
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(((int32_t)(LEVEL)) <= SPI_DMAReceiveLevel_16))
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/**
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* @}
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*/
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/** @defgroup SPI_DMATransmitLevel
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* @{
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*/
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#define SPI_DMATransmitLevel_0 ((uint32_t)0x0000)
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#define SPI_DMATransmitLevel_1 ((uint32_t)0x0001)
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#define SPI_DMATransmitLevel_2 ((uint32_t)0x0002)
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#define SPI_DMATransmitLevel_3 ((uint32_t)0x0003)
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#define SPI_DMATransmitLevel_4 ((uint32_t)0x0004)
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#define SPI_DMATransmitLevel_5 ((uint32_t)0x0005)
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#define SPI_DMATransmitLevel_6 ((uint32_t)0x0006)
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#define SPI_DMATransmitLevel_7 ((uint32_t)0x0007)
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#define SPI_DMATransmitLevel_8 ((uint32_t)0x0008)
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#define SPI_DMATransmitLevel_9 ((uint32_t)0x0009)
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#define SPI_DMATransmitLevel_10 ((uint32_t)0x000A)
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#define SPI_DMATransmitLevel_11 ((uint32_t)0x000B)
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#define SPI_DMATransmitLevel_12 ((uint32_t)0x000C)
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#define SPI_DMATransmitLevel_13 ((uint32_t)0x000D)
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#define SPI_DMATransmitLevel_14 ((uint32_t)0x000E)
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#define SPI_DMATransmitLevel_15 ((uint32_t)0x000F)
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#define IS_SPI_DMA_TRANSMIT_LEVEL(LEVEL) ((((int32_t)(LEVEL)) >= SPI_DMATransmitLevel_0) && \
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(((int32_t)(LEVEL)) <= SPI_DMATransmitLevel_15))
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/**
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* @}
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*/
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/** @defgroup SPI_DMA_transfer_requests
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* @{
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*/
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#define SPI_DMAReq_Rx ((uint32_t)0x0001)
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#define SPI_DMAReq_Tx ((uint32_t)0x0002)
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#define IS_SPI_DMAREQ(DMAREQ) ((((DMAREQ) & (uint32_t)0xFFFC) == (uint32_t)0x00) && \
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((DMAREQ) != (uint32_t)0x00))
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/**
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* @}
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*/
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/** @defgroup SPI_Interrupt Mask and Status Flag
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* @{
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*/
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#define SPI_IT_TXE ((uint32_t)0x0001) //clear by hardware
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#define SPI_IT_TXOVF ((uint32_t)0x0002) //clear by read TXOICR register
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#define SPI_IT_RXF ((uint32_t)0x0010) //clear by hardware
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#define SPI_IT_RXOVF ((uint32_t)0x0008) //clear by read RXOICR register
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#define SPI_IT_RXUDF ((uint32_t)0x0004) //clear by read RXURCR register
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#define SPI_IT_MMC ((uint32_t)0x0020) //clear by read MSTICR register
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#define SPI_IT_All ((uint32_t)0x002E)
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#define IS_SPI_GET_IT(IT) (((IT) == SPI_IT_TXE) || \
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((IT) == SPI_IT_TXOVF) || \
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((IT) == SPI_IT_RXF) || \
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((IT) == SPI_IT_RXUDF) || \
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((IT) == SPI_IT_RXOVF) || \
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((IT) == SPI_IT_MMC))
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#define SPI_FLAG_BSY ((uint32_t)0x0001)
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#define SPI_FLAG_TXNF ((uint32_t)0x0002) //clear by hardware
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#define SPI_FLAG_TXE ((uint32_t)0x0004) //clear by hardware
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#define SPI_FLAG_RXNE ((uint32_t)0x0008) //clear by hardware
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#define SPI_FLAG_RXF ((uint32_t)0x0010) //clear by hardware
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#define SPI_FLAG_TXERR ((uint32_t)0x0020) //read clear
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#define SPI_FLAG_DCERR ((uint32_t)0x0040) //read clear
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#define IS_SPI_GET_FLAG(FLAG) (((FLAG) == SPI_SR_RFNE) || \
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((FLAG) == SPI_SR_RFF) || \
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((FLAG) == SPI_SR_TFE) || \
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((FLAG) == SPI_SR_TFNF) || \
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((FLAG) == SPI_SR_BUSY))
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/**
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* @}
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*/
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/** @defgroup NSM_Direction
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* @{
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*/
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#define NSM_Direction_Data_Transmit ((uint32_t)(0x0001))
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#define NSM_Direction_Data_Receive ((uint32_t)(0x0002))
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#define IS_NSM_DIRECTION_MODE(MODE) (((MODE) == NSM_Direction_Data_Transmit) || \
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((MODE) == NSM_Direction_Data_Receive))
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/**
|
|
* @}
|
|
*/
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|
|
|
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/** @defgroup NSM_TransferMode
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|
* @{
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|
*/
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#define NSM_TransferMode_Non_Sequential ((uint32_t)(0x0001))
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#define NSM_TransferMode_Sequential ((uint32_t)(0x0002))
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|
#define IS_NSM_TRANSFER_MODE(MODE) (((MODE) == NSM_TransferMode_Non_Sequential) || \
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|
((MODE) == NSM_TransferMode_Sequential))
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|
/**
|
|
* @}
|
|
*/
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|
|
|
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/** @defgroup NSM_DataSize
|
|
* @{
|
|
*/
|
|
#define NSM_DataSize_8b ((uint32_t)0x0007)
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|
#define NSM_DataSize_16b ((uint32_t)0x000F)
|
|
#define IS_NSM_DATASIZE(DATASIZE) (((DATASIZE) == NSM_DataSize_8b) || \
|
|
((DATASIZE) == NSM_DataSize_16b))
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
|
|
/** @defgroup NSM_ControlDataSize
|
|
* @{
|
|
*/
|
|
#define NSM_ControlDataSize_8b ((uint32_t)0x0007)
|
|
#define NSM_ControlDataSize_16b ((uint32_t)0x000F)
|
|
#define IS_NSM_CONTROL_DATASIZE(DATASIZE) (((DATASIZE) == NSM_ControlDataSize_8b) || \
|
|
((DATASIZE) == NSM_ControlDataSize_16b))
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
void SPI_DeInit(SPI_TypeDef* SPIx);
|
|
void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
|
|
void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
|
|
void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
|
|
|
void SPI_DMAInit(SPI_TypeDef* SPIx, SPI_DMAInitTypeDef* SPI_DMAInitStruct);
|
|
void SPI_DMAStructInit(SPI_DMAInitTypeDef* SPI_DMAInitStruct);
|
|
void SPI_DMACmd(SPI_TypeDef* SPIx, uint32_t SPI_DMAReq, FunctionalState NewState);
|
|
|
|
void SPI_ITConfig(SPI_TypeDef* SPIx, uint32_t SPI_IT, FunctionalState NewState);
|
|
void SPI_SendData(SPI_TypeDef* SPIx, uint16_t Data);
|
|
uint16_t SPI_ReceiveData(SPI_TypeDef* SPIx);
|
|
void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint32_t SPI_DataSize);
|
|
void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint32_t SPI_Direction);
|
|
|
|
ITStatus SPI_GetITStatus(SPI_TypeDef* SPIx, uint32_t SPI_IT);
|
|
void SPI_ClearITPendingBit(SPI_TypeDef* SPIx, uint32_t SPI_IT);
|
|
|
|
FlagStatus SPI_GetFlagStatus(SPI_TypeDef* SPIx, uint32_t SPI_FLAG);
|
|
uint32_t SPI_GetFlagStatusReg(SPI_TypeDef* SPIx);
|
|
|
|
FlagStatus SPI_IsBusy(SPI_TypeDef* SPIx);
|
|
FlagStatus SPI_IsTXErr(SPI_TypeDef* SPIx);
|
|
FlagStatus SPI_IsDataCollisionErr(SPI_TypeDef* SPIx);
|
|
|
|
void SSP_Init(SPI_TypeDef* SPIx, SSP_InitTypeDef* SSP_InitStruct);
|
|
void SSP_StructInit(SSP_InitTypeDef* SSP_InitStruct);
|
|
|
|
void NSM_Init(SPI_TypeDef* SPIx, NSM_InitTypeDef* NSM_InitStruct);
|
|
void NSM_StructInit(NSM_InitTypeDef* NSM_InitStruct);
|
|
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /*__MSSCPU_SPI_H */
|
|
|
|
|
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/************************** (C) COPYRIGHT Megahunt *****END OF FILE****/
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