168 lines
5.6 KiB
C
168 lines
5.6 KiB
C
#ifndef __RASPI4_H__
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#define __RASPI4_H__
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#include <rthw.h>
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#define __REG32(x) (*((volatile unsigned int *)(x)))
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//base address
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#define PER_BASE (0xFE000000)
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//gpio offset
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#define GPIO_BASE_OFFSET (0x00200000)
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//pl011 offset
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#define PL011_UART_BASE_OFFSET (0x00201000)
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//pactl cs offset
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#define PACTL_CS_OFFSET (0x00204E00)
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//aux offset
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#define AUX_BASE_OFFSET (0x00215000)
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//gpio
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#define GPIO_BASE (PER_BASE + GPIO_BASE_OFFSET)
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#define GPIO_IRQ_NUM (3) //40 pin mode
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#define IRQ_GPIO0 (96 + 49) //bank0 (0 to 27)
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#define IRQ_GPIO1 (96 + 50) //bank1 (28 to 45)
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#define IRQ_GPIO2 (96 + 51) //bank2 (46 to 57)
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#define IRQ_GPIO3 (96 + 52) //bank3
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//system timer
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#define ARM_TIMER_IRQ (64)
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#define ARM_TIMER_BASE (PER_BASE + 0xB000)
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#define ARM_TIMER_LOAD HWREG32(ARM_TIMER_BASE + 0x400)
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#define ARM_TIMER_VALUE HWREG32(ARM_TIMER_BASE + 0x404)
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#define ARM_TIMER_CTRL HWREG32(ARM_TIMER_BASE + 0x408)
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#define ARM_TIMER_IRQCLR HWREG32(ARM_TIMER_BASE + 0x40C)
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#define ARM_TIMER_RAWIRQ HWREG32(ARM_TIMER_BASE + 0x410)
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#define ARM_TIMER_MASKIRQ HWREG32(ARM_TIMER_BASE + 0x414)
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#define ARM_TIMER_RELOAD HWREG32(ARM_TIMER_BASE + 0x418)
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#define ARM_TIMER_PREDIV HWREG32(ARM_TIMER_BASE + 0x41C)
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#define ARM_TIMER_CNTR HWREG32(ARM_TIMER_BASE + 0x420)
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//uart
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#define UART_BASE (PER_BASE + PL011_UART_BASE_OFFSET)
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#define UART0_BASE (UART_BASE + 0x0)
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#define UART2_BASE (UART_BASE + 0x400)
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#define UART3_BASE (UART_BASE + 0x600)
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#define UART4_BASE (UART_BASE + 0x800)
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#define UART5_BASE (UART_BASE + 0xA00)
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#define IRQ_AUX_UART (96 + 29)
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#define UART_REFERENCE_CLOCK (48000000)
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//aux
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#define AUX_BASE (PER_BASE + AUX_BASE_OFFSET)
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#define IRQ_PL011 (96 + 57)
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//pactl cs
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#define PACTL_CS_ADDR (PER_BASE + PACTL_CS_OFFSET)
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#define PACTL_CS HWREG32(PACTL_CS_ADDR)
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typedef enum
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{
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IRQ_SPI0 = 0x00000000,
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IRQ_SPI1 = 0x00000002,
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IRQ_SPI2 = 0x00000004,
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IRQ_SPI3 = 0x00000008,
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IRQ_SPI4 = 0x00000010,
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IRQ_SPI5 = 0x00000020,
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IRQ_SPI6 = 0x00000040,
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IRQ_I2C0 = 0x00000100,
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IRQ_I2C1 = 0x00000200,
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IRQ_I2C2 = 0x00000400,
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IRQ_I2C3 = 0x00000800,
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IRQ_I2C4 = 0x00001000,
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IRQ_I2C5 = 0x00002000,
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IRQ_I2C6 = 0x00004000,
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IRQ_I2C7 = 0x00008000,
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IRQ_UART5 = 0x00010000,
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IRQ_UART4 = 0x00020000,
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IRQ_UART3 = 0x00040000,
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IRQ_UART2 = 0x00080000,
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IRQ_UART0 = 0x00100000
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} PACTL_CS_VAL;
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// 0x40, 0x44, 0x48, 0x4c: Core 0~3 Timers interrupt control
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#define CORE_TIMER_IRQ_CTRL(n) HWREG32((unsigned long)(0xFF800040 + (n) * 4))
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#define TIMER_IRQ 30
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#define NON_SECURE_TIMER_IRQ (1 << 1)
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rt_inline void core_timer_enable(int cpu_id)
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{
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CORE_TIMER_IRQ_CTRL(cpu_id) |= NON_SECURE_TIMER_IRQ;
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}
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//core timer
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#define ST_BASE_OFFSET (0x003000)
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#define STIMER_BASE (PER_BASE + ST_BASE_OFFSET)
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#define STIMER_CS HWREG32(STIMER_BASE + 0x0000)
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#define STIMER_CLO HWREG32(STIMER_BASE + 0x0004)
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#define STIMER_CHI HWREG32(STIMER_BASE + 0x0008)
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#define STIMER_C0 HWREG32(STIMER_BASE + 0x000C)
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#define STIMER_C1 HWREG32(STIMER_BASE + 0x0010)
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#define STIMER_C2 HWREG32(STIMER_BASE + 0x0014)
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#define STIMER_C3 HWREG32(STIMER_BASE + 0x0018)
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#define DELAY_MICROS(micros) \
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do { \
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rt_uint32_t compare = STIMER_CLO + micros * 25; \
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while (STIMER_CLO < compare); \
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} while (0) \
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//mmc
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#define MMC0_BASE_ADDR (PER_BASE + 0x300000)
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#define MMC2_BASE_ADDR (PER_BASE + 0x340000)
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//eth
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#define MAC_BASE_ADDR (0xfd580000)
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#define MAC_REG_BASE_ADDR (void *)(MAC_BASE_ADDR)
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#define ETH_IRQ (160 + 29)
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#define SEND_DATA_NO_CACHE (0x08200000)
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#define RECV_DATA_NO_CACHE (0x08400000)
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//watchdog
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#define WDT_BASE (PER_BASE + 0x00100000)
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#define PM_RSTC HWREG32(WDT_BASE + 0x0000001c)
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#define PM_RSTS HWREG32(WDT_BASE + 0x00000020)
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#define PM_WDOG HWREG32(WDT_BASE + 0x00000024)
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#define PM_PASSWORD (0x5A000000)
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#define PM_WDOG_TIME_SET (0x000fffff)
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#define PM_RSTS_HADWRH_SET (0x00000040)
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#define PM_RSTC_WRCFG_FULL_RESET (0x00000020)
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#define PM_RSTC_WRCFG_CLR (0xffffffcf)
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#define PM_RSTC_RESET (0x00000102)
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//gic max
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#define MAX_HANDLERS (256)
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#define ARM_GIC_NR_IRQS (512)
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#define INTC_BASE (0xff800000)
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#define ARM_GIC_MAX_NR (512)
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#define GIC_V2_BASE (INTC_BASE + 0x00040000)
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#define GIC_V2_DISTRIBUTOR_BASE (INTC_BASE + 0x00041000)
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#define GIC_V2_CPU_INTERFACE_BASE (INTC_BASE + 0x00042000)
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#define GIC_V2_HYPERVISOR_BASE (INTC_BASE + 0x00044000)
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#define GIC_V2_VIRTUAL_CPU_BASE (INTC_BASE + 0x00046000)
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/* ipi interrupt number */
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#define IRQ_ARM_IPI_KICK 0
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#define IRQ_ARM_IPI_CALL 1
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#define GIC_IRQ_START 0
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#define GIC_ACK_INTID_MASK 0x000003ff
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#define GIC_PL400_DISTRIBUTOR_PPTR GIC_V2_DISTRIBUTOR_BASE
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#define GIC_PL400_CONTROLLER_PPTR GIC_V2_CPU_INTERFACE_BASE
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/* the basic constants and interfaces needed by gic */
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rt_inline rt_uint32_t platform_get_gic_dist_base(void)
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{
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return GIC_PL400_DISTRIBUTOR_PPTR;
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}
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rt_inline rt_uint32_t platform_get_gic_cpu_base(void)
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{
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return GIC_PL400_CONTROLLER_PPTR;
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}
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#endif
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