369 lines
9.3 KiB
C
369 lines
9.3 KiB
C
/**************************************************************************//**
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*
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* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-11-11 Wayne First version
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*
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******************************************************************************/
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#include <rthw.h>
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#include <rtthread.h>
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#include "drv_sys.h"
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#include <stdio.h>
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#define LOG_TAG "drv.sys"
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#undef DBG_ENABLE
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#define DBG_SECTION_NAME LOG_TAG
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#define DBG_LEVEL LOG_LVL_DBG
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#define DBG_COLOR
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#include <rtdbg.h>
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#define DEF_RAISING_CPU_FREQUENCY
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//Dont enable #define DEF_RAISING_CPU_VOLTAGE
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void machine_shutdown(void)
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{
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rt_kprintf("machine_shutdown...\n");
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rt_hw_interrupt_disable();
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/* Unlock */
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SYS_UnlockReg();
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while (1);
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}
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void machine_reset(void)
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{
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rt_kprintf("machine_reset...\n");
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rt_hw_interrupt_disable();
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/* Unlock */
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SYS_UnlockReg();
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SYS->IPRST0 = SYS_IPRST0_CHIPRST_Msk;
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SYS->IPRST0 = 0;
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while (1);
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}
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int reboot(int argc, char **argv)
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{
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machine_reset();
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return 0;
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}
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MSH_CMD_EXPORT(reboot, Reboot System);
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void nu_sys_ip_reset(uint32_t u32ModuleIndex)
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{
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SYS_ResetModule(u32ModuleIndex);
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}
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E_SYS_USB0_ID nu_sys_usb0_role(void)
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{
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#if 0
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/* Check Role on USB0 dual-role port. */
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/*
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[17] USB0_IDS
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USB0_ID Status
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0 = USB port 0 used as a USB device port.
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1 = USB port 0 used as a USB host port.
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*/
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return ((inpw(REG_SYS_MISCISR) & (1 << 17)) > 0) ? USB0_ID_HOST : USB0_ID_DEVICE;
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#else
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return USB0_ID_DEVICE;
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#endif
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}
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void nu_sys_check_register(S_NU_REG *psNuReg)
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{
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if (psNuReg == RT_NULL)
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return;
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while (psNuReg->vu32RegAddr != 0)
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{
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vu32 vc32RegValue = *((vu32 *)psNuReg->vu32RegAddr);
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vu32 vc32BMValue = vc32RegValue & psNuReg->vu32BitMask;
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LOG_I("[%3s] %32s(0x%08x) %24s(0x%08x): 0x%08x(AndBitMask:0x%08x)\n",
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(psNuReg->vu32Value == vc32BMValue) ? "Ok" : "!OK",
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psNuReg->szVName,
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psNuReg->vu32Value,
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psNuReg->szRegName,
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psNuReg->vu32RegAddr,
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vc32RegValue,
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vc32BMValue);
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psNuReg++;
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}
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}
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static int nu_tempsen_init()
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{
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SYS->TSENSRFCR &= ~SYS_TSENSRFCR_PD_Msk; // Disable power down, don't wait, takes double conv time (350ms * 2)
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return 0;
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}
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static int nu_tempsen_get_value()
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{
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char sztmp[32];
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double temp;
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static rt_tick_t _old_tick = 0;
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static int32_t count = 0;
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_old_tick = rt_tick_get();
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// Wait valid bit set
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while ((SYS->TSENSRFCR & SYS_TSENSRFCR_DATAVALID_Msk) == 0)
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{
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// 700 ms after clear pd bit. other conversion takes 350 ms
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if (rt_tick_get() > (500 + _old_tick))
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{
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return -1;
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}
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}
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if (++count == 8)
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{
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count = 0;
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temp = (double)((SYS->TSENSRFCR & 0x0FFF0000) >> 16) * 274.3531 / 4096.0 - 93.3332;
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snprintf(sztmp, sizeof(sztmp), "Temperature: %.1f\n", temp);
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LOG_I("%s", sztmp);
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}
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// Clear Valid bit
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SYS->TSENSRFCR = SYS_TSENSRFCR_DATAVALID_Msk;
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return 0;
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}
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void nu_tempsen_hook(void)
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{
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nu_tempsen_get_value();
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}
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static int nu_tempsen_go(void)
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{
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rt_err_t err = rt_thread_idle_sethook(nu_tempsen_hook);
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if (err != RT_EOK)
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{
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LOG_E("set %s idle hook failed!\n", __func__);
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return -1;
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}
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nu_tempsen_init();
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return 0;
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}
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//INIT_APP_EXPORT(nu_tempsen_go);
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MSH_CMD_EXPORT(nu_tempsen_go, go tempsen);
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#define REG_SYS_CHIPCFG (SYS_BASE + 0x1F4)
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uint32_t nu_chipcfg_ddrsize(void)
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{
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uint32_t u32ChipCfg = *((vu32 *)REG_SYS_CHIPCFG);
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return ((u32ChipCfg & 0xF0000) != 0) ? (1 << ((u32ChipCfg & 0xF0000) >> 16)) << 20 : 0;
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}
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void nu_chipcfg_dump(void)
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{
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uint32_t u32ChipCfg = *((vu32 *)REG_SYS_CHIPCFG);
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uint32_t u32ChipCfg_DDRSize = ((u32ChipCfg & 0xF0000) != 0) ? 1 << ((u32ChipCfg & 0xF0000) >> 16) : 0;
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uint32_t u32ChipCfg_DDRType = ((u32ChipCfg & 0x8000) >> 15);
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LOG_I("CHIPCFG: 0x%08x ", u32ChipCfg);
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LOG_I("DDR SDRAM Size: %d MB", u32ChipCfg_DDRSize);
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LOG_I("MCP DDR TYPE: %s", u32ChipCfg_DDRSize ? (u32ChipCfg_DDRType ? "DDR2" : "DDR3/3L") : "Unknown");
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}
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void nu_clock_dump(void)
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{
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LOG_I("HXT: %d Hz", CLK_GetHXTFreq());
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LOG_I("LXT: %d Hz", CLK_GetLXTFreq());
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LOG_I("CAPLL: %d Hz(OpMode=%d)", CLK_GetPLLClockFreq(CAPLL), CLK_GetPLLOpMode(CAPLL));
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LOG_I("DDRPLL: %d Hz(OpMode=%d)", CLK_GetPLLClockFreq(DDRPLL), CLK_GetPLLOpMode(DDRPLL));
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LOG_I("APLL: %d Hz(OpMode=%d)", CLK_GetPLLClockFreq(APLL), CLK_GetPLLOpMode(APLL));
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LOG_I("EPLL: %d Hz(OpMode=%d)", CLK_GetPLLClockFreq(EPLL), CLK_GetPLLOpMode(EPLL));
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LOG_I("VPLL: %d Hz(OpMode=%d)", CLK_GetPLLClockFreq(VPLL), CLK_GetPLLOpMode(VPLL));
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LOG_I("M4-CPU: %d Hz", CLK_GetCPUFreq());
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LOG_I("SYSCLK0: %d Hz", CLK_GetSYSCLK0Freq());
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LOG_I("SYSCLK1: %d Hz", CLK_GetSYSCLK1Freq());
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LOG_I("HCLK0: %d Hz", CLK_GetHCLK0Freq());
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LOG_I("HCLK1: %d Hz", CLK_GetHCLK1Freq());
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LOG_I("HCLK2: %d Hz", CLK_GetHCLK2Freq());
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LOG_I("HCLK3: %d Hz", CLK_GetHCLK3Freq());
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LOG_I("PCLK0: %d Hz", CLK_GetPCLK0Freq());
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LOG_I("PCLK1: %d Hz", CLK_GetPCLK1Freq());
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LOG_I("PCLK2: %d Hz", CLK_GetPCLK2Freq());
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LOG_I("PCLK3: %d Hz", CLK_GetPCLK3Freq());
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LOG_I("PCLK4: %d Hz", CLK_GetPCLK4Freq());
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}
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static const char *szClockName [] =
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{
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"HXT",
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"LXT",
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"N/A",
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"LIRC",
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"HIRC",
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"N/A",
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"CAPLL",
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"N/A",
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"DDRPLL",
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"EPLL",
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"APLL",
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"VPLL"
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};
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#define CLOCKNAME_SIZE (sizeof(szClockName)/sizeof(char*))
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void nu_clock_isready(void)
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{
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uint32_t u32IsReady, i;
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for (i = 0; i < CLOCKNAME_SIZE; i++)
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{
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if (i == 5 || i == 7 || i == 2) continue;
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u32IsReady = CLK_WaitClockReady(1 << i);
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LOG_I("%s: %s\n", szClockName[i], (u32IsReady == 1) ? "[Stable]" : "[Unstable]");
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}
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}
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extern uint32_t ma35d1_set_cpu_voltage(uint32_t sys_clk, uint32_t u32Vol);
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void nu_clock_raise(void)
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{
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uint32_t u32PllRefClk;
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/* Unlock protected registers */
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SYS_UnlockReg();
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/* Enable HXT, LXT */
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CLK->PWRCTL |= (CLK_PWRCTL_HXTEN_Msk | CLK_PWRCTL_HIRCEN_Msk);
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if (CLK->STATUS & CLK_STATUS_HXTSTB_Msk) // Check Ready
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{
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u32PllRefClk = __HXT;
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}
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else if (CLK->STATUS & CLK_STATUS_HIRCSTB_Msk) // Check Ready
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{
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u32PllRefClk = __HIRC; // HXT_CHECK_FAIL
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}
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else
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{
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return;
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}
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CLK_SetPLLFreq(VPLL, PLL_OPMODE_INTEGER, u32PllRefClk, 102000000ul);
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CLK_SetPLLFreq(APLL, PLL_OPMODE_INTEGER, u32PllRefClk, 144000000ul);
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CLK_SetPLLFreq(EPLL, PLL_OPMODE_INTEGER, u32PllRefClk, 500000000ul);
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/* Waiting clock ready */
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CLK_WaitClockReady(CLK_STATUS_VPLLSTB_Msk | CLK_STATUS_APLLSTB_Msk | CLK_STATUS_EPLLSTB_Msk);
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#if defined(DEF_RAISING_CPU_FREQUENCY)
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/* Switch clock source of CA35 to DDRPLL before raising CA-PLL */
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CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_CA35CKSEL_Msk)) | CLK_CLKSEL0_CA35CKSEL_DDRPLL;
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#if defined(DEF_RAISING_CPU_VOLTAGE)
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if (ma35d1_set_cpu_voltage(CLK_GetPLLClockFreq(SYSPLL), 0x68))
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{
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CLK_SetPLLFreq(CAPLL, PLL_OPMODE_INTEGER, u32PllRefClk, 1000000000ul);
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}
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else
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#endif
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{
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#if defined(DEF_RAISING_CPU_VOLTAGE)
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ma35d1_set_cpu_voltage(CLK_GetPLLClockFreq(SYSPLL), 0x5F);
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#endif
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CLK_SetPLLFreq(CAPLL, PLL_OPMODE_INTEGER, u32PllRefClk, 800000000ul);
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}
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/* Waiting clock ready */
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CLK_WaitClockReady(CLK_STATUS_CAPLLSTB_Msk);
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/* Switch clock source of CA35 to CA-PLL after raising */
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CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_CA35CKSEL_Msk)) | CLK_CLKSEL0_CA35CKSEL_CAPLL;
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#endif
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}
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#ifdef FINSH_USING_MSH
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MSH_CMD_EXPORT(nu_clock_dump, Dump all clocks);
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MSH_CMD_EXPORT(nu_clock_raise, Raise clock);
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MSH_CMD_EXPORT(nu_clock_isready, Check PLL clocks);
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#endif
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void devmem(int argc, char *argv[])
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{
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volatile unsigned int u32Addr;
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unsigned int value = 0, mode = 0;
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if (argc < 2 || argc > 3)
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{
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goto exit_devmem;
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}
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if (argc == 3)
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{
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if (sscanf(argv[2], "0x%x", &value) != 1)
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goto exit_devmem;
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mode = 1; //Write
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}
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if (sscanf(argv[1], "0x%x", &u32Addr) != 1)
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goto exit_devmem;
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else if (u32Addr & (4 - 1))
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goto exit_devmem;
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if (mode)
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{
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*((volatile uint32_t *)u32Addr) = value;
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}
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LOG_I("0x%08x\n", *((volatile uint32_t *)u32Addr));
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return;
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exit_devmem:
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rt_kprintf("Read: devmem <physical address in hex>\n");
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rt_kprintf("Write: devmem <physical address in hex> <value in hex format>\n");
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return;
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}
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MSH_CMD_EXPORT(devmem, dump device registers);
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void devmem2(int argc, char *argv[])
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{
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volatile unsigned int u32Addr;
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unsigned int value = 0, word_count = 1;
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if (argc < 2 || argc > 3)
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{
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goto exit_devmem;
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}
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if (argc == 3)
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{
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if (sscanf(argv[2], "%d", &value) != 1)
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goto exit_devmem;
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word_count = value;
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}
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if (sscanf(argv[1], "0x%x", &u32Addr) != 1)
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goto exit_devmem;
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else if (u32Addr & (4 - 1))
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goto exit_devmem;
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if (word_count > 0)
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{
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LOG_HEX("devmem", 16, (void *)u32Addr, word_count * sizeof(rt_base_t));
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}
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return;
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exit_devmem:
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rt_kprintf("devmem2: <physical address in hex> <count in dec>\n");
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return;
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}
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MSH_CMD_EXPORT(devmem2, dump device registers);
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