651 lines
19 KiB
C
651 lines
19 KiB
C
/*
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* Copyright (c) 2006-2020, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-10-27 bigmagic first version
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*/
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#include "mbox.h"
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#include "raspi4.h"
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#include "drv_sdio.h"
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static rt_uint32_t mmc_base_clock = 0;
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static rt_uint32_t sdCommandTable[] = {
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SD_CMD_INDEX(0),
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SD_CMD_RESERVED(1),
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SD_CMD_INDEX(2) | SD_RESP_R2,
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SD_CMD_INDEX(3) | SD_RESP_R1,
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SD_CMD_INDEX(4),
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SD_CMD_RESERVED(5), //SD_CMD_INDEX(5) | SD_RESP_R4,
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SD_CMD_INDEX(6) | SD_RESP_R1,
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SD_CMD_INDEX(7) | SD_RESP_R1b,
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SD_CMD_INDEX(8) | SD_RESP_R1,
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SD_CMD_INDEX(9) | SD_RESP_R2,
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SD_CMD_INDEX(10) | SD_RESP_R2,
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SD_CMD_INDEX(11) | SD_RESP_R1,
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SD_CMD_INDEX(12) | SD_RESP_R1b | SD_CMD_TYPE_ABORT,
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SD_CMD_INDEX(13) | SD_RESP_R1,
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SD_CMD_RESERVED(14),
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SD_CMD_INDEX(15),
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SD_CMD_INDEX(16) | SD_RESP_R1,
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SD_CMD_INDEX(17) | SD_RESP_R1 | SD_DATA_READ,
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SD_CMD_INDEX(18) | SD_RESP_R1 | SD_DATA_READ | SD_CMD_MULTI_BLOCK | SD_CMD_BLKCNT_EN,
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SD_CMD_INDEX(19) | SD_RESP_R1 | SD_DATA_READ,
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SD_CMD_INDEX(20) | SD_RESP_R1b,
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SD_CMD_RESERVED(21),
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SD_CMD_RESERVED(22),
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SD_CMD_INDEX(23) | SD_RESP_R1,
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SD_CMD_INDEX(24) | SD_RESP_R1 | SD_DATA_WRITE,
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SD_CMD_INDEX(25) | SD_RESP_R1 | SD_DATA_WRITE | SD_CMD_MULTI_BLOCK | SD_CMD_BLKCNT_EN,
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SD_CMD_INDEX(26) | SD_RESP_R1 | SD_DATA_WRITE, //add
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SD_CMD_INDEX(27) | SD_RESP_R1 | SD_DATA_WRITE,
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SD_CMD_INDEX(28) | SD_RESP_R1b,
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SD_CMD_INDEX(29) | SD_RESP_R1b,
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SD_CMD_INDEX(30) | SD_RESP_R1 | SD_DATA_READ,
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SD_CMD_RESERVED(31),
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SD_CMD_INDEX(32) | SD_RESP_R1,
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SD_CMD_INDEX(33) | SD_RESP_R1,
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SD_CMD_RESERVED(34),
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SD_CMD_INDEX(35) | SD_RESP_R1, //add
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SD_CMD_INDEX(36) | SD_RESP_R1, //add
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SD_CMD_RESERVED(37),
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SD_CMD_INDEX(38) | SD_RESP_R1b,
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SD_CMD_INDEX(39) | SD_RESP_R4, //add
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SD_CMD_INDEX(40) | SD_RESP_R5, //add
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SD_CMD_INDEX(41) | SD_RESP_R3, //add, mov from harbote
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SD_CMD_RESERVED(42) | SD_RESP_R1,
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SD_CMD_RESERVED(43),
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SD_CMD_RESERVED(44),
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SD_CMD_RESERVED(45),
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SD_CMD_RESERVED(46),
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SD_CMD_RESERVED(47),
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SD_CMD_RESERVED(48),
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SD_CMD_RESERVED(49),
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SD_CMD_RESERVED(50),
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SD_CMD_INDEX(51) | SD_RESP_R1 | SD_DATA_READ,
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SD_CMD_RESERVED(52),
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SD_CMD_RESERVED(53),
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SD_CMD_RESERVED(54),
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SD_CMD_INDEX(55) | SD_RESP_R3,
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SD_CMD_INDEX(56) | SD_RESP_R1 | SD_CMD_ISDATA,
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SD_CMD_RESERVED(57),
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SD_CMD_RESERVED(58),
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SD_CMD_RESERVED(59),
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SD_CMD_RESERVED(60),
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SD_CMD_RESERVED(61),
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SD_CMD_RESERVED(62),
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SD_CMD_RESERVED(63)
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};
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static inline rt_uint32_t read32(rt_uint32_t addr)
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{
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return (*((volatile unsigned int*)(addr)));
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}
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static inline void write32(rt_uint32_t addr, rt_uint32_t value)
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{
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(*((volatile unsigned int*)(addr))) = value;
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}
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rt_err_t sd_int(struct sdhci_pdata_t * pdat, rt_uint32_t mask)
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{
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rt_uint32_t r;
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rt_uint32_t m = mask | INT_ERROR_MASK;
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int cnt = 1000000;
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while (!(read32(pdat->virt + EMMC_INTERRUPT) & (m | INT_ERROR_MASK)) && cnt--)
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DELAY_MICROS(1);
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r = read32(pdat->virt + EMMC_INTERRUPT);
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if (cnt <= 0 || (r & INT_CMD_TIMEOUT) || (r & INT_DATA_TIMEOUT))
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{
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write32(pdat->virt + EMMC_INTERRUPT, r);
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//qemu maybe can not use sdcard
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rt_kprintf("send cmd/data timeout wait for %x int: %x, status: %x\n",mask, r, read32(pdat->virt + EMMC_STATUS));
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return -RT_ETIMEOUT;
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}
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else if (r & INT_ERROR_MASK)
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{
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write32(pdat->virt + EMMC_INTERRUPT, r);
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rt_kprintf("send cmd/data error %x -> %x\n",r, read32(pdat->virt + EMMC_INTERRUPT));
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return -RT_ERROR;
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}
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write32(pdat->virt + EMMC_INTERRUPT, mask);
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return RT_EOK;
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}
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rt_err_t sd_status(struct sdhci_pdata_t * pdat, unsigned int mask)
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{
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int cnt = 500000;
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while ((read32(pdat->virt + EMMC_STATUS) & mask) && !(read32(pdat->virt + EMMC_INTERRUPT) & INT_ERROR_MASK) && cnt--)
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DELAY_MICROS(1);
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if (cnt <= 0)
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{
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return -RT_ETIMEOUT;
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}
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else if (read32(pdat->virt + EMMC_INTERRUPT) & INT_ERROR_MASK)
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{
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return -RT_ERROR;
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}
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return RT_EOK;
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}
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static rt_err_t raspi_transfer_command(struct sdhci_pdata_t * pdat, struct sdhci_cmd_t * cmd)
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{
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rt_uint32_t cmdidx;
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rt_err_t ret = RT_EOK;
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ret = sd_status(pdat, SR_CMD_INHIBIT);
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if (ret)
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{
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rt_kprintf("ERROR: EMMC busy %d\n", ret);
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return ret;
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}
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cmdidx = sdCommandTable[cmd->cmdidx];
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if (cmdidx == 0xFFFFFFFF)
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return -RT_EINVAL;
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if (cmd->datarw == DATA_READ)
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cmdidx |= SD_DATA_READ;
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if (cmd->datarw == DATA_WRITE)
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cmdidx |= SD_DATA_WRITE;
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mmcsd_dbg("transfer cmd %x(%d) %x %x\n", cmdidx, cmd->cmdidx, cmd->cmdarg, read32(pdat->virt + EMMC_INTERRUPT));
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write32(pdat->virt + EMMC_INTERRUPT,read32(pdat->virt + EMMC_INTERRUPT));
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write32(pdat->virt + EMMC_ARG1, cmd->cmdarg);
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write32(pdat->virt + EMMC_CMDTM, cmdidx);
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if (cmd->cmdidx == SD_APP_OP_COND)
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DELAY_MICROS(1000);
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else if ((cmd->cmdidx == SD_SEND_IF_COND) || (cmd->cmdidx == APP_CMD))
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DELAY_MICROS(100);
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ret = sd_int(pdat, INT_CMD_DONE);
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if (ret)
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{
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return ret;
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}
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if (cmd->resptype & RESP_MASK)
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{
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if (cmd->resptype & RESP_R2)
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{
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rt_uint32_t resp[4];
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resp[0] = read32(pdat->virt + EMMC_RESP0);
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resp[1] = read32(pdat->virt + EMMC_RESP1);
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resp[2] = read32(pdat->virt + EMMC_RESP2);
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resp[3] = read32(pdat->virt + EMMC_RESP3);
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if (cmd->resptype == RESP_R2)
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{
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cmd->response[0] = resp[3]<<8 |((resp[2]>>24)&0xff);
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cmd->response[1] = resp[2]<<8 |((resp[1]>>24)&0xff);
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cmd->response[2] = resp[1]<<8 |((resp[0]>>24)&0xff);
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cmd->response[3] = resp[0]<<8 ;
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}
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else
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{
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cmd->response[0] = resp[0];
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cmd->response[1] = resp[1];
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cmd->response[2] = resp[2];
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cmd->response[3] = resp[3];
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}
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}
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else
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cmd->response[0] = read32(pdat->virt + EMMC_RESP0);
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}
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mmcsd_dbg("response: %x: %x %x %x %x (%x, %x)\n", cmd->resptype, cmd->response[0], cmd->response[1], cmd->response[2], cmd->response[3], read32(pdat->virt + EMMC_STATUS),read32(pdat->virt + EMMC_INTERRUPT));
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return ret;
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}
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static rt_err_t read_bytes(struct sdhci_pdata_t * pdat, rt_uint32_t * buf, rt_uint32_t blkcount, rt_uint32_t blksize)
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{
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int c = 0;
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rt_err_t ret;
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int d;
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while (c < blkcount)
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{
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if ((ret = sd_int(pdat, INT_READ_RDY)))
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{
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rt_kprintf("timeout happens when reading block %d\n",c);
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return ret;
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}
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for (d=0; d < blksize / 4; d++)
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if (read32(pdat->virt + EMMC_STATUS) & SR_READ_AVAILABLE)
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buf[d] = read32(pdat->virt + EMMC_DATA);
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c++;
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buf += blksize / 4;
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}
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return RT_EOK;
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}
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static rt_err_t write_bytes(struct sdhci_pdata_t * pdat, rt_uint32_t * buf, rt_uint32_t blkcount, rt_uint32_t blksize)
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{
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int c = 0;
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rt_err_t ret;
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int d;
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while (c < blkcount)
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{
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if ((ret = sd_int(pdat, INT_WRITE_RDY)))
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{
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return ret;
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}
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for (d=0; d < blksize / 4; d++)
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write32(pdat->virt + EMMC_DATA, buf[d]);
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c++;
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buf += blksize / 4;
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}
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if ((ret = sd_int(pdat, INT_DATA_DONE)))
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{
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return ret;
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}
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return RT_EOK;
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}
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static rt_err_t raspi_transfer_data(struct sdhci_pdata_t * pdat, struct sdhci_cmd_t * cmd, struct sdhci_data_t * dat)
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{
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rt_uint32_t dlen = (rt_uint32_t)(dat->blkcnt * dat->blksz);
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rt_err_t ret = sd_status(pdat, SR_DAT_INHIBIT);
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if (ret)
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{
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rt_kprintf("ERROR: EMMC busy\n");
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return ret;
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}
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if (dat->blkcnt > 1)
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{
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struct sdhci_cmd_t newcmd;
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newcmd.cmdidx = SET_BLOCK_COUNT;
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newcmd.cmdarg = dat->blkcnt;
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newcmd.resptype = RESP_R1;
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ret = raspi_transfer_command(pdat, &newcmd);
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if (ret) return ret;
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}
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if(dlen < 512)
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{
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write32(pdat->virt + EMMC_BLKSIZECNT, dlen | 1 << 16);
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}
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else
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{
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write32(pdat->virt + EMMC_BLKSIZECNT, 512 | (dat->blkcnt) << 16);
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}
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if (dat->flag & DATA_DIR_READ)
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{
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cmd->datarw = DATA_READ;
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ret = raspi_transfer_command(pdat, cmd);
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if (ret) return ret;
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mmcsd_dbg("read_block %d, %d\n", dat->blkcnt, dat->blksz );
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ret = read_bytes(pdat, (rt_uint32_t *)dat->buf, dat->blkcnt, dat->blksz);
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}
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else if (dat->flag & DATA_DIR_WRITE)
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{
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cmd->datarw = DATA_WRITE;
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ret = raspi_transfer_command(pdat, cmd);
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if (ret) return ret;
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mmcsd_dbg("write_block %d, %d", dat->blkcnt, dat->blksz );
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ret = write_bytes(pdat, (rt_uint32_t *)dat->buf, dat->blkcnt, dat->blksz);
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}
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return ret;
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}
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static rt_err_t sdhci_transfer(struct sdhci_t * sdhci, struct sdhci_cmd_t * cmd, struct sdhci_data_t * dat)
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{
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struct sdhci_pdata_t * pdat = (struct sdhci_pdata_t *)sdhci->priv;
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if (!dat)
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return raspi_transfer_command(pdat, cmd);
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return raspi_transfer_data(pdat, cmd, dat);
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}
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static void mmc_request_send(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
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{
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struct sdhci_t *sdhci = (struct sdhci_t *)host->private_data;
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struct sdhci_cmd_t cmd;
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struct sdhci_cmd_t stop;
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struct sdhci_data_t dat;
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rt_memset(&cmd, 0, sizeof(struct sdhci_cmd_t));
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rt_memset(&stop, 0, sizeof(struct sdhci_cmd_t));
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rt_memset(&dat, 0, sizeof(struct sdhci_data_t));
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cmd.cmdidx = req->cmd->cmd_code;
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cmd.cmdarg = req->cmd->arg;
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cmd.resptype =resp_type(req->cmd);
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if (req->data)
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{
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dat.buf = (rt_uint8_t *)req->data->buf;
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dat.flag = req->data->flags;
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dat.blksz = req->data->blksize;
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dat.blkcnt = req->data->blks;
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req->cmd->err = sdhci_transfer(sdhci, &cmd, &dat);
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}
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else
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{
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req->cmd->err = sdhci_transfer(sdhci, &cmd, RT_NULL);
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}
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req->cmd->resp[3] = cmd.response[3];
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req->cmd->resp[2] = cmd.response[2];
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req->cmd->resp[1] = cmd.response[1];
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req->cmd->resp[0] = cmd.response[0];
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if (req->stop)
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{
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stop.cmdidx = req->stop->cmd_code;
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stop.cmdarg = req->stop->arg;
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cmd.resptype =resp_type(req->stop);
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req->stop->err = sdhci_transfer(sdhci, &stop, RT_NULL);
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}
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mmcsd_req_complete(host);
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}
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rt_int32_t mmc_card_status(struct rt_mmcsd_host *host)
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{
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return 0;
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}
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static rt_err_t sdhci_detect(struct sdhci_t * sdhci)
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{
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return RT_EOK;
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}
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static rt_err_t sdhci_setwidth(struct sdhci_t * sdhci, rt_uint32_t width)
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{
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rt_uint32_t temp = 0;
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struct sdhci_pdata_t * pdat = (struct sdhci_pdata_t *)sdhci->priv;
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if (width == MMCSD_BUS_WIDTH_4)
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{
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temp = read32((pdat->virt + EMMC_CONTROL0));
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temp |= C0_HCTL_HS_EN;
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temp |= C0_HCTL_DWITDH; // always use 4 data lines:
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write32((pdat->virt + EMMC_CONTROL0), temp);
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}
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return RT_EOK;
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}
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static uint32_t sd_get_clock_divider(rt_uint32_t sdHostVer ,rt_uint32_t base_clock, rt_uint32_t target_rate)
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{
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rt_uint32_t targetted_divisor = 0;
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rt_uint32_t freq_select = 0;
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rt_uint32_t upper_bits = 0;
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rt_uint32_t ret = 0;
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if(target_rate > base_clock)
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targetted_divisor = 1;
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else
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{
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targetted_divisor = base_clock / target_rate;
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rt_uint32_t mod = base_clock % target_rate;
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if(mod)
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targetted_divisor--;
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}
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// Decide on the clock mode to use
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// Currently only 10-bit divided clock mode is supported
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// HCI version 3 or greater supports 10-bit divided clock mode
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// This requires a power-of-two divider
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// Find the first bit set
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int divisor = -1;
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for(int first_bit = 31; first_bit >= 0; first_bit--)
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{
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rt_uint32_t bit_test = (1 << first_bit);
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if(targetted_divisor & bit_test)
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{
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divisor = first_bit;
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targetted_divisor &= ~bit_test;
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if(targetted_divisor)
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{
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// The divisor is not a power-of-two, increase it
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divisor++;
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}
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break;
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}
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}
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if(divisor == -1)
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divisor = 31;
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if(divisor >= 32)
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divisor = 31;
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if(divisor != 0)
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divisor = (1 << (divisor - 1));
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if(divisor >= 0x400)
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divisor = 0x3ff;
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freq_select = divisor & 0xff;
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upper_bits = (divisor >> 8) & 0x3;
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ret = (freq_select << 8) | (upper_bits << 6) | (0 << 5);
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return ret;
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}
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static rt_err_t sdhci_setclock(struct sdhci_t * sdhci, rt_uint32_t clock)
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{
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rt_uint32_t temp = 0;
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rt_uint32_t sdHostVer = 0;
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int count = 100000;
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struct sdhci_pdata_t * pdat = (struct sdhci_pdata_t *)(sdhci->priv);
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while ((read32(pdat->virt + EMMC_STATUS) & (SR_CMD_INHIBIT | SR_DAT_INHIBIT)) && (--count))
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DELAY_MICROS(1);
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if (count <= 0)
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{
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rt_kprintf("EMMC: Set clock: timeout waiting for inhibit flags. Status %08x.\n",read32(pdat->virt + EMMC_STATUS));
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return RT_ERROR;
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}
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// Switch clock off.
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temp = read32((pdat->virt + EMMC_CONTROL1));
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temp &= ~C1_CLK_EN;
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write32((pdat->virt + EMMC_CONTROL1),temp);
|
|
DELAY_MICROS(10);
|
|
// Request the new clock setting and enable the clock
|
|
temp = read32(pdat->virt + EMMC_SLOTISR_VER);
|
|
sdHostVer = (temp & HOST_SPEC_NUM) >> HOST_SPEC_NUM_SHIFT;
|
|
int cdiv = sd_get_clock_divider(sdHostVer, mmc_base_clock, clock);
|
|
temp = read32((pdat->virt + EMMC_CONTROL1));
|
|
temp |= 1;
|
|
temp |= cdiv;
|
|
temp |= (7 << 16);
|
|
|
|
temp = (temp & 0xffff003f) | cdiv;
|
|
write32((pdat->virt + EMMC_CONTROL1),temp);
|
|
DELAY_MICROS(10);
|
|
|
|
// Enable the clock.
|
|
temp = read32(pdat->virt + EMMC_CONTROL1);
|
|
temp |= C1_CLK_EN;
|
|
write32((pdat->virt + EMMC_CONTROL1),temp);
|
|
DELAY_MICROS(10);
|
|
|
|
// Wait for clock to be stable.
|
|
count = 10000;
|
|
while (!(read32(pdat->virt + EMMC_CONTROL1) & C1_CLK_STABLE) && count--)
|
|
DELAY_MICROS(10);
|
|
if (count <= 0)
|
|
{
|
|
rt_kprintf("EMMC: ERROR: failed to get stable clock %d.\n", clock);
|
|
return RT_ERROR;
|
|
}
|
|
|
|
mmcsd_dbg("set stable clock %d.\n", clock);
|
|
return RT_EOK;
|
|
}
|
|
|
|
static void mmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
|
|
{
|
|
struct sdhci_t * sdhci = (struct sdhci_t *)host->private_data;
|
|
sdhci_setclock(sdhci, io_cfg->clock);
|
|
sdhci_setwidth(sdhci, io_cfg->bus_width);
|
|
}
|
|
|
|
static const struct rt_mmcsd_host_ops ops =
|
|
{
|
|
mmc_request_send,
|
|
mmc_set_iocfg,
|
|
RT_NULL,
|
|
RT_NULL,
|
|
};
|
|
|
|
static rt_err_t reset_emmc(struct sdhci_pdata_t * pdat)
|
|
{
|
|
rt_uint32_t control1;
|
|
|
|
//Reset the controller
|
|
control1 = read32((pdat->virt + EMMC_CONTROL1));
|
|
control1 |= (1 << 24);
|
|
// Disable clock
|
|
control1 &= ~(1 << 2);
|
|
control1 &= ~(1 << 0);
|
|
//temp |= C1_CLK_INTLEN | C1_TOUNIT_MAX;
|
|
write32((pdat->virt + EMMC_CONTROL1),control1);
|
|
int cnt = 10000;
|
|
do
|
|
{
|
|
DELAY_MICROS(10);
|
|
cnt = cnt - 1;
|
|
if(cnt == 0)
|
|
{
|
|
break;
|
|
}
|
|
} while ((read32(pdat->virt + EMMC_CONTROL1) & (0x7 << 24)) != 0);
|
|
|
|
// Enable SD Bus Power VDD1 at 3.3V
|
|
rt_uint32_t control0 = read32(pdat->virt + EMMC_CONTROL0);
|
|
control0 |= 0x0F << 8;
|
|
write32(pdat->virt + EMMC_CONTROL0, control0);
|
|
|
|
rt_thread_delay(100);
|
|
//usleep(2000);
|
|
|
|
|
|
// Check for a valid card
|
|
mmcsd_dbg("EMMC: checking for an inserted card\n");
|
|
cnt = 10000;
|
|
do
|
|
{
|
|
DELAY_MICROS(10);
|
|
cnt = cnt - 1;
|
|
if(cnt == 0)
|
|
{
|
|
break;
|
|
}
|
|
} while ((read32(pdat->virt + EMMC_STATUS) & (0x1 << 16)) == 0);
|
|
|
|
rt_uint32_t status_reg = read32(pdat->virt + EMMC_STATUS);
|
|
|
|
if((status_reg & (1 << 16)) == 0)
|
|
{
|
|
rt_kprintf("EMMC: no card inserted\n");
|
|
return -1;
|
|
}
|
|
else
|
|
{
|
|
mmcsd_dbg("EMMC: status: %08x\n", status_reg);
|
|
}
|
|
|
|
// Clear control2
|
|
write32(pdat->virt + EMMC_CONTROL2, 0);
|
|
// Get the base clock rate //12
|
|
mmc_base_clock = bcm271x_mbox_clock_get_rate(EMMC_CLK_ID);
|
|
if(mmc_base_clock == 0)
|
|
{
|
|
rt_kprintf("EMMC: assuming clock rate to be 100MHz\n");
|
|
mmc_base_clock = 100000000;
|
|
}
|
|
mmcsd_dbg("EMMC: setting clock rate is %d\n", mmc_base_clock);
|
|
return RT_EOK;
|
|
}
|
|
|
|
#ifdef RT_MMCSD_DBG
|
|
void dump_registers(struct sdhci_pdata_t * pdat)
|
|
{
|
|
rt_kprintf("EMMC registers:");
|
|
int i = EMMC_ARG2;
|
|
for (; i <= EMMC_CONTROL2; i += 4)
|
|
rt_kprintf("\t%x:%x\n", i, read32(pdat->virt + i));
|
|
rt_kprintf("\t%x:%x\n", 0x50, read32(pdat->virt + 0x50));
|
|
rt_kprintf("\t%x:%x\n", 0x70, read32(pdat->virt + 0x70));
|
|
rt_kprintf("\t%x:%x\n", 0x74, read32(pdat->virt + 0x74));
|
|
rt_kprintf("\t%x:%x\n", 0x80, read32(pdat->virt + 0x80));
|
|
rt_kprintf("\t%x:%x\n", 0x84, read32(pdat->virt + 0x84));
|
|
rt_kprintf("\t%x:%x\n", 0x88, read32(pdat->virt + 0x88));
|
|
rt_kprintf("\t%x:%x\n", 0x8c, read32(pdat->virt + 0x8c));
|
|
rt_kprintf("\t%x:%x\n", 0x90, read32(pdat->virt + 0x90));
|
|
rt_kprintf("\t%x:%x\n", 0xf0, read32(pdat->virt + 0xf0));
|
|
rt_kprintf("\t%x:%x\n", 0xfc, read32(pdat->virt + 0xfc));
|
|
}
|
|
#endif
|
|
|
|
int raspi_sdmmc_init(void)
|
|
{
|
|
rt_uint32_t virt;
|
|
struct rt_mmcsd_host * host = RT_NULL;
|
|
struct sdhci_pdata_t * pdat = RT_NULL;
|
|
struct sdhci_t * sdhci = RT_NULL;
|
|
#ifdef BSP_USING_SDIO0
|
|
host = mmcsd_alloc_host();
|
|
if (!host)
|
|
{
|
|
rt_kprintf("alloc host failed");
|
|
goto err;
|
|
}
|
|
sdhci = rt_malloc(sizeof(struct sdhci_t));
|
|
if (!sdhci)
|
|
{
|
|
rt_kprintf("alloc sdhci failed");
|
|
goto err;
|
|
}
|
|
rt_memset(sdhci, 0, sizeof(struct sdhci_t));
|
|
|
|
virt = MMC2_BASE_ADDR;
|
|
pdat = (struct sdhci_pdata_t *)rt_malloc(sizeof(struct sdhci_pdata_t));
|
|
RT_ASSERT(pdat != RT_NULL);
|
|
|
|
pdat->virt = (rt_uint32_t)virt;
|
|
reset_emmc(pdat);
|
|
sdhci->name = "sd0";
|
|
sdhci->voltages = VDD_33_34;
|
|
sdhci->width = MMCSD_BUSWIDTH_4;
|
|
sdhci->clock = 1000 * 1000 * 1000;
|
|
sdhci->removeable = RT_TRUE;
|
|
|
|
sdhci->detect = sdhci_detect;
|
|
sdhci->setwidth = sdhci_setwidth;
|
|
sdhci->setclock = sdhci_setclock;
|
|
sdhci->transfer = sdhci_transfer;
|
|
sdhci->priv = pdat;
|
|
host->ops = &ops;
|
|
host->freq_min = 400000;
|
|
host->freq_max = 50000000;
|
|
host->valid_ocr = VDD_32_33 | VDD_33_34;
|
|
host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ | MMCSD_BUSWIDTH_4;
|
|
host->max_seg_size = 2048;
|
|
host->max_dma_segs = 10;
|
|
host->max_blk_size = 512;
|
|
host->max_blk_count = 1;
|
|
|
|
host->private_data = sdhci;
|
|
write32((pdat->virt + EMMC_IRPT_EN),0xffffffff);
|
|
write32((pdat->virt + EMMC_IRPT_MASK),0xffffffff);
|
|
#ifdef RT_MMCSD_DBG
|
|
dump_registers(pdat);
|
|
#endif
|
|
mmcsd_change(host);
|
|
#endif
|
|
return RT_EOK;
|
|
err:
|
|
if (host) rt_free(host);
|
|
if (sdhci) rt_free(sdhci);
|
|
|
|
return -RT_EIO;
|
|
}
|
|
|
|
INIT_DEVICE_EXPORT(raspi_sdmmc_init);
|