573 lines
15 KiB
C
573 lines
15 KiB
C
/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-08-25 liYony first version
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*/
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#include <board.h>
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#include "drv_gpio.h"
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#ifdef BSP_USING_GPIO
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#define PIN_NUM(port, no) (((((port) & 0xFu) << 4) | ((no) & 0xFu)))
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#define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu))
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#define PIN_NO(pin) ((uint8_t)((pin) & 0xFu))
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#define PIN_STPORT(pin) ((GPIO_TypeDef *)(GPIOA_BASE + (0x400u * PIN_PORT(pin))))
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#define PIN_STPIN(pin) ((uint16_t)(1u << PIN_NO(pin)))
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#if defined(GPIOZ)
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#define __CH32_PORT_MAX 12u
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#elif defined(GPIOK)
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#define __CH32_PORT_MAX 11u
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#elif defined(GPIOJ)
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#define __CH32_PORT_MAX 10u
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#elif defined(GPIOI)
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#define __CH32_PORT_MAX 9u
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#elif defined(GPIOH)
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#define __CH32_PORT_MAX 8u
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#elif defined(GPIOG)
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#define __CH32_PORT_MAX 7u
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#elif defined(GPIOF)
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#define __CH32_PORT_MAX 6u
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#elif defined(GPIOE)
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#define __CH32_PORT_MAX 5u
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#elif defined(GPIOD)
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#define __CH32_PORT_MAX 4u
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#elif defined(GPIOC)
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#define __CH32_PORT_MAX 3u
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#elif defined(GPIOB)
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#define __CH32_PORT_MAX 2u
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#elif defined(GPIOA)
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#define __CH32_PORT_MAX 1u
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#else
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#define __CH32_PORT_MAX 0u
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#error Unsupported CH32 GPIO peripheral.
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#endif
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#define PIN_STPORT_MAX __CH32_PORT_MAX
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static const struct pin_irq_map pin_irq_map[] =
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{
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{GPIO_Pin_0, EXTI0_IRQn},
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{GPIO_Pin_1, EXTI1_IRQn},
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{GPIO_Pin_2, EXTI2_IRQn},
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{GPIO_Pin_3, EXTI3_IRQn},
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{GPIO_Pin_4, EXTI4_IRQn},
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{GPIO_Pin_5, EXTI9_5_IRQn},
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{GPIO_Pin_6, EXTI9_5_IRQn},
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{GPIO_Pin_7, EXTI9_5_IRQn},
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{GPIO_Pin_8, EXTI9_5_IRQn},
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{GPIO_Pin_9, EXTI9_5_IRQn},
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{GPIO_Pin_10, EXTI15_10_IRQn},
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{GPIO_Pin_11, EXTI15_10_IRQn},
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{GPIO_Pin_12, EXTI15_10_IRQn},
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{GPIO_Pin_13, EXTI15_10_IRQn},
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{GPIO_Pin_14, EXTI15_10_IRQn},
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{GPIO_Pin_15, EXTI15_10_IRQn},
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};
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static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
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{
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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};
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static uint32_t pin_irq_enable_mask = 0;
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#define ITEM_NUM(items) (sizeof(items) / sizeof((items)[0]))
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static rt_base_t ch32_pin_get(const char *name)
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{
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rt_base_t pin = 0;
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int hw_port_num, hw_pin_num = 0;
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int i, name_len;
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name_len = rt_strlen(name);
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if ((name_len < 4) || (name_len >= 6))
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{
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return -RT_EINVAL;
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}
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if ((name[0] != 'P') || (name[2] != '.'))
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{
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return -RT_EINVAL;
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}
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if ((name[1] >= 'A') && (name[1] <= 'Z'))
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{
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hw_port_num = (int)(name[1] - 'A');
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}
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else
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{
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return -RT_EINVAL;
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}
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for (i = 3; i < name_len; i++)
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{
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hw_pin_num *= 10;
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hw_pin_num += name[i] - '0';
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}
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pin = PIN_NUM(hw_port_num, hw_pin_num);
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return pin;
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}
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static void ch32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
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{
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GPIO_TypeDef *gpio_port;
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uint16_t gpio_pin;
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if (PIN_PORT(pin) < PIN_STPORT_MAX)
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{
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gpio_port = PIN_STPORT(pin);
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gpio_pin = PIN_STPIN(pin);
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GPIO_WriteBit(gpio_port, gpio_pin, (BitAction)value);
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}
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}
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static int ch32_pin_read(rt_device_t dev, rt_base_t pin)
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{
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GPIO_TypeDef *gpio_port;
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uint16_t gpio_pin;
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int value = PIN_LOW;
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if (PIN_PORT(pin) < PIN_STPORT_MAX)
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{
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gpio_port = PIN_STPORT(pin);
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gpio_pin = PIN_STPIN(pin);
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value = GPIO_ReadInputDataBit(gpio_port, gpio_pin);
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}
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return value;
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}
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static void ch32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
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{
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GPIO_InitTypeDef GPIO_InitStruct;
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if (PIN_PORT(pin) >= PIN_STPORT_MAX)
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{
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return;
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}
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/* Configure GPIO_InitStructure */
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GPIO_InitStruct.GPIO_Pin = PIN_STPIN(pin);
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GPIO_InitStruct.GPIO_Mode = GPIO_Mode_Out_PP;
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GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz;
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if (mode == PIN_MODE_OUTPUT)
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{
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/* output setting */
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GPIO_InitStruct.GPIO_Mode = GPIO_Mode_Out_PP;
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}
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else if (mode == PIN_MODE_INPUT)
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{
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/* input setting: pull up. */
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GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
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}
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else if (mode == PIN_MODE_INPUT_PULLDOWN)
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{
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/* input setting: pull down. */
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GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IPD;
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}
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else if (mode == PIN_MODE_INPUT_PULLUP)
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{
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/* output setting: od. */
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GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IPU;
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}
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else if (mode == PIN_MODE_OUTPUT_OD)
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{
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/* output setting: od. */
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GPIO_InitStruct.GPIO_Mode = GPIO_Mode_Out_OD;
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}
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GPIO_Init(PIN_STPORT(pin), &GPIO_InitStruct);
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}
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rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
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{
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rt_int32_t i;
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for (i = 0; i < 32; i++)
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{
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if (((rt_uint32_t)0x01 << i) == bit)
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{
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return i;
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}
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}
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return -1;
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}
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rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
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{
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rt_int32_t mapindex = bit2bitno(pinbit);
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if (mapindex < 0 || mapindex >= (rt_int32_t)ITEM_NUM(pin_irq_map))
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{
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return RT_NULL;
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}
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return &pin_irq_map[mapindex];
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};
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static rt_err_t ch32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
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rt_uint32_t mode, void (*hdr)(void *args), void *args)
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{
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rt_base_t level;
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rt_int32_t irqindex = -1;
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if (PIN_PORT(pin) >= PIN_STPORT_MAX)
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{
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return -RT_ENOSYS;
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}
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irqindex = bit2bitno(PIN_STPIN(pin));
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if (irqindex < 0 || irqindex >= (rt_int32_t)ITEM_NUM(pin_irq_map))
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{
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return -RT_ENOSYS;
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}
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[irqindex].pin == pin &&
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pin_irq_hdr_tab[irqindex].hdr == hdr &&
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pin_irq_hdr_tab[irqindex].mode == mode &&
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pin_irq_hdr_tab[irqindex].args == args)
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{
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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if (pin_irq_hdr_tab[irqindex].pin != -1)
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{
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rt_hw_interrupt_enable(level);
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return -RT_EBUSY;
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}
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pin_irq_hdr_tab[irqindex].pin = pin;
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pin_irq_hdr_tab[irqindex].hdr = hdr;
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pin_irq_hdr_tab[irqindex].mode = mode;
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pin_irq_hdr_tab[irqindex].args = args;
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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static rt_err_t ch32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
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{
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rt_base_t level;
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rt_int32_t irqindex = -1;
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if (PIN_PORT(pin) >= PIN_STPORT_MAX)
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{
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return -RT_ENOSYS;
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}
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irqindex = bit2bitno(PIN_STPIN(pin));
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if (irqindex < 0 || irqindex >= (rt_int32_t)ITEM_NUM(pin_irq_map))
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{
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return -RT_ENOSYS;
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}
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[irqindex].pin == -1)
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{
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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pin_irq_hdr_tab[irqindex].pin = -1;
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pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
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pin_irq_hdr_tab[irqindex].mode = 0;
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pin_irq_hdr_tab[irqindex].args = RT_NULL;
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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static rt_err_t ch32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
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rt_uint32_t enabled)
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{
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const struct pin_irq_map *irqmap;
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rt_base_t level;
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rt_int32_t irqindex = -1;
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rt_uint8_t gpio_port_souce=0;
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GPIO_InitTypeDef GPIO_InitStruct={0};
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EXTI_InitTypeDef EXTI_InitStructure={0};
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if (PIN_PORT(pin) >= PIN_STPORT_MAX)
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{
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return -RT_ENOSYS;
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}
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if (enabled == PIN_IRQ_ENABLE)
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{
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irqindex = bit2bitno(PIN_STPIN(pin));
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if (irqindex < 0 || irqindex >= (rt_int32_t)ITEM_NUM(pin_irq_map))
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{
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return -RT_ENOSYS;
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}
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[irqindex].pin == -1)
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{
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rt_hw_interrupt_enable(level);
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return -RT_ENOSYS;
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}
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irqmap = &pin_irq_map[irqindex];
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/* Configure GPIO_InitStructure */
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO , ENABLE);
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GPIO_InitStruct.GPIO_Pin = PIN_STPIN(pin);
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GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz;
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EXTI_InitStructure.EXTI_Line=PIN_STPIN(pin);
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EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
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EXTI_InitStructure.EXTI_LineCmd = ENABLE;
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switch (pin_irq_hdr_tab[irqindex].mode)
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{
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case PIN_IRQ_MODE_RISING:
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GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IPD;
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EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
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break;
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case PIN_IRQ_MODE_FALLING:
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GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IPU;
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EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
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break;
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case PIN_IRQ_MODE_RISING_FALLING:
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GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
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EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
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break;
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}
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GPIO_Init(PIN_STPORT(pin), &GPIO_InitStruct);
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gpio_port_souce=PIN_PORT(pin);
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GPIO_EXTILineConfig(gpio_port_souce,(rt_uint8_t)irqindex);
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EXTI_Init(&EXTI_InitStructure);
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NVIC_SetPriority(irqmap->irqno,5<<4);
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NVIC_EnableIRQ( irqmap->irqno );
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pin_irq_enable_mask |= irqmap->pinbit;
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rt_hw_interrupt_enable(level);
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}
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else if (enabled == PIN_IRQ_DISABLE)
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{
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irqmap = get_pin_irq_map(PIN_STPIN(pin));
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if (irqmap == RT_NULL)
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{
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return -RT_ENOSYS;
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}
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level = rt_hw_interrupt_disable();
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pin_irq_enable_mask &= ~irqmap->pinbit;
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if (( irqmap->pinbit>=GPIO_Pin_5 )&&( irqmap->pinbit<=GPIO_Pin_9 ))
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{
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if(!(pin_irq_enable_mask&(GPIO_Pin_5|GPIO_Pin_6|GPIO_Pin_7|GPIO_Pin_8|GPIO_Pin_9)))
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{
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NVIC_DisableIRQ(irqmap->irqno);
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}
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}
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else if (( irqmap->pinbit>=GPIO_Pin_10 )&&( irqmap->pinbit<=GPIO_Pin_15 ))
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{
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if(!(pin_irq_enable_mask&(GPIO_Pin_10|GPIO_Pin_11|GPIO_Pin_12|GPIO_Pin_13|GPIO_Pin_14|GPIO_Pin_15)))
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{
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NVIC_DisableIRQ(irqmap->irqno);
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}
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}
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else
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{
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NVIC_DisableIRQ(irqmap->irqno);
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}
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rt_hw_interrupt_enable(level);
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}
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else
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{
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return -RT_ENOSYS;
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}
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return RT_EOK;
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}
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static const struct rt_pin_ops _ch32_pin_ops =
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{
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ch32_pin_mode,
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ch32_pin_write,
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ch32_pin_read,
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ch32_pin_attach_irq,
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ch32_pin_dettach_irq,
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ch32_pin_irq_enable,
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ch32_pin_get,
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};
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rt_inline void pin_irq_hdr(int irqno)
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{
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if (pin_irq_hdr_tab[irqno].hdr)
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{
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pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
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}
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}
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void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
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{
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pin_irq_hdr(bit2bitno(GPIO_Pin));
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}
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void EXTI0_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
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void EXTI1_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
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void EXTI2_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
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void EXTI3_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
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void EXTI4_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
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void EXTI9_5_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
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void EXTI0_IRQHandler(void)
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{
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GET_INT_SP();
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rt_interrupt_enter();
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if(EXTI_GetITStatus(EXTI_Line0)!=RESET)
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{
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HAL_GPIO_EXTI_Callback(GPIO_Pin_0);
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EXTI_ClearITPendingBit(EXTI_Line0);
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}
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rt_interrupt_leave();
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FREE_INT_SP();
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}
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void EXTI1_IRQHandler(void)
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{
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GET_INT_SP();
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rt_interrupt_enter();
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if(EXTI_GetITStatus(EXTI_Line1)!=RESET)
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{
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HAL_GPIO_EXTI_Callback(GPIO_Pin_1);
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EXTI_ClearITPendingBit(EXTI_Line1);
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}
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rt_interrupt_leave();
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FREE_INT_SP();
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}
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void EXTI2_IRQHandler(void)
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{
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GET_INT_SP();
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rt_interrupt_enter();
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if(EXTI_GetITStatus(EXTI_Line2)!=RESET)
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{
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HAL_GPIO_EXTI_Callback(GPIO_Pin_2);
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EXTI_ClearITPendingBit(EXTI_Line2);
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}
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rt_interrupt_leave();
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FREE_INT_SP();
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}
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void EXTI3_IRQHandler(void)
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{
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GET_INT_SP();
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rt_interrupt_enter();
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if(EXTI_GetITStatus(EXTI_Line3)!=RESET)
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{
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HAL_GPIO_EXTI_Callback(GPIO_Pin_3);
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EXTI_ClearITPendingBit(EXTI_Line3);
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}
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rt_interrupt_leave();
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FREE_INT_SP();
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}
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void EXTI4_IRQHandler(void)
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{
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GET_INT_SP();
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rt_interrupt_enter();
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if(EXTI_GetITStatus(EXTI_Line4)!=RESET)
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{
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HAL_GPIO_EXTI_Callback(GPIO_Pin_4);
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EXTI_ClearITPendingBit(EXTI_Line4);
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}
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rt_interrupt_leave();
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FREE_INT_SP();
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}
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void EXTI9_5_IRQHandler(void)
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{
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GET_INT_SP();
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rt_interrupt_enter();
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if( (EXTI_GetITStatus(EXTI_Line5)!=RESET)|| \
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(EXTI_GetITStatus(EXTI_Line6)!=RESET)|| \
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(EXTI_GetITStatus(EXTI_Line7)!=RESET)|| \
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(EXTI_GetITStatus(EXTI_Line8)!=RESET)|| \
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(EXTI_GetITStatus(EXTI_Line9)!=RESET) )
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{
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HAL_GPIO_EXTI_Callback(GPIO_Pin_5);
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HAL_GPIO_EXTI_Callback(GPIO_Pin_6);
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HAL_GPIO_EXTI_Callback(GPIO_Pin_7);
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HAL_GPIO_EXTI_Callback(GPIO_Pin_8);
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HAL_GPIO_EXTI_Callback(GPIO_Pin_9);
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EXTI_ClearITPendingBit(EXTI_Line5|EXTI_Line6|EXTI_Line7|EXTI_Line8|EXTI_Line9);
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|
}
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|
rt_interrupt_leave();
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|
FREE_INT_SP();
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|
}
|
|
|
|
int rt_hw_pin_init(void)
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|
{
|
|
#if defined(RCC_APB2Periph_GPIOA)
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|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA , ENABLE);
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|
#if defined(RCC_APB2Periph_GPIOB)
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|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB , ENABLE);
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|
#if defined(RCC_APB2Periph_GPIOC)
|
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC , ENABLE);
|
|
#if defined(RCC_APB2Periph_GPIOD)
|
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD , ENABLE);
|
|
#if defined(RCC_APB2Periph_GPIOE)
|
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOE , ENABLE);
|
|
#if defined(RCC_APB2Periph_GPIOF)
|
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOF , ENABLE);
|
|
#if defined(RCC_APB2Periph_GPIOG)
|
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOG , ENABLE);
|
|
#if defined(RCC_APB2Periph_GPIOH)
|
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOH , ENABLE);
|
|
#if defined(RCC_APB2Periph_GPIOI)
|
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOI , ENABLE);
|
|
#if defined(RCC_APB2Periph_GPIOJ)
|
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOJ , ENABLE);
|
|
#if defined(RCC_APB2Periph_GPIOK)
|
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOK , ENABLE);
|
|
#if defined(RCC_APB2Periph_GPIOZ)
|
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOZ , ENABLE);
|
|
#endif /* defined(RCC_APB2Periph_GPIOZ) */
|
|
#endif /* defined(RCC_APB2Periph_GPIOK) */
|
|
#endif /* defined(RCC_APB2Periph_GPIOJ) */
|
|
#endif /* defined(RCC_APB2Periph_GPIOI) */
|
|
#endif /* defined(RCC_APB2Periph_GPIOH) */
|
|
#endif /* defined(RCC_APB2Periph_GPIOG) */
|
|
#endif /* defined(RCC_APB2Periph_GPIOF) */
|
|
#endif /* defined(RCC_APB2Periph_GPIOE) */
|
|
#endif /* defined(RCC_APB2Periph_GPIOD) */
|
|
#endif /* defined(RCC_APB2Periph_GPIOC) */
|
|
#endif /* defined(RCC_APB2Periph_GPIOB) */
|
|
#endif /* defined(RCC_APB2Periph_GPIOA) */
|
|
|
|
return rt_device_pin_register("pin", &_ch32_pin_ops, RT_NULL);
|
|
}
|
|
INIT_BOARD_EXPORT(rt_hw_pin_init);
|
|
|
|
#endif /* BSP_USING_GPIO */
|