f51bce3fed
We currently only support building with CCS and SCons is not using.
bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file.
You may need to regenerate the source file as you like, providing that:
1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The
channel 5 in enabled and connected to IRQ.
2, RTI driver is enabled and compare3 source is selected to counter1
and the compare3 will generate tick in the period of 10ms. This
value is coresponding with RT_TICK_PER_SECOND in rtconfig.h.
In CCS, you need to create a new CCS project and create link folders
pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember
to add the include path to the Build Properties.
122 lines
5.9 KiB
C
122 lines
5.9 KiB
C
/** @file pinmux.c
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* @brief PINMUX Driver Inmplmentation File
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* @date 23.May.2013
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* @version 03.05.01
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*
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*/
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/* (c) Texas Instruments 2009-2013, All rights reserved. */
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/* Include Files */
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#include "pinmux.h"
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#define PINMUX_SET(REG, BALLID, MUX) \
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pinMuxReg->PINMMR##REG## = (pinMuxReg->PINMMR##REG## & PINMUX_BALL_##BALLID##_MASK) | (PINMUX_BALL_##BALLID##_##MUX)
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#define PINMUX_GATE_EMIF_CLK_ENABLE(state) \
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pinMuxReg->PINMMR29 = (pinMuxReg->PINMMR29 & PINMUX_GATE_EMIF_CLK_MASK) | (PINMUX_GATE_EMIF_CLK_##state)
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#define PINMUX_GIOB_DISABLE_HET2_ENABLE(state) \
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pinMuxReg->PINMMR29 = (pinMuxReg->PINMMR29 & PINMUX_GIOB_DISABLE_HET2_MASK) | (PINMUX_GIOB_DISABLE_HET2_##state)
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#define PINMUX_ALT_ADC_TRIGGER_SELECT(num) \
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pinMuxReg->PINMMR30 = (pinMuxReg->PINMMR30 & PINMUX_ALT_ADC_TRIGGER_MASK) | (PINMUX_ALT_ADC_TRIGGER_##num)
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#define PINMUX_ETHERNET_SELECT(interface) \
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pinMuxReg->PINMMR29 = (pinMuxReg->PINMMR29 & PINMUX_ETHERNET_MASK) | (PINMUX_ETHERNET_##interface)
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/* USER CODE BEGIN (0) */
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/* USER CODE END */
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void muxInit(void){
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/* USER CODE BEGIN (1) */
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/* USER CODE END */
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/* Enable Pin Muxing */
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kickerReg->KICKER0 = 0x83E70B13U;
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kickerReg->KICKER1 = 0x95A4F1E0U;
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/* USER CODE BEGIN (2) */
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/* USER CODE END */
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pinMuxReg->PINMMR0 = PINMUX_BALL_W10_GIOB_3 | PINMUX_BALL_A5_GIOA_0 | PINMUX_BALL_C3_MIBSPI3NCS_3 | PINMUX_BALL_B2_MIBSPI3NCS_2;
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pinMuxReg->PINMMR1 = PINMUX_BALL_C2_GIOA_1 | PINMUX_BALL_E3_HET1_11 | PINMUX_BALL_E5_ETMDATA_20 | PINMUX_BALL_F5_ETMDATA_21;
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pinMuxReg->PINMMR2 = PINMUX_BALL_C1_GIOA_2 | PINMUX_BALL_G5_ETMDATA_22 | PINMUX_BALL_E1_GIOA_3 | PINMUX_BALL_B5_GIOA_5;
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pinMuxReg->PINMMR3 = PINMUX_BALL_K5_ETMDATA_23 | PINMUX_BALL_B3_HET1_22 | PINMUX_BALL_H3_GIOA_6 | PINMUX_BALL_L5_ETMDATA_24;
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pinMuxReg->PINMMR4 = PINMUX_BALL_M1_GIOA_7 | PINMUX_BALL_M5_ETMDATA_25 | PINMUX_BALL_V2_HET1_01 | PINMUX_BALL_U1_HET1_03;
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pinMuxReg->PINMMR5 = PINMUX_BALL_K18_HET1_0 | PINMUX_BALL_W5_HET1_02 | PINMUX_BALL_V6_HET1_05 | PINMUX_BALL_N5_ETMDATA_26;
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pinMuxReg->PINMMR6 = PINMUX_BALL_T1_HET1_07 | PINMUX_BALL_P5_ETMDATA_27 | PINMUX_BALL_V7_HET1_09 | PINMUX_BALL_R5_ETMDATA_28;
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pinMuxReg->PINMMR7 = PINMUX_BALL_R6_ETMDATA_29 | PINMUX_BALL_V5_MIBSPI3NCS_1 | PINMUX_BALL_W3_HET1_06 | PINMUX_BALL_R7_ETMDATA_30;
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pinMuxReg->PINMMR8 = PINMUX_BALL_N2_HET1_13 | PINMUX_BALL_G3_MIBSPI1NCS_2 | PINMUX_BALL_N1_HET1_15 | PINMUX_BALL_R8_ETMDATA_31;
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pinMuxReg->PINMMR9 = (~(pinMuxReg->PINMMR9 >> 18U) & 0x00000001U ) << 18U| PINMUX_BALL_R9_ETMTRACECLKIN | PINMUX_BALL_W9_MIBSPI3NENA | PINMUX_BALL_V10_MIBSPI3NCS_0 | PINMUX_BALL_J3_MIBSPI1NCS_3;
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pinMuxReg->PINMMR10 = PINMUX_BALL_N19_AD1EVT | PINMUX_BALL_N15_ETMDATA_19 | PINMUX_BALL_N17_EMIF_nCS_0 | PINMUX_BALL_M15_ETMDATA_18;
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pinMuxReg->PINMMR11 = PINMUX_BALL_K17_EMIF_nCS_3 | PINMUX_BALL_M17_EMIF_nCS_4 | PINMUX_BALL_L15_ETMDATA_17 | PINMUX_BALL_P1_HET1_24;
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pinMuxReg->PINMMR12 = PINMUX_BALL_A14_HET1_26 | PINMUX_BALL_K15_ETMDATA_16 | PINMUX_BALL_G19_MIBSPI1NENA | PINMUX_BALL_H18_MIBSPI5NENA;
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pinMuxReg->PINMMR13 = PINMUX_BALL_J18_MIBSPI5SOMI_0 | PINMUX_BALL_J19_MIBSPI5SIMO_0 | PINMUX_BALL_H19_MIBSPI5CLK | PINMUX_BALL_R2_MIBSPI1NCS_0;
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pinMuxReg->PINMMR14 = PINMUX_BALL_E18_HET1_08 | PINMUX_BALL_K19_HET1_28 | PINMUX_BALL_D17_EMIF_nWE | PINMUX_BALL_D16_EMIF_BA_1;
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pinMuxReg->PINMMR15 = PINMUX_BALL_C17_EMIF_ADDR_21 | PINMUX_BALL_C16_EMIF_ADDR_20 | PINMUX_BALL_C15_EMIF_ADDR_19 | PINMUX_BALL_D15_EMIF_ADDR_18;
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pinMuxReg->PINMMR16 = PINMUX_BALL_E13_ETMDATA_12 | PINMUX_BALL_C14_EMIF_ADDR_17 | PINMUX_BALL_D14_EMIF_ADDR_16 | PINMUX_BALL_E12_ETMDATA_13;
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pinMuxReg->PINMMR17 = PINMUX_BALL_D19_HET1_10 | PINMUX_BALL_E11_ETMDATA_14 | PINMUX_BALL_B4_HET1_12 | PINMUX_BALL_E9_ETMDATA_08;
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pinMuxReg->PINMMR18 = PINMUX_BALL_C13_EMIF_ADDR_15 | PINMUX_BALL_A11_HET1_14 | PINMUX_BALL_C12_EMIF_ADDR_14 | PINMUX_BALL_M2_GIOB_0;
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pinMuxReg->PINMMR19 = PINMUX_BALL_E8_ETMDATA_09 | PINMUX_BALL_B11_HET1_30 | PINMUX_BALL_E10_ETMDATA_15 | PINMUX_BALL_E7_ETMDATA_10;
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pinMuxReg->PINMMR20 = PINMUX_BALL_C11_EMIF_ADDR_13 | PINMUX_BALL_C10_EMIF_ADDR_12 | PINMUX_BALL_F3_MIBSPI1NCS_1 | PINMUX_BALL_C9_EMIF_ADDR_11;
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pinMuxReg->PINMMR21 = PINMUX_BALL_D5_EMIF_ADDR_1 | PINMUX_BALL_K2_GIOB_1 | PINMUX_BALL_C8_EMIF_ADDR_10 | PINMUX_BALL_C7_EMIF_ADDR_9;
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pinMuxReg->PINMMR22 = PINMUX_BALL_D4_EMIF_ADDR_0 | PINMUX_BALL_C5_EMIF_ADDR_7 | PINMUX_BALL_C4_EMIF_ADDR_6 | PINMUX_BALL_E6_ETMDATA_11;
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pinMuxReg->PINMMR23 = (~(pinMuxReg->PINMMR5 >> 1U) & 0x00000001U ) << 8U |(~(pinMuxReg->PINMMR5 >> 9U) & 0x00000001U ) << 16U|(~(pinMuxReg->PINMMR5 >> 17U) & 0x00000001U ) << 24U| PINMUX_BALL_C6_EMIF_ADDR_8;
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pinMuxReg->PINMMR24 = (~(pinMuxReg->PINMMR4 >> 17U) & 0x00000001U ) << 0U|(~(pinMuxReg->PINMMR4 >> 25U) & 0x00000001U ) << 8U|(~(pinMuxReg->PINMMR20 >> 17U) & 0x00000001U ) << 16U | (~(pinMuxReg->PINMMR8 >> 9U) & 0x00000001U ) << 24U;
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pinMuxReg->PINMMR25 = (~(pinMuxReg->PINMMR12 >> 17U) & 0x00000001U ) << 8U|(~(pinMuxReg->PINMMR7 >> 9U) & 0x00000001U ) << 16U|(~(pinMuxReg->PINMMR0 >> 26U) & 0x00000001U ) << 24U;
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pinMuxReg->PINMMR26 = (~(pinMuxReg->PINMMR0 >> 18U) & 0x00000001U ) << 0U|(~(pinMuxReg->PINMMR9 >> 10U) & 0x00000001U ) << 8U|PINMUX_BALL_W6_MIBSPI5NCS_2 | PINMUX_BALL_T12_MIBSPI5NCS_3;
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pinMuxReg->PINMMR27 = PINMUX_BALL_E19_MIBSPI5NCS_0 | PINMUX_BALL_B6_MIBSPI5NCS_1 | PINMUX_BALL_E16_MIBSPI5SIMO_1 | PINMUX_BALL_H17_MIBSPI5SIMO_2;
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pinMuxReg->PINMMR28 = PINMUX_BALL_G17_MIBSPI5SIMO_3 | PINMUX_BALL_E17_MIBSPI5SOMI_1 | PINMUX_BALL_H16_MIBSPI5SOMI_2 | PINMUX_BALL_G16_MIBSPI5SOMI_3;
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pinMuxReg->PINMMR29 = PINMUX_BALL_D3_SPI2NENA;
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PINMUX_GATE_EMIF_CLK_ENABLE(OFF);
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PINMUX_GIOB_DISABLE_HET2_ENABLE(OFF);
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PINMUX_ALT_ADC_TRIGGER_SELECT(1);
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PINMUX_ETHERNET_SELECT(RMII);
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/* USER CODE BEGIN (3) */
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/* USER CODE END */
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/* Disable Pin Muxing */
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kickerReg->KICKER0 = 0x00000000U;
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kickerReg->KICKER1 = 0x00000000U;
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/* USER CODE BEGIN (4) */
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/* USER CODE END */
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}
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/* USER CODE BEGIN (5) */
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/* USER CODE END */
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