f51bce3fed
We currently only support building with CCS and SCons is not using.
bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file.
You may need to regenerate the source file as you like, providing that:
1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The
channel 5 in enabled and connected to IRQ.
2, RTI driver is enabled and compare3 source is selected to counter1
and the compare3 will generate tick in the period of 10ms. This
value is coresponding with RT_TICK_PER_SECOND in rtconfig.h.
In CCS, you need to create a new CCS project and create link folders
pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember
to add the include path to the Build Properties.
156 lines
4.9 KiB
C
156 lines
4.9 KiB
C
/** @file reg_spi.h
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* @brief SPI Register Layer Header File
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* @date 23.May.2013
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* @version 03.05.01
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*
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* This file contains:
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* - Definitions
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* - Types
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* - Interface Prototypes
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* .
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* which are relevant for the SPI driver.
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*/
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/* (c) Texas Instruments 2009-2013, All rights reserved. */
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#ifndef __REG_SPI_H__
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#define __REG_SPI_H__
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#include "sys_common.h"
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#include "gio.h"
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/* USER CODE BEGIN (0) */
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/* USER CODE END */
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/* Spi Register Frame Definition */
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/** @struct spiBase
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* @brief SPI Register Definition
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*
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* This structure is used to access the SPI module registers.
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*/
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/** @typedef spiBASE_t
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* @brief SPI Register Frame Type Definition
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*
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* This type is used to access the SPI Registers.
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*/
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typedef volatile struct spiBase
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{
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uint32 GCR0; /**< 0x0000: Global Control 0 */
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uint32 GCR1; /**< 0x0004: Global Control 1 */
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uint32 INT0; /**< 0x0008: Interrupt Register */
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uint32 LVL; /**< 0x000C: Interrupt Level */
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uint32 FLG; /**< 0x0010: Interrupt flags */
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uint32 PCFUN; /**< 0x0014: Function Pin Enable */
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uint32 PCDIR; /**< 0x0018: Pin Direction */
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uint32 PCDIN; /**< 0x001C: Pin Input Latch */
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uint32 PCDOUT; /**< 0x0020: Pin Output Latch */
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uint32 PCSET; /**< 0x0024: Output Pin Set */
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uint32 PCCLR; /**< 0x0028: Output Pin Clr */
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uint32 PCPDR; /**< 0x002C: Open Drain Output Enable */
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uint32 PCDIS; /**< 0x0030: Pullup/Pulldown Disable */
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uint32 PCPSL; /**< 0x0034: Pullup/Pulldown Selection */
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uint32 DAT0; /**< 0x0038: Transmit Data */
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uint32 DAT1; /**< 0x003C: Transmit Data with Format and Chip Select */
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uint32 BUF; /**< 0x0040: Receive Buffer */
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uint32 EMU; /**< 0x0044: Emulation Receive Buffer */
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uint32 DELAY; /**< 0x0048: Delays */
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uint32 CSDEF; /**< 0x004C: Default Chip Select */
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uint32 FMT0; /**< 0x0050: Data Format 0 */
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uint32 FMT1; /**< 0x0054: Data Format 1 */
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uint32 FMT2; /**< 0x0058: Data Format 2 */
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uint32 FMT3; /**< 0x005C: Data Format 3 */
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uint32 INTVECT0; /**< 0x0060: Interrupt Vector 0 */
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uint32 INTVECT1; /**< 0x0064: Interrupt Vector 1 */
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uint32 SRSEL; /**< 0x0068: Slew Rate Select */
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uint32 RESERVED[50U]; /**< 0x006C to 0x0130: Reserved */
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uint32 IOLPKTSTCR; /**< 0x0134: IO loopback */
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} spiBASE_t;
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/** @def spiREG1
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* @brief SPI1 (MIBSPI - Compatibility Mode) Register Frame Pointer
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*
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* This pointer is used by the SPI driver to access the spi module registers.
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*/
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#define spiREG1 ((spiBASE_t *)0xFFF7F400U)
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/** @def spiPORT1
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* @brief SPI1 (MIBSPI - Compatibility Mode) GIO Port Register Pointer
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*
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* Pointer used by the GIO driver to access I/O PORT of SPI1
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* (use the GIO drivers to access the port pins).
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*/
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#define spiPORT1 ((gioPORT_t *)0xFFF7F418U)
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/** @def spiREG2
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* @brief SPI2 Register Frame Pointer
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*
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* This pointer is used by the SPI driver to access the spi module registers.
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*/
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#define spiREG2 ((spiBASE_t *)0xFFF7F600U)
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/** @def spiPORT2
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* @brief SPI2 GIO Port Register Pointer
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*
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* Pointer used by the GIO driver to access I/O PORT of SPI2
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* (use the GIO drivers to access the port pins).
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*/
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#define spiPORT2 ((gioPORT_t *)0xFFF7F618U)
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/** @def spiREG3
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* @brief SPI3 (MIBSPI - Compatibility Mode) Register Frame Pointer
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*
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* This pointer is used by the SPI driver to access the spi module registers.
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*/
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#define spiREG3 ((spiBASE_t *)0xFFF7F800U)
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/** @def spiPORT3
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* @brief SPI3 (MIBSPI - Compatibility Mode) GIO Port Register Pointer
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*
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* Pointer used by the GIO driver to access I/O PORT of SPI3
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* (use the GIO drivers to access the port pins).
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*/
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#define spiPORT3 ((gioPORT_t *)0xFFF7F818U)
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/** @def spiREG4
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* @brief SPI4 Register Frame Pointer
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*
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* This pointer is used by the SPI driver to access the spi module registers.
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*/
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#define spiREG4 ((spiBASE_t *)0xFFF7FA00U)
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/** @def spiPORT4
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* @brief SPI4 GIO Port Register Pointer
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*
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* Pointer used by the GIO driver to access I/O PORT of SPI4
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* (use the GIO drivers to access the port pins).
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*/
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#define spiPORT4 ((gioPORT_t *)0xFFF7FA18U)
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/** @def spiREG5
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* @brief SPI5 (MIBSPI - Compatibility Mode) Register Frame Pointer
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*
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* This pointer is used by the SPI driver to access the spi module registers.
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*/
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#define spiREG5 ((spiBASE_t *)0xFFF7FC00U)
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/** @def spiPORT5
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* @brief SPI5 (MIBSPI - Compatibility Mode) GIO Port Register Pointer
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*
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* Pointer used by the GIO driver to access I/O PORT of SPI5
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* (use the GIO drivers to access the port pins).
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*/
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#define spiPORT5 ((gioPORT_t *)0xFFF7FC18U)
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/* USER CODE BEGIN (1) */
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/* USER CODE END */
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#endif
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