f51bce3fed
We currently only support building with CCS and SCons is not using.
bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file.
You may need to regenerate the source file as you like, providing that:
1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The
channel 5 in enabled and connected to IRQ.
2, RTI driver is enabled and compare3 source is selected to counter1
and the compare3 will generate tick in the period of 10ms. This
value is coresponding with RT_TICK_PER_SECOND in rtconfig.h.
In CCS, you need to create a new CCS project and create link folders
pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember
to add the include path to the Build Properties.
107 lines
3.4 KiB
C
107 lines
3.4 KiB
C
/** @file reg_sci.h
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* @brief SCI Register Layer Header File
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* @date 23.May.2013
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* @version 03.05.01
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*
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* This file contains:
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* - Definitions
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* - Types
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* - Interface Prototypes
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* .
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* which are relevant for the SCI driver.
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*/
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/* (c) Texas Instruments 2009-2013, All rights reserved. */
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#ifndef __REG_SCI_H__
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#define __REG_SCI_H__
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#include "sys_common.h"
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#include "gio.h"
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/* USER CODE BEGIN (0) */
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/* USER CODE END */
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/* Sci Register Frame Definition */
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/** @struct sciBase
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* @brief SCI Base Register Definition
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*
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* This structure is used to access the SCI module registers.
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*/
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/** @typedef sciBASE_t
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* @brief SCI Register Frame Type Definition
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*
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* This type is used to access the SCI Registers.
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*/
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typedef volatile struct sciBase
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{
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uint32 GCR0; /**< 0x0000 Global Control Register 0 */
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uint32 GCR1; /**< 0x0004 Global Control Register 1 */
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uint32 GCR2; /**< 0x0008 Global Control Register 2 */
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uint32 SETINT; /**< 0x000C Set Interrupt Enable Register */
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uint32 CLRINT; /**< 0x0010 Clear Interrupt Enable Register */
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uint32 SETINTLVL; /**< 0x0014 Set Interrupt Level Register */
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uint32 CLRINTLVL; /**< 0x0018 Set Interrupt Level Register */
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uint32 FLR; /**< 0x001C Interrupt Flag Register */
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uint32 INTVECT0; /**< 0x0020 Interrupt Vector Offset 0 */
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uint32 INTVECT1; /**< 0x0024 Interrupt Vector Offset 1 */
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uint32 FORMAT; /**< 0x0028 Format Control Register */
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uint32 BRS; /**< 0x002C Baud Rate Selection Register */
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uint32 ED; /**< 0x0030 Emulation Register */
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uint32 RD; /**< 0x0034 Receive Data Buffer */
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uint32 TD; /**< 0x0038 Transmit Data Buffer */
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uint32 FUN; /**< 0x003C Pin Function Register */
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uint32 DIR; /**< 0x0040 Pin Direction Register */
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uint32 DIN; /**< 0x0044 Pin Data In Register */
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uint32 DOUT; /**< 0x0048 Pin Data Out Register */
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uint32 SET; /**< 0x004C Pin Data Set Register */
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uint32 CLR; /**< 0x0050 Pin Data Clr Register */
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uint32 ODR; /**< 0x0054: Pin Open Drain Output Enable Register */
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uint32 PD; /**< 0x0058: Pin Pullup/Pulldown Disable Register */
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uint32 PSL; /**< 0x005C: Pin Pullup/Pulldown Selection Register */
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uint32 rsdv1[12U]; /**< 0x060: Reserved */
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uint32 IODFTCTRL; /**< 0x0090: I/O Error Enable Register */
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} sciBASE_t;
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/** @def sciREG
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* @brief Register Frame Pointer
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*
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* This pointer is used by the SCI driver to access the sci module registers.
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*/
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#define sciREG ((sciBASE_t *)0xFFF7E500U)
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/** @def sciPORT
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* @brief SCI GIO Port Register Pointer
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*
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* Pointer used by the GIO driver to access I/O PORT of SCI
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* (use the GIO drivers to access the port pins).
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*/
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#define sciPORT ((gioPORT_t *)0xFFF7E540U)
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/** @def scilinREG
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* @brief SCILIN (LIN - Compatibility Mode) Register Frame Pointer
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*
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* This pointer is used by the SCI driver to access the sci module registers.
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*/
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#define scilinREG ((sciBASE_t *)0xFFF7E400U)
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/** @def scilinPORT
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* @brief SCILIN (LIN - Compatibility Mode) Register Frame Pointer
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*
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* Pointer used by the GIO driver to access I/O PORT of LIN
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* (use the GIO drivers to access the port pins).
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*/
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#define scilinPORT ((gioPORT_t *)0xFFF7E440U)
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/* USER CODE BEGIN (1) */
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/* USER CODE END */
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#endif
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