f51bce3fed
We currently only support building with CCS and SCons is not using.
bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file.
You may need to regenerate the source file as you like, providing that:
1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The
channel 5 in enabled and connected to IRQ.
2, RTI driver is enabled and compare3 source is selected to counter1
and the compare3 will generate tick in the period of 10ms. This
value is coresponding with RT_TICK_PER_SECOND in rtconfig.h.
In CCS, you need to create a new CCS project and create link folders
pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember
to add the include path to the Build Properties.
84 lines
2.8 KiB
C
84 lines
2.8 KiB
C
/** @file reg_rtp.h
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* @brief RTP Register Layer Header File
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* @date 23.May.2013
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* @version 03.05.01
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*
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* This file contains:
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* - Definitions
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* - Types
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* - Interface Prototypes
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* .
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* which are relevant for the RTP driver.
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*/
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/* (c) Texas Instruments 2009-2013, All rights reserved. */
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#ifndef __REG_RTP_H__
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#define __REG_RTP_H__
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#include "sys_common.h"
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#include "gio.h"
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/* USER CODE BEGIN (0) */
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/* USER CODE END */
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/* Rtp Register Frame Definition */
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/** @struct rtpBase
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* @brief RTP Base Register Definition
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*
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* This structure is used to access the RTP module registers.
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*/
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/** @typedef rtpBASE_t
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* @brief RTP Register Frame Type Definition
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*
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* This type is used to access the RTP Registers.
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*/
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typedef volatile struct rtpBase
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{
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uint32 GLBCTRL; /**< 0x0000: RTP Global Control Register */
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uint32 TRENA; /**< 0x0004: RTP Trace Enable Register */
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uint32 GSR; /**< 0x0008: RTP Global Status Register */
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uint32 RAM1REG1; /**< 0x000C: RTP RAM 1 Trace Region 1 Register */
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uint32 RAM1REG2; /**< 0x0010: RTP RAM 1 Trace Region 2 Register */
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uint32 RAM2REG1; /**< 0x0014: RTP RAM 2 Trace Region 1 Register */
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uint32 RAM2REG2; /**< 0x0018: RTP RAM 2 Trace Region 2 Register */
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uint32 rsvd1[2U]; /**< 0x001C: Reserved */
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uint32 ERREG1; /**< 0x0024: RTP Peripheral Trace Region 1 Register */
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uint32 ERREG2; /**< 0x0028: RTP Peripheral Trace Region 2 Register */
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uint32 DDMW; /**< 0x002C: RTP Direct Data Mode Write Register */
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uint32 rsvd2; /**< 0x0030: Reserved */
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uint32 PC0; /**< 0x0034: RTP Pin Control 0 Register */
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uint32 PC1; /**< 0x0038: RTP Pin Control 1 Register */
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uint32 PC2; /**< 0x003C: RTP Pin Control 2 Register */
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uint32 PC3; /**< 0x0040: RTP Pin Control 3 Register */
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uint32 PC4; /**< 0x0044: RTP Pin Control 4 Register */
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uint32 PC5; /**< 0x0048: RTP Pin Control 5 Register */
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uint32 PC6; /**< 0x004C: RTP Pin Control 6 Register */
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uint32 PC7; /**< 0x0050: RTP Pin Control 7 Register */
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uint32 PC8; /**< 0x0054: RTP Pin Control 8 Register */
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} rtpBASE_t;
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/** @def rtpREG
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* @brief RTP Register Frame Pointer
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*
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* This pointer is used by the RTP driver to access the RTP module registers.
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*/
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#define rtpREG ((rtpBASE_t *)0xFFFFFA00U)
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/** @def rtpPORT
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* @brief RTP Port Register Pointer
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*
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* Pointer used by the GIO driver to access I/O PORT of RTP
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* (use the GIO drivers to access the port pins).
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*/
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#define rtpPORT ((gioPORT_t *)0xFFFFFA38U)
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/* USER CODE BEGIN (1) */
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/* USER CODE END */
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#endif
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