f51bce3fed
We currently only support building with CCS and SCons is not using.
bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file.
You may need to regenerate the source file as you like, providing that:
1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The
channel 5 in enabled and connected to IRQ.
2, RTI driver is enabled and compare3 source is selected to counter1
and the compare3 will generate tick in the period of 10ms. This
value is coresponding with RT_TICK_PER_SECOND in rtconfig.h.
In CCS, you need to create a new CCS project and create link folders
pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember
to add the include path to the Build Properties.
95 lines
2.8 KiB
C
95 lines
2.8 KiB
C
/** @file reg_pom.h
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* @brief POM Register Layer Header File
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* @date 23.May.2013
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* @version 03.05.01
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*
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* This file contains:
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* - Definitions
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* - Types
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* - Interface Prototypes
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* .
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* which are relevant for the POM driver.
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*/
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/* (c) Texas Instruments 2009-2013, All rights reserved. */
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#ifndef __REG_POM_H__
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#define __REG_POM_H__
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#include "sys_common.h"
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/* USER CODE BEGIN (0) */
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/* USER CODE END */
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/* Pom Register Frame Definition */
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/** @struct POMBase
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* @brief POM Register Frame Definition
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*
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* This structure is used to access the POM module registers(POM Register Map).
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*/
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typedef struct
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{
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uint32 POMGLBCTRL_UL; /* 0x00 */
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uint32 POMREV_UL; /* 0x04 */
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uint32 POMCLKCTRL_UL; /* 0x08 */
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uint32 POMFLG_UL; /* 0x0C */
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struct
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{
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uint32 rsdv1;
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}RESERVED_REG[124U];
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struct /* 0x200 ... */
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{
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uint32 POMPROGSTART_UL;
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uint32 POMOVLSTART_UL;
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uint32 POMREGSIZE_UL;
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uint32 rsdv2;
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}POMRGNCONF_ST[32U];
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}pomBASE_t;
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/** @struct POM_CORESIGHT_ST
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* @brief POM_CORESIGHT_ST Register Definition
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*
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* This structure is used to access the POM module registers(POM CoreSight Registers ).
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*/
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typedef struct
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{
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uint32 POMITCTRL_UL; /* 0xF00 */
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struct /* 0xF04 to 0xF9C */
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{
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uint32 Reserved_Reg_UL;
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}Reserved1_ST[39U];
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uint32 POMCLAIMSET_UL; /* 0xFA0 */
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uint32 POMCLAIMCLR_UL; /* 0xFA4 */
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uint32 rsvd1[2U]; /* 0xFA8 */
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uint32 POMLOCKACCESS_UL; /* 0xFB0 */
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uint32 POMLOCKSTATUS_UL; /* 0xFB4 */
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uint32 POMAUTHSTATUS_UL; /* 0xFB8 */
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uint32 rsvd2[3U]; /* 0xFBC */
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uint32 POMDEVID_UL; /* 0xFC8 */
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uint32 POMDEVTYPE_UL; /* 0xFCC */
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uint32 POMPERIPHERALID4_UL; /* 0xFD0 */
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uint32 POMPERIPHERALID5_UL; /* 0xFD4 */
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uint32 POMPERIPHERALID6_UL; /* 0xFD8 */
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uint32 POMPERIPHERALID7_UL; /* 0xFDC */
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uint32 POMPERIPHERALID0_UL; /* 0xFE0 */
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uint32 POMPERIPHERALID1_UL; /* 0xFE4 */
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uint32 POMPERIPHERALID2_UL; /* 0xFE8 */
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uint32 POMPERIPHERALID3_UL; /* 0xFEC */
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uint32 POMCOMPONENTID0_UL; /* 0xFF0 */
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uint32 POMCOMPONENTID1_UL; /* 0xFF4 */
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uint32 POMCOMPONENTID2_UL; /* 0xFF8 */
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uint32 POMCOMPONENTID3_UL; /* 0xFFC */
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}POM_CORESIGHT_ST;
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#define pomREG ((pomBASE_t *)0xFFA04000U)
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/* USER CODE BEGIN (1) */
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/* USER CODE END */
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#endif
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