f51bce3fed
We currently only support building with CCS and SCons is not using.
bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file.
You may need to regenerate the source file as you like, providing that:
1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The
channel 5 in enabled and connected to IRQ.
2, RTI driver is enabled and compare3 source is selected to counter1
and the compare3 will generate tick in the period of 10ms. This
value is coresponding with RT_TICK_PER_SECOND in rtconfig.h.
In CCS, you need to create a new CCS project and create link folders
pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember
to add the include path to the Build Properties.
225 lines
7.7 KiB
C
225 lines
7.7 KiB
C
/** @file reg_mibspi.h
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* @brief MIBSPI Register Layer Header File
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* @date 23.May.2013
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* @version 03.05.01
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*
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* This file contains:
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* - Definitions
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* - Types
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* - Interface Prototypes
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* .
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* which are relevant for the MIBSPI driver.
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*/
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/* (c) Texas Instruments 2009-2013, All rights reserved. */
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#ifndef __REG_MIBSPI_H__
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#define __REG_MIBSPI_H__
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#include "sys_common.h"
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#include "gio.h"
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/* USER CODE BEGIN (0) */
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/* USER CODE END */
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/* Mibspi Register Frame Definition */
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/** @struct mibspiBase
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* @brief MIBSPI Register Definition
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*
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* This structure is used to access the MIBSPI module registers.
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*/
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/** @typedef mibspiBASE_t
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* @brief MIBSPI Register Frame Type Definition
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*
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* This type is used to access the MIBSPI Registers.
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*/
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typedef volatile struct mibspiBase
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{
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uint32 GCR0; /**< 0x0000: Global Control 0 */
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uint32 GCR1; /**< 0x0004: Global Control 1 */
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uint32 INT0; /**< 0x0008: Interrupt Register */
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uint32 LVL; /**< 0x000C: Interrupt Level */
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uint32 FLG; /**< 0x0010: Interrupt flags */
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uint32 PCFUN; /**< 0x0014: Function Pin Enable */
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uint32 PCDIR; /**< 0x0018: Pin Direction */
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uint32 PCDIN; /**< 0x001C: Pin Input Latch */
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uint32 PCDOUT; /**< 0x0020: Pin Output Latch */
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uint32 PCSET; /**< 0x0024: Output Pin Set */
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uint32 PCCLR; /**< 0x0028: Output Pin Clr */
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uint32 PCPDR; /**< 0x002C: Open Drain Output Enable */
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uint32 PCDIS; /**< 0x0030: Pullup/Pulldown Disable */
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uint32 PCPSL; /**< 0x0034: Pullup/Pulldown Selection */
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uint32 DAT0; /**< 0x0038: Transmit Data */
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uint32 DAT1; /**< 0x003C: Transmit Data with Format and Chip Select */
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uint32 BUF; /**< 0x0040: Receive Buffer */
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uint32 EMU; /**< 0x0044: Emulation Receive Buffer */
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uint32 DELAY; /**< 0x0048: Delays */
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uint32 CSDEF; /**< 0x004C: Default Chip Select */
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uint32 FMT0; /**< 0x0050: Data Format 0 */
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uint32 FMT1; /**< 0x0054: Data Format 1 */
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uint32 FMT2; /**< 0x0058: Data Format 2 */
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uint32 FMT3; /**< 0x005C: Data Format 3 */
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uint32 INTVECT0; /**< 0x0060: Interrupt Vector 0 */
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uint32 INTVECT1; /**< 0x0064: Interrupt Vector 1 */
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uint32 SRSEL; /**< 0x0068: Slew Rate Select */
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uint32 PMCTRL; /**< 0x006C: Parallel Mode Control */
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uint32 MIBSPIE; /**< 0x0070: Multi-buffer Mode Enable */
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uint32 TGITENST; /**< 0x0074: TG Interrupt Enable Set */
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uint32 TGITENCR; /**< 0x0078: TG Interrupt Enable Clear */
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uint32 TGITLVST; /**< 0x007C: Transfer Group Interrupt Level Set */
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uint32 TGITLVCR; /**< 0x0080: Transfer Group Interrupt Level Clear */
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uint32 TGINTFLG; /**< 0x0084: Transfer Group Interrupt Flag */
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uint32 rsvd1[2U]; /**< 0x0088: Reserved */
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uint32 TICKCNT; /**< 0x0090: Tick Counter */
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uint32 LTGPEND; /**< 0x0090: Last TG End Pointer */
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uint32 TGCTRL[16U]; /**< 0x0098 - 0x00D4: Transfer Group Control */
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uint32 DMACTRL[8U]; /**< 0x00D8 - 0x00F4: DMA Control */
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uint32 DMACOUNT[8U]; /**< 0x00F8 - 0x0114: DMA Count */
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uint32 DMACNTLEN; /**< 0x0118 - 0x0114: DMA Control length */
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uint32 rsvd2; /**< 0x011C: Reserved */
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uint32 UERRCTRL; /**< 0x0120: Multi-buffer RAM Uncorrectable Parity Error Control */
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uint32 UERRSTAT; /**< 0x0124: Multi-buffer RAM Uncorrectable Parity Error Status */
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uint32 UERRADDRRX; /**< 0x0128: RXRAM Uncorrectable Parity Error Address */
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uint32 UERRADDRTX; /**< 0x012C: TXRAM Uncorrectable Parity Error Address */
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uint32 RXOVRN_BUF_ADDR; /**< 0x0130: RXRAM Overrun Buffer Address */
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uint32 IOLPKTSTCR; /**< 0x0134: IO loopback */
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uint32 EXT_PRESCALE1; /**< 0x0138: */
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uint32 EXT_PRESCALE2; /**< 0x013C: */
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} mibspiBASE_t;
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/** @def mibspiREG1
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* @brief MIBSPI1 Register Frame Pointer
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*
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* This pointer is used by the MIBSPI driver to access the mibspi module registers.
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*/
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#define mibspiREG1 ((mibspiBASE_t *)0xFFF7F400U)
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/** @def mibspiPORT1
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* @brief MIBSPI1 GIO Port Register Pointer
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*
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* Pointer used by the GIO driver to access I/O PORT of MIBSPI1
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* (use the GIO drivers to access the port pins).
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*/
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#define mibspiPORT1 ((gioPORT_t *)0xFFF7F418U)
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/** @def mibspiREG3
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* @brief MIBSPI3 Register Frame Pointer
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*
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* This pointer is used by the MIBSPI driver to access the mibspi module registers.
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*/
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#define mibspiREG3 ((mibspiBASE_t *)0xFFF7F800U)
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/** @def mibspiPORT3
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* @brief MIBSPI3 GIO Port Register Pointer
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*
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* Pointer used by the GIO driver to access I/O PORT of MIBSPI3
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* (use the GIO drivers to access the port pins).
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*/
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#define mibspiPORT3 ((gioPORT_t *)0xFFF7F818U)
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/** @def mibspiREG5
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* @brief MIBSPI5 Register Frame Pointer
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*
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* This pointer is used by the MIBSPI driver to access the mibspi module registers.
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*/
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#define mibspiREG5 ((mibspiBASE_t *)0xFFF7FC00U)
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/** @def mibspiPORT5
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* @brief MIBSPI5 GIO Port Register Pointer
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*
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* Pointer used by the GIO driver to access I/O PORT of MIBSPI5
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* (use the GIO drivers to access the port pins).
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*/
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#define mibspiPORT5 ((gioPORT_t *)0xFFF7FC18U)
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/** @struct mibspiRamBase
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* @brief MIBSPI Buffer RAM Definition
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*
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* This structure is used to access the MIBSPI buffer memory.
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*/
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/** @typedef mibspiRAM_t
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* @brief MIBSPI RAM Type Definition
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*
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* This type is used to access the MIBSPI RAM.
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*/
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typedef volatile struct mibspiRamBase
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{
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struct
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{
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#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
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uint16 data; /**< tx buffer data */
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uint16 control; /**< tx buffer control */
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#else
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uint16 control; /**< tx buffer control */
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uint16 data; /**< tx buffer data */
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#endif
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} tx[128];
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struct
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{
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#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
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uint16 data; /**< rx buffer data */
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uint16 flags; /**< rx buffer flags */
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#else
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uint16 flags; /**< rx buffer flags */
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uint16 data; /**< rx buffer data */
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#endif
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} rx[128];
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} mibspiRAM_t;
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/** @def mibspiRAM1
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* @brief MIBSPI1 Buffer RAM Pointer
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*
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* This pointer is used by the MIBSPI driver to access the mibspi buffer memory.
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*/
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#define mibspiRAM1 ((mibspiRAM_t *)0xFF0E0000U)
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/** @def mibspiRAM3
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* @brief MIBSPI3 Buffer RAM Pointer
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*
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* This pointer is used by the MIBSPI driver to access the mibspi buffer memory.
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*/
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#define mibspiRAM3 ((mibspiRAM_t *)0xFF0C0000U)
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/** @def mibspiRAM5
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* @brief MIBSPI5 Buffer RAM Pointer
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*
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* This pointer is used by the MIBSPI driver to access the mibspi buffer memory.
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*/
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#define mibspiRAM5 ((mibspiRAM_t *)0xFF0A0000U)
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/** @def mibspiPARRAM1
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* @brief MIBSPI1 Buffer RAM PARITY Pointer
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*
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* This pointer is used by the MIBSPI driver to access the mibspi buffer memory.
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*/
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#define mibspiPARRAM1 (*(volatile uint32 *)(0xFF0E0000U + 0x00000400U))
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/** @def mibspiPARRAM3
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* @brief MIBSPI3 Buffer RAM PARITY Pointer
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*
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* This pointer is used by the MIBSPI driver to access the mibspi buffer memory.
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*/
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#define mibspiPARRAM3 (*(volatile uint32 *)(0xFF0C0000U + 0x00000400U))
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/** @def mibspiPARRAM5
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* @brief MIBSPI5 Buffer RAM PARITY Pointer
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*
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* This pointer is used by the MIBSPI driver to access the mibspi buffer memory.
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*/
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#define mibspiPARRAM5 (*(volatile uint32 *)(0xFF0A0000U + 0x00000400U))
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/* USER CODE BEGIN (1) */
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/* USER CODE END */
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#endif
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