f51bce3fed
We currently only support building with CCS and SCons is not using.
bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file.
You may need to regenerate the source file as you like, providing that:
1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The
channel 5 in enabled and connected to IRQ.
2, RTI driver is enabled and compare3 source is selected to counter1
and the compare3 will generate tick in the period of 10ms. This
value is coresponding with RT_TICK_PER_SECOND in rtconfig.h.
In CCS, you need to create a new CCS project and create link folders
pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember
to add the include path to the Build Properties.
98 lines
4.0 KiB
C
98 lines
4.0 KiB
C
/** @file reg_lin.h
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* @brief LIN Register Layer Header File
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* @date 23.May.2013
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* @version 03.05.01
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*
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* This file contains:
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* - Definitions
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* - Types
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* - Interface Prototypes
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* .
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* which are relevant for the LIN driver.
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*/
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/* (c) Texas Instruments 2009-2013, All rights reserved. */
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#ifndef __REG_LIN_H__
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#define __REG_LIN_H__
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#include "sys_common.h"
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#include "gio.h"
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/* USER CODE BEGIN (0) */
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/* USER CODE END */
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/* Lin Register Frame Definition */
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/** @struct linBase
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* @brief LIN Base Register Definition
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*
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* This structure is used to access the LIN module registers.
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*/
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/** @typedef linBASE_t
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* @brief LIN Register Frame Type Definition
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*
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* This type is used to access the LIN Registers.
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*/
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typedef volatile struct linBase
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{
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uint32 GCR0; /**< 0x0000: Global control register 0 */
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uint32 GCR1; /**< 0x0004: Global control register 1 */
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uint32 GCR2; /**< 0x0008: Global control register 2 */
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uint32 SETINT; /**< 0x000C: Set interrupt enable register */
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uint32 CLRINT; /**< 0x0010: Clear interrupt enable register */
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uint32 SETINTLVL; /**< 0x0014: Set interrupt level register */
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uint32 CLRINTLVL; /**< 0x0018: Set interrupt level register */
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uint32 FLR; /**< 0x001C: interrupt flag register */
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uint32 INTVECT0; /**< 0x0020: interrupt vector Offset 0 */
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uint32 INTVECT1; /**< 0x0024: interrupt vector Offset 1 */
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uint32 FORMAT; /**< 0x0028: Format Control Register */
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uint32 BRSR; /**< 0x002C: Baud rate selection register */
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uint32 ED; /**< 0x0030: Emulation register */
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uint32 RD; /**< 0x0034: Receive data register */
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uint32 TD; /**< 0x0038: Transmit data register */
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uint32 FUN; /**< 0x003C: Pin function register */
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uint32 DIR; /**< 0x0040: Pin direction register */
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uint32 DIN; /**< 0x0044: Pin data in register */
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uint32 DOUT; /**< 0x0048: Pin data out register */
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uint32 SET; /**< 0x004C: Pin data set register */
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uint32 CLR; /**< 0x0050: Pin data clr register */
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uint32 ODR; /**< 0x0054: Pin open drain output enable register */
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uint32 PD; /**< 0x0058: Pin pullup/pulldown disable register */
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uint32 PSL; /**< 0x005C: Pin pullup/pulldown selection register */
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uint32 COMP; /**< 0x0060: Compare register */
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uint8 RDx[8U]; /**< 0x0064-0x0068: RX buffer register */
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uint32 MASK; /**< 0x006C: Mask register */
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uint32 ID; /**< 0x0070: Identification Register */
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uint8 TDx[8U]; /**< 0x0074-0x0078: TX buffer register */
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uint32 MBRSR; /**< 0x007C: Maximum baud rate selection register */
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uint32 SL; /**< 0x0080: Pin slew rate register */
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uint32 rsvd1[3U]; /**< 0x0084: Reserved */
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uint32 IODFTCTRL; /**< 0x0090: IODFT loopback register */
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} linBASE_t;
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/** @def linREG
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* @brief LIN Register Frame Pointer
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*
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* This pointer is used by the LIN driver to access the lin module registers.
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*/
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#define linREG ((linBASE_t *)0xFFF7E400U)
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/** @def linPORT
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* @brief LIN GIO Port Register Pointer
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*
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* Pointer used by the GIO driver to access I/O PORT of LIN
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* (use the GIO drivers to access the port pins).
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*/
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#define linPORT ((gioPORT_t *)0xFFF7E440U)
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/* USER CODE BEGIN (1) */
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/* USER CODE END */
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#endif
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