f51bce3fed
We currently only support building with CCS and SCons is not using.
bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file.
You may need to regenerate the source file as you like, providing that:
1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The
channel 5 in enabled and connected to IRQ.
2, RTI driver is enabled and compare3 source is selected to counter1
and the compare3 will generate tick in the period of 10ms. This
value is coresponding with RT_TICK_PER_SECOND in rtconfig.h.
In CCS, you need to create a new CCS project and create link folders
pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember
to add the include path to the Build Properties.
95 lines
3.4 KiB
C
95 lines
3.4 KiB
C
/** @file reg_i2c.h
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* @brief I2C Register Layer Header File
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* @date 23.May.2013
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* @version 03.05.01
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*
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* This file contains:
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* - Definitions
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* - Types
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* - Interface Prototypes
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* .
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* which are relevant for the I2C driver.
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*/
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/* (c) Texas Instruments 2009-2013, All rights reserved. */
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#ifndef __REG_I2C_H__
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#define __REG_I2C_H__
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#include "sys_common.h"
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#include "gio.h"
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/* USER CODE BEGIN (0) */
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/* USER CODE END */
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/* I2c Register Frame Definition */
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/** @struct i2cBase
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* @brief I2C Base Register Definition
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*
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* This structure is used to access the I2C module registers.
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*/
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/** @typedef i2cBASE_t
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* @brief I2C Register Frame Type Definition
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*
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* This type is used to access the I2C Registers.
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*/
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typedef volatile struct i2cBase
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{
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uint32 OAR; /**< 0x0000 I2C Own Address register */
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uint32 IMR; /**< 0x0004 I2C Interrupt Mask/Status register */
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uint32 STR; /**< 0x0008 I2C Interrupt Status register */
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uint32 CLKL; /**< 0x000C I2C Clock Divider Low register */
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uint32 CLKH; /**< 0x0010 I2C Clock Divider High register */
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uint32 CNT; /**< 0x0014 I2C Data Count register */
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uint32 DRR; /**< 0x0018 I2C Data Receive register */
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uint32 SAR; /**< 0x001C I2C Slave Address register */
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uint32 DXR; /**< 0x0020 I2C Data Transmit register */
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uint32 MDR; /**< 0x0024 I2C Mode register */
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uint32 IVR; /**< 0x0028 I2C Interrupt Vector register */
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uint32 EMDR; /**< 0x002C I2C Extended Mode register */
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uint32 PSC; /**< 0x0030 I2C Prescaler register */
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uint32 PID11; /**< 0x0034 I2C Peripheral ID register 1 */
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uint32 PID12; /**< 0x0038 I2C Peripheral ID register 2 */
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uint32 DMAC; /**< 0x003C I2C DMA Control Register */
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uint32 rsvd1; /**< 0x0040 Reserved */
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uint32 rsvd2; /**< 0x0044 Reserved */
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uint32 FUN; /**< 0x0048 Pin Function Register */
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uint32 DIR; /**< 0x004C Pin Direction Register */
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uint32 DIN; /**< 0x0050 Pin Data In Register */
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uint32 DOUT; /**< 0x0054 Pin Data Out Register */
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uint32 SET; /**< 0x0058 Pin Data Set Register */
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uint32 CLR; /**< 0x005C Pin Data Clr Register */
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uint32 ODR; /**< 0x0060 Pin Open Drain Output Enable Register */
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uint32 PD; /**< 0x0064 Pin Pullup/Pulldown Disable Register */
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uint32 PSL; /**< 0x0068 Pin Pullup/Pulldown Selection Register */
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} i2cBASE_t;
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/** @def i2cREG1
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* @brief I2C Register Frame Pointer
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*
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* This pointer is used by the I2C driver to access the I2C module registers.
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*/
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#define i2cREG1 ((i2cBASE_t *)0xFFF7D400U)
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/* USER CODE BEGIN (1) */
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/* USER CODE END */
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/** @def i2cPORT1
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* @brief I2C GIO Port Register Pointer
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*
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* Pointer used by the GIO driver to access I/O PORT of I2C
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* (use the GIO drivers to access the port pins).
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*/
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#define i2cPORT1 ((gioPORT_t *)0xFFF7D44CU)
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/* USER CODE BEGIN (2) */
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/* USER CODE END */
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#endif
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