f51bce3fed
We currently only support building with CCS and SCons is not using.
bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file.
You may need to regenerate the source file as you like, providing that:
1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The
channel 5 in enabled and connected to IRQ.
2, RTI driver is enabled and compare3 source is selected to counter1
and the compare3 will generate tick in the period of 10ms. This
value is coresponding with RT_TICK_PER_SECOND in rtconfig.h.
In CCS, you need to create a new CCS project and create link folders
pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember
to add the include path to the Build Properties.
102 lines
2.5 KiB
C
102 lines
2.5 KiB
C
/** @file reg_htu.h
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* @brief HTU Register Layer Header File
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* @date 23.May.2013
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* @version 03.05.01
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*
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* This file contains:
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* - Definitions
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* - Types
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* - Interface Prototypes
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* .
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* which are relevant for the HTU driver.
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*/
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/* (c) Texas Instruments 2009-2013, All rights reserved. */
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#ifndef __REG_HTU_H__
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#define __REG_HTU_H__
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#include "sys_common.h"
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/* USER CODE BEGIN (0) */
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/* USER CODE END */
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/* htu Register Frame Definition */
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/** @struct htuBase
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* @brief HTU Base Register Definition
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*
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* This structure is used to access the HTU module registers.
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*/
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/** @typedef htuBASE_t
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* @brief HTU Register Frame Type Definition
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*
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* This type is used to access the HTU Registers.
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*/
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typedef volatile struct htuBase
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{
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uint32 GC; /** 0x00 */
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uint32 CPENA; /** 0x04 */
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uint32 BUSY0; /** 0x08 */
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uint32 BUSY1; /** 0x0C */
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uint32 BUSY2; /** 0x10 */
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uint32 BUSY3; /** 0x14 */
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uint32 ACPE; /** 0x18 */
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uint32 rsvd1; /** 0x1C */
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uint32 RLBECTRL; /** 0x20 */
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uint32 BFINTS; /** 0x24 */
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uint32 BFINTC; /** 0x28 */
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uint32 INTMAP; /** 0x2C */
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uint32 rsvd2; /** 0x30 */
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uint32 INTOFF0; /** 0x34 */
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uint32 INTOFF1; /** 0x38 */
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uint32 BIM; /** 0x3C */
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uint32 RLOSTFL; /** 0x40 */
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uint32 BFINTFL; /** 0x44 */
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uint32 BERINTFL; /** 0x48 */
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uint32 MP1S; /** 0x4C */
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uint32 MP1E; /** 0x50 */
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uint32 DCTRL; /** 0x54 */
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uint32 WPR; /** 0x58 */
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uint32 WMR; /** 0x5C */
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uint32 ID; /** 0x60 */
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uint32 PCR; /** 0x64 */
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uint32 PAR; /** 0x68 */
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uint32 rsvd3; /** 0x6C */
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uint32 MPCS; /** 0x70 */
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uint32 MP0S; /** 0x74 */
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uint32 MP0E; /** 0x78 */
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} htuBASE_t;
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typedef volatile struct htudcp
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{
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uint32 IFADDRA;
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uint32 IFADDRB;
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uint32 IHADDRCT;
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uint32 ITCOUNT;
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} htudcp_t;
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typedef volatile struct htucdcp
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{
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uint32 CFADDRA;
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uint32 CFADDRB;
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uint32 CFCOUNT;
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uint32 rsvd4;
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} htucdcp_t;
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#define htuREG1 ((htuBASE_t *)0xFFF7A400U)
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#define htuREG2 ((htuBASE_t *)0xFFF7A500U)
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#define htuDCP1 ((htudcp_t *)0xFF4E0000U)
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#define htuDCP2 ((htudcp_t *)0xFF4C0000U)
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#define htuCDCP1 ((htucdcp_t *)0xFF4E0100U)
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#define htuCDCP2 ((htucdcp_t *)0xFF4C0100U)
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/* USER CODE BEGIN (1) */
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/* USER CODE END */
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#endif
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