f51bce3fed
We currently only support building with CCS and SCons is not using.
bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file.
You may need to regenerate the source file as you like, providing that:
1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The
channel 5 in enabled and connected to IRQ.
2, RTI driver is enabled and compare3 source is selected to counter1
and the compare3 will generate tick in the period of 10ms. This
value is coresponding with RT_TICK_PER_SECOND in rtconfig.h.
In CCS, you need to create a new CCS project and create link folders
pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember
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153 lines
6.3 KiB
C
153 lines
6.3 KiB
C
/** @file reg_het.h
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* @brief HET Register Layer Header File
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* @date 23.May.2013
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* @version 03.05.01
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*
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* This file contains:
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* - Definitions
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* - Types
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* - Interface Prototypes
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* .
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* which are relevant for the HET driver.
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*/
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/* (c) Texas Instruments 2009-2013, All rights reserved. */
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#ifndef __REG_HET_H__
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#define __REG_HET_H__
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#include "sys_common.h"
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#include "gio.h"
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/* USER CODE BEGIN (0) */
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/* USER CODE END */
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/* Het Register Frame Definition */
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/** @struct hetBase
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* @brief HET Base Register Definition
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*
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* This structure is used to access the HET module registers.
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*/
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/** @typedef hetBASE_t
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* @brief HET Register Frame Type Definition
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*
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* This type is used to access the HET Registers.
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*/
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typedef volatile struct hetBase
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{
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uint32 GCR; /**< 0x0000: Global control register */
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uint32 PFR; /**< 0x0004: Prescale factor register */
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uint32 ADDR; /**< 0x0008: Current address register */
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uint32 OFF1; /**< 0x000C: Interrupt offset register 1 */
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uint32 OFF2; /**< 0x0010: Interrupt offset register 2 */
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uint32 INTENAS; /**< 0x0014: Interrupt enable set register */
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uint32 INTENAC; /**< 0x0018: Interrupt enable clear register */
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uint32 EXC1; /**< 0x001C: Exception control register 1 */
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uint32 EXC2; /**< 0x0020: Exception control register 2 */
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uint32 PRY; /**< 0x0024: Interrupt priority register */
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uint32 FLG; /**< 0x0028: Interrupt flag register */
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uint32 AND; /**< 0x002C: AND share control register */
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uint32 rsvd1; /**< 0x0030: Reserved */
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uint32 HRSH; /**< 0x0034: High resolution share register */
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uint32 XOR; /**< 0x0038: XOR share register */
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uint32 REQENS; /**< 0x003C: Request enable set register */
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uint32 REQENC; /**< 0x0040: Request enable clear register */
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uint32 REQDS; /**< 0x0044: Request destination select register */
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uint32 rsvd2; /**< 0x0048: Reserved */
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uint32 DIR; /**< 0x004C: Direction register */
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uint32 DIN; /**< 0x0050: Data input register */
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uint32 DOUT; /**< 0x0054: Data output register */
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uint32 DSET; /**< 0x0058: Data output set register */
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uint32 DCLR; /**< 0x005C: Data output clear register */
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uint32 PDR; /**< 0x0060: Open drain register */
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uint32 PULDIS; /**< 0x0064: Pull disable register */
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uint32 PSL; /**< 0x0068: Pull select register */
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uint32 rsvd3; /**< 0x006C: Reserved */
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uint32 rsvd4; /**< 0x0070: Reserved */
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uint32 PCR; /**< 0x0074: Parity control register */
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uint32 PAR; /**< 0x0078: Parity address register */
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uint32 PPR; /**< 0x007C: Parity pin select register */
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uint32 SFPRLD; /**< 0x0080: Suppression filter preload register */
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uint32 SFENA; /**< 0x0084: Suppression filter enable register */
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uint32 rsvd5; /**< 0x0088: Reserved */
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uint32 LBPSEL; /**< 0x008C: Loop back pair select register */
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uint32 LBPDIR; /**< 0x0090: Loop back pair direction register */
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uint32 PINDIS; /**< 0x0094: Pin disable register */
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uint32 rsvd6; /**< 0x0098: Reserved */
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uint32 HWAPINSEL;/**< 0x009C: HWAG Pin select register */
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uint32 HWAGCR0; /**< 0x00A0: HWAG Global control register 0 */
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uint32 HWAGCR1; /**< 0x00A4: HWAG Global control register 1 */
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uint32 HWAGCR2; /**< 0x00A8: HWAG Global control register 2 */
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uint32 HWAENASET;/**< 0x00AC: HWAG Interrupt enable set register */
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uint32 HWAENACLR;/**< 0x00B0: HWAG Interrupt enable clear register*/
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uint32 HWALVLSET;/**< 0x00B4: HWAG Interrupt level set register */
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uint32 HWALVLCLR;/**< 0x00B8: HWAG Interrupt level clear register */
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uint32 HWAFLG; /**< 0x00BC: HWAG Interrupt flag register */
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uint32 HWAOFF1; /**< 0x00C0: HWAG Interrupt offset 1 register */
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uint32 HWAOFF2; /**< 0x00C4: HWAG Interrupt offset 2 register */
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uint32 HWAACNT; /**< 0x00C8: HWAG Angle value register */
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uint32 HWAPCNT1; /**< 0x00CC: HWAG Period value register 1 */
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uint32 HWAPCNT; /**< 0x00D0: HWAG Period value register */
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uint32 HWASTWD; /**< 0x00D4: HWAG Step width register */
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uint32 HWATHNB; /**< 0x00D8: HWAG Teeth number register */
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uint32 HWATHVL; /**< 0x00DC: HWAG Teeth Value register */
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uint32 HWAFIL; /**< 0x00E0: HWAG Filter register */
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uint32 rsvd7; /**< 0x00E4: Reserved */
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uint32 HWAFIL2; /**< 0x00E8: HWAG Second filter register */
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uint32 rsvd8; /**< 0x00EC: Reserved */
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uint32 HWAANGI; /**< 0x00F0: HWAG Angle increment register */
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} hetBASE_t;
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/** @def hetREG1
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* @brief HET Register Frame Pointer
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*
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* This pointer is used by the HET driver to access the het module registers.
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*/
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#define hetREG1 ((hetBASE_t *)0xFFF7B800U)
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/** @def hetPORT1
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* @brief HET GIO Port Register Pointer
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*
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* Pointer used by the GIO driver to access I/O PORT of HET1
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* (use the GIO drivers to access the port pins).
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*/
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#define hetPORT1 ((gioPORT_t *)0xFFF7B84CU)
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/** @def hetREG2
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* @brief HET2 Register Frame Pointer
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*
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* This pointer is used by the HET driver to access the het module registers.
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*/
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#define hetREG2 ((hetBASE_t *)0xFFF7B900U)
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/** @def hetPORT2
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* @brief HET2 GIO Port Register Pointer
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*
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* Pointer used by the GIO driver to access I/O PORT of HET2
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* (use the GIO drivers to access the port pins).
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*/
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#define hetPORT2 ((gioPORT_t *)0xFFF7B94CU)
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#define hetRAM1 ((hetRAMBASE_t *)0xFF460000U)
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#define hetRAM2 ((hetRAMBASE_t *)0xFF440000U)
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#define NHET1RAMPARLOC (*(volatile uint32 *)0xFF462000U)
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#define NHET1RAMLOC (*(volatile uint32 *)0xFF460000U)
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#define NHET2RAMPARLOC (*(volatile uint32 *)0xFF442000U)
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#define NHET2RAMLOC (*(volatile uint32 *)0xFF440000U)
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/* USER CODE BEGIN (1) */
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/* USER CODE END */
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#endif
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