f51bce3fed
We currently only support building with CCS and SCons is not using.
bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file.
You may need to regenerate the source file as you like, providing that:
1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The
channel 5 in enabled and connected to IRQ.
2, RTI driver is enabled and compare3 source is selected to counter1
and the compare3 will generate tick in the period of 10ms. This
value is coresponding with RT_TICK_PER_SECOND in rtconfig.h.
In CCS, you need to create a new CCS project and create link folders
pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember
to add the include path to the Build Properties.
100 lines
2.7 KiB
C
100 lines
2.7 KiB
C
/** @file reg_gio.h
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* @brief GIO Register Layer Header File
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* @date 23.May.2013
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* @version 03.05.01
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*
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* This file contains:
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* - Definitions
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* - Types
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* - Interface Prototypes
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* .
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* which are relevant for the GIO driver.
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*/
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/* (c) Texas Instruments 2009-2013, All rights reserved. */
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#ifndef __REG_GIO_H__
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#define __REG_GIO_H__
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#include "sys_common.h"
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/* USER CODE BEGIN (0) */
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/* USER CODE END */
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/* Gio Register Frame Definition */
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/** @struct gioBase
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* @brief GIO Base Register Definition
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*
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* This structure is used to access the GIO module registers.
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*/
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/** @typedef gioBASE_t
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* @brief GIO Register Frame Type Definition
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*
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* This type is used to access the GIO Registers.
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*/
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typedef volatile struct gioBase
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{
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uint32 GCR0; /**< 0x0000: Global Control Register */
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uint32 PWDN; /**< 0x0004: Power Down Register */
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uint32 INTDET; /**< 0x0008: Interrupt Detect Register*/
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uint32 POL; /**< 0x000C: Interrupt Polarity Register */
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uint32 INTENASET; /**< 0x0010: Interrupt Enable Set Register */
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uint32 INTENACLR; /**< 0x0014: Interrupt Enable Clear Register */
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uint32 LVLSET; /**< 0x0018: Interrupt Priority Set Register */
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uint32 LVLCLR; /**< 0x001C: Interrupt Priority Clear Register */
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uint32 FLG; /**< 0x0020: Interrupt Flag Register */
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uint32 OFFSET0; /**< 0x0024: Interrupt Offset A Register */
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uint32 OFFSET1; /**< 0x0028: Interrupt Offset B Register */
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} gioBASE_t;
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/** @struct gioPort
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* @brief GIO Port Register Definition
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*/
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/** @typedef gioPORT_t
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* @brief GIO Port Register Type Definition
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*
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* This type is used to access the GIO Port Registers.
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*/
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typedef volatile struct gioPort
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{
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uint32 DIR; /**< 0x0000: Data Direction Register */
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uint32 DIN; /**< 0x0004: Data Input Register */
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uint32 DOUT; /**< 0x0008: Data Output Register */
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uint32 DSET; /**< 0x000C: Data Output Set Register */
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uint32 DCLR; /**< 0x0010: Data Output Clear Register */
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uint32 PDR; /**< 0x0014: Open Drain Register */
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uint32 PULDIS; /**< 0x0018: Pullup Disable Register */
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uint32 PSL; /**< 0x001C: Pull Up/Down Selection Register */
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} gioPORT_t;
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/** @def gioREG
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* @brief GIO Register Frame Pointer
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*
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* This pointer is used by the GIO driver to access the gio module registers.
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*/
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#define gioREG ((gioBASE_t *)0xFFF7BC00U)
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/** @def gioPORTA
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* @brief GIO Port (A) Register Pointer
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*
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* Pointer used by the GIO driver to access PORTA
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*/
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#define gioPORTA ((gioPORT_t *)0xFFF7BC34U)
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/** @def gioPORTB
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* @brief GIO Port (B) Register Pointer
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*
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* Pointer used by the GIO driver to access PORTB
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*/
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#define gioPORTB ((gioPORT_t *)0xFFF7BC54U)
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/* USER CODE BEGIN (1) */
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/* USER CODE END */
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#endif
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