f51bce3fed
We currently only support building with CCS and SCons is not using. bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file. You may need to regenerate the source file as you like, providing that: 1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The channel 5 in enabled and connected to IRQ. 2, RTI driver is enabled and compare3 source is selected to counter1 and the compare3 will generate tick in the period of 10ms. This value is coresponding with RT_TICK_PER_SECOND in rtconfig.h. In CCS, you need to create a new CCS project and create link folders pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember to add the include path to the Build Properties.
112 lines
3.4 KiB
C
112 lines
3.4 KiB
C
/** @file reg_flash.h
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* @brief Flash Register Layer Header File
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* @date 23.May.2013
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* @version 03.05.01
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*
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* This file contains:
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* - Definitions
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* - Types
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* .
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* which are relevant for the System driver.
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*/
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/* (c) Texas Instruments 2009-2013, All rights reserved. */
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#ifndef __REG_FLASH_H__
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#define __REG_FLASH_H__
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#include "sys_common.h"
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/* Flash Register Frame Definition */
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/** @struct flashWBase
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* @brief Flash Wrapper Register Frame Definition
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*
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* This type is used to access the Flash Wrapper Registers.
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*/
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/** @typedef flashWBASE_t
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* @brief Flash Wrapper Register Frame Type Definition
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*
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* This type is used to access the Flash Wrapper Registers.
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*/
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typedef volatile struct flashWBase
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{
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uint32 FRDCNTL; /* 0x0000 */
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uint32 FSPRD; /* 0x0004 */
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uint32 FEDACCTRL1; /* 0x0008 */
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uint32 FEDACCTRL2; /* 0x000C */
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uint32 FCORERRCNT; /* 0x0010 */
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uint32 FCORERRADD; /* 0x0014 */
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uint32 FCORERRPOS; /* 0x0018 */
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uint32 FEDACSTATUS; /* 0x001C */
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uint32 FUNCERRADD; /* 0x0020 */
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uint32 FEDACSDIS; /* 0x0024 */
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uint32 FPRIMADDTAG; /* 0x0028 */
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uint32 FREDUADDTAG; /* 0x002C */
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uint32 FBPROT; /* 0x0030 */
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uint32 FBSE; /* 0x0034 */
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uint32 FBBUSY; /* 0x0038 */
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uint32 FBAC; /* 0x003C */
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uint32 FBFALLBACK; /* 0x0040 */
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uint32 FBPRDY; /* 0x0044 */
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uint32 FPAC1; /* 0x0048 */
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uint32 FPAC2; /* 0x004C */
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uint32 FMAC; /* 0x0050 */
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uint32 FMSTAT; /* 0x0054 */
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uint32 FEMUDMSW; /* 0x0058 */
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uint32 FEMUDLSW; /* 0x005C */
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uint32 FEMUECC; /* 0x0060 */
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uint32 FLOCK; /* 0x0064 */
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uint32 FEMUADDR; /* 0x0068 */
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uint32 FDIAGCTRL; /* 0x006C */
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uint32 FRAWDATAH; /* 0x0070 */
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uint32 FRAWDATAL; /* 0x0074 */
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uint32 FRAWECC; /* 0x0078 */
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uint32 FPAROVR; /* 0x007C */
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uint32 FVREADCT; /* 0x0080 */
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uint32 FVHVCT1; /* 0x0084 */
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uint32 FVHVCT2; /* 0x0088 */
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uint32 FVNVCT; /* 0x008C */
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uint32 FVPPCT; /* 0x0090 */
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uint32 FVWLCT; /* 0x0094 */
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uint32 FEFUSE; /* 0x0098 */
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uint32 rsvd1[9U]; /* 0x009C */
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uint32 FEDACSDIS2; /* 0x00C0 */
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uint32 rsvd2[15U]; /* 0x00C4 */
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uint32 FBSTROBES; /* 0x0100 */
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uint32 FPSTROBES; /* 0x0104 */
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uint32 FBMODE; /* 0x0108 */
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uint32 FTCR; /* 0x010C */
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uint32 FADDR; /* 0x0110 */
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uint32 FWRITE; /* 0x0114 */
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uint32 FCBITSEL; /* 0x0118 */
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uint32 FTCTRL; /* 0x011C */
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uint32 FWPWRITE0; /* 0x0120 */
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uint32 FWPWRITE1; /* 0x0124 */
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uint32 FWPWRITE2; /* 0x0128 */
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uint32 FWPWRITE3; /* 0x012C */
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uint32 FWPWRITE4; /* 0x0130 */
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uint32 rsvd3[85U]; /* 0x0134 */
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uint32 FSMWRENA; /* 0x0288 */
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uint32 rsvd4[6U]; /* 0x028C */
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uint32 FSMSECTOR; /* 0x02A4 */
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uint32 rsvd5[4U]; /* 0x02A8 */
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uint32 EEPROMCONFIG;/* 0x02B8 */
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uint32 rsvd6[19U]; /* 0x02BC */
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uint32 EECTRL1; /* 0x0308 */
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uint32 EECTRL2; /* 0x030C */
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uint32 EECORRERRCNT;/* 0x0310 */
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uint32 EECORRERRADD;/* 0x0314 */
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uint32 EECORRERRPOS;/* 0x0318 */
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uint32 EESTATUS; /* 0x031C */
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uint32 EEUNCERRADD; /* 0x0320 */
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} flashWBASE_t;
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/** @def flashWREG
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* @brief Flash Wrapper Register Frame Pointer
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*
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* This pointer is used by the system driver to access the flash wrapper registers.
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*/
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#define flashWREG ((flashWBASE_t *)(0xFFF87000U))
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#endif
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