f51bce3fed
We currently only support building with CCS and SCons is not using.
bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file.
You may need to regenerate the source file as you like, providing that:
1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The
channel 5 in enabled and connected to IRQ.
2, RTI driver is enabled and compare3 source is selected to counter1
and the compare3 will generate tick in the period of 10ms. This
value is coresponding with RT_TICK_PER_SECOND in rtconfig.h.
In CCS, you need to create a new CCS project and create link folders
pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember
to add the include path to the Build Properties.
64 lines
2.0 KiB
C
64 lines
2.0 KiB
C
/** @file reg_efc.h
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* @brief EFC Register Layer Header File
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* @date 23.May.2013
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* @version 03.05.01
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*
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* This file contains:
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* - Definitions
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* - Types
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* .
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* which are relevant for the System driver.
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*/
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/* (c) Texas Instruments 2009-2013, All rights reserved. */
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#ifndef __REG_EFC_H__
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#define __REG_EFC_H__
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#include "sys_common.h"
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/* USER CODE BEGIN (0) */
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/* USER CODE END */
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/* Efc Register Frame Definition */
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/** @struct efcBase
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* @brief Efc Register Frame Definition
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*
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* This type is used to access the Efc Registers.
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*/
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/** @typedef efcBASE_t
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* @brief Efc Register Frame Type Definition
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*
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* This type is used to access the Efc Registers.
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*/
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typedef volatile struct efcBase
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{
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uint32 INSTRUCTION; /* 0x0 INSTRUCTION AN DUMPWORD REGISTER */
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uint32 ADDRESS; /* 0x4 ADDRESS REGISTER */
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uint32 DATA_UPPER; /* 0x8 DATA UPPER REGISTER */
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uint32 DATA_LOWER; /* 0xc DATA LOWER REGISTER */
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uint32 SYSTEM_CONFIG; /* 0x10 SYSTEM CONFIG REGISTER */
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uint32 SYSTEM_STATUS; /* 0x14 SYSTEM STATUS REGISTER */
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uint32 ACCUMULATOR; /* 0x18 ACCUMULATOR REGISTER */
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uint32 BOUNDARY; /* 0x1C BOUNDARY REGISTER */
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uint32 KEY_FLAG; /* 0x20 KEY FLAG REGISTER */
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uint32 KEY; /* 0x24 KEY REGISTER */
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uint32 rsvd1; /* 0x28 RESERVED */
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uint32 PINS; /* 0x2C PINS REGISTER */
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uint32 CRA; /* 0x30 CRA */
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uint32 READ; /* 0x34 READ REGISTER */
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uint32 PROGRAMME; /* 0x38 PROGRAMME REGISTER */
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uint32 ERROR; /* 0x3C ERROR STATUS REGISTER */
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uint32 SINGLE_BIT; /* 0x40 SINGLE BIT ERROR */
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uint32 TWO_BIT_ERROR; /* 0x44 DOUBLE BIT ERROR */
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uint32 SELF_TEST_CYCLES; /* 0x48 SELF TEST CYCLEX */
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uint32 SELF_TEST_SIGN; /* 0x4C SELF TEST SIGNATURE */
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} efcBASE_t;
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#define efcREG ((efcBASE_t *)0xFFF8C000U)
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/* USER CODE BEGIN (1) */
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/* USER CODE END */
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#endif
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