f51bce3fed
We currently only support building with CCS and SCons is not using.
bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file.
You may need to regenerate the source file as you like, providing that:
1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The
channel 5 in enabled and connected to IRQ.
2, RTI driver is enabled and compare3 source is selected to counter1
and the compare3 will generate tick in the period of 10ms. This
value is coresponding with RT_TICK_PER_SECOND in rtconfig.h.
In CCS, you need to create a new CCS project and create link folders
pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember
to add the include path to the Build Properties.
100 lines
4.0 KiB
C
100 lines
4.0 KiB
C
/** @file reg_dmm.h
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* @brief DMM Register Layer Header File
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* @date 23.May.2013
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* @version 03.05.01
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*
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* This file contains:
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* - Definitions
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* - Types
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* - Interface Prototypes
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* .
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* which are relevant for the DMM driver.
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*/
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/* (c) Texas Instruments 2009-2013, All rights reserved. */
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#ifndef __REG_DMM_H__
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#define __REG_DMM_H__
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#include "sys_common.h"
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#include "gio.h"
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/* USER CODE BEGIN (0) */
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/* USER CODE END */
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/* Dmm Register Frame Definition */
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/** @struct dmmBase
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* @brief DMM Base Register Definition
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*
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* This structure is used to access the DMM module registers.
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*/
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/** @typedef dmmBASE_t
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* @brief DMM Register Frame Type Definition
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*
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* This type is used to access the DMM Registers.
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*/
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typedef volatile struct dmmBase
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{
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uint32 GLBCTRL; /**< 0x0000: Global control register 0 */
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uint32 INTSET; /**< 0x0004: DMM Interrupt Set Register */
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uint32 INTCLR; /**< 0x0008: DMM Interrupt Clear Register */
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uint32 INTLVL; /**< 0x000C: DMM Interrupt Level Register */
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uint32 INTFLG; /**< 0x0010: DMM Interrupt Flag Register */
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uint32 OFF1; /**< 0x0014: DMM Interrupt Offset 1 Register */
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uint32 OFF2; /**< 0x0018: DMM Interrupt Offset 2 Register */
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uint32 DDMDEST; /**< 0x001C: DMM Direct Data Mode Destination Register */
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uint32 DDMBL; /**< 0x0020: DMM Direct Data Mode Blocksize Register */
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uint32 DDMPT; /**< 0x0024: DMM Direct Data Mode Pointer Register */
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uint32 INTPT; /**< 0x0028: DMM Direct Data Mode Interrupt Pointer Register */
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uint32 DEST0REG1; /**< 0x002C: DMM Destination 0 Region 1 */
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uint32 DEST0BL1; /**< 0x0030: DMM Destination 0 Blocksize 1 */
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uint32 DEST0REG2; /**< 0x0034: DMM Destination 0 Region 2 */
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uint32 DEST0BL2; /**< 0x0038: DMM Destination 0 Blocksize 2 */
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uint32 DEST1REG1; /**< 0x003C: DMM Destination 1 Region 1 */
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uint32 DEST1BL1; /**< 0x0040: DMM Destination 1 Blocksize 1 */
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uint32 DEST1REG2; /**< 0x0044: DMM Destination 1 Region 2 */
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uint32 DEST1BL2; /**< 0x0048: DMM Destination 1 Blocksize 2 */
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uint32 DEST2REG1; /**< 0x004C: DMM Destination 2 Region 1 */
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uint32 DEST2BL1; /**< 0x0050: DMM Destination 2 Blocksize 1 */
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uint32 DEST2REG2; /**< 0x0054: DMM Destination 2 Region 2 */
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uint32 DEST2BL2; /**< 0x0058: DMM Destination 2 Blocksize 2 */
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uint32 DEST3REG1; /**< 0x005C: DMM Destination 3 Region 1 */
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uint32 DEST3BL1; /**< 0x0060: DMM Destination 3 Blocksize 1 */
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uint32 DEST3REG2; /**< 0x0064: DMM Destination 3 Region 2 */
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uint32 DEST3BL2; /**< 0x0068: DMM Destination 3 Blocksize 2 */
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uint32 PC0; /**< 0x006C: DMM Pin Control 0 */
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uint32 PC1; /**< 0x0070: DMM Pin Control 1 */
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uint32 PC2; /**< 0x0074: DMM Pin Control 2 */
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uint32 PC3; /**< 0x0078: DMM Pin Control 3 */
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uint32 PC4; /**< 0x007C: DMM Pin Control 4 */
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uint32 PC5; /**< 0x0080: DMM Pin Control 5 */
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uint32 PC6; /**< 0x0084: DMM Pin Control 6 */
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uint32 PC7; /**< 0x0088: DMM Pin Control 7 */
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uint32 PC8; /**< 0x008C: DMM Pin Control 8 */
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} dmmBASE_t;
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/** @def dmmREG
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* @brief DMM Register Frame Pointer
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*
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* This pointer is used by the DMM driver to access the DMM module registers.
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*/
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#define dmmREG ((dmmBASE_t *)0xFFFFF700U)
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/** @def dmmPORT
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* @brief DMM Port Register Pointer
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*
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* Pointer used by the GIO driver to access I/O PORT of DMM
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* (use the GIO drivers to access the port pins).
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*/
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#define dmmPORT ((gioPORT_t *)0xFFFFF738U)
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/* USER CODE BEGIN (1) */
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/* USER CODE END */
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#endif
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