f51bce3fed
We currently only support building with CCS and SCons is not using.
bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file.
You may need to regenerate the source file as you like, providing that:
1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The
channel 5 in enabled and connected to IRQ.
2, RTI driver is enabled and compare3 source is selected to counter1
and the compare3 will generate tick in the period of 10ms. This
value is coresponding with RT_TICK_PER_SECOND in rtconfig.h.
In CCS, you need to create a new CCS project and create link folders
pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember
to add the include path to the Build Properties.
73 lines
1.9 KiB
C
73 lines
1.9 KiB
C
/** @file reg_dcc.h
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* @brief DCC Register Layer Header File
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* @date 23.May.2013
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* @version 03.05.01
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*
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* This file contains:
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* - Definitions
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* - Types
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* - Interface Prototypes
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* .
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* which are relevant for the DCC driver.
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*/
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/* (c) Texas Instruments 2009-2013, All rights reserved. */
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#ifndef __REG_DCC_H__
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#define __REG_DCC_H__
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#include "sys_common.h"
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/* USER CODE BEGIN (0) */
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/* USER CODE END */
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/* Dcc Register Frame Definition */
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/** @struct dccBase
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* @brief DCC Base Register Definition
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*
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* This structure is used to access the DCC module registers.
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*/
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/** @typedef dccBASE_t
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* @brief DCC Register Frame Type Definition
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*
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* This type is used to access the DCC Registers.
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*/
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typedef volatile struct dccBase
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{
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uint32 GCTRL; /**< 0x0000: DCC Control Register */
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uint32 REV; /**< 0x0004: DCC Revision Id Register */
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uint32 CNT0SEED; /**< 0x0008: DCC Counter0 Seed Register */
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uint32 VALID0SEED; /**< 0x000C: DCC Valid0 Seed Register */
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uint32 CNT1SEED; /**< 0x0010: DCC Counter1 Seed Register */
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uint32 STAT; /**< 0x0014: DCC Status Register */
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uint32 CNT0; /**< 0x0018: DCC Counter0 Value Register */
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uint32 VALID0; /**< 0x001C: DCC Valid0 Value Register */
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uint32 CNT1; /**< 0x0020: DCC Counter1 Value Register */
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uint32 CLKSRC1; /**< 0x0024: DCC Counter1 Clock Source Selection Register */
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uint32 CLKSRC0; /**< 0x0028: DCC Counter0 Clock Source Selection Register */
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} dccBASE_t;
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/** @def dccREG1
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* @brief DCC1 Register Frame Pointer
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*
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* This pointer is used by the DCC driver to access the dcc2 module registers.
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*/
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#define dccREG1 ((dccBASE_t *)0xFFFFEC00U)
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/** @def dccREG2
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* @brief DCC2 Register Frame Pointer
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*
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* This pointer is used by the DCC driver to access the dcc2 module registers.
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*/
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#define dccREG2 ((dccBASE_t *)0xFFFFF400U)
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/* USER CODE BEGIN (1) */
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/* USER CODE END */
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#endif
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