Grissiom f51bce3fed add rm48x50 bsp and libcpu
We currently only support building with CCS and SCons is not using.
bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file.
You may need to regenerate the source file as you like, providing that:

    1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The
    channel 5 in enabled and connected to IRQ.

    2, RTI driver is enabled and compare3 source is selected to counter1
    and the compare3 will generate tick in the period of 10ms. This
    value is coresponding with RT_TICK_PER_SECOND in rtconfig.h.

In CCS, you need to create a new CCS project and create link folders
pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember
to add the include path to the Build Properties.
2013-05-24 22:55:13 +08:00

46 lines
1.1 KiB
C

/** @file gio.h
* @brief GIO Driver Definition File
* @date 23.May.2013
* @version 03.05.01
*
*/
/* (c) Texas Instruments 2009-2013, All rights reserved. */
#ifndef __GIO_H__
#define __GIO_H__
#include "reg_gio.h"
/**
* @defgroup GIO GIO
* @brief General-Purpose Input/Output Module.
*
* The GIO module provides the family of devices with input/output (I/O) capability.
* The I/O pins are bidirectional and bit-programmable.
* The GIO module also supports external interrupt capability.
*
* Related Files
* - reg_gio.h
* - gio.h
* - gio.c
* @addtogroup GIO
* @{
*/
/* GIO Interface Functions */
void gioInit(void);
void gioSetDirection(gioPORT_t *port, uint32 dir);
void gioSetBit(gioPORT_t *port, uint32 bit, uint32 value);
void gioSetPort(gioPORT_t *port, uint32 value);
uint32 gioGetBit(gioPORT_t *port, uint32 bit);
uint32 gioGetPort(gioPORT_t *port);
void gioToggleBit(gioPORT_t *port, uint32 bit);
void gioEnableNotification(gioPORT_t *port, uint32 bit);
void gioDisableNotification(gioPORT_t *port, uint32 bit);
void gioNotification(gioPORT_t *port, sint32 bit);
/**@}*/
#endif