652 lines
21 KiB
C
652 lines
21 KiB
C
/*
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* Copyright : (C) 2022 Phytium Information Technology, Inc.
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* All Rights Reserved.
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it
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* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
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* either version 1.0 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the Phytium Public License for more details.
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*
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*
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* FilePath: fgdma.c
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* Date: 2022-02-10 14:53:42
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* LastEditTime: 2022-02-18 08:25:29
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* Description: This files is for
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*
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* Modify History:
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* Ver Who Date Changes
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* ----- ------ -------- --------------------------------------
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* 1.0 huanghe 2021-11-5 init commit
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* 1.1 zhugengyu 2022-5-16 support chan alloc. and qos setting
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*/
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/***************************** Include Files *********************************/
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#include <string.h>
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#include "fdebug.h"
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#include "fgdma_hw.h"
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#include "fgdma.h"
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/************************** Constant Definitions *****************************/
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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#define FGDMA_DEBUG_TAG "GDMA"
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#define FGDMA_ERROR(format, ...) FT_DEBUG_PRINT_E(FGDMA_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FGDMA_WARN(format, ...) FT_DEBUG_PRINT_W(FGDMA_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FGDMA_INFO(format, ...) FT_DEBUG_PRINT_I(FGDMA_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FGDMA_DEBUG(format, ...) FT_DEBUG_PRINT_D(FGDMA_DEBUG_TAG, format, ##__VA_ARGS__)
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/************************** Function Prototypes ******************************/
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static void FGdmaReset(FGdma *const instance_p);
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/************************** Variable Definitions *****************************/
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/*****************************************************************************/
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/**
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* @name: FGdmaCfgInitialize
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* @msg: 初始化GDMA控制器实例
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* @return {FError} 返回FGDMA_SUCCESS表示初始化成功，返回其它表示失败
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* @param FGdma *const instance_p, GDMA控制器实例
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* @param const FGdmaConfig *input_config, GDMA控制器配置
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*/
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FError FGdmaCfgInitialize(FGdma *const instance_p, const FGdmaConfig *input_config)
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{
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FASSERT(instance_p && input_config);
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uintptr base_addr = input_config->base_addr;
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FError ret = FGDMA_SUCCESS;
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if (FT_COMPONENT_IS_READY == instance_p->is_ready)
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{
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FGDMA_WARN("device is already initialized!!!");
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}
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FGdmaDeInitialize(instance_p);
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if (&instance_p->config != input_config)
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instance_p->config = *input_config;
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FASSERT_MSG((0 != base_addr), "invalid device base address");
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FGdmaReset(instance_p);
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if (FGDMA_SUCCESS == ret)
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{
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instance_p->is_ready = FT_COMPONENT_IS_READY;
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}
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return ret;
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}
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/**
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* @name: FGdmaDeInitialize
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* @msg: 去初始化GDMA控制器实例
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* @return {void} 无
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* @param FGdma *const instance_p, GDMA控制器实例
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*/
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void FGdmaDeInitialize(FGdma *const instance_p)
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{
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FASSERT(instance_p);
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u32 chan;
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for (chan = FGDMA_CHAN0_INDEX; chan < FGDMA_NUM_OF_CHAN; chan++)
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{
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if (NULL != instance_p->chans[chan])
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{
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FGDMA_WARN("chan-%d might be in use !!!", chan);
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}
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}
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memset(instance_p, 0, sizeof(*instance_p));
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return;
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}
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/**
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* @name: FGdmaSetChanQos
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* @msg: 设置GDMA通道的Qos配置
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* @return {void} 无
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* @param {uintptr} base_addr, GDMA控制器基地址
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* @param {FGdmaChan} *dma_chan, GDMA通道实例
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*/
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static void FGdmaSetChanQos(uintptr base_addr, FGdmaChan *const dma_chan)
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{
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FASSERT(dma_chan);
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FGdmaChanIndex chan_id = dma_chan->config.chan_id;
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u32 reg_val = FGDMA_READREG(base_addr, FGDMA_CHX_MODE_OFFSET(chan_id));
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FGdmaOperPriority prev_rd_qos = FGDMA_CHX_MODE_RD_QOS_GET(reg_val);
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FGdmaOperPriority prev_wr_qos = FGDMA_CHX_MODE_WR_QOS_GET(reg_val);
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FGDMA_INFO("prev rd qos: 0x%x, set rd qos: 0x%x", prev_rd_qos, dma_chan->config.rd_qos);
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FGDMA_INFO("prev wr qos: 0x%x, set wr qos: 0x%x", prev_wr_qos, dma_chan->config.wr_qos);
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if (prev_rd_qos != dma_chan->config.rd_qos) /* need to update rd qos */
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{
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/* replace with new rd qos config */
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reg_val &= ~FGDMA_CHX_MODE_RD_QOS_MASK;
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reg_val |= FGDMA_CHX_MODE_RD_QOS_EN |
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FGDMA_CHX_MODE_RD_QOS_SET(dma_chan->config.rd_qos);
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}
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if (prev_wr_qos != dma_chan->config.wr_qos) /* need to update wr qos */
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{
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/* replace with new wr qos config */
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reg_val &= ~FGDMA_CHX_MODE_WR_QOS_MASK;
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reg_val |= FGDMA_CHX_MODE_WR_QOS_EN |
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FGDMA_CHX_MODE_WR_QOS_SET(dma_chan->config.wr_qos);
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}
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FGDMA_WRITEREG(base_addr, FGDMA_CHX_MODE_OFFSET(chan_id), reg_val);
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return;
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}
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/**
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* @name: FGdmaAllocateChan
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* @msg: 分配指定GDMA通道
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* @return {FError} FGDMA_SUCCESS表示分配成功，返回其它值表示分配失败
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* @param FGdma *const instance_p, GDMA控制器实例
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* @param FGdmaChan *const dma_chan, GDMA通道实例
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* @param const FGdmaChanConfig *dma_chan_config, GDMA通道配置
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*/
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FError FGdmaAllocateChan(FGdma *const instance_p, FGdmaChan *const dma_chan,
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const FGdmaChanConfig *dma_chan_config)
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{
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FASSERT(instance_p);
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FASSERT(dma_chan);
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FASSERT(dma_chan_config);
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uintptr base_addr = instance_p->config.base_addr;
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FError ret = FGDMA_SUCCESS;
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FGdmaChanIndex chan_idx = dma_chan_config->chan_id;
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u32 reg_val;
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if (FT_COMPONENT_IS_READY != instance_p->is_ready)
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{
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FGDMA_ERROR("dma instance not init !!!");
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return FGDMA_ERR_NOT_INIT;
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}
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if (NULL != instance_p->chans[chan_idx])
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{
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FGDMA_ERROR("chan %d is in use !!!", chan_idx);
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return FGDMA_ERR_CHAN_IN_USE;
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}
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if (&dma_chan->config != dma_chan_config)
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dma_chan->config = *dma_chan_config;
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/* disable and reset chan */
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FGdmaChanDisable(base_addr, chan_idx);
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FGdmaChanReset(base_addr, chan_idx);
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/* enable channel clock */
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FGdmaSetChanClock(base_addr, chan_idx, TRUE);
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/* set chan mode */
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reg_val = FGDMA_READREG(base_addr, FGDMA_CHX_MODE_OFFSET(chan_idx));
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if (FGDMA_OPER_BDL == dma_chan->config.trans_mode)
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{
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FGDMA_INFO("set as BDL mode");
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reg_val |= FGDMA_CHX_MODE_BDL_EN;
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if (dma_chan->config.roll_back)
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{
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reg_val |= FGDMA_CHX_MODE_BDL_ROLL_EN; /* run BDL in roll-back mode */
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}
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else
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{
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reg_val &= ~FGDMA_CHX_MODE_BDL_ROLL_EN;
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}
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}
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else
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{
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FGDMA_INFO("set as Direct mode");
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reg_val &= ~FGDMA_CHX_MODE_BDL_EN;
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reg_val &= ~FGDMA_CHX_MODE_BDL_ROLL_EN;
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}
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FGDMA_WRITEREG(base_addr, FGDMA_CHX_MODE_OFFSET(chan_idx), reg_val);
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FGdmaSetChanQos(base_addr, dma_chan);
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FGDMA_INFO("mode: 0x%x", FGDMA_READREG(base_addr, FGDMA_CHX_MODE_OFFSET(chan_idx)));
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/* set xfer config */
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reg_val = 0;
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reg_val |= FGDMA_CHX_XFER_CFG_AR_LEN_SET(FGDMA_MAX_BURST_LEN) | /* burst length configed as max 8, which adapted when trans bytes less than 8 */
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FGDMA_CHX_XFER_CFG_AR_SIZE_SET((u32)dma_chan->config.rd_align) |
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FGDMA_CHX_XFER_CFG_AR_BRUST_SET(FGDMA_INCR); /* mem to mem trans work in incr mode */
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reg_val |= FGDMA_CHX_XFER_CFG_AW_LEN_SET(FGDMA_MAX_BURST_LEN) |
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FGDMA_CHX_XFER_CFG_AW_SIZE_SET((u32)dma_chan->config.wr_align) |
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FGDMA_CHX_XFER_CFG_AW_BRUST_SET(FGDMA_INCR); /* mem to mem trans work in incr mode */
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FGDMA_WRITEREG(base_addr, FGDMA_CHX_XFER_CFG_OFFSET(chan_idx), reg_val);
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FGDMA_INFO("xfer cfg: 0x%x", FGDMA_READREG(base_addr, FGDMA_CHX_XFER_CFG_OFFSET(chan_idx)));
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instance_p->chans[chan_idx] = dma_chan;
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dma_chan->gdma = instance_p;
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return ret;
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}
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/**
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* @name: FGdmaDellocateChan
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* @msg: 释放GDMA通道
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* @return {FError} FGDMA_SUCCESS表示处理成功
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* @param FGdmaChan *const dma_chan, GDMA通道实例
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*/
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FError FGdmaDellocateChan(FGdmaChan *const dma_chan)
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{
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FASSERT(dma_chan);
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FASSERT(dma_chan->gdma);
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FGdma *const instance_p = dma_chan->gdma;
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uintptr base_addr = instance_p->config.base_addr;
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FError ret = FGDMA_SUCCESS;
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FGdmaChanIndex chan_idx = dma_chan->config.chan_id;
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u32 reg_val;
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if (FT_COMPONENT_IS_READY != instance_p->is_ready)
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{
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FGDMA_ERROR("dma instance not init !!!");
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return FGDMA_ERR_NOT_INIT;
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}
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if (dma_chan != instance_p->chans[chan_idx])
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{
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FGDMA_ERROR("chan %d not bind !!!", chan_idx);
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return FGDMA_ERR_CHAN_NOT_INIT;
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}
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/* disable chan and it irq */
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FGdmaChanIrqDisable(base_addr, chan_idx);
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FGdmaChanDisable(base_addr, chan_idx);
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/* disable channel clock */
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FGdmaSetChanClock(base_addr, chan_idx, FALSE);
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instance_p->chans[chan_idx] = NULL;
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memset(dma_chan, 0, sizeof(*dma_chan));
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return ret;
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}
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/**
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* @name: FGdmaDirectTransfer
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* @msg: 直接操作模式下发起DMA传输
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* @return {FError} FGDMA_SUCCESS表示传输成功
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* @param FGdmaChan *const chan_p, GDMA通道实例
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* @param uintptr src_addr, 传输源地址
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* @param uintptr dst_addr, 传输目的地址
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*/
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FError FGdmaDirectTransfer(FGdmaChan *const chan_p, uintptr src_addr, uintptr dst_addr, fsize_t data_len)
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{
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FASSERT(chan_p);
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FASSERT(chan_p->gdma);
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u32 reg_val;
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FGdma *const instance_p = chan_p->gdma;
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uintptr base_addr = instance_p->config.base_addr;
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FGdmaChanIndex chan_idx = chan_p->config.chan_id;
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if (FT_COMPONENT_IS_READY != instance_p->is_ready)
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{
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FGDMA_ERROR("dma instance not init !!!");
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return FGDMA_ERR_NOT_INIT;
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}
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if ((src_addr % FGDMA_GET_BURST_SIZE(chan_p->config.rd_align)) ||
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(dst_addr % FGDMA_GET_BURST_SIZE(chan_p->config.wr_align)))
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{
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FGDMA_ERROR("src addr 0x%x or dst addr 0x%x not aligned with %d bytes",
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src_addr, dst_addr, FGDMA_ADDR_ALIGMENT);
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return FGDMA_ERR_INVALID_ADDR;
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}
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if (0 != (data_len % chan_p->config.wr_align))
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{
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FGDMA_ERROR("data length %d must be N times of burst size %d !!!",
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data_len, chan_p->config.wr_align);
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return FGDMA_ERR_INVALID_SIZE;
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}
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/* src address */
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#ifdef __aarch64__
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FGDMA_WRITEREG(base_addr, FGDMA_CHX_UPSADDR_OFFSET(chan_idx), UPPER_32_BITS(src_addr));
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FGDMA_WRITEREG(base_addr, FGDMA_CHX_LWSADDR_OFFSET(chan_idx), LOWER_32_BITS(src_addr));
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#else
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FGDMA_WRITEREG(base_addr, FGDMA_CHX_UPSADDR_OFFSET(chan_idx), 0x0U);
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FGDMA_WRITEREG(base_addr, FGDMA_CHX_LWSADDR_OFFSET(chan_idx), (u32)(src_addr));
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#endif
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FGDMA_INFO("src: 0x%x-0x%x",
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FGDMA_READREG(base_addr, FGDMA_CHX_UPSADDR_OFFSET(chan_idx)),
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FGDMA_READREG(base_addr, FGDMA_CHX_LWSADDR_OFFSET(chan_idx)));
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/* dest address */
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#ifdef __aarch64__
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FGDMA_WRITEREG(base_addr, FGDMA_CHX_UPDADDR_OFFSET(chan_idx), UPPER_32_BITS(dst_addr));
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FGDMA_WRITEREG(base_addr, FGDMA_CHX_LWDADDR_OFFSET(chan_idx), LOWER_32_BITS(dst_addr));
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#else
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FGDMA_WRITEREG(base_addr, FGDMA_CHX_UPDADDR_OFFSET(chan_idx), 0x0U);
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FGDMA_WRITEREG(base_addr, FGDMA_CHX_LWDADDR_OFFSET(chan_idx), (u32)(dst_addr));
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#endif
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FGDMA_INFO("dst: 0x%x-0x%x",
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FGDMA_READREG(base_addr, FGDMA_CHX_UPDADDR_OFFSET(chan_idx)),
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FGDMA_READREG(base_addr, FGDMA_CHX_LWDADDR_OFFSET(chan_idx)));
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/* num of BDL entry not used in direct mode */
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FGDMA_WRITEREG(base_addr, FGDMA_CHX_LVI_OFFSET(chan_idx), 0x0U);
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/* length of data to transfer */
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FGDMA_WRITEREG(base_addr, FGDMA_CHX_TS_OFFSET(chan_idx), data_len);
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FGDMA_INFO("ts: 0x%x", FGDMA_READREG(base_addr, FGDMA_CHX_TS_OFFSET(chan_idx)));
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/* enable channel interrupt */
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FGdmaChanIrqEnable(base_addr, chan_idx, FGDMA_CHX_INT_CTRL_TRANS_END_ENABLE);
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/* enable channel and start transfer */
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FGdmaChanEnable(base_addr, chan_idx);
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return FGDMA_SUCCESS;
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}
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/**
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* @name: FGdmaSetupBDLEntry
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* @msg: 设置BDL描述符的一个条目
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* @return {FError} FGDMA_SUCCESS 表示设置成功
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* @param FGdmaBdlDesc *desc_entry, 一条BDL描述符
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* @param uintptr src_addr, 传输源地址
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* @param uintptr dst_addr, 传输目的地址
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* @param fsize_t data_len, 传输数据长度
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*/
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FError FGdmaAppendBDLEntry(FGdmaChan *const chan_p, uintptr src_addr, uintptr dst_addr, fsize_t data_len)
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{
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FASSERT(chan_p);
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FASSERT_MSG((chan_p->config.descs) && (chan_p->config.total_desc_num > 0), "BDL descriptor list not yet assign !!!");
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u32 desc_idx = chan_p->config.valid_desc_num;
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FGdmaBdlDesc *desc_entry = &(chan_p->config.descs[desc_idx]);
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if (chan_p->config.valid_desc_num >= chan_p->config.total_desc_num)
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{
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FGDMA_ERROR("total BDL descriptor num is %d, already used up", chan_p->config.total_desc_num);
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return FGDMA_ERR_BDL_NOT_ENOUGH;
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}
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if ((0U != (dst_addr % FGDMA_GET_BURST_SIZE(chan_p->config.wr_align))) ||
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(0U != (src_addr % FGDMA_GET_BURST_SIZE(chan_p->config.rd_align))))
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{
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FGDMA_ERROR("src addr 0x%x or dst addr 0x%x not aligned with %d bytes",
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src_addr, dst_addr, FGDMA_GET_BURST_SIZE(chan_p->config.wr_align));
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return FGDMA_ERR_INVALID_ADDR;
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}
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if (0U != (data_len % chan_p->config.wr_align))
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{
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FGDMA_ERROR("data length %d must be N times of burst size %d !!!",
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data_len, chan_p->config.wr_align);
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return FGDMA_ERR_INVALID_SIZE;
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}
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#ifdef __aarch64___
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desc_entry->src_addr_h = UPPER_32_BITS(src_addr);
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desc_entry->src_addr_l = LOWER_32_BITS(src_addr);
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desc_entry->dst_addr_h = UPPER_32_BITS(dst_addr);
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desc_entry->dst_addr_l = LOWER_32_BITS(dst_addr);
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#else
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desc_entry->src_addr_h = 0U;
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desc_entry->src_addr_l = src_addr;
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desc_entry->dst_addr_h = 0U;
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desc_entry->dst_addr_l = dst_addr;
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#endif
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/* rd = src */
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desc_entry->src_tc = FGDMA_SRC_TC_BDL_BURST_SET(FGDMA_INCR) |
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FGDMA_SRC_TC_BDL_SIZE_SET((u32)chan_p->config.rd_align) |
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FGDMA_SRC_TC_BDL_LEN_SET(FGDMA_MAX_BURST_LEN);
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/* wr = dst */
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desc_entry->dst_tc = FGDMA_DST_TC_BDL_BURST_SET(FGDMA_INCR) |
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FGDMA_DST_TC_BDL_SIZE_SET((u32)chan_p->config.wr_align) |
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FGDMA_DST_TC_BDL_LEN_SET(FGDMA_MAX_BURST_LEN);
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desc_entry->total_bytes = data_len;
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desc_entry->ioc = 0U;
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chan_p->config.valid_desc_num++;
|
||
|
||
return FGDMA_SUCCESS;
|
||
}
|
||
|
||
/**
|
||
* @name: FGdmaBDLTransfer
|
||
* @msg: BDL操作模式下发起DMA传输
|
||
* @return {FError} FGDMA_SUCCESS 表示传输成功
|
||
* @param FGdmaChan *const chan_p, DMA通道实例
|
||
*/
|
||
FError FGdmaBDLTransfer(FGdmaChan *const chan_p)
|
||
{
|
||
FASSERT(chan_p);
|
||
FASSERT(chan_p->gdma);
|
||
FASSERT_MSG((chan_p->config.descs) && (chan_p->config.total_desc_num > 0), "BDL descriptor list not yet assign !!!");
|
||
u32 reg_val;
|
||
FGdma *const instance_p = chan_p->gdma;
|
||
uintptr base_addr = instance_p->config.base_addr;
|
||
FGdmaChanIndex chan_idx = chan_p->config.chan_id;
|
||
|
||
if (FT_COMPONENT_IS_READY != instance_p->is_ready)
|
||
{
|
||
FGDMA_ERROR("dma instance not init !!!");
|
||
return FGDMA_ERR_NOT_INIT;
|
||
}
|
||
|
||
if (0 == chan_p->config.valid_desc_num)
|
||
{
|
||
FGDMA_WARN("need to assign BDL entry fisrt !!!");
|
||
return FGDMA_SUCCESS;
|
||
}
|
||
|
||
if (((uintptr)(void *)chan_p->config.descs) % FGDMA_ADDR_ALIGMENT)
|
||
{
|
||
FGDMA_ERROR("BDL addr %p not aligned with %d bytes", chan_p->config.descs, FGDMA_ADDR_ALIGMENT);
|
||
return FGDMA_ERR_INVALID_ADDR;
|
||
}
|
||
|
||
u32 desc_idx = chan_p->config.valid_desc_num - 1;
|
||
FGdmaBdlDesc *descs = chan_p->config.descs; /* get the first BDL entry */
|
||
|
||
chan_p->config.descs[desc_idx].ioc = 1U; /* set as the last BDL entry */
|
||
|
||
/* src address, and dst address has been defined in BDL */
|
||
#ifdef __aarch64__
|
||
FGDMA_WRITEREG(base_addr, FGDMA_CHX_UPSADDR_OFFSET(chan_idx), UPPER_32_BITS((uintptr)descs));
|
||
FGDMA_WRITEREG(base_addr, FGDMA_CHX_LWSADDR_OFFSET(chan_idx), LOWER_32_BITS((uintptr)descs));
|
||
#else
|
||
FGDMA_WRITEREG(base_addr, FGDMA_CHX_UPSADDR_OFFSET(chan_idx), 0x0U);
|
||
FGDMA_WRITEREG(base_addr, FGDMA_CHX_LWSADDR_OFFSET(chan_idx), (u32)((uintptr)descs));
|
||
#endif
|
||
|
||
/* dst address not used in BDL mode */
|
||
FGDMA_WRITEREG(base_addr, FGDMA_CHX_UPDADDR_OFFSET(chan_idx), 0x0U);
|
||
FGDMA_WRITEREG(base_addr, FGDMA_CHX_LWDADDR_OFFSET(chan_idx), 0x0U);
|
||
|
||
/* ts not used in BDL mode */
|
||
FGDMA_WRITEREG(base_addr, FGDMA_CHX_TS_OFFSET(chan_idx), 0x0U);
|
||
|
||
/* num of BDL entry */
|
||
FGDMA_WRITEREG(base_addr, FGDMA_CHX_LVI_OFFSET(chan_idx), FGDMA_CHX_LVI_SET(chan_p->config.valid_desc_num));
|
||
|
||
/* enable channel interrupt */
|
||
FGdmaChanIrqEnable(base_addr, chan_idx, FGDMA_CHX_INT_CTRL_TRANS_END_ENABLE);
|
||
|
||
/* enable channel and start transfer */
|
||
FGdmaChanEnable(base_addr, chan_idx);
|
||
|
||
return FGDMA_SUCCESS;
|
||
}
|
||
|
||
/**
|
||
* @name: FGdmaStart
|
||
* @msg: 使能启动GDMA控制器
|
||
* @return {FError} FGDMA_SUCCESS表示启动成功
|
||
* @param FGdma *const instance_p, GDMA控制器实例
|
||
* @note: 先调用此函数，后调用FGdmaAllocateChan配置特定通道
|
||
*/
|
||
FError FGdmaStart(FGdma *const instance_p)
|
||
{
|
||
FASSERT(instance_p);
|
||
uintptr base_addr = instance_p->config.base_addr;
|
||
u32 reg_val;
|
||
|
||
if (FT_COMPONENT_IS_READY != instance_p->is_ready)
|
||
{
|
||
FGDMA_ERROR("dma instance not init !!!");
|
||
return FGDMA_ERR_NOT_INIT;
|
||
}
|
||
|
||
FGdmaIrqEnable(base_addr);
|
||
|
||
reg_val = FGDMA_READREG(base_addr, FGDMA_CTL_OFFSET);
|
||
reg_val &= ~FGDMA_CTL_OT_MASK;
|
||
reg_val |= FGDMA_CTL_OT_SET(FGDMA_OUTSTANDING); /* 设置传输outstanding数 */
|
||
reg_val |= FGDMA_CTL_ENABLE; /* 使能DMA传输 */
|
||
FGDMA_WRITEREG(base_addr, FGDMA_CTL_OFFSET, reg_val);
|
||
|
||
return FGDMA_SUCCESS; // 放到初始化
|
||
}
|
||
|
||
/**
|
||
* @name: FGdmaStop
|
||
* @msg: 停止GDMA控制器
|
||
* @return {FError} FGDMA_SUCCESS表示处理成功
|
||
* @param FGdma *const instance_p, GDMA控制器实例
|
||
*/
|
||
FError FGdmaStop(FGdma *const instance_p)
|
||
{
|
||
FASSERT(instance_p);
|
||
uintptr base_addr = instance_p->config.base_addr;
|
||
u32 reg_val;
|
||
u32 chan_id;
|
||
u32 chan_status;
|
||
|
||
if (FT_COMPONENT_IS_READY != instance_p->is_ready)
|
||
{
|
||
FGDMA_ERROR("dma instance not init !!!");
|
||
return FGDMA_ERR_NOT_INIT;
|
||
}
|
||
|
||
/* Abort 流程 */
|
||
for (chan_id = FGDMA_CHAN0_INDEX; chan_id < FGDMA_NUM_OF_CHAN; chan_id++)
|
||
{
|
||
if (NULL == instance_p->chans[chan_id])
|
||
continue; /* skip un-allocate channel */
|
||
|
||
chan_status = FGdmaReadChanStatus(base_addr, chan_id);
|
||
if (FGDMA_CHX_INT_STATE_BUSY & chan_status)
|
||
{
|
||
FGDMA_WARN("chan-%d has abort unfinished request !!!", chan_id);
|
||
FGdmaChanDisable(base_addr, chan_id); /* 关闭通道 */
|
||
FGdmaChanReset(base_addr, chan_id); /* 需要进行软复位，否则再次使能通道时，仍然会执行之前的请求 */
|
||
}
|
||
else
|
||
{
|
||
FGdmaChanDisable(base_addr, chan_id); /* 关闭通道 */
|
||
}
|
||
|
||
FGdmaClearChanStatus(base_addr, chan_id, chan_status); /* 清除通道状态 */
|
||
}
|
||
|
||
FGdmaDisable(base_addr);
|
||
|
||
return FGDMA_SUCCESS;
|
||
}
|
||
|
||
/**
|
||
* @name: FGdmaSetQos
|
||
* @msg: 设置GDMA控制器的全局Qos配置
|
||
* @return {void} 无
|
||
* @param {FGdma} *instance_p, GDMA控制器实例
|
||
*/
|
||
static void FGdmaSetQos(FGdma *const instance_p)
|
||
{
|
||
uintptr base_addr = instance_p->config.base_addr;
|
||
u32 reg_val;
|
||
|
||
/* enable/disable Qos */
|
||
reg_val = FGDMA_READREG(base_addr, FGDMA_CTL_OFFSET);
|
||
if (FGDMA_OPER_NONE_PRIORITY_POLL == instance_p->config.rd_qos) /* Poll mode */
|
||
{
|
||
reg_val &= ~FGDMA_CTL_RD_ARB;
|
||
}
|
||
else /* Qos mode */
|
||
{
|
||
reg_val |= FGDMA_CTL_RD_ARB;
|
||
}
|
||
|
||
if (FGDMA_OPER_NONE_PRIORITY_POLL == instance_p->config.wr_qos) /* Poll mode */
|
||
{
|
||
reg_val &= ~FGDMA_CTL_WR_ARB;
|
||
}
|
||
else /* Qos mode */
|
||
{
|
||
reg_val |= FGDMA_CTL_WR_ARB;
|
||
}
|
||
FGDMA_WRITEREG(base_addr, FGDMA_CTL_OFFSET, reg_val);
|
||
|
||
/* set Qos configure */
|
||
reg_val = FGDMA_READREG(base_addr, FGDMA_QOS_CFG_OFFSET);
|
||
if (FGDMA_OPER_NONE_PRIORITY_POLL == instance_p->config.rd_qos) /* Poll mode */
|
||
{
|
||
reg_val &= ~FGDMA_QOS_CFG_ARGOS_MASK;
|
||
}
|
||
else /* Qos value */
|
||
{
|
||
reg_val |= FGDMA_QOS_CFG_ARGOS_SET((u32)instance_p->config.rd_qos);
|
||
}
|
||
|
||
if (FGDMA_OPER_NONE_PRIORITY_POLL == instance_p->config.wr_qos) /* Poll mode */
|
||
{
|
||
reg_val &= ~FGDMA_QOS_CFG_AWQOS_MASK;
|
||
}
|
||
else /* Qos value */
|
||
{
|
||
reg_val |= FGDMA_QOS_CFG_AWQOS_SET((u32)instance_p->config.wr_qos);
|
||
}
|
||
FGDMA_WRITEREG(base_addr, FGDMA_QOS_CFG_OFFSET, reg_val);
|
||
|
||
return;
|
||
}
|
||
|
||
/**
|
||
* @name: FGdmaReset
|
||
* @msg: 重置GDMA控制器
|
||
* @return {void} 无
|
||
* @param {FGdma} *instance_p, GDMA控制器实例
|
||
*/
|
||
static void FGdmaReset(FGdma *const instance_p)
|
||
{
|
||
uintptr base_addr = instance_p->config.base_addr;
|
||
u32 chan;
|
||
u32 reg_val;
|
||
|
||
FGDMA_INFO("reset ctrl @0x%x ...", base_addr);
|
||
|
||
FGdmaDisable(base_addr);
|
||
FGdmaSoftwareReset(base_addr);
|
||
|
||
FGdmaSetQos(instance_p);
|
||
|
||
FGDMA_INFO("reset chan ...");
|
||
|
||
for (chan = FGDMA_CHAN0_INDEX; chan < FGDMA_NUM_OF_CHAN; chan++)
|
||
{
|
||
FGdmaChanDisable(base_addr, chan);
|
||
FGdmaChanIrqDisable(base_addr, chan);
|
||
FGdmaChanReset(base_addr, chan);
|
||
FGdmaSetChanClock(base_addr, chan, FALSE);
|
||
}
|
||
|
||
return;
|
||
} |