158 lines
5.7 KiB
C
158 lines
5.7 KiB
C
/***************************************************************************//**
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* \file cybsp.c
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*
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* Description:
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* Provides initialization code for starting up the hardware contained on the
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* Infineon board.
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*
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********************************************************************************
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* \copyright
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* Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
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* an affiliate of Cypress Semiconductor Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*******************************************************************************/
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#include <stdlib.h>
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#include "cy_syspm.h"
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#include "cy_sysclk.h"
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#include "cybsp.h"
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#if defined(CY_USING_HAL)
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#include "cyhal_hwmgr.h"
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#include "cyhal_syspm.h"
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#if defined(CYBSP_WIFI_CAPABLE) && defined(CYHAL_UDB_SIO)
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#include "SDIO_HOST.h"
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#endif
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#endif // defined(CY_USING_HAL)
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#if defined(COMPONENT_MW_CAT1CM0P)
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#include "mtb_cat1cm0p.h"
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#endif
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#if defined(__cplusplus)
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extern "C" {
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#endif
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// The sysclk deep sleep callback is recommended to be the last callback that is executed before
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// entry into deep sleep mode and the first one upon exit the deep sleep mode.
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// Doing so minimizes the time spent on low power mode entry and exit.
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#ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER
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#define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u)
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#endif
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#if !defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK)
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//--------------------------------------------------------------------------------------------------
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// cybsp_register_sysclk_pm_callback
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//
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// Registers a power management callback that prepares the clock system for entering deep sleep mode
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// and restore the clocks upon wakeup from deep sleep.
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// NOTE: This is called automatically as part of \ref cybsp_init
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//--------------------------------------------------------------------------------------------------
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static cy_rslt_t cybsp_register_sysclk_pm_callback(void)
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{
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cy_rslt_t result = CY_RSLT_SUCCESS;
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static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = { NULL, NULL };
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static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback =
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{
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.callback = &Cy_SysClk_DeepSleepCallback,
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.type = CY_SYSPM_DEEPSLEEP,
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.callbackParams = &cybsp_sysclk_pm_callback_param,
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.order = CYBSP_SYSCLK_PM_CALLBACK_ORDER
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};
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if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback))
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{
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result = CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK;
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}
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return result;
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}
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#endif // if !defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK)
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//--------------------------------------------------------------------------------------------------
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// cybsp_init
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//--------------------------------------------------------------------------------------------------
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cy_rslt_t cybsp_init(void)
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{
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// Setup hardware manager to track resource usage then initialize all system (clock/power) board
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// configuration
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#if defined(CY_USING_HAL)
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cy_rslt_t result = cyhal_hwmgr_init();
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if (CY_RSLT_SUCCESS == result)
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{
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result = cyhal_syspm_init();
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}
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#ifdef CY_CFG_PWR_VDDA_MV
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if (CY_RSLT_SUCCESS == result)
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{
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cyhal_syspm_set_supply_voltage(CYHAL_VOLTAGE_SUPPLY_VDDA, CY_CFG_PWR_VDDA_MV);
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}
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#endif
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#else // if defined(CY_USING_HAL)
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cy_rslt_t result = CY_RSLT_SUCCESS;
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#endif // if defined(CY_USING_HAL)
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// By default, the peripheral configuration will be done on the first core running user code.
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// This is the CM0+ if it is available and not running a pre-built image, and the CM4 otherwise.
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// This is done to ensure configuration is available for all cores that might need to use it.
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// In the case of a dual core project, this can be changed below to perform initialization on
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// the CM4 if necessary.
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#if defined(CORE_NAME_CM0P_0) || !(__CM0P_PRESENT) || (defined(CORE_NAME_CM4_0) && \
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defined(CY_USING_PREBUILT_CM0P_IMAGE))
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cycfg_config_init();
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#endif
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// Do any additional configuration reservations that are needed on all cores.
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cycfg_config_reservations();
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if (CY_RSLT_SUCCESS == result)
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{
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#if defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK)
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result = cybsp_register_custom_sysclk_pm_callback();
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#else
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result = cybsp_register_sysclk_pm_callback();
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#endif
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}
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#if defined(CYBSP_WIFI_CAPABLE) && defined(CYHAL_UDB_SIO)
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// Reserve resources for the UDB SDIO interface that might want to be used by others. This
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// includes specific clock and DMA instances. This must be done before other HAL API calls as
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// specific peripheral instances are needed
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// NOTE: The full SDIO/WiFi interface still needs to be initialized via
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// cybsp_wifi_init_primary(). This is typically done when starting up WiFi.
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if (CY_RSLT_SUCCESS == result)
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{
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result = SDIO_ReserveResources();
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}
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#endif // defined(CYBSP_WIFI_CAPABLE) && defined(CYHAL_UDB_SIO)
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// CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was
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// reserved by user previously. Please review the Device Configurator (design.modus) and the BSP
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// reservation list (cyreservedresources.list) to make sure no resources are reserved by both.
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return result;
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}
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#if defined(__cplusplus)
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}
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#endif
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