171 lines
4.8 KiB
C
171 lines
4.8 KiB
C
/*
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* File : board.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2012, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2012-11-20 Bernard the first version
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include "board.h"
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#include <interrupt.h>
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#ifdef RT_USING_VMM
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#include <vmm.h>
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static rt_uint32_t DMTIMER = 0;
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#define TIMER_HW_BASE (DMTIMER)
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#else
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#define TIMER_HW_BASE AM33XX_DMTIMER_7_REGS
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#endif
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#define DMTIMER_TCLR_AR (0x00000002u)
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#define DMTIMER_TCLR_CE (0x00000040u)
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#define DMTIMER_TCLR_PRE (0x00000020u)
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#define DMTIMER_TCLR_ST (0x00000001u)
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#define DMTIMER_IRQENABLE_SET_OVF_EN_FLAG (0x00000002u)
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#define DMTIMER_IRQSTATUS_RAW_OVF_IT_FLAG (0x00000002u)
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#define CM_DPLL_CLKSEL_CLK_CLKSEL (0x00000003u)
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#define CM_DPLL_CLKSEL_CLK_CLKSEL_SEL3 (0x2u)
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#define CM_PER_CLKCTRL_MODULEMODE_ENABLE (0x2u)
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#define CM_PER_CLKCTRL_MODULEMODE (0x00000003u)
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#define CM_PER_CLKCTRL_IDLEST (0x00030000u)
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#define CM_PER_CLKCTRL_IDLEST_FUNC (0x0u)
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#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK (0x00000100u)
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#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER2_GCLK (0x00004000u)
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#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER7_GCLK (1<<13)
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static void rt_hw_timer_isr(int vector, void* param)
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{
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rt_tick_increase();
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DMTIMER_IRQSTATUS(TIMER_HW_BASE) = DMTIMER_IRQSTATUS_RAW_OVF_IT_FLAG;
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}
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static void timer_clk_init(void)
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{
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unsigned long prcm_base;
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#ifdef RT_USING_VMM
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prcm_base = vmm_find_iomap("PRCM");
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#else
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prcm_base = AM33XX_PRCM_REGS;
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#endif
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/* software forced wakeup */
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CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) |= 0x2;
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/* Waiting for the L4LS clock */
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while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & (1<<8)))
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;
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/* Select the clock source for the Timer2 instance. */
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CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) &= ~(CM_DPLL_CLKSEL_CLK_CLKSEL);
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/* 32k clock source */
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CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) |= CM_DPLL_CLKSEL_CLK_CLKSEL_SEL3;
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while ((CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) & CM_DPLL_CLKSEL_CLK_CLKSEL) !=
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CM_DPLL_CLKSEL_CLK_CLKSEL_SEL3);
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/* Writing to MODULEMODE field of CM_PER_TIMER7_CLKCTRL register. */
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CM_PER_TIMER7_CLKCTRL(prcm_base) |= CM_PER_CLKCTRL_MODULEMODE_ENABLE;
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/* Waiting for MODULEMODE field to reflect the written value. */
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while ((CM_PER_TIMER7_CLKCTRL(prcm_base) & CM_PER_CLKCTRL_MODULEMODE) !=
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CM_PER_CLKCTRL_MODULEMODE_ENABLE);
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/*
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* Waiting for IDLEST field in CM_PER_TIMER7_CLKCTRL register
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* for the module is fully functional.
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*/
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while ((CM_PER_TIMER7_CLKCTRL(prcm_base) & CM_PER_CLKCTRL_IDLEST) !=
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CM_PER_CLKCTRL_IDLEST_FUNC);
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/* Waiting for the L4LS clock */
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while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK));
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/* Waiting for the TIMER7 clock */
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while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER7_GCLK));
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}
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int rt_hw_timer_init(void)
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{
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rt_uint32_t counter;
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#ifdef RT_USING_VMM
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DMTIMER = vmm_find_iomap("TIMER7");
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#endif
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timer_clk_init();
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/* soft reset the timer */
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DMTIMER_TIOCP_CFG(TIMER_HW_BASE) |= 1;
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while ((DMTIMER_TIOCP_CFG(TIMER_HW_BASE) & 0x1) == 1)
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;
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/* calculate count */
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counter = 0xffffffff - (32768UL/RT_TICK_PER_SECOND);
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/* set initial count */
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DMTIMER_TCRR(TIMER_HW_BASE) = counter;
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/* set reload count */
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DMTIMER_TLDR(TIMER_HW_BASE) = counter;
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/* set mode: auto reload */
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DMTIMER_TCLR(TIMER_HW_BASE) |= DMTIMER_TCLR_AR;
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/* interrupt enable for match */
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DMTIMER_IRQENABLE_SET(TIMER_HW_BASE) = DMTIMER_IRQENABLE_SET_OVF_EN_FLAG;
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DMTIMER_IRQSTATUS(TIMER_HW_BASE) = DMTIMER_IRQSTATUS_RAW_OVF_IT_FLAG;
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rt_hw_interrupt_install(TINT7, rt_hw_timer_isr, RT_NULL, "tick");
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rt_hw_interrupt_control(TINT7, 0, 0);
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rt_hw_interrupt_umask(TINT7);
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while (DMTIMER_TWPS(TIMER_HW_BASE) != 0)
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;
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/* start timer */
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DMTIMER_TCLR(TIMER_HW_BASE) |= DMTIMER_TCLR_ST;
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while (DMTIMER_TWPS(TIMER_HW_BASE) != 0)
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;
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return 0;
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}
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INIT_BOARD_EXPORT(rt_hw_timer_init);
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/**
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* This function will initialize beaglebone board
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*/
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void rt_hw_board_init(void)
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{
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rt_components_board_init();
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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}
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void rt_hw_cpu_reset(void)
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{
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unsigned long prcm_base;
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#ifdef RT_USING_VMM
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prcm_base = vmm_find_iomap("PRCM");
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#else
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prcm_base = AM33XX_PRCM_REGS;
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#endif
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REG32(PRM_DEVICE(prcm_base)) = 0x1;
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RT_ASSERT(0);
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}
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FINSH_FUNCTION_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reboot the cpu);
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FINSH_FUNCTION_EXPORT_ALIAS(rt_hw_cpu_reset, __cmd_reboot, reboot the cpu);
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