1132 lines
37 KiB
C
1132 lines
37 KiB
C
/**
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******************************************************************************
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* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup GD32f10x_system
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* @{
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*/
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/** @addtogroup GD32f10x_System_Private_Includes
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* @{
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*/
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#include "gd32f10x.h"
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/**
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* @}
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*/
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/** @addtogroup GD32f10x_System_Private_Variables
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* @{
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*/
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/* Uncomment the corresponding line to configure system clock that you need */
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/* The clock is from HSE oscillator clock */
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//#define SYSCLK_FREQ_HSE HSE_VALUE
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//#define SYSCLK_FREQ_24MHz 24000000
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//#define SYSCLK_FREQ_36MHz 36000000
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//#define SYSCLK_FREQ_48MHz 48000000
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//#define SYSCLK_FREQ_56MHz 56000000
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//#define SYSCLK_FREQ_72MHz 72000000
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//#define SYSCLK_FREQ_96MHz 96000000
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#define SYSCLK_FREQ_108MHz 108000000
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/* Uncomment the corresponding line to configure system clock that you need */
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/* The clock is from HSI oscillator clock */
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//#define SYSCLK_FREQ_48MHz_HSI 48000000
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//#define SYSCLK_FREQ_72MHz_HSI 72000000
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//#define SYSCLK_FREQ_108MHz_HSI 108000000
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/* ---------------------- RCC registers mask -------------------------------- */
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/* RCC GCCR_HSIEN mask */
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#define SYS_GCCR_HSIEN_SET ((uint32_t)0x00000001)
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/* RCC GCFGR_Reset mask */
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#define SYS_GCFGR_RESET_CL ((uint32_t)0xE0FF0000)
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#define SYS_GCFGR_RESET ((uint32_t)0xE8FF0000)
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/* RCC GCCR_HSEEN_CKMEN_PLLEN masks */
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#define SYS_GCCR_HSEEN_CKMEN_PLLEN_RESET ((uint32_t)0xFEF6FFFF)
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/* RCC GCCR_HSEBPS mask */
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#define SYS_GCCR_HSEBPS_RESET ((uint32_t)0xFFFBFFFF)
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/* RCC GCFGR_PLLSEL_PLLPREDV_PLLMF masks */
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#define SYS_GCFGR_PLLSEL_PLLPREDV_PLLMF_USBPS_RESET ((uint32_t)0xF700FFFF)
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#define SYS_GCFGR_PLLSEL_PLLPREDV_PLLMF_USBPS_RESET_CL ((uint32_t)0xDF00FFFF)
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/* RCC GCCR_PLL2EN_PLL3EN masks */
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#define SYS_GCCR_PLL2EN_PLL3EN_RESET ((uint32_t)0xEBFFFFFF)
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/* RCC GCFGR2 reset */
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#define SYS_GCFGR2_RESET ((uint32_t)0x00000000)
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/* RCC GCIR_INT ans FLAG masks */
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#define SYS_GCIR_INT_FLAG_RESET ((uint32_t)0x009F0000)
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#define SYS_GCIR_INT_FLAG_RESET_CL ((uint32_t)0x00FF0000)
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#define SYS_GCCR_HSEEN_HSEBPS_RESET ((uint32_t)0xFFF8FFFF)
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/* RCC GCCR_HSIADJ masks */
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#define SYS_GCCR_HSIADJ_OFFSET ((uint32_t)0x00000003)
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#define SYS_RCC_GCFGR_PLLMF_3_0 ((uint32_t)0x003C0000) /*!< PLLMF[3:0] Bits */
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/* RCC HSI clock divided by 2 masks */
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#define SYS_HSI_CLOCK_DIVIDED_2 ((uint32_t)0x00000001)
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/**
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* @}
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*/
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/** @addtogroup GD32F10x_System_Private_Variables
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* @{
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*/
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/*******************************************************************************
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* System Clock Select
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*******************************************************************************/
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#ifdef SYSCLK_FREQ_HSE
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uint32_t SystemCoreClock = SYSCLK_FREQ_HSE;
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#elif defined SYSCLK_FREQ_24MHz
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uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz;
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#elif defined SYSCLK_FREQ_36MHz
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uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz;
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#elif defined SYSCLK_FREQ_48MHz
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uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz;
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#elif defined SYSCLK_FREQ_56MHz
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uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz;
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#elif defined SYSCLK_FREQ_72MHz
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uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz;
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#elif defined SYSCLK_FREQ_96MHz
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uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz;
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#elif defined SYSCLK_FREQ_108MHz
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uint32_t SystemCoreClock = SYSCLK_FREQ_108MHz;
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#elif defined SYSCLK_FREQ_48MHz_HSI
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uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI;
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#elif defined SYSCLK_FREQ_72MHz_HSI
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uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSI;
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#elif defined SYSCLK_FREQ_108MHz_HSI
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uint32_t SystemCoreClock = SYSCLK_FREQ_108MHz_HSI;
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#else /*!< HSI Selected as System Clock source */
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uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */
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#endif
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__I uint8_t AHBPrescTableList[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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/**
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* @}
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*/
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/** @addtogroup GD32f10x_System_Private_FunctionPrototypes
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* @{
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*/
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static void SetSysClock(void);
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#ifdef SYSCLK_FREQ_HSE
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static void SetSysClockToHSE(void);
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#elif defined SYSCLK_FREQ_24MHz
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static void SetSysClockTo24(void);
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#elif defined SYSCLK_FREQ_36MHz
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static void SetSysClockTo36(void);
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#elif defined SYSCLK_FREQ_48MHz
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static void SetSysClockTo48(void);
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#elif defined SYSCLK_FREQ_56MHz
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static void SetSysClockTo56(void);
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#elif defined SYSCLK_FREQ_72MHz
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static void SetSysClockTo72(void);
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#elif defined SYSCLK_FREQ_96MHz
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static void SetSysClockTo96(void);
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#elif defined SYSCLK_FREQ_108MHz
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static void SetSysClockTo108(void);
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#elif defined SYSCLK_FREQ_48MHz_HSI
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static void SetSysClockTo48HSI(void);
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#elif defined SYSCLK_FREQ_72MHz_HSI
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static void SetSysClockTo72HSI(void);
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#elif defined SYSCLK_FREQ_108MHz_HSI
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static void SetSysClockTo108HSI(void);
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#endif
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/**
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* @}
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*/
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/** @addtogroup GD32f10x_System_Private_Functions
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* @{
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*/
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/**
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* @brief Initialize the Embedded Flash Interface, the PLL and set the
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* SystemCoreClock variable.
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* @param None
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* @retval None
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*/
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void SystemInit(void)
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{
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/* Set RCC GCCR_HSIEN mask */
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RCC->GCCR |= SYS_GCCR_HSIEN_SET;
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/* Reset SCS[1:0], AHBPS[3:0], APB1PS[2:0],APB2PS[2:0], ADCPS[2:0],CKOTUSEL[2:0] bits */
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#ifdef GD32F10X_CL
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RCC->GCFGR &= SYS_GCFGR_RESET_CL;
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#else
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RCC->GCFGR &= SYS_GCFGR_RESET;
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#endif /* GD32F10X_CL */
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/* Reset HSEEN, CKMEN and PLLEN bits */
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RCC->GCCR &= SYS_GCCR_HSEEN_CKMEN_PLLEN_RESET;
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/* Reset HSEBPS bit */
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RCC->GCCR &= SYS_GCCR_HSEBPS_RESET;
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/* Reset PLLSEL, PLLPREDV and PLLMF[4:0] USBPS/OTGPS bits */
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#ifdef GD32F10X_CL
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RCC->GCFGR &= SYS_GCFGR_PLLSEL_PLLPREDV_PLLMF_USBPS_RESET_CL;
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#else
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RCC->GCFGR &= SYS_GCFGR_PLLSEL_PLLPREDV_PLLMF_USBPS_RESET;
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#endif /* GD32F10X_CL */
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#ifdef GD32F10X_CL
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/* Reset PLL2EN and PLL3EN bits */
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RCC->GCCR &= SYS_GCCR_PLL2EN_PLL3EN_RESET;
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/* Reset GCFGR2 register */
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RCC->GCFGR2 = SYS_GCFGR2_RESET ;
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/* Disable all interrupts and clear flag bits */
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RCC->GCIR = SYS_GCIR_INT_FLAG_RESET_CL;
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#else
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/* Disable all interrupts and clear flag bits */
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RCC->GCIR = SYS_GCIR_INT_FLAG_RESET;
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#endif /* GD32F10X_CL */
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/* Configure the System clock frequency, AHB, APB2 and APB1 prescalers */
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/* Configure the Flash Latency cycles and enable prefetch buffer */
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SetSysClock();
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}
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/**
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* @brief Update SystemCoreClock according to RCC Register Values
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* @note Update the SystemCoreClock variable values, when the core clock (HCLK) changes.
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* Otherwise, any configuration based on this variable will be wrong.
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* @param None
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* @retval None
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*/
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void SystemCoreClockUpdate(void)
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{
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uint32_t temp = 0, pllmf = 0, pllmf4 = 0, pllselect = 0, presc = 0;
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#ifdef GD32F10X_CL
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uint32_t prediv1select = 0, prediv1factor = 0, prediv2factor = 0, pll2mf = 0;
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#endif /* GD32F10X_CL */
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/* Get CK_SYS source -------------------------------------------------------*/
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temp = RCC->GCFGR & RCC_GCFGR_SCSS;
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switch (temp) {
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case 0x00: /* HSI used as CK_SYS */
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SystemCoreClock = HSI_VALUE;
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break;
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case 0x04: /* HSE used as CK_SYS */
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SystemCoreClock = HSE_VALUE;
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break;
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case 0x08: /* PLL used as CK_SYS */
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#ifdef GD32F10X_CL
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/* Get PLL clock source and multiplication factor ----------------------*/
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/* Get PLLMF[3:0] */
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pllmf = RCC->GCFGR & SYS_RCC_GCFGR_PLLMF_3_0;
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/* Get PLLMF[4] */
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pllmf4 = RCC->GCFGR & RCC_GCFGR_PLLMF_4;
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pllmf4 = ((pllmf4 >> 29) * 15);
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pllmf = (pllmf >> 18) + pllmf4;
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if (pllmf != 0x0D) {
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pllmf += 2;
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} else {
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/* PLL multiplication factor = PLL input clock * 6.5 */
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pllmf = 13 / 2;
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}
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pllselect = RCC->GCFGR & RCC_GCFGR_PLLSEL;
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if (pllselect == 0x00) {
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/* HSI clock divided by 2 selected as PLL clock source */
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SystemCoreClock = (HSI_VALUE >> SYS_HSI_CLOCK_DIVIDED_2) * pllmf;
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} else {
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/* PREDIV1 selected as PLL clock entry */
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/* Get PREDIV1 clock source and division factor */
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prediv1select = RCC->GCFGR2 & RCC_GCFGR2_PREDV1SEL;
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prediv1factor = (RCC->GCFGR2 & RCC_GCFGR2_PREDV1) + 1;
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if (prediv1select == 0) {
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/* HSE clock selected as PREDIV1 clock entry */
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SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmf;
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} else {
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/* PLL2 clock selected as PREDIV1 clock entry */
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/* Get PREDIV2 division factor and PLL2 multiplication factor */
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prediv2factor = ((RCC->GCFGR2 & RCC_GCFGR2_PREDV2) >> 4) + 1;
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pll2mf = ((RCC->GCFGR2 & RCC_GCFGR2_PLL2MF) >> 8);
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if (pll2mf != 15) {
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pll2mf += 2;
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} else {
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pll2mf += 5;
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}
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SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mf) / prediv1factor) * pllmf;
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}
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}
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#else
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/* Get PLL clock source and multiplication factor ----------------------*/
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/* Get PLLMF[3:0] */
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pllmf = RCC->GCFGR & SYS_RCC_GCFGR_PLLMF_3_0;
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/* Get PLLMF[4] */
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pllmf4 = RCC->GCFGR & RCC_GCFGR_PLLMF_4;
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pllmf4 = ((pllmf4 >> 27) * 15);
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pllmf = (pllmf >> 18) + pllmf4 + 2;
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pllselect = RCC->GCFGR & RCC_GCFGR_PLLSEL;
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if (pllselect == 0x00) {
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/* HSI clock divided by 2 selected as PLL clock source */
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SystemCoreClock = (HSI_VALUE >> SYS_HSI_CLOCK_DIVIDED_2) * pllmf;
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} else {
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if ((RCC->GCFGR & RCC_GCFGR_PLLPREDV) != (uint32_t)RESET) {
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/* HSE clock divided by 2 */
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SystemCoreClock = (HSE_VALUE >> 1) * pllmf;
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} else {
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SystemCoreClock = HSE_VALUE * pllmf;
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}
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}
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#endif
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break;
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default: /* HSI used as system clock */
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SystemCoreClock = HSI_VALUE;
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break;
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}
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/* Get AHB prescaler */
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temp = RCC->GCFGR & RCC_GCFGR_AHBPS;
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temp = temp >> 4;
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presc = AHBPrescTableList[temp];
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/* Get AHB clock frequency */
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SystemCoreClock = SystemCoreClock >> presc;
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}
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/**
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* @brief Configure the System clock frequency, AHB, APB2 and APB1 prescalers.
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* @param None
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* @retval None
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*/
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static void SetSysClock(void)
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{
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#ifdef SYSCLK_FREQ_HSE
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SetSysClockToHSE();
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#elif defined SYSCLK_FREQ_24MHz
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SetSysClockTo24();
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#elif defined SYSCLK_FREQ_36MHz
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SetSysClockTo36();
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#elif defined SYSCLK_FREQ_48MHz
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SetSysClockTo48();
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#elif defined SYSCLK_FREQ_56MHz
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SetSysClockTo56();
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#elif defined SYSCLK_FREQ_72MHz
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SetSysClockTo72();
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#elif defined SYSCLK_FREQ_96MHz
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SetSysClockTo96();
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#elif defined SYSCLK_FREQ_108MHz
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SetSysClockTo108();
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#elif defined SYSCLK_FREQ_48MHz_HSI
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SetSysClockTo48HSI();
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#elif defined SYSCLK_FREQ_72MHz_HSI
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SetSysClockTo72HSI();
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#elif defined SYSCLK_FREQ_108MHz_HSI
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SetSysClockTo108HSI();
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#endif
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}
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#ifdef SYSCLK_FREQ_HSE
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/**
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* @brief Select HSE as System clock source and configure AHB, APB2
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* and APB1 prescalers.
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* @param None
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* @retval None
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*/
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static void SetSysClockToHSE(void)
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{
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__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
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/* CK_SYS, AHB, APB2 and APB1 configuration ---------------------------*/
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/* Enable HSE */
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RCC->GCCR |= ((uint32_t)RCC_GCCR_HSEEN);
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/* Wait till HSE is ready and if Time out is reached exit */
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do {
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HSEStatus = RCC->GCCR & RCC_GCCR_HSESTB;
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StartUpCounter++;
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} while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
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if ((RCC->GCCR & RCC_GCCR_HSESTB) != RESET) {
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HSEStatus = (uint32_t)0x01;
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} else {
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HSEStatus = (uint32_t)0x00;
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}
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if (HSEStatus == (uint32_t)0x01) {
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/* AHB = CK_SYS not divided */
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RCC->GCFGR |= (uint32_t)RCC_GCFGR_AHBPS_DIV1;
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/* APB2 = AHB not divided */
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RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB2PS_DIV1;
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/* APB1 = AHB is divided 2 */
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RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB1PS_DIV2;
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/* Select HSE as system clock source */
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RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_SCS));
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RCC->GCFGR |= (uint32_t)RCC_GCFGR_SCS_HSE;
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/* Wait till HSE is used as system clock source */
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while ((RCC->GCFGR & (uint32_t)RCC_GCFGR_SCSS) != (uint32_t)0x04) {
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}
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} else {
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}
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}
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#elif defined SYSCLK_FREQ_24MHz
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/**
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* @brief Set System clock frequency to 24MHz and configure AHB, APB1, and APB2 prescalers.
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* @note This function should be used only after reset.
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* @param None
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* @retval None
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*/
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static void SetSysClockTo24(void)
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{
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__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
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/* CK_SYS, AHB, APB2 and APB1 configuration ---------------------------*/
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/* Enable HSE */
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RCC->GCCR |= ((uint32_t)RCC_GCCR_HSEEN);
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/* Wait till HSE is ready and if Time out is reached exit */
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do {
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HSEStatus = RCC->GCCR & RCC_GCCR_HSESTB;
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StartUpCounter++;
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} while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
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if ((RCC->GCCR & RCC_GCCR_HSESTB) != RESET) {
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HSEStatus = (uint32_t)0x01;
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} else {
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HSEStatus = (uint32_t)0x00;
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}
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if (HSEStatus == (uint32_t)0x01) {
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/* AHB = CK_SYS not divided */
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RCC->GCFGR |= (uint32_t)RCC_GCFGR_AHBPS_DIV1;
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/* APB2 = AHB not divided */
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RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB2PS_DIV1;
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/* APB1 = AHB is divided 2 */
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RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB1PS_DIV2;
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#ifdef GD32F10X_CL
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/* Configure PLLs ------------------------------------------------------*/
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/* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
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RCC->GCFGR &= (uint32_t)~(RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLMF);
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RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLPREDV_PREDIV1 | RCC_GCFGR_PLLSEL_PREDIV1 | RCC_GCFGR_PLLMF6);
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/* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
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/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
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RCC->GCFGR2 &= (uint32_t)~(RCC_GCFGR2_PREDV2 | RCC_GCFGR2_PLL2MF |
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RCC_GCFGR2_PREDV1 | RCC_GCFGR2_PREDV1SEL);
|
|
RCC->GCFGR2 |= (uint32_t)(RCC_GCFGR2_PREDV2_DIV5 | RCC_GCFGR2_PLL2MF8 |
|
|
RCC_GCFGR2_PREDV1SEL_PLL2 | RCC_GCFGR2_PREDV1_DIV10);
|
|
|
|
/* Enable PLL2 */
|
|
RCC->GCCR |= RCC_GCCR_PLL2EN;
|
|
/* Wait till PLL2 is ready */
|
|
while ((RCC->GCCR & RCC_GCCR_PLL2STB) == 0) {
|
|
}
|
|
#else
|
|
/* PLL configuration: PLLCLK = (HSE /2)* 6 = 24 MHz */
|
|
RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLMF));
|
|
RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLPREDV_HSE_DIV2 | RCC_GCFGR_PLLSEL_HSE | RCC_GCFGR_PLLMF6);
|
|
|
|
#endif /* GD32F10X_CL */
|
|
|
|
/* Enable PLL */
|
|
RCC->GCCR |= RCC_GCCR_PLLEN;
|
|
|
|
/* Wait till PLL is ready */
|
|
while ((RCC->GCCR & RCC_GCCR_PLLSTB) == 0) {
|
|
}
|
|
|
|
/* Select PLL as system clock source */
|
|
RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_SCS));
|
|
RCC->GCFGR |= (uint32_t)RCC_GCFGR_SCS_PLL;
|
|
|
|
/* Wait till PLL is used as system clock source */
|
|
while ((RCC->GCFGR & (uint32_t)RCC_GCFGR_SCSS) != (uint32_t)0x08) {
|
|
}
|
|
} else {
|
|
}
|
|
}
|
|
|
|
#elif defined SYSCLK_FREQ_36MHz
|
|
/**
|
|
* @brief Set System clock frequency to 36MHz and configure AHB, APB1, and APB2 prescalers.
|
|
* @note This function should be used only after reset.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void SetSysClockTo36(void)
|
|
{
|
|
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
|
|
|
/* CK_SYS, AHB, APB2 and APB1 configuration ---------------------------*/
|
|
/* Enable HSE */
|
|
RCC->GCCR |= ((uint32_t)RCC_GCCR_HSEEN);
|
|
|
|
/* Wait till HSE is ready and if Time out is reached exit */
|
|
do {
|
|
HSEStatus = RCC->GCCR & RCC_GCCR_HSESTB;
|
|
StartUpCounter++;
|
|
} while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
|
|
|
if ((RCC->GCCR & RCC_GCCR_HSESTB) != RESET) {
|
|
HSEStatus = (uint32_t)0x01;
|
|
} else {
|
|
HSEStatus = (uint32_t)0x00;
|
|
}
|
|
|
|
if (HSEStatus == (uint32_t)0x01) {
|
|
/* AHB = CK_SYS not divided */
|
|
RCC->GCFGR |= (uint32_t)RCC_GCFGR_AHBPS_DIV1;
|
|
|
|
/* APB2 = AHB not divided */
|
|
RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB2PS_DIV1;
|
|
|
|
/* APB1 = AHB is divided 2 */
|
|
RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB1PS_DIV2;
|
|
|
|
#ifdef GD32F10X_CL
|
|
/* Configure PLLs ------------------------------------------------------*/
|
|
/* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
|
|
RCC->GCFGR &= (uint32_t)~(RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLMF);
|
|
RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLSEL_PREDIV1 | RCC_GCFGR_PLLMF9);
|
|
|
|
/* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
|
|
/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
|
|
|
|
RCC->GCFGR2 &= (uint32_t)~(RCC_GCFGR2_PREDV2 | RCC_GCFGR2_PLL2MF |
|
|
RCC_GCFGR2_PREDV1 | RCC_GCFGR2_PREDV1SEL);
|
|
RCC->GCFGR2 |= (uint32_t)(RCC_GCFGR2_PREDV2_DIV5 | RCC_GCFGR2_PLL2MF8 |
|
|
RCC_GCFGR2_PREDV1SEL_PLL2 | RCC_GCFGR2_PREDV1_DIV10);
|
|
|
|
/* Enable PLL2 */
|
|
RCC->GCCR |= RCC_GCCR_PLL2EN;
|
|
/* Wait till PLL2 is ready */
|
|
while ((RCC->GCCR & RCC_GCCR_PLL2STB) == 0) {
|
|
}
|
|
|
|
#else
|
|
/* PLL configuration: PLLCLK = (HSE /2)* 9 = 36 MHz */
|
|
RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLMF));
|
|
RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLPREDV_HSE_DIV2 | RCC_GCFGR_PLLSEL_HSE | RCC_GCFGR_PLLMF9);
|
|
|
|
#endif /* GD32F10X_CL */
|
|
|
|
/* Enable PLL */
|
|
RCC->GCCR |= RCC_GCCR_PLLEN;
|
|
|
|
/* Wait till PLL is ready */
|
|
while ((RCC->GCCR & RCC_GCCR_PLLSTB) == 0) {
|
|
}
|
|
|
|
/* Select PLL as system clock source */
|
|
RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_SCS));
|
|
RCC->GCFGR |= (uint32_t)RCC_GCFGR_SCS_PLL;
|
|
|
|
/* Wait till PLL is used as system clock source */
|
|
while ((RCC->GCFGR & (uint32_t)RCC_GCFGR_SCSS) != (uint32_t)0x08) {
|
|
}
|
|
} else {
|
|
}
|
|
}
|
|
#elif defined SYSCLK_FREQ_48MHz
|
|
/**
|
|
* @brief Set System clock frequency to 48MHz and configure AHB, APB1, and APB2 prescalers.
|
|
* @note This function should be used only after reset.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void SetSysClockTo48(void)
|
|
{
|
|
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
|
|
|
/* CK_SYS, AHB, APB2 and APB1 configuration ---------------------------*/
|
|
/* Enable HSE */
|
|
RCC->GCCR |= ((uint32_t)RCC_GCCR_HSEEN);
|
|
|
|
/* Wait till HSE is ready and if Time out is reached exit */
|
|
do {
|
|
HSEStatus = RCC->GCCR & RCC_GCCR_HSESTB;
|
|
StartUpCounter++;
|
|
} while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
|
|
|
if ((RCC->GCCR & RCC_GCCR_HSESTB) != RESET) {
|
|
HSEStatus = (uint32_t)0x01;
|
|
} else {
|
|
HSEStatus = (uint32_t)0x00;
|
|
}
|
|
|
|
if (HSEStatus == (uint32_t)0x01) {
|
|
/* AHB = CK_SYS not divided */
|
|
RCC->GCFGR |= (uint32_t)RCC_GCFGR_AHBPS_DIV1;
|
|
|
|
/* APB2 = AHB not divided */
|
|
RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB2PS_DIV1;
|
|
|
|
/* APB1 = AHB is divided 2 */
|
|
RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB1PS_DIV2;
|
|
|
|
#ifdef GD32F10X_CL
|
|
/* Configure PLLs ------------------------------------------------------*/
|
|
|
|
/* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
|
|
RCC->GCFGR &= (uint32_t)~(RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLMF);
|
|
RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLSEL_PREDIV1 | RCC_GCFGR_PLLMF6);
|
|
/* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
|
|
/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
|
|
|
|
RCC->GCFGR2 &= (uint32_t)~(RCC_GCFGR2_PREDV2 | RCC_GCFGR2_PLL2MF |
|
|
RCC_GCFGR2_PREDV1 | RCC_GCFGR2_PREDV1SEL);
|
|
RCC->GCFGR2 |= (uint32_t)(RCC_GCFGR2_PREDV2_DIV5 | RCC_GCFGR2_PLL2MF8 |
|
|
RCC_GCFGR2_PREDV1SEL_PLL2 | RCC_GCFGR2_PREDV1_DIV5);
|
|
|
|
|
|
|
|
/* Enable PLL2 */
|
|
RCC->GCCR |= RCC_GCCR_PLL2EN;
|
|
/* Wait till PLL2 is ready */
|
|
while ((RCC->GCCR & RCC_GCCR_PLL2STB) == 0) {
|
|
}
|
|
|
|
#else
|
|
/* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
|
|
RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLMF));
|
|
RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLPREDV_HSE | RCC_GCFGR_PLLSEL_HSE | RCC_GCFGR_PLLMF6);
|
|
|
|
#endif /* GD32F10X_CL */
|
|
|
|
/* Enable PLL */
|
|
RCC->GCCR |= RCC_GCCR_PLLEN;
|
|
|
|
/* Wait till PLL is ready */
|
|
while ((RCC->GCCR & RCC_GCCR_PLLSTB) == 0) {
|
|
}
|
|
|
|
/* Select PLL as system clock source */
|
|
RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_SCS));
|
|
RCC->GCFGR |= (uint32_t)RCC_GCFGR_SCS_PLL;
|
|
|
|
/* Wait till PLL is used as system clock source */
|
|
while ((RCC->GCFGR & (uint32_t)RCC_GCFGR_SCSS) != (uint32_t)0x08) {
|
|
}
|
|
} else {
|
|
}
|
|
}
|
|
|
|
#elif defined SYSCLK_FREQ_56MHz
|
|
/**
|
|
* @brief Set System clock frequency to 56MHz and configure AHB, APB1, and APB2 prescalers.
|
|
* @note This function should be used only after reset.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void SetSysClockTo56(void)
|
|
{
|
|
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
|
|
|
/* CK_SYS, AHB, APB2 and APB1 configuration ---------------------------*/
|
|
/* Enable HSE */
|
|
RCC->GCCR |= ((uint32_t)RCC_GCCR_HSEEN);
|
|
|
|
/* Wait till HSE is ready and if Time out is reached exit */
|
|
do {
|
|
HSEStatus = RCC->GCCR & RCC_GCCR_HSESTB;
|
|
StartUpCounter++;
|
|
} while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
|
|
|
if ((RCC->GCCR & RCC_GCCR_HSESTB) != RESET) {
|
|
HSEStatus = (uint32_t)0x01;
|
|
} else {
|
|
HSEStatus = (uint32_t)0x00;
|
|
}
|
|
|
|
if (HSEStatus == (uint32_t)0x01) {
|
|
/* AHB = CK_SYS not divided */
|
|
RCC->GCFGR |= (uint32_t)RCC_GCFGR_AHBPS_DIV1;
|
|
|
|
/* APB2 = AHB not divided */
|
|
RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB2PS_DIV1;
|
|
|
|
/* APB1 = AHB is divided 2 */
|
|
RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB1PS_DIV2;
|
|
|
|
#ifdef GD32F10X_CL
|
|
/* Configure PLLs ------------------------------------------------------*/
|
|
|
|
/* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
|
|
RCC->GCFGR &= (uint32_t)~(RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLMF);
|
|
RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLSEL_PREDIV1 | RCC_GCFGR_PLLMF7);
|
|
/* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
|
|
/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
|
|
|
|
RCC->GCFGR2 &= (uint32_t)~(RCC_GCFGR2_PREDV2 | RCC_GCFGR2_PLL2MF |
|
|
RCC_GCFGR2_PREDV1 | RCC_GCFGR2_PREDV1SEL);
|
|
RCC->GCFGR2 |= (uint32_t)(RCC_GCFGR2_PREDV2_DIV5 | RCC_GCFGR2_PLL2MF8 |
|
|
RCC_GCFGR2_PREDV1SEL_PLL2 | RCC_GCFGR2_PREDV1_DIV5);
|
|
|
|
/* Enable PLL2 */
|
|
RCC->GCCR |= RCC_GCCR_PLL2EN;
|
|
/* Wait till PLL2 is ready */
|
|
while ((RCC->GCCR & RCC_GCCR_PLL2STB) == 0) {
|
|
}
|
|
|
|
#else
|
|
/* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
|
|
RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLMF));
|
|
RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLPREDV_HSE | RCC_GCFGR_PLLSEL_HSE | RCC_GCFGR_PLLMF7);
|
|
|
|
#endif /* GD32F10X_CL */
|
|
|
|
/* Enable PLL */
|
|
RCC->GCCR |= RCC_GCCR_PLLEN;
|
|
|
|
/* Wait till PLL is ready */
|
|
while ((RCC->GCCR & RCC_GCCR_PLLSTB) == 0) {
|
|
}
|
|
|
|
/* Select PLL as system clock source */
|
|
RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_SCS));
|
|
RCC->GCFGR |= (uint32_t)RCC_GCFGR_SCS_PLL;
|
|
|
|
/* Wait till PLL is used as system clock source */
|
|
while ((RCC->GCFGR & (uint32_t)RCC_GCFGR_SCSS) != (uint32_t)0x08) {
|
|
}
|
|
} else {
|
|
}
|
|
}
|
|
|
|
#elif defined SYSCLK_FREQ_72MHz
|
|
/**
|
|
* @brief Set System clock frequency to 72MHz and configure AHB, APB1, and APB2 prescalers.
|
|
* @note This function should be used only after reset.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void SetSysClockTo72(void)
|
|
{
|
|
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
|
|
|
/* CK_SYS, AHB, APB2 and APB1 configuration ---------------------------*/
|
|
/* Enable HSE */
|
|
RCC->GCCR |= ((uint32_t)RCC_GCCR_HSEEN);
|
|
|
|
/* Wait till HSE is ready and if Time out is reached exit */
|
|
do {
|
|
HSEStatus = RCC->GCCR & RCC_GCCR_HSESTB;
|
|
StartUpCounter++;
|
|
} while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
|
|
|
if ((RCC->GCCR & RCC_GCCR_HSESTB) != RESET) {
|
|
HSEStatus = (uint32_t)0x01;
|
|
} else {
|
|
HSEStatus = (uint32_t)0x00;
|
|
}
|
|
|
|
if (HSEStatus == (uint32_t)0x01) {
|
|
/* AHB = CK_SYS not divided */
|
|
RCC->GCFGR |= (uint32_t)RCC_GCFGR_AHBPS_DIV1;
|
|
|
|
/* APB2 = AHB not divided */
|
|
RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB2PS_DIV1;
|
|
|
|
/* APB1 = AHB is divided 2 */
|
|
RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB1PS_DIV2;
|
|
|
|
#ifdef GD32F10X_CL
|
|
/* Configure PLLs ------------------------------------------------------*/
|
|
|
|
/* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
|
|
RCC->GCFGR &= (uint32_t)~(RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLMF);
|
|
RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLSEL_PREDIV1 | RCC_GCFGR_PLLMF9);
|
|
|
|
/* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
|
|
/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
|
|
|
|
RCC->GCFGR2 &= (uint32_t)~(RCC_GCFGR2_PREDV2 | RCC_GCFGR2_PLL2MF |
|
|
RCC_GCFGR2_PREDV1 | RCC_GCFGR2_PREDV1SEL);
|
|
RCC->GCFGR2 |= (uint32_t)(RCC_GCFGR2_PREDV2_DIV5 | RCC_GCFGR2_PLL2MF8 |
|
|
RCC_GCFGR2_PREDV1SEL_PLL2 | RCC_GCFGR2_PREDV1_DIV5);
|
|
|
|
/* Enable PLL2 */
|
|
RCC->GCCR |= RCC_GCCR_PLL2EN;
|
|
/* Wait till PLL2 is ready */
|
|
while ((RCC->GCCR & RCC_GCCR_PLL2STB) == 0) {
|
|
}
|
|
|
|
#else
|
|
/* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
|
|
RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLMF));
|
|
RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLPREDV_HSE | RCC_GCFGR_PLLSEL_HSE | RCC_GCFGR_PLLMF9);
|
|
|
|
#endif /* GD32F10X_CL */
|
|
|
|
/* Enable PLL */
|
|
RCC->GCCR |= RCC_GCCR_PLLEN;
|
|
|
|
/* Wait till PLL is ready */
|
|
while ((RCC->GCCR & RCC_GCCR_PLLSTB) == 0) {
|
|
}
|
|
|
|
/* Select PLL as system clock source */
|
|
RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_SCS));
|
|
RCC->GCFGR |= (uint32_t)RCC_GCFGR_SCS_PLL;
|
|
|
|
/* Wait till PLL is used as system clock source */
|
|
while ((RCC->GCFGR & (uint32_t)RCC_GCFGR_SCSS) != (uint32_t)0x08) {
|
|
}
|
|
} else {
|
|
}
|
|
}
|
|
#elif defined SYSCLK_FREQ_96MHz
|
|
/**
|
|
* @brief Set System clock frequency to 96MHz and configure AHB, APB1, and APB2 prescalers.
|
|
* @note This function should be used only after reset.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void SetSysClockTo96(void)
|
|
{
|
|
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
|
|
|
/* CK_SYS, AHB, APB2 and APB1 configuration ---------------------------*/
|
|
/* Enable HSE */
|
|
RCC->GCCR |= ((uint32_t)RCC_GCCR_HSEEN);
|
|
|
|
/* Wait till HSE is ready and if Time out is reached exit */
|
|
do {
|
|
HSEStatus = RCC->GCCR & RCC_GCCR_HSESTB;
|
|
StartUpCounter++;
|
|
} while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
|
|
|
if ((RCC->GCCR & RCC_GCCR_HSESTB) != RESET) {
|
|
HSEStatus = (uint32_t)0x01;
|
|
} else {
|
|
HSEStatus = (uint32_t)0x00;
|
|
}
|
|
|
|
if (HSEStatus == (uint32_t)0x01) {
|
|
/* AHB = CK_SYS not divided */
|
|
RCC->GCFGR |= (uint32_t)RCC_GCFGR_AHBPS_DIV1;
|
|
|
|
/* APB2 = AHB not divided */
|
|
RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB2PS_DIV1;
|
|
|
|
/* APB1 = AHB is divided 2 */
|
|
RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB1PS_DIV2;
|
|
|
|
#ifdef GD32F10X_CL
|
|
/* Configure PLLs ------------------------------------------------------*/
|
|
|
|
/* PLL configuration: PLLCLK = PREDIV1 * 12 = 96 MHz */
|
|
RCC->GCFGR &= (uint32_t)~(RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLMF);
|
|
RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLSEL_PREDIV1 | RCC_GCFGR_PLLMF12);
|
|
|
|
/* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
|
|
/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
|
|
|
|
RCC->GCFGR2 &= (uint32_t)~(RCC_GCFGR2_PREDV2 | RCC_GCFGR2_PLL2MF |
|
|
RCC_GCFGR2_PREDV1 | RCC_GCFGR2_PREDV1SEL);
|
|
RCC->GCFGR2 |= (uint32_t)(RCC_GCFGR2_PREDV2_DIV5 | RCC_GCFGR2_PLL2MF8 |
|
|
RCC_GCFGR2_PREDV1SEL_PLL2 | RCC_GCFGR2_PREDV1_DIV5);
|
|
|
|
/* Enable PLL2 */
|
|
RCC->GCCR |= RCC_GCCR_PLL2EN;
|
|
/* Wait till PLL2 is ready */
|
|
while ((RCC->GCCR & RCC_GCCR_PLL2STB) == 0) {
|
|
}
|
|
|
|
#else
|
|
/* PLL configuration: PLLCLK = HSE * 12 = 96 MHz */
|
|
RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLMF));
|
|
RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLPREDV_HSE | RCC_GCFGR_PLLSEL_HSE | RCC_GCFGR_PLLMF12);
|
|
|
|
#endif /* GD32F10X_CL */
|
|
|
|
/* Enable PLL */
|
|
RCC->GCCR |= RCC_GCCR_PLLEN;
|
|
|
|
/* Wait till PLL is ready */
|
|
while ((RCC->GCCR & RCC_GCCR_PLLSTB) == 0) {
|
|
}
|
|
|
|
/* Select PLL as system clock source */
|
|
RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_SCS));
|
|
RCC->GCFGR |= (uint32_t)RCC_GCFGR_SCS_PLL;
|
|
|
|
/* Wait till PLL is used as system clock source */
|
|
while ((RCC->GCFGR & (uint32_t)RCC_GCFGR_SCSS) != (uint32_t)0x08) {
|
|
}
|
|
} else {
|
|
}
|
|
}
|
|
|
|
#elif defined SYSCLK_FREQ_108MHz
|
|
/**
|
|
* @brief Set System clock frequency to 108MHz and configure AHB, APB1, and APB2 prescalers.
|
|
* @note This function should be used only after reset.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void SetSysClockTo108(void)
|
|
{
|
|
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
|
|
|
/* CK_SYS, AHB, APB2 and APB1 configuration ---------------------------*/
|
|
/* Enable HSE */
|
|
RCC->GCCR |= ((uint32_t)RCC_GCCR_HSEEN);
|
|
|
|
/* Wait till HSE is ready and if Time out is reached exit */
|
|
do {
|
|
HSEStatus = RCC->GCCR & RCC_GCCR_HSESTB;
|
|
StartUpCounter++;
|
|
} while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
|
|
|
if ((RCC->GCCR & RCC_GCCR_HSESTB) != RESET) {
|
|
HSEStatus = (uint32_t)0x01;
|
|
} else {
|
|
HSEStatus = (uint32_t)0x00;
|
|
}
|
|
|
|
if (HSEStatus == (uint32_t)0x01) {
|
|
/* AHB = CK_SYS not divided */
|
|
RCC->GCFGR |= (uint32_t)RCC_GCFGR_AHBPS_DIV1;
|
|
/* APB2 = AHB not divided */
|
|
RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB2PS_DIV1;
|
|
/* APB1 = AHB is divided 2 */
|
|
RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB1PS_DIV2;
|
|
|
|
#ifdef GD32F10X_CL
|
|
/* Configure PLLs ------------------------------------------------------*/
|
|
|
|
/* PLL configuration: PLLCLK = PREDIV1 * 9 = 108 MHz */
|
|
RCC->GCFGR &= (uint32_t)~(RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLMF);
|
|
RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLPREDV_PREDIV1 | RCC_GCFGR_PLLSEL_PREDIV1 | RCC_GCFGR_PLLMF9);
|
|
|
|
/* PLL2 configuration: PLL2CLK = (HSE / 5) * 12 = 60 MHz */
|
|
/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 12 MHz */
|
|
|
|
RCC->GCFGR2 &= (uint32_t)~(RCC_GCFGR2_PREDV2 | RCC_GCFGR2_PLL2MF |
|
|
RCC_GCFGR2_PREDV1 | RCC_GCFGR2_PREDV1SEL);
|
|
RCC->GCFGR2 |= (uint32_t)(RCC_GCFGR2_PREDV2_DIV5 | RCC_GCFGR2_PLL2MF12 |
|
|
RCC_GCFGR2_PREDV1SEL_PLL2 | RCC_GCFGR2_PREDV1_DIV5);
|
|
|
|
/* Enable PLL2 */
|
|
RCC->GCCR |= RCC_GCCR_PLL2EN;
|
|
/* Wait till PLL2 is ready */
|
|
while ((RCC->GCCR & RCC_GCCR_PLL2STB) == 0) {
|
|
}
|
|
|
|
#else
|
|
/* PLL configuration: PLLCLK = (HSE/2) * 27 = 108 MHz */
|
|
RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLMF));
|
|
RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLPREDV_HSE_DIV2 | RCC_GCFGR_PLLSEL_HSE | RCC_GCFGR_PLLMF27);
|
|
|
|
#endif /* GD32F10X_CL */
|
|
|
|
/* Enable PLL */
|
|
RCC->GCCR |= RCC_GCCR_PLLEN;
|
|
|
|
/* Wait till PLL is ready */
|
|
while ((RCC->GCCR & RCC_GCCR_PLLSTB) == 0) {
|
|
}
|
|
|
|
/* Select PLL as system clock source */
|
|
RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_SCS));
|
|
RCC->GCFGR |= (uint32_t)RCC_GCFGR_SCS_PLL;
|
|
|
|
/* Wait till PLL is used as system clock source */
|
|
while ((RCC->GCFGR & (uint32_t)RCC_GCFGR_SCSS) != (uint32_t)0x08) {
|
|
}
|
|
} else {
|
|
}
|
|
}
|
|
#elif defined SYSCLK_FREQ_48MHz_HSI
|
|
/**
|
|
* @brief Set System clock frequency to 48MHz and configure AHB, APB1, and APB2 prescalers.
|
|
* @note This function should be used only after reset.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void SetSysClockTo48HSI(void)
|
|
{
|
|
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
|
|
|
/* CK_SYS, AHB, APB2 and APB1 configuration ---------------------------*/
|
|
|
|
/* AHB = CK_SYS not divided */
|
|
RCC->GCFGR |= (uint32_t)RCC_GCFGR_AHBPS_DIV1;
|
|
|
|
/* APB2 = AHB not divided */
|
|
RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB2PS_DIV1;
|
|
|
|
/* APB1 = AHB is divided 2 */
|
|
RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB1PS_DIV2;
|
|
|
|
/* Configure PLLs ------------------------------------------------------*/
|
|
|
|
/* PLL configuration: PLLCLK = (HSI/2) * 12 = 48 MHz */
|
|
RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLMF));
|
|
RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLSEL_HSI_DIV2 | RCC_GCFGR_PLLMF12);
|
|
|
|
/* Enable PLL */
|
|
RCC->GCCR |= RCC_GCCR_PLLEN;
|
|
|
|
/* Wait till PLL is ready */
|
|
while ((RCC->GCCR & RCC_GCCR_PLLSTB) == 0) {
|
|
}
|
|
|
|
/* Select PLL as system clock source */
|
|
RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_SCS));
|
|
RCC->GCFGR |= (uint32_t)RCC_GCFGR_SCS_PLL;
|
|
|
|
/* Wait till PLL is used as system clock source */
|
|
while ((RCC->GCFGR & (uint32_t)RCC_GCFGR_SCSS) != (uint32_t)0x08) {
|
|
}
|
|
}
|
|
#elif defined SYSCLK_FREQ_72MHz_HSI
|
|
/**
|
|
* @brief Set System clock frequency to 72MHz and configure AHB, APB1, and APB2 prescalers.
|
|
* @note This function should be used only after reset.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void SetSysClockTo72HSI(void)
|
|
{
|
|
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
|
|
|
/* CK_SYS, AHB, APB2 and APB1 configuration ---------------------------*/
|
|
|
|
/* AHB = CK_SYS not divided */
|
|
RCC->GCFGR |= (uint32_t)RCC_GCFGR_AHBPS_DIV1;
|
|
|
|
/* APB2 = AHB not divided */
|
|
RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB2PS_DIV1;
|
|
|
|
/* APB1 = AHB is divided 2 */
|
|
RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB1PS_DIV2;
|
|
|
|
/* Configure PLLs ------------------------------------------------------*/
|
|
|
|
/* PLL configuration: PLLCLK = (HSI/2) * 18 = 72 MHz */
|
|
RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLMF));
|
|
RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLSEL_HSI_DIV2 | RCC_GCFGR_PLLMF18);
|
|
|
|
/* Enable PLL */
|
|
RCC->GCCR |= RCC_GCCR_PLLEN;
|
|
|
|
/* Wait till PLL is ready */
|
|
while ((RCC->GCCR & RCC_GCCR_PLLSTB) == 0) {
|
|
}
|
|
|
|
/* Select PLL as system clock source */
|
|
RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_SCS));
|
|
RCC->GCFGR |= (uint32_t)RCC_GCFGR_SCS_PLL;
|
|
|
|
/* Wait till PLL is used as system clock source */
|
|
while ((RCC->GCFGR & (uint32_t)RCC_GCFGR_SCSS) != (uint32_t)0x08) {
|
|
}
|
|
}
|
|
|
|
#elif defined SYSCLK_FREQ_108MHz_HSI
|
|
/**
|
|
* @brief Set System clock frequency to 108MHz and configure AHB, APB1, and APB2 prescalers.
|
|
* @note This function should be used only after reset.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void SetSysClockTo108HSI(void)
|
|
{
|
|
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
|
|
|
/* CK_SYS, AHB, APB2 and APB1 configuration ---------------------------*/
|
|
|
|
/* AHB = CK_SYS not divided */
|
|
RCC->GCFGR |= (uint32_t)RCC_GCFGR_AHBPS_DIV1;
|
|
|
|
/* APB2 = AHB not divided */
|
|
RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB2PS_DIV1;
|
|
|
|
/* APB1 = AHB is divided 2 */
|
|
RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB1PS_DIV2;
|
|
|
|
/* Configure PLLs ------------------------------------------------------*/
|
|
|
|
/* PLL configuration: PLLCLK = (HSI/2) * 27 = 108 MHz */
|
|
RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLMF));
|
|
RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLSEL_HSI_DIV2 | RCC_GCFGR_PLLMF27);
|
|
|
|
/* Enable PLL */
|
|
RCC->GCCR |= RCC_GCCR_PLLEN;
|
|
|
|
/* Wait till PLL is ready */
|
|
while ((RCC->GCCR & RCC_GCCR_PLLSTB) == 0) {
|
|
}
|
|
|
|
/* Select PLL as system clock source */
|
|
RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_SCS));
|
|
RCC->GCFGR |= (uint32_t)RCC_GCFGR_SCS_PLL;
|
|
|
|
/* Wait till PLL is used as system clock source */
|
|
while ((RCC->GCFGR & (uint32_t)RCC_GCFGR_SCSS) != (uint32_t)0x08) {
|
|
}
|
|
}
|
|
#endif
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
|