342 lines
11 KiB
C
342 lines
11 KiB
C
/*
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* Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "sdk.h"
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#include "registers/regsccm.h"
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#include "registers/regsccmanalog.h"
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#include "registers/regsuart.h"
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#include "registers/regsepit.h"
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#include "registers/regsspba.h"
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#include "registers/regssdmaarm.h"
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#include "registers/regsgpt.h"
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#include "registers/regsi2c.h"
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#include "registers/regsecspi.h"
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#include "ccm_pll.h"
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//#include "hardware.h"
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//#include "soc_memory_map.h"
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#define HW_ANADIG_REG_CORE (ANATOP_IPS_BASE_ADDR + 0x140)
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#define HW_ANADIG_PLL_SYS_RW (ANATOP_IPS_BASE_ADDR + 0x000)
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#define HW_ANADIG_REG_CORE_V_CORE_VALUE_mv(x) ((((x)-700)/25) << 0)
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#define HW_ANADIG_REG_CORE_V_SOC_VALUE_mv(x) ((((x)-700)/25) << 18)
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#define HW_ANADIG_REG_CORE_V_CORE_MSK 0x1F
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#define HW_ANADIG_REG_CORE_V_SOC_MSK (0x1F << 18)
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uint32_t g_arm_clk = 528000000;
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const uint32_t PLL2_OUTPUT[] = { 528000000, 396000000, 352000000, 198000000 };
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const uint32_t PLL3_OUTPUT[] = { 480000000, 720000000, 540000000, 508235294, 454736842 };
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const uint32_t PLL4_OUTPUT = 650000000;
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const uint32_t PLL5_OUTPUT = 650000000;
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////////////////////////////////////////////////////////////////////////////////
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// Code
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////////////////////////////////////////////////////////////////////////////////
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void set_soc_core_voltage(unsigned int v_core_mv, unsigned int v_soc_mv)
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{
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unsigned int val, val_v_core, val_v_soc;
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val = reg32_read(HW_ANADIG_REG_CORE);
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val &= ~HW_ANADIG_REG_CORE_V_CORE_MSK;
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val &= ~HW_ANADIG_REG_CORE_V_SOC_MSK;
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val_v_core = HW_ANADIG_REG_CORE_V_CORE_VALUE_mv(v_core_mv);
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val_v_soc = HW_ANADIG_REG_CORE_V_SOC_VALUE_mv(v_soc_mv);
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val |= val_v_core | val_v_soc;
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reg32_write(HW_ANADIG_REG_CORE, val);
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}
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void setup_clk(void)
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{
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uint32_t div_select;
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uint32_t temp;
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uint32_t arm_clk = g_arm_clk/1000000;
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switch(arm_clk)
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{
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case 400:
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div_select = 33;
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set_soc_core_voltage(1150, 1175);
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return;
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case 528:
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div_select = 44;
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set_soc_core_voltage(1250, 1250);
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break;
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case 756:
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div_select = 63;
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set_soc_core_voltage(1250, 1250);
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printf("ARM Clock set to 756MHz\r\n");
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break;
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default:
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return;
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}
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// first, make sure ARM_PODF is clear
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HW_CCM_CACRR_WR(0);
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// write the div_select value into HW_ANADIG_PLL_SYS_RW
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// this will re-program the PLL to the new freq
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temp = readl(HW_ANADIG_PLL_SYS_RW);
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temp |= 0x10000;// set BYBASS
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writel(temp, HW_ANADIG_PLL_SYS_RW);
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temp = readl(HW_ANADIG_PLL_SYS_RW);
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temp &= ~(0x0000007F);
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temp |= div_select; // Update div
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writel(temp, HW_ANADIG_PLL_SYS_RW);
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/* Wait for PLL to lock */
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while(!(readl(HW_ANADIG_PLL_SYS_RW) & 0x80000000));
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/*disable BYPASS*/
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temp = readl(HW_ANADIG_PLL_SYS_RW);
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temp &= ~0x10000;
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writel(temp, HW_ANADIG_PLL_SYS_RW);
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}
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void ccm_init(void)
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{
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HW_CCM_CCGR0_WR(0xffffffff);
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HW_CCM_CCGR1_WR(0xffffffff); // EPIT, ESAI, GPT enabled by driver
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HW_CCM_CCGR2_WR(0xffffffff); // I2C enabled by driver
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HW_CCM_CCGR3_WR(0xffffffff);
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HW_CCM_CCGR4_WR(0xffffffff); // GPMI, Perfmon enabled by driver
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HW_CCM_CCGR5_WR(0xffffffff); // UART, SATA enabled by driver
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HW_CCM_CCGR6_WR(0xffffffff);
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/*
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* Keep default settings at reset.
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* pre_periph_clk_sel is by default at 0, so the selected output
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* of PLL2 is the main output at 528MHz.
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* => by default, ahb_podf divides by 4 => AHB_CLK@132MHz.
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* => by default, ipg_podf divides by 2 => IPG_CLK@66MHz.
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*/
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HW_CCM_CBCDR.U = BF_CCM_CBCDR_AHB_PODF(3)
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| BF_CCM_CBCDR_AXI_PODF(1)
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| BF_CCM_CBCDR_IPG_PODF(1);
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setup_clk();
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/* Power up 480MHz PLL */
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reg32_write_mask(HW_CCM_ANALOG_PLL_USB1_ADDR, 0x00001000, 0x00001000);
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/* Enable 480MHz PLL */
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reg32_write_mask(HW_CCM_ANALOG_PLL_USB1_ADDR, 0x00002000, 0x00002000);
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reg32_write_mask(HW_CCM_CSCDR1_ADDR, 0x00000000, 0x0000003F);
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}
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uint32_t get_main_clock(main_clocks_t clock)
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{
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uint32_t ret_val = 0;
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uint32_t pre_periph_clk_sel = HW_CCM_CBCMR.B.PRE_PERIPH_CLK_SEL;
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switch (clock) {
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case CPU_CLK:
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ret_val = g_arm_clk;
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break;
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case AXI_CLK:
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ret_val = PLL2_OUTPUT[pre_periph_clk_sel] / (HW_CCM_CBCDR.B.AXI_PODF + 1);
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break;
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case MMDC_CH0_AXI_CLK:
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ret_val = PLL2_OUTPUT[pre_periph_clk_sel] / (HW_CCM_CBCDR.B.MMDC_CH0_AXI_PODF + 1);
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break;
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case AHB_CLK:
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ret_val = PLL2_OUTPUT[pre_periph_clk_sel] / (HW_CCM_CBCDR.B.AHB_PODF + 1);
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break;
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case IPG_CLK:
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ret_val =
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PLL2_OUTPUT[pre_periph_clk_sel] / (HW_CCM_CBCDR.B.AHB_PODF +
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1) / (HW_CCM_CBCDR.B.IPG_PODF + 1);
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break;
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case IPG_PER_CLK:
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ret_val =
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PLL2_OUTPUT[pre_periph_clk_sel] / (HW_CCM_CBCDR.B.AHB_PODF +
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1) / (HW_CCM_CBCDR.B.IPG_PODF +
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1) / (HW_CCM_CSCMR1.B.PERCLK_PODF + 1);
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break;
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default:
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break;
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}
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return ret_val;
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}
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uint32_t get_peri_clock(peri_clocks_t clock)
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{
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uint32_t ret_val = 0;
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switch (clock)
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{
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case UART1_MODULE_CLK:
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case UART2_MODULE_CLK:
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case UART3_MODULE_CLK:
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case UART4_MODULE_CLK:
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case UART5_MODULE_CLK:
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case UART6_MODULE_CLK:
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case UART7_MODULE_CLK:
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case UART8_MODULE_CLK:
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// UART source clock is a fixed PLL3 / 6
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ret_val = PLL3_OUTPUT[0] / 6 / (HW_CCM_CSCDR1.B.UART_CLK_PODF + 1);
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break;
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case SPI_CLK:
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ret_val = PLL3_OUTPUT[0] / 8 / (HW_CCM_CSCDR2.B.ECSPI_CLK_PODF + 1);
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break;
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case RAWNAND_CLK:
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ret_val =
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PLL3_OUTPUT[0] / (HW_CCM_CS2CDR.B.ENFC_CLK_PRED + 1) / (HW_CCM_CS2CDR.B.ENFC_CLK_PODF +
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1);
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break;
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case CAN_CLK:
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// For i.mx6dq/sdl CAN source clock is a fixed PLL3 / 8
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ret_val = PLL3_OUTPUT[0] / 8 / (HW_CCM_CSCMR2.B.CAN_CLK_PODF + 1);
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break;
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default:
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break;
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}
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return ret_val;
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}
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void ccm_ccgr_config(uint32_t ccm_ccgrx, uint32_t cgx_offset, uint32_t gating_mode)
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{
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if (gating_mode == CLOCK_ON)
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{
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*(volatile uint32_t *)(ccm_ccgrx) |= cgx_offset;
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}
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else
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{
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*(volatile uint32_t *)(ccm_ccgrx) &= ~cgx_offset;
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}
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}
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void clock_gating_config(uint32_t base_address, uint32_t gating_mode)
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{
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uint32_t ccm_ccgrx = 0;
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uint32_t cgx_offset = 0;
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switch (base_address)
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{
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case REGS_UART1_BASE:
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ccm_ccgrx = HW_CCM_CCGR5_ADDR;
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cgx_offset = CG(12);
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break;
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case REGS_UART2_BASE:
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ccm_ccgrx = HW_CCM_CCGR0_ADDR;
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cgx_offset = CG(14);
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break;
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case REGS_UART3_BASE:
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ccm_ccgrx = HW_CCM_CCGR1_ADDR;
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cgx_offset = CG(5);
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break;
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case REGS_UART4_BASE:
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ccm_ccgrx = HW_CCM_CCGR1_ADDR;
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cgx_offset = CG(12);
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break;
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case REGS_UART5_BASE:
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ccm_ccgrx = HW_CCM_CCGR3_ADDR;
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cgx_offset = CG(1);
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break;
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case REGS_UART6_BASE:
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ccm_ccgrx = HW_CCM_CCGR3_ADDR;
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cgx_offset = CG(3);
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break;
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case REGS_UART7_BASE:
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ccm_ccgrx = HW_CCM_CCGR5_ADDR;
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cgx_offset = CG(13);
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break;
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case REGS_UART8_BASE:
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ccm_ccgrx = HW_CCM_CCGR6_ADDR;
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cgx_offset = CG(7);
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break;
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case REGS_SPBA_BASE:
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ccm_ccgrx = HW_CCM_CCGR5_ADDR;
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cgx_offset = CG(6);
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break;
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case REGS_SDMAARM_BASE:
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ccm_ccgrx = HW_CCM_CCGR5_ADDR;
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cgx_offset = CG(3);
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break;
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case REGS_EPIT1_BASE:
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ccm_ccgrx = HW_CCM_CCGR1_ADDR;
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cgx_offset = CG(6);
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break;
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case REGS_EPIT2_BASE:
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ccm_ccgrx = HW_CCM_CCGR1_ADDR;
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cgx_offset = CG(7);
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break;
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case REGS_GPT1_BASE:
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case REGS_GPT2_BASE:
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ccm_ccgrx = HW_CCM_CCGR1_ADDR;
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cgx_offset = CG(10)|CG(11);
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break;
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case REGS_I2C1_BASE:
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ccm_ccgrx = HW_CCM_CCGR2_ADDR;
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cgx_offset = CG(3);
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break;
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case REGS_I2C2_BASE:
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ccm_ccgrx = HW_CCM_CCGR2_ADDR;
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cgx_offset = CG(4);
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break;
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case REGS_I2C3_BASE:
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ccm_ccgrx = HW_CCM_CCGR2_ADDR;
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cgx_offset = CG(5);
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break;
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case REGS_ECSPI1_BASE:
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ccm_ccgrx = HW_CCM_CCGR1_ADDR;
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cgx_offset = CG(0);
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break;
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case REGS_ECSPI2_BASE:
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ccm_ccgrx = HW_CCM_CCGR1_ADDR;
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cgx_offset = CG(1);
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break;
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case REGS_ECSPI3_BASE:
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ccm_ccgrx = HW_CCM_CCGR1_ADDR;
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cgx_offset = CG(2);
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break;
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case REGS_ECSPI4_BASE:
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ccm_ccgrx = HW_CCM_CCGR1_ADDR;
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cgx_offset = CG(3);
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break;
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default:
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break;
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}
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// apply changes only if a valid address was found
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if (ccm_ccgrx != 0)
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{
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ccm_ccgr_config(ccm_ccgrx, cgx_offset, gating_mode);
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}
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}
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////////////////////////////////////////////////////////////////////////////////
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// End of file
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////////////////////////////////////////////////////////////////////////////////
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