320 lines
9.0 KiB
ArmAsm
320 lines
9.0 KiB
ArmAsm
/*
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* File : start_gcc.S
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2011-01-13 weety first version
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* 2015-04-15 ArdaFu Split from AT91SAM9260 BSP
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* 2015-04-21 ArdaFu Remove remap code. Using mmu to map vector table
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* 2015-06-04 aozima Align stack address to 8 byte.
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*/
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#include "rt_low_level_init.h"
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#define S_FRAME_SIZE (18*4) //72
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@#define S_SPSR (17*4) //SPSR
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@#define S_CPSR (16*4) //CPSR
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#define S_PC (15*4) //R15
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@#define S_LR (14*4) //R14
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@#define S_SP (13*4) //R13
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@#define S_IP (12*4) //R12
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@#define S_FP (11*4) //R11
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@#define S_R10 (10*4)
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@#define S_R9 (9*4)
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@#define S_R8 (8*4)
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@#define S_R7 (7*4)
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@#define S_R6 (6*4)
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@#define S_R5 (5*4)
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@#define S_R4 (4*4)
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@#define S_R3 (3*4)
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@#define S_R2 (2*4)
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@#define S_R1 (1*4)
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@#define S_R0 (0*4)
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#define MODE_SYS 0x1F
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#define MODE_FIQ 0x11
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#define MODE_IRQ 0x12
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#define MODE_SVC 0x13
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#define MODE_ABT 0x17
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#define MODE_UND 0x1B
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#define MODEMASK 0x1F
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#define NOINT 0xC0
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@;----------------------- Stack and Heap Definitions ---------------------------
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.section .nobss, "w"
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.space UND_STK_SIZE
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.align 3
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.global UND_STACK_START
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UND_STACK_START:
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.space ABT_STK_SIZE
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.align 3
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.global ABT_STACK_START
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ABT_STACK_START:
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.space FIQ_STK_SIZE
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.align 3
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.global FIQ_STACK_START
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FIQ_STACK_START:
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.space IRQ_STK_SIZE
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.align 3
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.global IRQ_STACK_START
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IRQ_STACK_START:
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.skip SYS_STK_SIZE
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.align 3
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.global SYS_STACK_START
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SYS_STACK_START:
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.space SVC_STK_SIZE
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.align 3
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.global SVC_STACK_START
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SVC_STACK_START:
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@;--------------Jump vector table-----------------------------------------------
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.section .init, "ax"
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.arm
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.global start
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start:
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LDR PC, vector_reset
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LDR PC, vector_undef
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LDR PC, vector_swi
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LDR PC, vector_pabt
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LDR PC, vector_dabt
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LDR PC, vector_resv
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LDR PC, vector_irq
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LDR PC, vector_fiq
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vector_reset:
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.word Reset_Handler
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vector_undef:
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.word Undef_Handler
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vector_swi:
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.word SWI_Handler
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vector_pabt:
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.word PAbt_Handler
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vector_dabt:
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.word DAbt_Handler
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vector_resv:
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.word Resv_Handler
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vector_irq:
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.word IRQ_Handler
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vector_fiq:
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.word FIQ_Handler
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.balignl 16,0xdeadbeef
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@;----------------- Reset Handler ---------------------------------------------
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.global rt_low_level_init
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.global main
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.global Reset_Handler
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Reset_Handler:
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@; Set the cpu to SVC32 mode
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MRS R0, CPSR
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BIC R0, R0, #MODEMASK
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ORR R0, R0, #MODE_SVC|NOINT
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MSR CPSR_cxsf, R0
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@; Set CO-Processor
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@; little-end，disbale I/D Cache MMU, vector table is 0x00000000
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MRC P15, 0, R0, C1, C0, 0 @; Read CP15
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LDR R1, =0x00003085 @; set clear bits
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BIC R0, R0, R1
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MCR P15, 0, R0, C1, C0, 0 @; Write CP15
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@; Call low level init function,
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@; disable and clear all IRQs, Init MMU, Init interrupt controller, etc.
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LDR SP, =SVC_STACK_START
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LDR R0, =rt_low_level_init
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BLX R0
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Setup_Stack:
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@; Setup Stack for each mode
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MRS R0, CPSR
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BIC R0, R0, #MODEMASK
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ORR R1, R0, #MODE_UND|NOINT
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MSR CPSR_cxsf, R1 @; Undef mode
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LDR SP, =UND_STACK_START
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ORR R1, R0, #MODE_ABT|NOINT
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MSR CPSR_cxsf, R1 @; Abort mode
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LDR SP, =ABT_STACK_START
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ORR R1, R0, #MODE_IRQ|NOINT
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MSR CPSR_cxsf, R1 @; IRQ mode
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LDR SP, =IRQ_STACK_START
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ORR R1, R0, #MODE_FIQ|NOINT
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MSR CPSR_cxsf, R1 @; FIQ mode
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LDR SP, =FIQ_STACK_START
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ORR R1, R0, #MODE_SYS|NOINT
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MSR CPSR_cxsf,R1 @; SYS/User mode
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LDR SP, =SYS_STACK_START
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ORR R1, R0, #MODE_SVC|NOINT
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MSR CPSR_cxsf, R1 @; SVC mode
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LDR SP, =SVC_STACK_START
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@; clear .bss
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MOV R0, #0 @; get a zero
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LDR R1, =__bss_start__ @; bss start
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LDR R2, =__bss_end__ @; bss end
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bss_clear_loop:
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CMP R1, R2 @; check if data to clear
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STRLO R0, [R1], #4 @; clear 4 bytes
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BLO bss_clear_loop @; loop until done
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@; call C++ constructors of global objects
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LDR R0, =__ctors_start__
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LDR R1, =__ctors_end__
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ctor_loop:
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CMP R0, R1
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BEQ ctor_end
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LDR R2, [R0], #4
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STMFD SP!, {R0-R1}
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MOV LR, PC
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BX R2
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LDMFD SP!, {R0-R1}
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B ctor_loop
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ctor_end:
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@; Enter the C code
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LDR R0, =rtthread_startup
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BLX R0
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@;----------------- Exception Handler -----------------------------------------
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.global rt_hw_trap_udef
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.global rt_hw_trap_swi
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.global rt_hw_trap_pabt
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.global rt_hw_trap_dabt
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.global rt_hw_trap_resv
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.global rt_hw_trap_irq
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.global rt_hw_trap_fiq
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.global rt_interrupt_enter
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.global rt_interrupt_leave
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.global rt_thread_switch_interrupt_flag
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.global rt_interrupt_from_thread
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.global rt_interrupt_to_thread
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.align 5
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Undef_Handler:
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SUB SP, SP, #S_FRAME_SIZE
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STMIA SP, {R0 - R12} @; Calling R0-R12
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ADD R8, SP, #S_PC
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STMDB R8, {SP, LR} @; Calling SP, LR
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STR LR, [R8, #0] @; Save calling PC
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MRS R6, SPSR
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STR R6, [R8, #4] @; Save CPSR
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STR R0, [R8, #8] @; Save SPSR
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MOV R0, SP
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BL rt_hw_trap_udef
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.align 5
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SWI_Handler:
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BL rt_hw_trap_swi
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.align 5
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PAbt_Handler:
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BL rt_hw_trap_pabt
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.align 5
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DAbt_Handler:
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SUB SP, SP, #S_FRAME_SIZE
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STMIA SP, {R0 - R12} @; Calling R0-R12
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ADD R8, SP, #S_PC
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STMDB R8, {SP, LR} @; Calling SP, LR
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STR LR, [R8, #0] @; Save calling PC
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MRS R6, SPSR
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STR R6, [R8, #4] @; Save CPSR
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STR R0, [R8, #8] @; Save SPSR
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MOV R0, SP
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BL rt_hw_trap_dabt
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.align 5
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Resv_Handler:
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BL rt_hw_trap_resv
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.align 5
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FIQ_Handler:
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STMFD SP!, {R0-R7,LR}
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BL rt_hw_trap_fiq
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LDMFD SP!, {R0-R7,LR}
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SUBS PC, LR, #4
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.align 5
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IRQ_Handler:
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STMFD SP!, {R0-R12,LR}
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BL rt_interrupt_enter
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BL rt_hw_trap_irq
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BL rt_interrupt_leave
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@; If rt_thread_switch_interrupt_flag set,
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@; jump to rt_hw_context_switch_interrupt_do and don't return
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LDR R0, =rt_thread_switch_interrupt_flag
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LDR R1, [R0]
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CMP R1, #1
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BEQ rt_hw_context_switch_interrupt_do
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LDMFD SP!, {R0-R12,LR}
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SUBS PC, LR, #4
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@;------ void rt_hw_context_switch_interrupt_do(rt_base_t flag) -----------------
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rt_hw_context_switch_interrupt_do:
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MOV R1, #0 @; Clear flag
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STR R1, [R0] @; Save to flag variable
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LDMFD SP!, {R0-R12,LR} @; Reload saved registers
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STMFD SP, {R0-R2} @; Save R0-R2
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SUB R1, SP, #4*3 @; Save old task's SP to R1
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SUB R2, LR, #4 @; Save old task's PC to R2
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MRS R0, SPSR @; Get CPSR of interrupt thread
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MSR CPSR_c, #MODE_SVC|NOINT @; Switch to SVC mode and no interrupt
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STMFD SP!, {R2} @; Push old task's PC
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STMFD SP!, {R3-R12,LR} @; Push old task's LR,R12-R3
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LDMFD R1, {R1-R3}
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STMFD SP!, {R1-R3} @; Push old task's R2-R0
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STMFD SP!, {R0} @; Push old task's CPSR
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LDR R4, =rt_interrupt_from_thread
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LDR R5, [R4] @; R5 = stack ptr in old tasks's TCB
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STR SP, [R5] @; Store SP in preempted tasks's TCB
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LDR R6, =rt_interrupt_to_thread
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LDR R6, [R6] @; R6 = stack ptr in new tasks's TCB
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LDR SP, [R6] @; Get new task's stack pointer
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LDMFD SP!, {R4} @; Pop new task's SPSR
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MSR SPSR_cxsf, R4
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LDMFD SP!, {R0-R12,LR,PC}^ @; pop new task's R0-R12,LR & PC SPSR 2 CPSR
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