884 lines
28 KiB
C
884 lines
28 KiB
C
/**
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* \file
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*
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* \brief SAM Direct Memory Access Controller Driver
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*
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* Copyright (C) 2014-2016 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
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*/
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#ifndef DMA_H_INCLUDED
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#define DMA_H_INCLUDED
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* \defgroup asfdoc_sam0_dma_group SAM Direct Memory Access Controller (DMAC) Driver
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*
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* This driver for Atmel® | SMART ARM®-based microcontrollers provides an interface for the configuration
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* and management of the Direct Memory Access Controller(DMAC) module within
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* the device. The DMAC can transfer data between memories and peripherals, and
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* thus off-load these tasks from the CPU. The module supports peripheral to
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* peripheral, peripheral to memory, memory to peripheral, and memory to memory
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* transfers.
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*
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* The following peripheral is used by the DMAC Driver:
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* - DMAC (Direct Memory Access Controller)
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*
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* The following devices can use this module:
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* - Atmel | SMART SAM D21
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* - Atmel | SMART SAM R21
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* - Atmel | SMART SAM D09/D10/D11
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* - Atmel | SMART SAM L21/L22
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* - Atmel | SMART SAM DA1
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* - Atmel | SMART SAM C20/C21
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* - Atmel | SMART SAM HA1
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* - Atmel | SMART SAM R30
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*
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* The outline of this documentation is as follows:
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* - \ref asfdoc_sam0_dma_prerequisites
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* - \ref asfdoc_sam0_dma_module_overview
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* - \ref asfdoc_sam0_dma_special_considerations
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* - \ref asfdoc_sam0_dma_extra_info
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* - \ref asfdoc_sam0_dma_examples
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* - \ref asfdoc_sam0_dma_api_overview
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*
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*
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* \section asfdoc_sam0_dma_prerequisites Prerequisites
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*
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* There are no prerequisites for this module.
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*
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*
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* \section asfdoc_sam0_dma_module_overview Module Overview
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*
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* SAM devices with DMAC enables high data transfer rates with minimum
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* CPU intervention and frees up CPU time. With access to all peripherals,
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* the DMAC can handle automatic transfer of data to/from modules.
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* It supports static and incremental addressing for both source and
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* destination.
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*
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* The DMAC when used with Event System or peripheral triggers, provides a
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* considerable advantage by reducing the power consumption and performing
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* data transfer in the background.
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* For example, if the ADC is configured to generate an event, it can trigger
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* the DMAC to transfer the data into another peripheral or SRAM.
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* The CPU can remain in sleep during this time to reduce the power consumption.
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*
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* <table>
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* <tr>
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* <th>Device</th>
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* <th>Dma channel number</th>
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* </tr>
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* <tr>
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* <td>SAM D21/R21/C20/C21</td>
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* <td>12</td>
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* </tr>
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* <tr>
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* <td>SAM D09/D10/D11</td>
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* <td>6</td>
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* </tr>
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* <tr>
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* <td>SAM L21,SAMR30</td>
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* <td>16</td>
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* </tr>
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* </table>
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* The DMA channel operation can be suspended at any time by software, by events
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* from event system, or after selectable descriptor execution. The operation
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* can be resumed by software or by events from the event system.
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* The DMAC driver for SAM supports four types of transfers such as
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* peripheral to peripheral, peripheral to memory, memory to peripheral, and
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* memory to memory.
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*
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* The basic transfer unit is a beat, which is defined as a single bus access.
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* There can be multiple beats in a single block transfer and multiple block
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* transfers in a DMA transaction.
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* DMA transfer is based on descriptors, which holds transfer properties
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* such as the source and destination addresses, transfer counter, and other
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* additional transfer control information.
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* The descriptors can be static or linked. When static, a single block transfer
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* is performed. When linked, a number of transfer descriptors can be used to
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* enable multiple block transfers within a single DMA transaction.
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*
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* The implementation of the DMA driver is based on the idea that the DMA channel
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* is a finite resource of entities with the same abilities. A DMA channel resource
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* is able to move a defined set of data from a source address to destination
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* address triggered by a transfer trigger. On the SAM devices there are 12
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* DMA resources available for allocation. Each of these DMA resources can trigger
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* interrupt callback routines and peripheral events.
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* The other main features are:
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*
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* - Selectable transfer trigger source
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* - Software
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* - Event System
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* - Peripheral
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* - Event input and output is supported for the four lower channels
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* - Four level channel priority
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* - Optional interrupt generation on transfer complete, channel error, or channel suspend
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* - Supports multi-buffer or circular buffer mode by linking multiple descriptors
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* - Beat size configurable as 8-bit, 16-bit, or 32-bit
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*
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* A simplified block diagram of the DMA Resource can be seen in
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* \ref asfdoc_sam0_dma_module_block_diagram "the figure below".
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*
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* \anchor asfdoc_sam0_dma_module_block_diagram
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* \dot
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* digraph overview {
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* splines = false;
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* rankdir=LR;
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*
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* mux1 [label="Transfer Trigger", shape=box];
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*
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* dma [label="DMA Channel", shape=polygon, sides=6, orientation=60, style=filled, fillcolor=darkolivegreen1, height=1, width=1];
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* descriptor [label="Transfer Descriptor", shape=box, style=filled, fillcolor=lightblue];
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*
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* mux1 -> dma;
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* descriptor -> dma;
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*
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* interrupt [label="Interrupt", shape=box];
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* events [label="Events", shape=box];
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*
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* dma:e -> interrupt:w;
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* dma:e -> events:w;
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*
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* {rank=same; descriptor dma}
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*
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* }
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* \enddot
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*
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* \subsection asfdoc_sam0_dma_features Driver Feature Macro Definition
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* <table>
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* <tr>
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* <th>Driver Feature Macro</th>
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* <th>Supported devices</th>
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* </tr>
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* <tr>
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* <td>FEATURE_DMA_CHANNEL_STANDBY</td>
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* <td>SAM L21/L22/C20/C21/R30</td>
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* </tr>
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* </table>
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* \note The specific features are only available in the driver when the
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* selected device supports those features.
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*
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* \subsection asfdoc_sam0_dma_module_overview_dma_transf_term Terminology Used in DMAC Transfers
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*
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* <table border="0" cellborder="1" cellspacing="0" >
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* <tr>
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* <th> Name </th> <th> Description </th>
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* </tr>
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* <tr>
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* <td > Beat </td>
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* <td > It is a single bus access by the DMAC.
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* Configurable as 8-bit, 16-bit, or 32-bit.
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* </td>
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* </tr>
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* <tr>
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* <td > Burst </td>
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* <td> It is a transfer of n-beats (n=1,4,8,16).
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* For the DMAC module in SAM, the burst size is one beat.
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* Arbitration takes place each time a burst transfer is completed.
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* </td>
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* </tr>
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* <tr>
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* <td > Block transfer </td>
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* <td> A single block transfer is a configurable number of (1 to 64k)
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* beat transfers
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* </td>
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* </tr>
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* </table>
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*
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* \subsection asfdoc_sam0_dma_module_overview_dma_channels DMA Channels
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* The DMAC in each device consists of several DMA channels, which
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* along with the transfer descriptors defines the data transfer properties.
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* - The transfer control descriptor defines the source and destination
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* addresses, source and destination address increment settings, the
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* block transfer count, and event output condition selection
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* - Dedicated channel registers control the peripheral trigger source,
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* trigger mode settings, event input actions, and channel priority level
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* settings
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*
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* With a successful DMA resource allocation, a dedicated
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* DMA channel will be assigned. The channel will be occupied until the
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* DMA resource is freed. A DMA resource handle is used to identify the specific
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* DMA resource.
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* When there are multiple channels with active requests, the arbiter prioritizes
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* the channels requesting access to the bus.
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*
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* \subsection asfdoc_sam0_dma_module_overview_dma_trigger DMA Triggers
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* DMA transfer can be started only when a DMA transfer request is acknowledged/granted by the arbiter. A
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* transfer request can be triggered from software, peripheral, or an event. There
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* are dedicated source trigger selections for each DMA channel usage.
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*
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* \subsection asfdoc_sam0_dma_module_overview_dma_transfer_descriptor DMA Transfer Descriptor
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* The transfer descriptor resides in the SRAM and
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* defines these channel properties.
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* <table border="0" cellborder="1" cellspacing="0" >
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* <tr>
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* <th> Field name </th> <th> Field width </th>
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* </tr>
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* <tr>
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* <td > Descriptor Next Address </td> <td > 32 bits </td>
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* </tr>
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* <tr>
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* <td > Destination Address </td> <td> 32 bits </td>
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* </tr>
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* <tr>
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* <td > Source Address </td> <td> 32 bits </td>
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* </tr>
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* <tr>
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* <td > Block Transfer Counter </td> <td> 16 bits </td>
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* </tr>
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* <tr>
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* <td > Block Transfer Control </td> <td> 16 bits </td>
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* </tr>
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* </table>
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*
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* Before starting a transfer, at least one descriptor should be configured.
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* After a successful allocation of a DMA channel, the transfer descriptor can
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* be added with a call to \ref dma_add_descriptor(). If there is a transfer
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* descriptor already allocated to the DMA resource, the descriptor will
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* be linked to the next descriptor address.
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*
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* \subsection asfdoc_sam0_dma_module_overview_dma_output DMA Interrupts/Events
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* Both an interrupt callback and an peripheral event can be triggered by the
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* DMA transfer. Three types of callbacks are supported by the DMA driver:
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* transfer complete, channel suspend, and transfer error. Each of these callback
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* types can be registered and enabled for each channel independently through
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* the DMA driver API.
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*
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* The DMAC module can also generate events on transfer complete. Event
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* generation is enabled through the DMA channel, event channel configuration,
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* and event user multiplexing is done through the events driver.
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*
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* The DMAC can generate events in the below cases:
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*
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* - When a block transfer is complete
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*
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* - When each beat transfer within a block transfer is complete
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*
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* \section asfdoc_sam0_dma_special_considerations Special Considerations
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*
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* There are no special considerations for this module.
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*
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*
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* \section asfdoc_sam0_dma_extra_info Extra Information
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*
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* For extra information, see \ref asfdoc_sam0_dma_extra. This includes:
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* - \ref asfdoc_sam0_dma_extra_acronyms
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* - \ref asfdoc_sam0_dma_extra_dependencies
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* - \ref asfdoc_sam0_dma_extra_errata
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* - \ref asfdoc_sam0_dma_extra_history
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*
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*
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* \section asfdoc_sam0_dma_examples Examples
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*
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* For a list of examples related to this driver, see
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* \ref asfdoc_sam0_dma_exqsg.
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*
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*
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* \section asfdoc_sam0_dma_api_overview API Overview
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* @{
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*/
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#include <compiler.h>
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#include "conf_dma.h"
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#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) || defined(__DOXYGEN__)
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#define FEATURE_DMA_CHANNEL_STANDBY
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#endif
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/** DMA invalid channel number. */
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#define DMA_INVALID_CHANNEL 0xff
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/** ExInitial description section. */
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extern DmacDescriptor descriptor_section[CONF_MAX_USED_CHANNEL_NUM];
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/* DMA channel interrup flag. */
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extern uint8_t g_chan_interrupt_flag[CONF_MAX_USED_CHANNEL_NUM];
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/** DMA priority level. */
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enum dma_priority_level {
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/** Priority level 0. */
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DMA_PRIORITY_LEVEL_0,
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/** Priority level 1. */
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DMA_PRIORITY_LEVEL_1,
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/** Priority level 2. */
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DMA_PRIORITY_LEVEL_2,
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/** Priority level 3. */
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DMA_PRIORITY_LEVEL_3,
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};
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/** DMA input actions. */
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enum dma_event_input_action {
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/** No action. */
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DMA_EVENT_INPUT_NOACT,
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/** Normal transfer and periodic transfer trigger. */
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DMA_EVENT_INPUT_TRIG,
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/** Conditional transfer trigger. */
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DMA_EVENT_INPUT_CTRIG,
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/** Conditional block transfer. */
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DMA_EVENT_INPUT_CBLOCK,
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/** Channel suspend operation. */
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DMA_EVENT_INPUT_SUSPEND,
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/** Channel resume operation. */
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DMA_EVENT_INPUT_RESUME,
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/** Skip next block suspend action. */
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DMA_EVENT_INPUT_SSKIP,
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};
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/**
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* Address increment step size. These bits select the address increment step
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* size. The setting apply to source or destination address, depending on
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* STEPSEL setting.
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*/
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enum dma_address_increment_stepsize {
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/** The address is incremented by (beat size * 1). */
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DMA_ADDRESS_INCREMENT_STEP_SIZE_1 = 0,
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/** The address is incremented by (beat size * 2). */
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DMA_ADDRESS_INCREMENT_STEP_SIZE_2,
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/** The address is incremented by (beat size * 4). */
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DMA_ADDRESS_INCREMENT_STEP_SIZE_4,
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/** The address is incremented by (beat size * 8). */
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DMA_ADDRESS_INCREMENT_STEP_SIZE_8,
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/** The address is incremented by (beat size * 16). */
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DMA_ADDRESS_INCREMENT_STEP_SIZE_16,
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/** The address is incremented by (beat size * 32). */
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DMA_ADDRESS_INCREMENT_STEP_SIZE_32,
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/** The address is incremented by (beat size * 64). */
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DMA_ADDRESS_INCREMENT_STEP_SIZE_64,
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/** The address is incremented by (beat size * 128). */
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DMA_ADDRESS_INCREMENT_STEP_SIZE_128,
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};
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/**
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* DMA step selection. This bit determines whether the step size setting
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* is applied to source or destination address.
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*/
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enum dma_step_selection {
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/** Step size settings apply to the destination address. */
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DMA_STEPSEL_DST = 0,
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/** Step size settings apply to the source address. */
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DMA_STEPSEL_SRC,
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};
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/** The basic transfer unit in DMAC is a beat, which is defined as a
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* single bus access. Its size is configurable and applies to both read
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* and write. */
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enum dma_beat_size {
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/** 8-bit access. */
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DMA_BEAT_SIZE_BYTE = 0,
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/** 16-bit access. */
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DMA_BEAT_SIZE_HWORD,
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/** 32-bit access. */
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DMA_BEAT_SIZE_WORD,
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};
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/**
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* Block action definitions.
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*/
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enum dma_block_action {
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/** No action. */
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DMA_BLOCK_ACTION_NOACT = 0,
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/** Channel in normal operation and sets transfer complete interrupt flag
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* after block transfer. */
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DMA_BLOCK_ACTION_INT,
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/** Trigger channel suspend after block transfer and sets channel
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* suspend interrupt flag once the channel is suspended. */
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DMA_BLOCK_ACTION_SUSPEND,
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/** Sets transfer complete interrupt flag after a block transfer and
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* trigger channel suspend. The channel suspend interrupt flag will be set
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* once the channel is suspended. */
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DMA_BLOCK_ACTION_BOTH,
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};
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/** Event output selection. */
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enum dma_event_output_selection {
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/** Event generation disable. */
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DMA_EVENT_OUTPUT_DISABLE = 0,
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/** Event strobe when block transfer complete. */
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DMA_EVENT_OUTPUT_BLOCK,
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/** Event output reserved. */
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DMA_EVENT_OUTPUT_RESERVED,
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/** Event strobe when beat transfer complete. */
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DMA_EVENT_OUTPUT_BEAT,
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};
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/** DMA trigger action type. */
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enum dma_transfer_trigger_action{
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/** Perform a block transfer when triggered. */
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DMA_TRIGGER_ACTION_BLOCK = DMAC_CHCTRLB_TRIGACT_BLOCK_Val,
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/** Perform a beat transfer when triggered. */
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DMA_TRIGGER_ACTION_BEAT = DMAC_CHCTRLB_TRIGACT_BEAT_Val,
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/** Perform a transaction when triggered. */
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DMA_TRIGGER_ACTION_TRANSACTION = DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val,
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};
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/**
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* Callback types for DMA callback driver.
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*/
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enum dma_callback_type {
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/** Callback for any of transfer errors. A transfer error is flagged
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* if a bus error is detected during an AHB access or when the DMAC
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* fetches an invalid descriptor. */
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DMA_CALLBACK_TRANSFER_ERROR,
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/** Callback for transfer complete. */
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DMA_CALLBACK_TRANSFER_DONE,
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/** Callback for channel suspend. */
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DMA_CALLBACK_CHANNEL_SUSPEND,
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/** Number of available callbacks. */
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DMA_CALLBACK_N,
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};
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/**
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* DMA transfer descriptor configuration. When the source or destination address
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* increment is enabled, the addresses stored into the configuration structure
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* must correspond to the end of the transfer.
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*
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*/
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struct dma_descriptor_config {
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/** Descriptor valid flag used to identify whether a descriptor is
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valid or not */
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bool descriptor_valid;
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/** This is used to generate an event on specific transfer action in
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a channel. Supported only in four lower channels. */
|
|
enum dma_event_output_selection event_output_selection;
|
|
/** Action taken when a block transfer is completed */
|
|
enum dma_block_action block_action;
|
|
/** Beat size is configurable as 8-bit, 16-bit, or 32-bit */
|
|
enum dma_beat_size beat_size;
|
|
/** Used for enabling the source address increment */
|
|
bool src_increment_enable;
|
|
/** Used for enabling the destination address increment */
|
|
bool dst_increment_enable;
|
|
/** This bit selects whether the source or destination address is
|
|
using the step size settings */
|
|
enum dma_step_selection step_selection;
|
|
/** The step size for source/destination address increment.
|
|
The next address is calculated
|
|
as next_addr = addr + (2^step_size * beat size). */
|
|
enum dma_address_increment_stepsize step_size;
|
|
/** It is the number of beats in a block. This count value is
|
|
* decremented by one after each beat data transfer. */
|
|
uint16_t block_transfer_count;
|
|
/** Transfer source address */
|
|
uint32_t source_address;
|
|
/** Transfer destination address */
|
|
uint32_t destination_address;
|
|
/** Set to zero for static descriptors. This must have a valid memory
|
|
address for linked descriptors. */
|
|
uint32_t next_descriptor_address;
|
|
};
|
|
|
|
/** Configurations for DMA events. */
|
|
struct dma_events_config {
|
|
/** Event input actions */
|
|
enum dma_event_input_action input_action;
|
|
/** Enable DMA event output */
|
|
bool event_output_enable;
|
|
};
|
|
|
|
/** DMA configurations for transfer. */
|
|
struct dma_resource_config {
|
|
/** DMA transfer priority */
|
|
enum dma_priority_level priority;
|
|
/**DMA peripheral trigger index */
|
|
uint8_t peripheral_trigger;
|
|
/** DMA trigger action */
|
|
enum dma_transfer_trigger_action trigger_action;
|
|
#ifdef FEATURE_DMA_CHANNEL_STANDBY
|
|
/** Keep DMA channel enabled in standby sleep mode if true */
|
|
bool run_in_standby;
|
|
#endif
|
|
/** DMA events configurations */
|
|
struct dma_events_config event_config;
|
|
};
|
|
|
|
/** Forward definition of the DMA resource. */
|
|
struct dma_resource;
|
|
/** Type definition for a DMA resource callback function. */
|
|
typedef void (*dma_callback_t)(struct dma_resource *const resource);
|
|
|
|
/** Structure for DMA transfer resource. */
|
|
struct dma_resource {
|
|
/** Allocated DMA channel ID */
|
|
uint8_t channel_id;
|
|
/** Array of callback functions for DMA transfer job */
|
|
dma_callback_t callback[DMA_CALLBACK_N];
|
|
/** Bit mask for enabled callbacks */
|
|
uint8_t callback_enable;
|
|
/** Status of the last job */
|
|
volatile enum status_code job_status;
|
|
/** Transferred data size */
|
|
uint32_t transfered_size;
|
|
/** DMA transfer descriptor */
|
|
DmacDescriptor* descriptor;
|
|
};
|
|
|
|
/**
|
|
* \brief Get DMA resource status.
|
|
*
|
|
* \param[in] resource Pointer to the DMA resource
|
|
*
|
|
* \return Status of the DMA resource.
|
|
*/
|
|
static inline enum status_code dma_get_job_status(struct dma_resource *resource)
|
|
{
|
|
Assert(resource);
|
|
|
|
return resource->job_status;
|
|
}
|
|
|
|
/**
|
|
* \brief Check if the given DMA resource is busy.
|
|
*
|
|
* \param[in] resource Pointer to the DMA resource
|
|
*
|
|
* \return Status which indicates whether the DMA resource is busy.
|
|
*
|
|
* \retval true The DMA resource has an on-going transfer
|
|
* \retval false The DMA resource is not busy
|
|
*/
|
|
static inline bool dma_is_busy(struct dma_resource *resource)
|
|
{
|
|
Assert(resource);
|
|
|
|
return (resource->job_status == STATUS_BUSY);
|
|
}
|
|
|
|
/**
|
|
* \brief Enable a callback function for a dedicated DMA resource.
|
|
*
|
|
* \param[in] resource Pointer to the DMA resource
|
|
* \param[in] type Callback function type
|
|
*
|
|
*/
|
|
static inline void dma_enable_callback(struct dma_resource *resource,
|
|
enum dma_callback_type type)
|
|
{
|
|
Assert(resource);
|
|
|
|
resource->callback_enable |= 1 << type;
|
|
g_chan_interrupt_flag[resource->channel_id] |= (1UL << type);
|
|
}
|
|
|
|
/**
|
|
* \brief Disable a callback function for a dedicated DMA resource.
|
|
*
|
|
* \param[in] resource Pointer to the DMA resource
|
|
* \param[in] type Callback function type
|
|
*
|
|
*/
|
|
static inline void dma_disable_callback(struct dma_resource *resource,
|
|
enum dma_callback_type type)
|
|
{
|
|
Assert(resource);
|
|
|
|
resource->callback_enable &= ~(1 << type);
|
|
g_chan_interrupt_flag[resource->channel_id] &= (~(1UL << type) & DMAC_CHINTENSET_MASK);
|
|
DMAC->CHINTENCLR.reg = (1UL << type);
|
|
}
|
|
|
|
/**
|
|
* \brief Register a callback function for a dedicated DMA resource.
|
|
*
|
|
* There are three types of callback functions, which can be registered:
|
|
* - Callback for transfer complete
|
|
* - Callback for transfer error
|
|
* - Callback for channel suspend
|
|
*
|
|
* \param[in] resource Pointer to the DMA resource
|
|
* \param[in] callback Pointer to the callback function
|
|
* \param[in] type Callback function type
|
|
*
|
|
*/
|
|
static inline void dma_register_callback(struct dma_resource *resource,
|
|
dma_callback_t callback, enum dma_callback_type type)
|
|
{
|
|
Assert(resource);
|
|
|
|
resource->callback[type] = callback;
|
|
}
|
|
|
|
/**
|
|
* \brief Unregister a callback function for a dedicated DMA resource.
|
|
*
|
|
* There are three types of callback functions:
|
|
* - Callback for transfer complete
|
|
* - Callback for transfer error
|
|
* - Callback for channel suspend
|
|
*
|
|
* The application can unregister any of the callback functions which
|
|
* are already registered and are no longer needed.
|
|
*
|
|
* \param[in] resource Pointer to the DMA resource
|
|
* \param[in] type Callback function type
|
|
*
|
|
*/
|
|
static inline void dma_unregister_callback(struct dma_resource *resource,
|
|
enum dma_callback_type type)
|
|
{
|
|
Assert(resource);
|
|
|
|
resource->callback[type] = NULL;
|
|
}
|
|
|
|
/**
|
|
* \brief Will set a software trigger for resource.
|
|
*
|
|
* This function is used to set a software trigger on the DMA channel
|
|
* associated with resource. If a trigger is already pending no new trigger
|
|
* will be generated for the channel.
|
|
*
|
|
* \param[in] resource Pointer to the DMA resource
|
|
*/
|
|
static inline void dma_trigger_transfer(struct dma_resource *resource) {
|
|
Assert(resource);
|
|
|
|
DMAC->SWTRIGCTRL.reg |= (1 << resource->channel_id);
|
|
}
|
|
|
|
/**
|
|
* \brief Initializes DMA transfer configuration with predefined default values.
|
|
*
|
|
* This function will initialize a given DMA descriptor configuration structure to
|
|
* a set of known default values. This function should be called on
|
|
* any new instance of the configuration structure before being
|
|
* modified by the user application.
|
|
*
|
|
* The default configuration is as follows:
|
|
* \li Set the descriptor as valid
|
|
* \li Disable event output
|
|
* \li No block action
|
|
* \li Set beat size as byte
|
|
* \li Enable source increment
|
|
* \li Enable destination increment
|
|
* \li Step size is applied to the destination address
|
|
* \li Address increment is beat size multiplied by 1
|
|
* \li Default transfer size is set to 0
|
|
* \li Default source address is set to NULL
|
|
* \li Default destination address is set to NULL
|
|
* \li Default next descriptor not available
|
|
* \param[out] config Pointer to the configuration
|
|
*
|
|
*/
|
|
static inline void dma_descriptor_get_config_defaults(struct dma_descriptor_config *config)
|
|
{
|
|
Assert(config);
|
|
|
|
/* Set descriptor as valid */
|
|
config->descriptor_valid = true;
|
|
/* Disable event output */
|
|
config->event_output_selection = DMA_EVENT_OUTPUT_DISABLE;
|
|
/* No block action */
|
|
config->block_action = DMA_BLOCK_ACTION_NOACT;
|
|
/* Set beat size to one byte */
|
|
config->beat_size = DMA_BEAT_SIZE_BYTE;
|
|
/* Enable source increment */
|
|
config->src_increment_enable = true;
|
|
/* Enable destination increment */
|
|
config->dst_increment_enable = true;
|
|
/* Step size is applied to the destination address */
|
|
config->step_selection = DMA_STEPSEL_DST;
|
|
/* Address increment is beat size multiplied by 1*/
|
|
config->step_size = DMA_ADDRESS_INCREMENT_STEP_SIZE_1;
|
|
/* Default transfer size is set to 0 */
|
|
config->block_transfer_count = 0;
|
|
/* Default source address is set to NULL */
|
|
config->source_address = (uint32_t)NULL;
|
|
/* Default destination address is set to NULL */
|
|
config->destination_address = (uint32_t)NULL;
|
|
/** Next descriptor address set to 0 */
|
|
config->next_descriptor_address = 0;
|
|
}
|
|
|
|
/**
|
|
* \brief Update DMA descriptor.
|
|
*
|
|
* This function can update the descriptor of an allocated DMA resource.
|
|
*
|
|
*/
|
|
static inline void dma_update_descriptor(struct dma_resource *resource,
|
|
DmacDescriptor* descriptor)
|
|
{
|
|
Assert(resource);
|
|
|
|
resource->descriptor = descriptor;
|
|
}
|
|
|
|
/**
|
|
* \brief Reset DMA descriptor.
|
|
*
|
|
* This function will clear the DESCADDR register of an allocated DMA resource.
|
|
*
|
|
*/
|
|
static inline void dma_reset_descriptor(struct dma_resource *resource)
|
|
{
|
|
Assert(resource);
|
|
|
|
resource->descriptor = NULL;
|
|
}
|
|
|
|
void dma_get_config_defaults(struct dma_resource_config *config);
|
|
enum status_code dma_allocate(struct dma_resource *resource,
|
|
struct dma_resource_config *config);
|
|
enum status_code dma_free(struct dma_resource *resource);
|
|
enum status_code dma_start_transfer_job(struct dma_resource *resource);
|
|
void dma_abort_job(struct dma_resource *resource);
|
|
void dma_suspend_job(struct dma_resource *resource);
|
|
void dma_resume_job(struct dma_resource *resource);
|
|
void dma_descriptor_create(DmacDescriptor* descriptor,
|
|
struct dma_descriptor_config *config);
|
|
enum status_code dma_add_descriptor(struct dma_resource *resource,
|
|
DmacDescriptor* descriptor);
|
|
|
|
/** @} */
|
|
|
|
/**
|
|
* \page asfdoc_sam0_dma_extra Extra Information for DMAC Driver
|
|
*
|
|
* \section asfdoc_sam0_dma_extra_acronyms Acronyms
|
|
* Below is a table listing the acronyms used in this module, along with their
|
|
* intended meanings.
|
|
*
|
|
* <table>
|
|
* <tr>
|
|
* <th>Acronym</th>
|
|
* <th>Description</th>
|
|
* </tr>
|
|
* <tr>
|
|
* <td>DMA</td>
|
|
* <td>Direct Memory Access</td>
|
|
* </tr>
|
|
* <tr>
|
|
* <td>DMAC</td>
|
|
* <td>Direct Memory Access Controller </td>
|
|
* </tr>
|
|
* <tr>
|
|
* <td>CPU</td>
|
|
* <td>Central Processing Unit</td>
|
|
* </tr>
|
|
* </table>
|
|
*
|
|
*
|
|
* \section asfdoc_sam0_dma_extra_dependencies Dependencies
|
|
* This driver has the following dependencies:
|
|
*
|
|
* - \ref asfdoc_sam0_system_clock_group "System Clock Driver"
|
|
*
|
|
*
|
|
* \section asfdoc_sam0_dma_extra_errata Errata
|
|
* There are no errata related to this driver.
|
|
*
|
|
*
|
|
* \section asfdoc_sam0_dma_extra_history Module History
|
|
* An overview of the module history is presented in the table below, with
|
|
* details on the enhancements and fixes made to the module since its first
|
|
* release. The current version of this corresponds to the newest version in
|
|
* the table.
|
|
*
|
|
* <table>
|
|
* <tr>
|
|
* <th>Changelog</th>
|
|
* </tr>
|
|
* <tr>
|
|
* <td>Add SAM C21 support</td>
|
|
* </tr>
|
|
* <tr>
|
|
* <td>Add SAM L21 support</td>
|
|
* </tr>
|
|
* <tr>
|
|
* <td>Add SAM R30 support</td>
|
|
* </tr>
|
|
* <tr>
|
|
* <td>Initial Release</td>
|
|
* </tr>
|
|
* </table>
|
|
*/
|
|
|
|
/**
|
|
* \page asfdoc_sam0_dma_exqsg Examples for DMAC Driver
|
|
*
|
|
* This is a list of the available Quick Start Guides (QSGs) and example
|
|
* applications for \ref asfdoc_sam0_dma_group. QSGs are simple examples with
|
|
* step-by-step instructions to configure and use this driver in a selection of
|
|
* use cases. Note that a QSG can be compiled as a standalone application or be
|
|
* added to the user application.
|
|
*
|
|
* - \subpage asfdoc_sam0_dma_basic_use_case
|
|
*
|
|
* \note More DMA usage examples are available in peripheral QSGs.
|
|
* A quick start guide for TC/TCC
|
|
* shows the usage of DMA event trigger; SERCOM SPI/USART/I<SUP>2</SUP>C has example for
|
|
* DMA transfer from peripheral to memory or from memory to peripheral;
|
|
* ADC/DAC shows peripheral to peripheral transfer.
|
|
*
|
|
* \page asfdoc_sam0_dma_document_revision_history Document Revision History
|
|
*
|
|
* <table>
|
|
* <tr>
|
|
* <th>Doc. Rev.</th>
|
|
* <th>Date</th>
|
|
* <th>Comments</th>
|
|
* </tr>
|
|
* <tr>
|
|
* <td>42257C</td>
|
|
* <td>12/2015</td>
|
|
* <td>Added suppport for SAM L21/L22, SAM C21, SAM D09, SAMR30 and SAM DA1</td>
|
|
* </tr>
|
|
* <tr>
|
|
* <td>42257B</td>
|
|
* <td>12/2014</td>
|
|
* <td>Added support for SAM R21 and SAM D10/D11</td>
|
|
* </tr>
|
|
* <tr>
|
|
* <td>42257A</td>
|
|
* <td>02/2014</td>
|
|
* <td>Initial release</td>
|
|
* </tr>
|
|
* </table>
|
|
*/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* DMA_H_INCLUDED */
|