133 lines
5.9 KiB
Markdown
133 lines
5.9 KiB
Markdown
# SAML10E16A BSP Introduction
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[中文](README_zh.md)
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- MCU: ATSAML10E16A @32MHz, 64KB FLASH, 16KB RAM, 1.62V – 3.63V
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- L10: Cortex-M23 + Hardware multiplier & divider + ultra low power(< 25 μA/MHz)
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- Pin: E=32 pins, D=24pins
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- Flash: 16=64KB, 15=32KB, 14=16KB(size=2^n)
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- SRAM : 16KB(Flash 64KB), 8KB(Flash 32KB), 4KB(Flash 16KB)
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- Datasheet: <https://www.microchip.com/en-us/product/ATSAML10E16A>
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#### KEY FEATURES
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#### Core
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- 32 MHz (2.64 CoreMark/MHz and up to 31 DMIPS) Arm® Cortex®-M23 with:
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- Single-cycle hardware multiplier
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- Hardware divider
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- Nested Vector Interrupt Controller (NVIC)
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- Memory Protection Unit (MPU)
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- Stack Limit Checking
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- TrustZone® for ARMv8-M (optional)
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#### Memories
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- 16/32/64-KB Flash
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- 4/8/16-KB SRAM
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- 2-KB Data Flash Write-While-Read (WWR) section for non-volatile data storage
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- 256 bytes TrustRAM with physical protection features
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#### System
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- Power-on Reset (POR) and programmable Brown-out Detection (BOD)
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- 8-channel Direct Memory Access Controller (DMAC)
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- 8-channel event system for Inter-peripheral Core-independent Operation
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- CRC-32 generator
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#### Clock Management
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- Flexible clock distribution optimized for low power
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- 32.768 kHz crystal oscillator
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- 32.768 kHz ultra low-power internal RC oscillator
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- 0.4 to 32 MHz crystal oscillator
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- 16/12/8/4 MHz low-power internal RC oscillator
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- Ultra low-power digital Frequency-Locked Loop (DFLLULP)
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- 32-96 MHz fractional digital Phase-Locked Loop (FDPLL96M)
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- One frequency meter
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- Low-Power and Power Management
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- Active, Idle, Standby with partial or full SRAM retention and off sleep modes:
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- Active mode (< 25 μA/MHz)
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- Idle mode (< 10 μA/MHz) with 1.5 μs wake-up time
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- Standby with Full SRAM Retention (0.5 μA) with 5.3 μs wake-up time
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- Off mode (< 100 nA)
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- Static and dynamic power gating architecture
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- Sleepwalking peripherals
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- Two performance levels
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- Embedded Buck/LDO regulator with on-the-fly selection
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#### Security
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- Up to four tamper pins for static and dynamic intrusion detections
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- Data Flash
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- Optimized for secure storage
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- Address and data scrambling with user-defined key (optional)
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- Rapid tamper erase on scrambling key and on one user-defined row
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- Silent access for data read noise reduction
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- TrustRAM
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- Address and data scrambling with user-defined key
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- Chip-level tamper detection on physical RAM to resist microprobing attacks
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- Rapid tamper erase on scrambling key and RAM data
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- Silent access for data read noise reduction
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- Data remanence prevention
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- Peripherals
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- One True Random Generator (TRNG)
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- AES-128, SHA-256, and GCM cryptography accelerators (optional)
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- Secure pin multiplexing to isolate on dedicated I/O pins a secured communication with external devices from the non-secure application (optional)
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- TrustZone for flexible hardware isolation of memories and peripherals (optional)
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- Up to six regions for the Flash
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- Up to two regions for the Data Flash
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- Up to two regions for the SRAM
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- Individual security attribution for each peripheral, I/O, external interrupt line, and Event System Channel
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- Secure Boot with SHA-based authentication (optional)
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- Up to three debug access levels
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- Up to three Chip Erase commands to erase part of or the entire embedded memories
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- Unique 128-bit serial number
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- SAM L11 Securely Key Provisioned (KPH) (optional)
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- Key Provisioning using Root of Trust flow
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- Security Software Framework using Kinibi-M™ Software Development Kit (SDK)
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#### Advanced Analog and Touch
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- One 12-bit 1 Msps Analog-to-Digital Converter (ADC) with up to 10 channels
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- Two Analog Comparators (AC) with window compare function
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- One 10-bit 350 kSPS Digital-to-Analog Converter (DAC) with external and internal outputs
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- Three Operational Amplifiers (OPAMP)
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- One enhanced Peripheral Touch Controller (PTC):
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- Up to 20 self-capacitance channels
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- Up to 100 (10x10) mutual-capacitance channels
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- Low-power, high-sensitivity, environmentally robust capacitive touch buttons, sliders, and wheels
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- Hardware noise filtering and noise signal desynchronization for high conducted immunity
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- Driven Shield Plus for better noise immunity and moisture tolerance
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- Parallel Acquisition through Polarity control
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- Supports wake-up on touch from Standby Sleep mode
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#### Communication Interfaces
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- Up to three Serial Communication Interfaces (SERCOM) that can operate as:
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- USART with full-duplex and single-wire half-duplex configuration
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- I2C up to 3.4 Mbit/s (High-Speed mode) on one instance and up to 1 Mbit/s (Fast-mode Plus) on the second instance
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- Serial Peripheral Interface (SPI)
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- ISO7816 on one instance (Available on 32-pin packages only)
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- RS-485 on one instance (Available on 32-pin packages only)
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- LIN Slave on one instance (Available on 32-pin packages only)
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- Timers/Output Compare/Input Capture
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- Three 16-bit Timers/Counters (TC), each configurable as:
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- One 16-bit TC with two compare/capture channels
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- One 8-bit TC with two compare/capture channels
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- One 32-bit TC with two compare/capture channels, by using two TCs
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- 32-bit Real-Time Counter (RTC) with clock/calendar functions
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- Watchdog Timer (WDT) with Window mode
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- Input/Output (I/O)
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- Up to 25 programmable I/O lines
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- Eight external interrupts (EIC)
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- One non-maskable interrupt (NMI)
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- One Configurable Custom Logic (CCL) that supports:
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- Combinatorial logic functions, such as AND, NAND, OR, and NOR
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- Sequential logic functions, such as Flip-Flop and Latches
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#### Qualification
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- AEC-Q100 Grade 1 (-40°C to 125°C)
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- Class-B safety library, IEC 60730 (future)
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#### Packages
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- 24-pin VQFN(4*4mm/17 I/O pins)
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- 32-pin VQFN(5*5mm/25 I/O pins)
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- 32-pin TQFP(7*7mm/17 I/O pins)
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- 32-pin WLCSP(2.79*2.79mm/25 I/O pins)
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#### Board info
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- [SAM L10 XPLAINED PRO](https://ww1.microchip.com/downloads/en/Appnotes/Getting-Started-with-SAM%20L10L11-Xplained-Pro-DS00002722A.pdf)
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