900 lines
28 KiB
C
900 lines
28 KiB
C
/**
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******************************************************************************
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* @brief I2C functions of the firmware library.
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "gd32f10x_i2c.h"
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#include "gd32f10x_rcc.h"
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/** @addtogroup GD32F10x_Firmware
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* @{
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*/
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/** @defgroup I2C
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* @brief I2C driver modules
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* @{
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*/
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/** @defgroup I2C_Private_Defines
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* @{
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*/
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/* I2C CTLR1_I2CEN mask */
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#define CTLR1_I2CEN_SET I2C_CTLR1_I2CEN
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#define CTLR1_I2CEN_RESET ((uint16_t)~I2C_CTLR1_I2CEN)
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/* I2C CTLR1_GENSTA mask */
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#define CTLR1_GENSTA_SET I2C_CTLR1_GENSTA
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#define CTLR1_GENSTA_RESET ((uint16_t)~I2C_CTLR1_GENSTA)
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/* I2C CTLR1_GENSTP mask */
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#define CTLR1_GENSTP_SET I2C_CTLR1_GENSTP
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#define CTLR1_GENSTP_RESET ((uint16_t)~I2C_CTLR1_GENSTP)
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/* I2C CTLR1_ACKEN mask */
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#define CTLR1_ACKEN_SET I2C_CTLR1_ACKEN
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#define CTLR1_ACKEN_RESET ((uint16_t)~I2C_CTLR1_ACKEN)
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/* I2C CTLR1_GCEN mask */
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#define CTLR1_GCEN_SET I2C_CTLR1_GCEN
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#define CTLR1_GCEN_RESET ((uint16_t)~I2C_CTLR1_GCEN)
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/* I2C CTLR1_SRESET mask */
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#define CTLR1_SRESET_SET I2C_CTLR1_SRESET
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#define CTLR1_SRESET_RESET ((uint16_t)~I2C_CTLR1_SRESET)
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/* I2C CTLR1_SALT mask */
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#define CTLR1_SALT_SET I2C_CTLR1_SALT
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#define CTLR1_SALT_RESET ((uint16_t)~I2C_CTLR1_SALT)
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/* I2C CTLR1_PECTRANS mask */
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#define CTLR1_PECTRANS_SET I2C_CTLR1_PECTRANS
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#define CTLR1_PECTRANS_RESET ((uint16_t)~I2C_CTLR1_PECTRANS)
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/* I2C CTLR1_PECEN mask */
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#define CTLR1_PECEN_SET I2C_CTLR1_PECEN
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#define CTLR1_PECEN_RESET ((uint16_t)~I2C_CTLR1_PECEN)
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/* I2C CTLR1_ARPEN mask */
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#define CTLR1_ARPEN_SET I2C_CTLR1_ARPEN
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#define CTLR1_ARPEN_RESET ((uint16_t)~I2C_CTLR1_ARPEN)
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/* I2C CTLR1_DISSTRC mask */
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#define CTLR1_DISSTRC_SET I2C_CTLR1_DISSTRC
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#define CTLR1_DISSTRC_RESET ((uint16_t)~I2C_CTLR1_DISSTRC)
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/* I2C registers Masks */
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#define CTLR1_CLEAR_MASK ((uint16_t)0xFBF5)
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/* I2C CTLR2_DMAON mask */
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#define CTLR2_DMAON_SET I2C_CTLR2_DMAON
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#define CTLR2_DMAON_RESET ((uint16_t)~I2C_CTLR2_DMAON)
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/* I2C CTLR2_DMALST mask */
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#define CTLR2_DMALST_SET I2C_CTLR2_DMALST
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#define CTLR2_DMALST_RESET ((uint16_t)~I2C_CTLR2_DMALST)
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/* I2C CTLR2_I2CCLK mask */
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#define CTLR2_I2CCLK_RESET ((uint16_t)0xFFC0)
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/* I2C I2CCLK_Freq_MAX */
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#define I2CCLK_FREQ_MAX I2C_CTLR2_I2CCLK
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/* I2C AR1_ADDRESS0 mask */
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#define AR1_ADDRESS0_SET I2C_AR1_ADDRESS0
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#define AR1_ADDRESS0_RESET ((uint16_t)~I2C_AR1_ADDRESS0)
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/* I2C AR2_DUADEN mask */
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#define AR2_DUADEN_SET ((uint16_t)0x0001)
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#define AR2_DUADEN_RESET ((uint16_t)0xFFFE)
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/* I2C AR2_ADDRESS2 mask */
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#define AR2_ADDRESS2_RESET ((uint16_t)0xFF01)
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/* I2C CLKR_FAST mask */
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#define CLKR_FAST_SET ((uint16_t)0x8000)
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/* I2C CLKR_CLKC mask */
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#define CLKR_CLKC_SET ((uint16_t)0x0FFF)
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/* I2C STR_FLAG mask */
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#define STR_FLAG_MASK ((uint32_t)0x00FFFFFF)
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/* I2C Interrupt Enable mask */
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#define INTEN_MASK ((uint32_t)0x07000000)
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/**
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* @}
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*/
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/** @defgroup I2C_Private_Functions
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* @{
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*/
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/**
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* @brief Reset the I2Cx interface.
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* @param I2Cx: the I2C interface where x can be 1 or 2.
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* @retval None.
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*/
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void I2C_DeInit(I2C_TypeDef *I2Cx)
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{
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if (I2Cx == I2C1) {
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/* Enable I2C1 reset state */
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RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_I2C1RST, ENABLE);
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/* Release I2C1 from reset state */
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RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_I2C1RST, DISABLE);
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} else {
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/* Enable I2C2 reset state */
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RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_I2C2RST, ENABLE);
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/* Release I2C2 from reset state */
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RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_I2C2RST, DISABLE);
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}
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}
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/**
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* @brief Initialize the I2Cx interface parameters.
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* @param I2Cx: the I2C interface where x can be 1 or 2.
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* @param I2C_InitParaStruct: the sturct I2C_InitPara pointer.
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* @retval None.
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*/
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void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitPara *I2C_InitParaStruct)
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{
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uint16_t temp = 0, freqrange = 0;
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uint16_t result = 0x04;
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uint32_t pclk1 = 8000000;
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RCC_ClocksPara rcc_clocks;
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/* Disable I2C */
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I2Cx->CTLR1 &= CTLR1_I2CEN_RESET;
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/* CTLR2 */
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temp = I2Cx->CTLR2;
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/* I2CCLK[5:0] */
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temp &= CTLR2_I2CCLK_RESET;
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RCC_GetClocksFreq(&rcc_clocks);
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pclk1 = rcc_clocks.APB1_Frequency;
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freqrange = (uint16_t)(pclk1 / 1000000);
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if (freqrange > I2CCLK_FREQ_MAX) {
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freqrange = I2CCLK_FREQ_MAX;
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}
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temp |= freqrange;
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I2Cx->CTLR2 = temp;
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/* RTR and CLKR */
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temp = 0;
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if (I2C_InitParaStruct->I2C_BitRate <= 100000) {
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/* Standard mode */
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result = (uint16_t)(pclk1 / (I2C_InitParaStruct->I2C_BitRate << 1));
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if (result < 0x04) {
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/* The CLKR.CLKC higher than 0x04 in standard mode*/
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result = 0x04;
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}
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temp |= result;
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I2Cx->CLKR = temp;
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/* RTR */
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if (freqrange >= I2CCLK_FREQ_MAX) {
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I2Cx->RTR = I2CCLK_FREQ_MAX;
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} else {
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I2Cx->RTR = freqrange + 1;
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}
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} else {
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/* Fast mode */
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if (I2C_InitParaStruct->I2C_DutyCycle == I2C_DUTYCYCLE_2) {
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/* I2C_DutyCycle == 2 */
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result = (uint16_t)(pclk1 / (I2C_InitParaStruct->I2C_BitRate * 3));
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} else {
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/* I2C_DutyCycle == 16/9 */
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result = (uint16_t)(pclk1 / (I2C_InitParaStruct->I2C_BitRate * 25));
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result |= I2C_DUTYCYCLE_16_9;
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}
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if ((result & CLKR_CLKC_SET) == 0) {
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/* The CLKR.CLKC higher than 0x01 in fast mode*/
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result |= (uint16_t)0x0001;
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}
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temp |= (uint16_t)(result | CLKR_FAST_SET);
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/* RTR */
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I2Cx->RTR = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);
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}
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I2Cx->CLKR = temp;
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/* CTLR1 */
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I2Cx->CTLR1 |= CTLR1_I2CEN_SET;
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temp = I2Cx->CTLR1;
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temp &= CTLR1_CLEAR_MASK;
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temp |= (uint16_t)((uint32_t)I2C_InitParaStruct->I2C_Protocol | CTLR1_ACKEN_SET);
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I2Cx->CTLR1 = temp;
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/* AR1 */
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I2Cx->AR1 = (I2C_InitParaStruct->I2C_AddressingMode | I2C_InitParaStruct->I2C_DeviceAddress);
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}
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/**
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* @brief Initial the sturct I2C_InitPara.
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* @param I2C_InitParaStruct: the sturct I2C_InitPara pointer.
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* @retval None.
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*/
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void I2C_ParaInit(I2C_InitPara *I2C_InitParaStruct)
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{
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I2C_InitParaStruct->I2C_Protocol = I2C_PROTOCOL_I2C;
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I2C_InitParaStruct->I2C_DutyCycle = I2C_DUTYCYCLE_2;
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I2C_InitParaStruct->I2C_BitRate = 10000;
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I2C_InitParaStruct->I2C_AddressingMode = I2C_ADDRESSING_MODE_7BIT;
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I2C_InitParaStruct->I2C_DeviceAddress = 0x08;
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}
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/**
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* @brief Enable or disable the I2Cx interface.
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* @param I2Cx: the I2C interface where x can be 1 or 2.
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* @param NewValue: new value of the I2Cx interface.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None.
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*/
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void I2C_Enable(I2C_TypeDef *I2Cx, TypeState NewValue)
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{
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if (NewValue != DISABLE) {
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/* Enable the I2Cx interface */
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I2Cx->CTLR1 |= CTLR1_I2CEN_SET;
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} else {
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/* Disable the I2Cx interface */
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I2Cx->CTLR1 &= CTLR1_I2CEN_RESET;
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}
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}
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/**
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* @brief Enable or disable the I2Cx DMA requests.
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* @param I2Cx: the I2C interface where x can be 1 or 2.
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* @param NewValue: new value of the I2C DMA transfer.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None.
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*/
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void I2C_DMA_Enable(I2C_TypeDef *I2Cx, TypeState NewValue)
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{
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if (NewValue != DISABLE) {
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/* Enable the I2Cx DMA requests */
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I2Cx->CTLR2 |= CTLR2_DMAON_SET;
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} else {
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/* Disable the I2Cx DMA requests */
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I2Cx->CTLR2 &= CTLR2_DMAON_RESET;
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}
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}
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/**
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* @brief Enable or disable the DMA last.
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* @param I2Cx: the I2C interface where x can be 1 or 2.
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* @param NewValue: new value of the I2C DMA last transfer.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None.
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*/
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void I2C_DMALastTransfer_Enable(I2C_TypeDef *I2Cx, TypeState NewValue)
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{
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if (NewValue != DISABLE) {
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/* Next DMA transfer is the last transfer */
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I2Cx->CTLR2 |= CTLR2_DMALST_SET;
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} else {
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/* Next DMA transfer is not the last transfer */
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I2Cx->CTLR2 &= CTLR2_DMALST_RESET;
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}
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}
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/**
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* @brief Enable or disable I2C_CTLR1_GENSTA control bit.
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* @param I2Cx: the I2C interface where x can be 1 or 2.
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* @param NewValue: new value of the I2C START condition generation.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None.
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*/
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void I2C_StartOnBus_Enable(I2C_TypeDef *I2Cx, TypeState NewValue)
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{
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if (NewValue != DISABLE) {
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/* Enable I2C_CTLR1_GENSTA control bit */
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I2Cx->CTLR1 |= CTLR1_GENSTA_SET;
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} else {
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/* Disable I2C_CTLR1_GENSTA control bit */
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I2Cx->CTLR1 &= CTLR1_GENSTA_RESET;
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}
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}
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/**
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* @brief Enable or disable I2C_CTLR1_GENSTP control bit.
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* @param I2Cx: the I2C interface where x can be 1 or 2.
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* @param NewValue: new value of the I2C STOP condition generation.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None.
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*/
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void I2C_StopOnBus_Enable(I2C_TypeDef *I2Cx, TypeState NewValue)
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{
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if (NewValue != DISABLE) {
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/* Enable I2C_CTLR1_GENSTP control bit */
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I2Cx->CTLR1 |= CTLR1_GENSTP_SET;
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} else {
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/* Disable I2C_CTLR1_GENSTP control bit */
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I2Cx->CTLR1 &= CTLR1_GENSTP_RESET;
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}
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}
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/**
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* @brief Enable or disable the I2C_CTLR1_ACKEN control bit.
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* @param I2Cx: the I2C interface where x can be 1 or 2.
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* @param NewValue: new value of the I2C Acknowledgement.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None.
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*/
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void I2C_Acknowledge_Enable(I2C_TypeDef *I2Cx, TypeState NewValue)
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{
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if (NewValue != DISABLE) {
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/* Enable I2C_CTLR1_ACKEN control bit */
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I2Cx->CTLR1 |= CTLR1_ACKEN_SET;
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} else {
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/* Disable I2C_CTLR1_ACKEN control bit */
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I2Cx->CTLR1 &= CTLR1_ACKEN_RESET;
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}
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}
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/**
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* @brief Set the I2Cx own address2.
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* @param I2Cx: the I2C interface where x can be 1 or 2.
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* @param Address: specifies the 7bit I2C own address2.
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* @retval None.
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*/
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void I2C_OwnAddress2(I2C_TypeDef *I2Cx, uint8_t Address)
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{
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uint16_t temp = 0;
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temp = I2Cx->AR2;
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temp &= AR2_ADDRESS2_RESET;
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temp |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);
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/* I2C_AR2_ADDRESS2 */
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I2Cx->AR2 = temp;
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}
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/**
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* @brief Enable or disable the I2C_AR2_DUADEN control bit.
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* @param I2Cx: the I2C interface where x can be 1 or 2.
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* @param NewValue: new value of the I2C dual addressing mode.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None.
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*/
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void I2C_DualAddress_Enable(I2C_TypeDef *I2Cx, TypeState NewValue)
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{
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if (NewValue != DISABLE) {
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/* Enable the I2C_AR2_DUADEN control bit */
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I2Cx->AR2 |= AR2_DUADEN_SET;
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} else {
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/* Disable the I2C_AR2_DUADEN control bit */
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I2Cx->AR2 &= AR2_DUADEN_RESET;
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}
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}
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/**
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* @brief Enable or disable I2C_CTLR1_GCEN control bit.
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* @param I2Cx: the I2C interface where x can be 1 or 2.
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* @param NewValue: new value of the I2C General call.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None.
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*/
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void I2C_GeneralCall_Enable(I2C_TypeDef *I2Cx, TypeState NewValue)
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{
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if (NewValue != DISABLE) {
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/* Enable I2C_CTLR1_GCEN control bit */
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I2Cx->CTLR1 |= CTLR1_GCEN_SET;
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} else {
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/* Disable I2C_CTLR1_GCEN control bit */
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I2Cx->CTLR1 &= CTLR1_GCEN_RESET;
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}
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}
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/**
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* @brief Enable or disable the specified I2C interrupt.
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* @param I2Cx: the I2C interface where x can be 1 or 2.
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* @param I2C_INT: the I2C interrupt sources.
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* This parameter can be any combination of the following values:
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* @arg I2C_INT_EIE: Error interrupt
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* @arg I2C_INT_EE: Event interrupt
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* @arg I2C_INT_BIE: Buffer interrupt
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* @param NewValue: new value of the specified I2C interrupts.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None.
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*/
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void I2C_INTConfig(I2C_TypeDef *I2Cx, uint16_t I2C_INT, TypeState NewValue)
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{
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if (NewValue != DISABLE) {
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/* Enable the I2C interrupt */
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I2Cx->CTLR2 |= I2C_INT;
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} else {
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/* Disable the I2C interrupt */
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I2Cx->CTLR2 &= (uint16_t)~I2C_INT;
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}
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}
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/**
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* @brief Send one byte to bus.
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* @param I2Cx: the I2C interface where x can be 1 or 2.
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* @param Data: Byte to be transmitted.
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* @retval None.
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*/
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void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data)
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{
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/* Write Data to DTR */
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I2Cx->DTR = Data;
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}
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/**
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* @brief Receive one byte from the bus.
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* @param I2Cx: the I2C interface where x can be 1 or 2.
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* @retval The received data.
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*/
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uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx)
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{
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/* Read the DTR register */
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return (uint8_t)I2Cx->DTR;
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}
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/**
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* @brief Addressing a device on the I2C bus.
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* @param I2Cx: the I2C interface where x can be 1 or 2.
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* @param Address: the slave device's address.
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* @param I2C_Direction: Transmitter or a Receiver.
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* This parameter can be one of the following values:
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* @arg I2C_DIRECTION_TRANSMITTER: Transmitter mode
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* @arg I2C_DIRECTION_RECEIVER: Receiver mode
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* @retval None.
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*/
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void I2C_AddressingDevice_7bit(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction)
|
|
{
|
|
if (I2C_Direction != I2C_DIRECTION_TRANSMITTER) {
|
|
/* Receiver mode */
|
|
Address |= AR1_ADDRESS0_SET;
|
|
} else {
|
|
/* Transmitter mode */
|
|
Address &= AR1_ADDRESS0_RESET;
|
|
}
|
|
I2Cx->DTR = Address;
|
|
}
|
|
|
|
/**
|
|
* @brief Read the I2Cx register.
|
|
* @param I2Cx: the I2C interface where x can be 1 or 2.
|
|
* @param I2C_Register: the I2Cx register.
|
|
* This parameter can be one of the following values:
|
|
* @arg I2C_REGISTER_CTLR1: CTLR1 register.
|
|
* @arg I2C_REGISTER_CTLR2: CTLR2 register.
|
|
* @arg I2C_REGISTER_AR1: AR1 register.
|
|
* @arg I2C_REGISTER_AR2: AR2 register.
|
|
* @arg I2C_REGISTER_DTR: DTR register.
|
|
* @arg I2C_REGISTER_STR1: STR1 register.
|
|
* @arg I2C_REGISTER_STR2: STR2 register.
|
|
* @arg I2C_REGISTER_CLKR: CLKR register.
|
|
* @arg I2C_REGISTER_RTR: RTR register.
|
|
* @retval The value of the read register.
|
|
*/
|
|
uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register)
|
|
{
|
|
__IO uint32_t temp = 0;
|
|
|
|
temp = (uint32_t) I2Cx;
|
|
temp += I2C_Register;
|
|
|
|
/* Return the selected register value */
|
|
return (*(__IO uint16_t *) temp);
|
|
}
|
|
|
|
/**
|
|
* @brief Enable or disable the I2C_CTLR1_SRESET control bit.
|
|
* @param I2Cx: the I2C interface where x can be 1 or 2.
|
|
* @param NewValue: new value of the I2C software reset.
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
* @retval None.
|
|
*/
|
|
void I2C_SoftwareReset_Enable(I2C_TypeDef *I2Cx, TypeState NewValue)
|
|
{
|
|
if (NewValue != DISABLE) {
|
|
/* Enable I2C_CTLR1_SRESET control bit */
|
|
I2Cx->CTLR1 |= CTLR1_SRESET_SET;
|
|
} else {
|
|
/* Disable I2C_CTLR1_SRESET control bit */
|
|
I2Cx->CTLR1 &= CTLR1_SRESET_RESET;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Enable or disable the I2C_CTLR1_POAP control bit.
|
|
* @param I2Cx: the I2C interface where x can be 1 or 2.
|
|
* @param I2C_NACKPosition: the position of NACK.
|
|
* This parameter can be one of the following values:
|
|
* @arg I2C_NACKPOSITION_NEXT: the next byte is the last received byte
|
|
* @arg I2C_NACKPOSITION_CURRENT: the current byte is the last received byte
|
|
* @retval None.
|
|
*/
|
|
void I2C_NACKPosition_Enable(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition)
|
|
{
|
|
if (I2C_NACKPosition == I2C_NACKPOSITION_NEXT) {
|
|
/* Next byte will be the last received byte */
|
|
I2Cx->CTLR1 |= I2C_NACKPOSITION_NEXT;
|
|
} else {
|
|
/* Current byte is the last received byte */
|
|
I2Cx->CTLR1 &= I2C_NACKPOSITION_CURRENT;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Enable or disable the I2C_CTLR1_SALT control bit.
|
|
* @param I2Cx: the I2C interface where x can be 1 or 2.
|
|
* @param NewValue: new value of the I2C software reset.
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
* @retval None
|
|
*/
|
|
void I2C_SMBusAlertSend_Enable(I2C_TypeDef *I2Cx, TypeState NewValue)
|
|
{
|
|
if (NewValue != DISABLE) {
|
|
/* Enable I2C_CTLR1_SALT control bit */
|
|
I2Cx->CTLR1 |= CTLR1_SALT_SET;
|
|
} else {
|
|
/* Disable I2C_CTLR1_SALT control bit */
|
|
I2Cx->CTLR1 &= CTLR1_SALT_RESET;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Enable or disable the I2C_CTLR1_PECTRANS control bit.
|
|
* @param I2Cx: the I2C interface where x can be 1 or 2.
|
|
* @param NewValue: new value of the I2C PEC transmission.
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
* @retval None
|
|
*/
|
|
void I2C_PECTransmit_Enable(I2C_TypeDef *I2Cx, TypeState NewValue)
|
|
{
|
|
if (NewValue != DISABLE) {
|
|
/* Enable I2C_CTLR1_PECTRANS control bit */
|
|
I2Cx->CTLR1 |= CTLR1_PECTRANS_SET;
|
|
} else {
|
|
/* Disable I2C_CTLR1_PECTRANS control bit */
|
|
I2Cx->CTLR1 &= CTLR1_PECTRANS_RESET;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Enable or disable the I2C_CTLR1_POAP control bit.
|
|
* @param I2Cx: the I2C interface where x can be 1 or 2.
|
|
* @param I2C_PECPosition: the position of PEC.
|
|
* This parameter can be one of the following values:
|
|
* @arg I2C_PECPOSITION_NEXT: the next byte is PEC
|
|
* @arg I2C_PECPOSITION_CURRENT: the current byte is PEC
|
|
* @retval None.
|
|
*/
|
|
void I2C_PECPosition_Enable(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition)
|
|
{
|
|
if (I2C_PECPosition == I2C_PECPOSITION_NEXT) {
|
|
/* The next byte is PEC */
|
|
I2Cx->CTLR1 |= I2C_PECPOSITION_NEXT;
|
|
} else {
|
|
/* The current byte is PEC */
|
|
I2Cx->CTLR1 &= I2C_PECPOSITION_CURRENT;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Enable or disable the I2C_CTLR1_PECEN control bit.
|
|
* @param I2Cx: the I2C interface where x can be 1 or 2.
|
|
* @param NewValue: new value of the I2Cx PEC value calculation.
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
* @retval None.
|
|
*/
|
|
void I2C_PEC_Enable(I2C_TypeDef *I2Cx, TypeState NewValue)
|
|
{
|
|
if (NewValue != DISABLE) {
|
|
/* Enable I2C_CTLR1_PECEN control bit */
|
|
I2Cx->CTLR1 |= CTLR1_PECEN_SET;
|
|
} else {
|
|
/* Disable I2C_CTLR1_PECEN control bit */
|
|
I2Cx->CTLR1 &= CTLR1_PECEN_RESET;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief The Packet Error Checking value.
|
|
* @param I2Cx: the I2C interface where x can be 1 or 2.
|
|
* @retval The PEC value.
|
|
*/
|
|
uint8_t I2C_GetPECValue(I2C_TypeDef *I2Cx)
|
|
{
|
|
/* I2C_STR2_ECV */
|
|
return ((I2Cx->STR2) >> 8);
|
|
}
|
|
|
|
/**
|
|
* @brief Enable or disable the I2C_CTLR1_ARPEN control bit.
|
|
* @param I2Cx: the I2C interface where x can be 1 or 2.
|
|
* @param NewValue: new value of the I2Cx ARP.
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
* @retval None.
|
|
*/
|
|
void I2C_ARP_Enable(I2C_TypeDef *I2Cx, TypeState NewValue)
|
|
{
|
|
if (NewValue != DISABLE) {
|
|
/* Enable I2C_CTLR1_ARPEN control bit */
|
|
I2Cx->CTLR1 |= CTLR1_ARPEN_SET;
|
|
} else {
|
|
/* Disable I2C_CTLR1_ARPEN control bit */
|
|
I2Cx->CTLR1 &= CTLR1_ARPEN_RESET;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Enable or disable the I2C_CTLR1_DISSTRC control bit.
|
|
* @param I2Cx: the I2C interface where x can be 1 or 2.
|
|
* @param NewValue: new value of the I2Cx Clock stretching.
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
* @retval None.
|
|
*/
|
|
void I2C_StretchClock_Enable(I2C_TypeDef *I2Cx, TypeState NewValue)
|
|
{
|
|
if (NewValue == DISABLE) {
|
|
/* Enable I2C_CTLR1_DISSTRC control bit */
|
|
I2Cx->CTLR1 |= CTLR1_DISSTRC_SET;
|
|
} else {
|
|
/* Enable I2C_CTLR1_DISSTRC control bit */
|
|
I2Cx->CTLR1 &= CTLR1_DISSTRC_RESET;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Enable or disable the I2C_CLKR_DTCY control bit.
|
|
* @param I2Cx: the I2C interface where x can be 1 or 2.
|
|
* @param I2C_DutyCycle: the duty cycle in fast mode.
|
|
* This parameter can be one of the following values:
|
|
* @arg I2C_DUTYCYCLE_2: I2C fast mode Tlow/Thigh = 2
|
|
* @arg I2C_DUTYCYCLE_16_9: I2C fast mode Tlow/Thigh = 16/9
|
|
* @retval None.
|
|
*/
|
|
void I2C_FastModeDutyCycle(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle)
|
|
{
|
|
if (I2C_DutyCycle != I2C_DUTYCYCLE_16_9) {
|
|
/* DutyCycle=2:1 */
|
|
I2Cx->CLKR &= I2C_DUTYCYCLE_2;
|
|
} else {
|
|
/* DutyCycle=16:9 */
|
|
I2Cx->CLKR |= I2C_DUTYCYCLE_16_9;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Detect I2Cx State Machine.
|
|
* @param I2Cx: the I2C interface where x can be 1 or 2.
|
|
* @param I2C_State: I2Cx State Machine.
|
|
* This parameter can be one of the following values:
|
|
* @arg I2C_PROGRAMMINGMODE_SLAVE_TRANSMITTER_ADDSEND
|
|
* @arg I2C_PROGRAMMINGMODE_SLAVE_RECEIVER_ADDSEND
|
|
* @arg I2C_PROGRAMMINGMODE_SLAVE_TRANSMITTER_SECONDADDRESS_SELECTED
|
|
* @arg I2C_PROGRAMMINGMODE_SLAVE_RECEIVER_SECONDADDRESS_SELECTED
|
|
* @arg I2C_PROGRAMMINGMODE_SLAVE_GENERALCALLADDRESS_SELECTED
|
|
* @arg I2C_PROGRAMMINGMODE_SLAVE_BYTE_RECEIVED
|
|
* @arg (I2C_PROGRAMMINGMODE_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUMODF)
|
|
* @arg (I2C_PROGRAMMINGMODE_SLAVE_BYTE_RECEIVED | I2C_FLAG_RXGC)
|
|
* @arg I2C_PROGRAMMINGMODE_SLAVE_BYTE_TRANSMITTED
|
|
* @arg (I2C_PROGRAMMINGMODE_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUMODF)
|
|
* @arg (I2C_PROGRAMMINGMODE_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_RXGC)
|
|
* @arg I2C_PROGRAMMINGMODE_SLAVE_ACK_FAILURE
|
|
* @arg I2C_PROGRAMMINGMODE_SLAVE_STOP_DETECTED
|
|
* @arg I2C_PROGRAMMINGMODE_MASTER_SBSEND
|
|
* @arg I2C_PROGRAMMINGMODE_MASTER_TRANSMITTER_ADDSEND
|
|
* @arg I2C_PROGRAMMINGMODE_MASTER_RECEIVER_ADDSEND
|
|
* @arg I2C_PROGRAMMINGMODE_MASTER_BYTE_RECEIVED
|
|
* @arg I2C_PROGRAMMINGMODE_MASTER_BYTE_TRANSMITTING
|
|
* @arg I2C_PROGRAMMINGMODE_MASTER_BYTE_TRANSMITTED
|
|
* @arg I2C_PROGRAMMINGMODE_MASTER_ADD10SEND
|
|
* @retval The detected result(SUCCESS or ERROR).
|
|
*/
|
|
TypeState I2C_StateDetect(I2C_TypeDef *I2Cx, uint32_t I2C_State)
|
|
{
|
|
uint32_t currentstate = 0;
|
|
uint32_t flag1 = 0, flag2 = 0;
|
|
TypeState state = ERROR;
|
|
|
|
/* Read the I2Cx status register */
|
|
flag1 = I2Cx->STR1;
|
|
flag2 = I2Cx->STR2;
|
|
flag2 = flag2 << 16;
|
|
|
|
/* Get the state value from I2C status register */
|
|
currentstate = (flag1 | flag2) & STR_FLAG_MASK;
|
|
|
|
if ((currentstate & I2C_State) == I2C_State) {
|
|
/* I2C_State is detected */
|
|
state = SUCCESS;
|
|
} else {
|
|
/* I2C_State is not detected */
|
|
state = ERROR;
|
|
}
|
|
return state;
|
|
}
|
|
|
|
/**
|
|
* @brief Get the I2Cx Current State.
|
|
* @param I2Cx: the I2C interface where x can be 1 or 2.
|
|
* @retval The current state.
|
|
*/
|
|
uint32_t I2C_GetCurrentState(I2C_TypeDef *I2Cx)
|
|
{
|
|
uint32_t currentstate = 0;
|
|
uint32_t flag1 = 0, flag2 = 0;
|
|
|
|
/* Read the I2Cx status register */
|
|
flag1 = I2Cx->STR1;
|
|
flag2 = I2Cx->STR2;
|
|
flag2 = flag2 << 16;
|
|
|
|
/* Get the last event value from I2C status register */
|
|
currentstate = (flag1 | flag2) & STR_FLAG_MASK;
|
|
|
|
return currentstate;
|
|
}
|
|
|
|
/**
|
|
* @brief Get the bit flag of STRx registers.
|
|
* @param I2Cx: the I2C interface where x can be 1 or 2.
|
|
* @param I2C_FLAG: the flag of STRx registers.
|
|
* This parameter can be one of the following values:
|
|
* @arg I2C_FLAG_DUMODF: Dual flag (Slave mode)
|
|
* @arg I2C_FLAG_HSTSMB: SMBus host header (Slave mode)
|
|
* @arg I2C_FLAG_DEFSMB: SMBus default header (Slave mode)
|
|
* @arg I2C_FLAG_RXGC: General call header flag (Slave mode)
|
|
* @arg I2C_FLAG_TRS: Transmitter or Receiver flag
|
|
* @arg I2C_FLAG_I2CBSY: Bus busy flag
|
|
* @arg I2C_FLAG_MASTER: Master or Slave flag
|
|
* @arg I2C_FLAG_SMBALTS: SMBus Alert flag
|
|
* @arg I2C_FLAG_SMBTO: Timeout or Tlow error flag
|
|
* @arg I2C_FLAG_PECE: PEC error in reception flag
|
|
* @arg I2C_FLAG_RXORE: Overrun or Underrun flag (Slave mode)
|
|
* @arg I2C_FLAG_AE: Acknowledge failure flag
|
|
* @arg I2C_FLAG_LOSTARB: Arbitration lost flag (Master mode)
|
|
* @arg I2C_FLAG_BE: Bus error flag
|
|
* @arg I2C_FLAG_TBE: Data register empty flag (Transmitter)
|
|
* @arg I2C_FLAG_RBNE: Data register not empty (Receiver) flag
|
|
* @arg I2C_FLAG_STPSEND: Stop detection flag (Slave mode)
|
|
* @arg I2C_FLAG_ADD10SEND: 10-bit header sent flag (Master mode)
|
|
* @arg I2C_FLAG_BTC: Byte transfer finished flag
|
|
* @arg I2C_FLAG_ADDSEND: Address sent flag (Master mode) or Address matched flag (Slave mode)
|
|
* @arg I2C_FLAG_SBSEND: Start bit flag (Master mode)
|
|
* @retval The new value of I2C_FLAG (SET or RESET).
|
|
*/
|
|
TypeState I2C_GetBitState(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
|
|
{
|
|
__IO uint32_t i2creg = 0, i2cxbase = 0;
|
|
|
|
/* Get the I2Cx peripheral base address */
|
|
i2cxbase = (uint32_t)I2Cx;
|
|
|
|
/* Read flag register index */
|
|
i2creg = I2C_FLAG >> 28;
|
|
|
|
/* Get bit[23:0] of the flag */
|
|
I2C_FLAG &= STR_FLAG_MASK;
|
|
|
|
if (i2creg != 0) {
|
|
/* Flag in I2Cx STR1 register */
|
|
i2cxbase += 0x14;
|
|
} else {
|
|
/* Flag in I2Cx STR2 Register */
|
|
I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);
|
|
/* Get the I2Cx STR2 register address */
|
|
i2cxbase += 0x18;
|
|
}
|
|
|
|
if (((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) {
|
|
/* I2C_FLAG is set */
|
|
return SET;
|
|
} else {
|
|
/* I2C_FLAG is reset */
|
|
return RESET;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Clear the bit flag of STRx registers.
|
|
* @param I2Cx: the I2C interface where x can be 1 or 2.
|
|
* @param I2C_FLAG: the flag of STRx registers.
|
|
* This parameter can be any combination of the following values:
|
|
* @arg I2C_FLAG_SMBALTS: SMBus Alert flag
|
|
* @arg I2C_FLAG_SMBTO: Timeout or Tlow error flag
|
|
* @arg I2C_FLAG_PECE: PEC error in reception flag
|
|
* @arg I2C_FLAG_RXORE: Overrun or Underrun flag (Slave mode)
|
|
* @arg I2C_FLAG_AE: Acknowledge failure flag
|
|
* @arg I2C_FLAG_LOSTARB: Arbitration lost flag (Master mode)
|
|
* @arg I2C_FLAG_BE: Bus error flag
|
|
* @retval None.
|
|
*/
|
|
void I2C_ClearBitState(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
|
|
{
|
|
uint32_t flagpos = 0;
|
|
|
|
/* Get the I2C flag position */
|
|
flagpos = I2C_FLAG & STR_FLAG_MASK;
|
|
/* Clear the selected I2C flag */
|
|
I2Cx->STR1 = (uint16_t)~flagpos;
|
|
}
|
|
|
|
/**
|
|
* @brief Get the interrupt bit flag.
|
|
* @param I2Cx: the I2C interface where x can be 1 or 2.
|
|
* @param I2C_INT: the interrupt bit flag.
|
|
* This parameter can be one of the following values:
|
|
* @arg I2C_INT_SMBALTS: SMBus Alert flag
|
|
* @arg I2C_INT_SMBTO: Timeout or Tlow error flag
|
|
* @arg I2C_INT_PECE: PEC error in reception flag
|
|
* @arg I2C_INT_RXORE: Overrun or Underrun flag (Slave mode)
|
|
* @arg I2C_INT_AE: Acknowledge failure flag
|
|
* @arg I2C_INT_LOSTARB: Arbitration lost flag (Master mode)
|
|
* @arg I2C_INT_BE: Bus error flag
|
|
* @arg I2C_INT_TBE: Data register empty flag (Transmitter)
|
|
* @arg I2C_INT_RBNE: Data register not empty (Receiver) flag
|
|
* @arg I2C_INT_STPSEND: Stop detection flag (Slave mode)
|
|
* @arg I2C_INT_ADD10SEND: 10-bit header sent flag (Master mode)
|
|
* @arg I2C_INT_BTC: Byte transfer finished flag
|
|
* @arg I2C_INT_ADDSEND: Address sent flag (Master mode) or Address matched flag (Slave mode)
|
|
* @arg I2C_INT_SBSEND: Start bit flag (Master mode)
|
|
* @retval The new value of I2C_INT (SET or RESET).
|
|
*/
|
|
TypeState I2C_GetIntBitState(I2C_TypeDef *I2Cx, uint32_t I2C_INT)
|
|
{
|
|
uint32_t enablestatus = 0;
|
|
|
|
/* Check if the interrupt source is enabled or not */
|
|
enablestatus = (uint32_t)(((I2C_INT & INTEN_MASK) >> 16) & (I2Cx->CTLR2)) ;
|
|
|
|
/* Get bit[23:0] of the flag */
|
|
I2C_INT &= STR_FLAG_MASK;
|
|
|
|
if (((I2Cx->STR1 & I2C_INT) != (uint32_t)RESET) && enablestatus) {
|
|
/* I2C_INT is set */
|
|
return SET;
|
|
} else {
|
|
/* I2C_INT is reset */
|
|
return RESET;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Clear the interrupt bit flag.
|
|
* @param I2Cx: the I2C interface where x can be 1 or 2.
|
|
* @param I2C_INT: the interrupt bit flag.
|
|
* This parameter can be any combination of the following values:
|
|
* @arg I2C_INT_SMBALTS: SMBus Alert interrupt
|
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* @arg I2C_INT_SMBTO: Timeout or Tlow error interrupt
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* @arg I2C_INT_PECE: PEC error in reception interrupt
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* @arg I2C_INT_RXORE: Overrun or Underrun interrupt (Slave mode)
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* @arg I2C_INT_AE: Acknowledge failure interrupt
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* @arg I2C_INT_LOSTARB: Arbitration lost interrupt (Master mode)
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* @arg I2C_INT_BE: Bus error interrupt
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* @retval None.
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*/
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void I2C_ClearIntBitState(I2C_TypeDef *I2Cx, uint32_t I2C_INT)
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{
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uint32_t flagpos = 0;
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/* Get the I2C flag position */
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flagpos = I2C_INT & STR_FLAG_MASK;
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/* Clear the selected I2C flag */
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I2Cx->STR1 = (uint16_t)~flagpos;
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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