217 lines
5.8 KiB
C
217 lines
5.8 KiB
C
/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-07-15 Emuzit first version
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*/
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#ifndef __CH56X_GPIO_H__
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#define __CH56X_GPIO_H__
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#include "soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Fixed linear mapping : 32 pins per port, for ports A,B,C,D...
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*/
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#define GET_PIN(port,pin) (GPIO_P##port##_PIN_START + pin)
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#ifdef SOC_SERIES_CH569
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#define GPIO_INT_PINS { \
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GET_PIN(A,2), GET_PIN(A,3), GET_PIN(A,4), GET_PIN(B,3), \
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GET_PIN(B,4), GET_PIN(B,11), GET_PIN(B,12), GET_PIN(B,15) \
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}
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#else
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#define GPIO_INT_PINS { \
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GET_PIN(A,3), GET_PIN(A,4), GET_PIN(A,6), GET_PIN(A,10), \
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GET_PIN(A,11), GET_PIN(A,12), GET_PIN(B,4), GET_PIN(B,10), \
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}
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#endif
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/*
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* R8_GPIO_INT_FLAG / R8_GPIO_INT_STATUS (CH567,CH568):
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* write 1 to specific bit to clear int flag
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*
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* R8_GPIO_INT_ENABLE:
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* To use EXTIx function, pin should be set as input.
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* For wakeup function, also set RB_SLP_GPIO_WAKE.
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*
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* R8_GPIO_INT_MODE:
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* R8_GPIO_INT_POLAR:
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*/
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#if defined(SOC_SERIES_CH569)
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union _gpio_interrupt
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{
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uint8_t reg;
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struct
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{
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uint8_t pa2 : 1;
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uint8_t pa3 : 1;
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uint8_t pa4 : 1;
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uint8_t pb3 : 1;
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uint8_t pb4 : 1;
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uint8_t pb11 : 1;
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uint8_t pb12 : 1;
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uint8_t pb15 : 1;
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};
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};
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#else
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union _gpio_interrupt
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{
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uint8_t reg;
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struct
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{
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uint8_t pa3 : 1;
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uint8_t pa4 : 1;
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uint8_t pa6 : 1;
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uint8_t pa10 : 1;
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uint8_t pa11 : 1;
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uint8_t pa12 : 1;
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uint8_t pb4 : 1;
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uint8_t pb10 : 1;
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};
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};
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#endif
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#define GPIO_IE_DISABLE 0
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#define GPIO_IE_ENABLE 1
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#define GPIO_IM_LEVEL 0
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#define GPIO_IM_EDGE 1
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#define GPIO_IP_LOW_FALLING 0
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#define GPIO_IP_HIGH_RISING 1
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/*
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* R8_PIN_ALTERNATE (CH569) : reset value is 0x01
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* R8_PORT_PIN (CH567/CH568) : reset value is 0x00
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*/
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union _gpio_pin_alternate
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{
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uint8_t reg;
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struct
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{
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uint8_t pin_mii : 1; // RW, ETH uses RMII/RGMII (CH565W/CH569W)
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uint8_t pin_tmr1 : 1; // RW, TMR1/PWM5/CAP1 remapping
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uint8_t pin_tmr2 : 1; // RW, TMR2/PWM6/CAP2 remapping
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uint8_t resv_3 : 1;
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uint8_t pin_uart0 : 1; // RW, RXD0/TXD0 remapping
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uint8_t pin_uart1 : 1; // RW, CH567 only
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uint8_t resv_6 : 2;
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};
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};
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#define RB_PIN_MII 0x01
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#define RB_PIN_TMR1 0x02
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#define RB_PIN_TMR2 0x04
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#define RB_PIN_UART0 0x10
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#define RB_PIN_UART1 0x20
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#ifdef SOC_SERIES_CH569
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#define GPIO_ALT_RMII 0
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#define GPIO_ALT_RGMII 1
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#define GPIO_ALT_TMR1_PB15 0
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#define GPIO_ALT_TMR1_PB0 1
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#define GPIO_ALT_TMR2_PA4 0
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#define GPIO_ALT_TMR2_PB3 1
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#define GPIO_ALT_UART0_PB5_6 0
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#define GPIO_ALT_UART0_PA5_6 1
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#else
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#define GPIO_ALT_TMR1_PA10 0
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#define GPIO_ALT_TMR1_PB2 1
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#define GPIO_ALT_TMR2_PA11 0
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#define GPIO_ALT_TMR2_PB11 1
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#define GPIO_ALT_UART0_PB4_7 0
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#define GPIO_ALT_UART0_PA15_14 1
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#define GPIO_ALT_UART1_PA8_9 0
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#define GPIO_ALT_UART1_PB8_9 1
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#endif
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struct gpio_px_regs
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{
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uint32_t DIR; // reset value for pins is 0, input pins
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uint32_t PIN; // RO
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uint32_t OUT; // reset value is 0
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uint32_t CLR; // reset value is 0
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uint32_t PU; // reset value is 0
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uint32_t PD; // reset value is 0
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uint32_t DRV; // reset value for pins is 0, 8mA
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uint32_t SMT; // reset value for pins is 1, enable schmitt trigger
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} __packed;
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CHECK_STRUCT_SIZE(struct gpio_px_regs, 0x20);
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#define GPIO_PX_DIR_IN 0
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#define GPIO_PX_DIR_OUT 1
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#define GPIO_PX_PU_DISABLE 0
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#define GPIO_PX_PU_ENABLE 1
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#define GPIO_PX_PD_DISABLE 0 // for DIR_IN
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#define GPIO_PX_PD_ENABLE 1 // for DIR_IN
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#define GPIO_PX_PD_PUSH_PULL 0 // for DIR_OUT
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#define GPIO_PX_PD_OPEN_DRAIN 1 // for DIR_OUT
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#define GPIO_PX_DRV_8mA 0
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#define GPIO_PX_DRV_16mA 1
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#define GPIO_PX_SMT_DISABLE 0
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#define GPIO_PX_SMT_SLOW 1 // for DIR_OUT
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#define GPIO_PX_SMT_ENABLE 1 // for DIR_IN
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/*
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* 0x12 R8_PIN_ALTERNATE: GPIO multi-use remapping register
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* 0x1c R8_GPIO_INT_FLAG: GPIO interrupt flag register
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* 0x1d R8_GPIO_INT_ENABLE: GPIO interrupt enable register
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* 0x1e R8_GPIO_INT_MODE: GPIO interrupt mode register
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* 0x1f R8_GPIO_INT_POLAR: GPIO interrupt polarity register
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*
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* 0x40 R32_PA_DIR: PA pin direction control
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* 0x44 R32_PA_PIN: PA pin input status
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* 0x48 R32_PA_OUT: PA pin output register
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* 0x4c R32_PA_CLR: PA pin output clear
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* 0x50 R32_PA_PU: PA pin pull-up resistor enable register
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* 0x54 R32_PA_PD: PA pin open drain output / input pull-down control
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* 0x58 R32_PA_DRV: PA pin output driving capability register
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* 0x5c R32_PA_SMT: PA pin slow output / schmitt trigger input control
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*
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* 0x60 R32_PB_DIR:
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* 0x64 R32_PB_PIN:
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* 0x68 R32_PB_OUT:
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* 0x6c R32_PB_CLR:
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* 0x70 R32_PB_PU:
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* 0x74 R32_PB_PD:
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* 0x78 R32_PB_DRV:
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* 0x7c R32_PB_SMT:
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*
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* CAVEAT: gcc (as of 8.2.0) tends to read 32-bit word for bit field test.
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* Be careful for those with side effect for read.
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*/
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struct gpio_registers
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{
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uint32_t resv_00[4];
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uint8_t resv_10[2];
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union _gpio_pin_alternate PIN_ALTERNATE;
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uint8_t resv_13;
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uint32_t resv_14[2];
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union _gpio_interrupt INT_FLAG;
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union _gpio_interrupt INT_ENABLE;
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union _gpio_interrupt INT_MODE;
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union _gpio_interrupt INT_POLAR;
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uint32_t resv_20[8];
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struct gpio_px_regs PA;
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struct gpio_px_regs PB;
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} __packed;
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CHECK_STRUCT_SIZE(struct gpio_registers, 0x80);
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#ifdef __cplusplus
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}
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#endif
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#endif
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