572 lines
14 KiB
C
572 lines
14 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-06-27 BalanceTWK first version
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*/
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#include "drv_gpio.h"
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#include <rthw.h>
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#ifdef RT_USING_PIN
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#define EXTI_(x) BIT(x)
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static const struct pin_index pins[] =
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{
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#if defined(GPIOA)
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__GD32VF_PIN(0 , A, 0 ),
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__GD32VF_PIN(1 , A, 1 ),
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__GD32VF_PIN(2 , A, 2 ),
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__GD32VF_PIN(3 , A, 3 ),
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__GD32VF_PIN(4 , A, 4 ),
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__GD32VF_PIN(5 , A, 5 ),
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__GD32VF_PIN(6 , A, 6 ),
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__GD32VF_PIN(7 , A, 7 ),
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__GD32VF_PIN(8 , A, 8 ),
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__GD32VF_PIN(9 , A, 9 ),
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__GD32VF_PIN(10, A, 10),
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__GD32VF_PIN(11, A, 11),
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__GD32VF_PIN(12, A, 12),
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__GD32VF_PIN(13, A, 13),
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__GD32VF_PIN(14, A, 14),
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__GD32VF_PIN(15, A, 15),
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#if defined(GPIOB)
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__GD32VF_PIN(16, B, 0),
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__GD32VF_PIN(17, B, 1),
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__GD32VF_PIN(18, B, 2),
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__GD32VF_PIN(19, B, 3),
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__GD32VF_PIN(20, B, 4),
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__GD32VF_PIN(21, B, 5),
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__GD32VF_PIN(22, B, 6),
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__GD32VF_PIN(23, B, 7),
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__GD32VF_PIN(24, B, 8),
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__GD32VF_PIN(25, B, 9),
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__GD32VF_PIN(26, B, 10),
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__GD32VF_PIN(27, B, 11),
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__GD32VF_PIN(28, B, 12),
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__GD32VF_PIN(29, B, 13),
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__GD32VF_PIN(30, B, 14),
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__GD32VF_PIN(31, B, 15),
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#if defined(GPIOC)
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__GD32VF_PIN(32, C, 0),
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__GD32VF_PIN(33, C, 1),
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__GD32VF_PIN(34, C, 2),
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__GD32VF_PIN(35, C, 3),
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__GD32VF_PIN(36, C, 4),
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__GD32VF_PIN(37, C, 5),
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__GD32VF_PIN(38, C, 6),
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__GD32VF_PIN(39, C, 7),
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__GD32VF_PIN(40, C, 8),
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__GD32VF_PIN(41, C, 9),
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__GD32VF_PIN(42, C, 10),
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__GD32VF_PIN(43, C, 11),
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__GD32VF_PIN(44, C, 12),
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__GD32VF_PIN(45, C, 13),
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__GD32VF_PIN(46, C, 14),
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__GD32VF_PIN(47, C, 15),
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#if defined(GPIOD)
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__GD32VF_PIN(48, D, 0),
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__GD32VF_PIN(49, D, 1),
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__GD32VF_PIN(50, D, 2),
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__GD32VF_PIN(51, D, 3),
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__GD32VF_PIN(52, D, 4),
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__GD32VF_PIN(53, D, 5),
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__GD32VF_PIN(54, D, 6),
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__GD32VF_PIN(55, D, 7),
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__GD32VF_PIN(56, D, 8),
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__GD32VF_PIN(57, D, 9),
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__GD32VF_PIN(58, D, 10),
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__GD32VF_PIN(59, D, 11),
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__GD32VF_PIN(60, D, 12),
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__GD32VF_PIN(61, D, 13),
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__GD32VF_PIN(62, D, 14),
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__GD32VF_PIN(63, D, 15),
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#if defined(GPIOE)
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__GD32VF_PIN(64, E, 0),
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__GD32VF_PIN(65, E, 1),
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__GD32VF_PIN(66, E, 2),
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__GD32VF_PIN(67, E, 3),
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__GD32VF_PIN(68, E, 4),
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__GD32VF_PIN(69, E, 5),
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__GD32VF_PIN(70, E, 6),
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__GD32VF_PIN(71, E, 7),
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__GD32VF_PIN(72, E, 8),
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__GD32VF_PIN(73, E, 9),
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__GD32VF_PIN(74, E, 10),
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__GD32VF_PIN(75, E, 11),
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__GD32VF_PIN(76, E, 12),
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__GD32VF_PIN(77, E, 13),
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__GD32VF_PIN(78, E, 14),
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__GD32VF_PIN(79, E, 15),
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#endif /* defined(GPIOE) */
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#endif /* defined(GPIOD) */
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#endif /* defined(GPIOC) */
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#endif /* defined(GPIOB) */
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#endif /* defined(GPIOA) */
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};
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static const struct pin_irq_map pin_irq_map[] =
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{
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{GPIO_PIN_0, EXTI0_IRQn},
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{GPIO_PIN_1, EXTI1_IRQn},
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{GPIO_PIN_2, EXTI2_IRQn},
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{GPIO_PIN_3, EXTI3_IRQn},
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{GPIO_PIN_4, EXTI4_IRQn},
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{GPIO_PIN_5, EXTI5_9_IRQn},
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{GPIO_PIN_6, EXTI5_9_IRQn},
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{GPIO_PIN_7, EXTI5_9_IRQn},
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{GPIO_PIN_8, EXTI5_9_IRQn},
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{GPIO_PIN_9, EXTI5_9_IRQn},
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{GPIO_PIN_10, EXTI10_15_IRQn},
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{GPIO_PIN_11, EXTI10_15_IRQn},
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{GPIO_PIN_12, EXTI10_15_IRQn},
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{GPIO_PIN_13, EXTI10_15_IRQn},
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{GPIO_PIN_14, EXTI10_15_IRQn},
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{GPIO_PIN_15, EXTI10_15_IRQn},
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};
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static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
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{
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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};
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static uint32_t pin_irq_enable_mask=0;
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#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
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static const struct pin_index *get_pin(uint8_t pin)
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{
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const struct pin_index *index;
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if (pin < ITEM_NUM(pins))
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{
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index = &pins[pin];
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if (index->index == -1)
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index = RT_NULL;
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}
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else
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{
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index = RT_NULL;
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}
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return index;
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};
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static void gd32vf_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
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{
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const struct pin_index *index;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return;
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}
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gpio_bit_write(index->gpio_periph, index->pin, (bit_status)value);
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}
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static int gd32vf_pin_read(rt_device_t dev, rt_base_t pin)
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{
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int value;
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const struct pin_index *index;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return PIN_LOW;
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}
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value = gpio_input_bit_get(index->gpio_periph, index->pin);
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return value;
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}
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static void gd32vf_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
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{
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const struct pin_index *index;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return;
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}
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/* Configure GPIO_InitStructure */
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if (mode == PIN_MODE_OUTPUT)
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{
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/* output setting */
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gpio_init(index->gpio_periph, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, index->pin);
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gpio_bit_reset(index->gpio_periph, index->pin);
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}
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else if (mode == PIN_MODE_INPUT)
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{
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/* input setting: not pull. */
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gpio_init(index->gpio_periph, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, index->pin);
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gpio_bit_reset(index->gpio_periph, index->pin);
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}
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else if (mode == PIN_MODE_INPUT_PULLUP)
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{
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/* input setting: pull up. */
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gpio_init(index->gpio_periph, GPIO_MODE_IPU, GPIO_OSPEED_50MHZ, index->pin);
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gpio_bit_reset(index->gpio_periph, index->pin);
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}
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else if (mode == PIN_MODE_INPUT_PULLDOWN)
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{
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/* input setting: pull down. */
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gpio_init(index->gpio_periph, GPIO_MODE_IPD, GPIO_OSPEED_50MHZ, index->pin);
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gpio_bit_reset(index->gpio_periph, index->pin);
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}
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else if (mode == PIN_MODE_OUTPUT_OD)
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{
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/* output setting: od. */
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gpio_init(index->gpio_periph, GPIO_MODE_OUT_OD, GPIO_OSPEED_50MHZ, index->pin);
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gpio_bit_reset(index->gpio_periph, index->pin);
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}
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}
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rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
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{
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int i;
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for (i = 0; i < 32; i++)
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{
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if ((0x01 << i) == bit)
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{
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return i;
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}
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}
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return -1;
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}
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rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
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{
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rt_int32_t mapindex = bit2bitno(pinbit);
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if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map))
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{
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return RT_NULL;
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}
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return &pin_irq_map[mapindex];
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};
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static rt_err_t gd32vf_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
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rt_uint32_t mode, void (*hdr)(void *args), void *args)
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{
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const struct pin_index *index;
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rt_base_t level;
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rt_int32_t irqindex = -1;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return RT_ENOSYS;
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}
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irqindex = bit2bitno(index->pin);
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if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
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{
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return RT_ENOSYS;
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}
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[irqindex].pin == pin &&
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pin_irq_hdr_tab[irqindex].hdr == hdr &&
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pin_irq_hdr_tab[irqindex].mode == mode &&
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pin_irq_hdr_tab[irqindex].args == args)
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{
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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if (pin_irq_hdr_tab[irqindex].pin != -1)
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{
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rt_hw_interrupt_enable(level);
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return RT_EBUSY;
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}
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pin_irq_hdr_tab[irqindex].pin = pin;
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pin_irq_hdr_tab[irqindex].hdr = hdr;
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pin_irq_hdr_tab[irqindex].mode = mode;
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pin_irq_hdr_tab[irqindex].args = args;
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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static rt_err_t gd32vf_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
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{
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const struct pin_index *index;
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rt_base_t level;
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rt_int32_t irqindex = -1;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return RT_ENOSYS;
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}
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irqindex = bit2bitno(index->pin);
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if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
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{
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return RT_ENOSYS;
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}
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[irqindex].pin == -1)
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{
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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pin_irq_hdr_tab[irqindex].pin = -1;
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pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
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pin_irq_hdr_tab[irqindex].mode = 0;
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pin_irq_hdr_tab[irqindex].args = RT_NULL;
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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static rt_err_t gd32vf_pin_irq_enable(struct rt_device *device, rt_base_t pin,
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rt_uint32_t enabled)
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{
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const struct pin_index *index;
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const struct pin_irq_map *irqmap;
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rt_base_t level;
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rt_int32_t irqindex = -1;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return RT_ENOSYS;
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}
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/* configure pin as input */
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gpio_init(index->gpio_periph, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, index->pin);
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if (enabled == PIN_IRQ_ENABLE)
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{
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irqindex = bit2bitno(index->pin);
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if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
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{
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return RT_ENOSYS;
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}
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[irqindex].pin == -1)
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{
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rt_hw_interrupt_enable(level);
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return RT_ENOSYS;
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}
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irqmap = &pin_irq_map[irqindex];
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/* enable and set EXTI interrupt to the lowest priority */
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eclic_irq_enable(irqmap->irqno, 1, 1);
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gpio_exti_source_select(GPIO_PORT_SOURCE_GPIOA, GPIO_PIN_SOURCE_0);
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/* Configure GPIO_InitStructure */
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switch (pin_irq_hdr_tab[irqindex].mode)
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{
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case PIN_IRQ_MODE_RISING:
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exti_init(EXTI_(irqindex), EXTI_INTERRUPT, EXTI_TRIG_RISING);
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break;
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case PIN_IRQ_MODE_FALLING:
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exti_init(EXTI_(irqindex), EXTI_INTERRUPT, EXTI_TRIG_FALLING);
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break;
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case PIN_IRQ_MODE_RISING_FALLING:
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exti_init(EXTI_(irqindex), EXTI_INTERRUPT, EXTI_TRIG_BOTH);
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break;
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}
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pin_irq_enable_mask |= irqmap->pinbit;
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exti_interrupt_flag_clear(EXTI_(index->pin));
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rt_hw_interrupt_enable(level);
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}
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else if (enabled == PIN_IRQ_DISABLE)
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{
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irqmap = get_pin_irq_map(index->pin);
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if (irqmap == RT_NULL)
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{
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return RT_ENOSYS;
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}
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level = rt_hw_interrupt_disable();
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gpio_bit_reset(index->gpio_periph, index->pin);
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pin_irq_enable_mask &= ~irqmap->pinbit;
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eclic_irq_disable(irqmap->irqno);
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exti_interrupt_flag_clear(EXTI_(index->pin));
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rt_hw_interrupt_enable(level);
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}
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else
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{
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return -RT_ENOSYS;
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}
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return RT_EOK;
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}
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const static struct rt_pin_ops _gd32vf_pin_ops =
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{
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gd32vf_pin_mode,
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gd32vf_pin_write,
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gd32vf_pin_read,
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gd32vf_pin_attach_irq,
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gd32vf_pin_dettach_irq,
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gd32vf_pin_irq_enable,
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RT_NULL,
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};
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rt_inline void pin_irq_hdr(int irqno)
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{
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if (pin_irq_hdr_tab[irqno].hdr)
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{
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pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
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}
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}
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/* IRQHandler start */
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void EXTI0_IRQHandler(void)
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{
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if(EXTI_PD & (uint32_t) EXTI_0)
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{
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exti_interrupt_flag_clear(EXTI_0);
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pin_irq_hdr(bit2bitno(GPIO_PIN_0));
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}
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}
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void EXTI1_IRQHandler(void)
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{
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if(EXTI_PD & (uint32_t) EXTI_1)
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{
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exti_interrupt_flag_clear(EXTI_1);
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pin_irq_hdr(bit2bitno(GPIO_PIN_1));
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}
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}
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void EXTI2_IRQHandler(void)
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{
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if(EXTI_PD & (uint32_t) EXTI_2)
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{
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exti_interrupt_flag_clear(EXTI_2);
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pin_irq_hdr(bit2bitno(GPIO_PIN_2));
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}
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}
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void EXTI3_IRQHandler(void)
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{
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if(EXTI_PD & (uint32_t) EXTI_3)
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{
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exti_interrupt_flag_clear(EXTI_3);
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pin_irq_hdr(bit2bitno(GPIO_PIN_3));
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}
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}
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void EXTI4_IRQHandler(void)
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{
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if(EXTI_PD & (uint32_t) EXTI_4)
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{
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exti_interrupt_flag_clear(EXTI_4);
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pin_irq_hdr(bit2bitno(GPIO_PIN_4));
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}
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}
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void EXTI5_9_IRQHandler(void)
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{
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if(EXTI_PD & (uint32_t) EXTI_5)
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{
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exti_interrupt_flag_clear(EXTI_5);
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pin_irq_hdr(bit2bitno(GPIO_PIN_5));
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}
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if(EXTI_PD & (uint32_t) EXTI_6)
|
|
{
|
|
exti_interrupt_flag_clear(EXTI_6);
|
|
pin_irq_hdr(bit2bitno(GPIO_PIN_6));
|
|
}
|
|
|
|
if(EXTI_PD & (uint32_t) EXTI_7)
|
|
{
|
|
exti_interrupt_flag_clear(EXTI_7);
|
|
pin_irq_hdr(bit2bitno(GPIO_PIN_7));
|
|
}
|
|
|
|
if(EXTI_PD & (uint32_t) EXTI_8)
|
|
{
|
|
exti_interrupt_flag_clear(EXTI_8);
|
|
pin_irq_hdr(bit2bitno(GPIO_PIN_8));
|
|
}
|
|
|
|
if(EXTI_PD & (uint32_t) EXTI_9)
|
|
{
|
|
exti_interrupt_flag_clear(EXTI_9);
|
|
pin_irq_hdr(bit2bitno(GPIO_PIN_9));
|
|
}
|
|
}
|
|
void EXTI10_15_IRQHandler(void)
|
|
{
|
|
if(EXTI_PD & (uint32_t) EXTI_10)
|
|
{
|
|
exti_interrupt_flag_clear(EXTI_10);
|
|
pin_irq_hdr(bit2bitno(GPIO_PIN_10));
|
|
}
|
|
|
|
if(EXTI_PD & (uint32_t) EXTI_11)
|
|
{
|
|
exti_interrupt_flag_clear(EXTI_11);
|
|
pin_irq_hdr(bit2bitno(GPIO_PIN_11));
|
|
}
|
|
|
|
if(EXTI_PD & (uint32_t) EXTI_12)
|
|
{
|
|
exti_interrupt_flag_clear(EXTI_12);
|
|
pin_irq_hdr(bit2bitno(GPIO_PIN_12));
|
|
}
|
|
|
|
if(EXTI_PD & (uint32_t) EXTI_13)
|
|
{
|
|
exti_interrupt_flag_clear(EXTI_13);
|
|
pin_irq_hdr(bit2bitno(GPIO_PIN_13));
|
|
}
|
|
|
|
if(EXTI_PD & (uint32_t) EXTI_14)
|
|
{
|
|
exti_interrupt_flag_clear(EXTI_14);
|
|
pin_irq_hdr(bit2bitno(GPIO_PIN_14));
|
|
}
|
|
|
|
if(EXTI_PD & (uint32_t) EXTI_15)
|
|
{
|
|
exti_interrupt_flag_clear(EXTI_15);
|
|
pin_irq_hdr(bit2bitno(GPIO_PIN_15));
|
|
}
|
|
}
|
|
/* IRQHandler end */
|
|
|
|
int rt_hw_pin_init(void)
|
|
{
|
|
/* enable the global interrupt */
|
|
eclic_global_interrupt_enable();
|
|
eclic_priority_group_set(ECLIC_PRIGROUP_LEVEL3_PRIO1);
|
|
|
|
rcu_periph_clock_enable(RCU_GPIOA);
|
|
rcu_periph_clock_enable(RCU_GPIOB);
|
|
rcu_periph_clock_enable(RCU_GPIOC);
|
|
rcu_periph_clock_enable(RCU_GPIOD);
|
|
rcu_periph_clock_enable(RCU_GPIOE);
|
|
|
|
rcu_periph_clock_enable(RCU_AF);
|
|
return rt_device_pin_register("pin", &_gd32vf_pin_ops, RT_NULL);
|
|
}
|
|
INIT_BOARD_EXPORT(rt_hw_pin_init);
|
|
|
|
#endif /* RT_USING_PIN */
|