162 lines
7.1 KiB
C
162 lines
7.1 KiB
C
/*
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* Copyright : (C) 2022 Phytium Information Technology, Inc.
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* All Rights Reserved.
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it
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* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
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* either version 1.0 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the Phytium Public License for more details.
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*
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*
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* FilePath: fqspi_flash.h
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* Date: 2022-02-10 14:53:42
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* LastEditTime: 2022-07-12 16:20:55
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* Description:
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* This file is for S25FS256, GD25Q256, GD25Q64 norflash program, includes reading and writing registers and data,
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* Users can refer to this file to adapt chips from other manufacturers.
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*
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* Modify History:
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* Ver Who Date Changes
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* ----- ------ -------- --------------------------------------
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* 1.0 wangxiaodong 2021/11/12 first release
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* 1.1 wangxiaodong 2022/3/29 improve functions
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* 1.2 wangxiaodong 2022/7/5 adapt to e2000
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* 1.3 wangxiaodong 2022/9/9 improve functions
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* 1.4 zhangyan 2022/12/7 improve functions
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*/
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#ifndef FQSPI_FLASH_H
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#define FQSPI_FLASH_H
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#include "fkernel.h"
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#include "ftypes.h"
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#include "ferror_code.h"
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#include "fqspi.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/* qspi flash support manufacturer JEDEC ID */
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#define FQSPI_FLASH_MF_ID_CYPRESS 0x01
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#define FQSPI_FLASH_MF_ID_GIGADEVICE 0xC8
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#define FQSPI_FLASH_MF_ID_BOYA 0x68
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/* qspi flash supported information table */
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#define FQSPI_FLASH_INFO_TABLE \
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{ \
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{"S25FS256S", FQSPI_FLASH_MF_ID_CYPRESS, 0x02, 0x19, FQSPI_FLASH_CAP_32MB}, \
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{"GD25Q32C", FQSPI_FLASH_MF_ID_GIGADEVICE, 0x40, 0x16, FQSPI_FLASH_CAP_4MB}, \
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{"GD25Q32E", FQSPI_FLASH_MF_ID_GIGADEVICE, 0x60, 0x16, FQSPI_FLASH_CAP_4MB}, \
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{"GD25Q64B", FQSPI_FLASH_MF_ID_GIGADEVICE, 0x40, 0x17, FQSPI_FLASH_CAP_8MB}, \
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{"GD25LQ128E", FQSPI_FLASH_MF_ID_GIGADEVICE, 0x40, 0x18, FQSPI_FLASH_CAP_16MB}, \
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{"GD25LQ128E", FQSPI_FLASH_MF_ID_GIGADEVICE, 0x60, 0x18, FQSPI_FLASH_CAP_16MB}, \
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{"GD25QL256D", FQSPI_FLASH_MF_ID_GIGADEVICE, 0x60, 0x19, FQSPI_FLASH_CAP_32MB}, \
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{"BY25Q64BS", FQSPI_FLASH_MF_ID_BOYA, 0x40, 0x17, FQSPI_FLASH_CAP_8MB}, \
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{"BY25Q128BS", FQSPI_FLASH_MF_ID_BOYA, 0x40, 0x18, FQSPI_FLASH_CAP_16MB}, \
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{"BY25Q32BS", FQSPI_FLASH_MF_ID_BOYA, 0x40, 0x16, FQSPI_FLASH_CAP_4MB} \
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}
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#define FQSPI_FLASH_CMD_WRR 0x01 /* Write status register */
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#define FQSPI_FLASH_CMD_PP 0x02 /* Page program */
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#define FQSPI_FLASH_CMD_READ 0x03 /* Normal read data bytes */
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#define FQSPI_FLASH_CMD_WRDI 0x04 /* Write disable */
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#define FQSPI_FLASH_CMD_RDSR1 0x05 /* Read status register */
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#define FQSPI_FLASH_CMD_WREN 0x06 /* Write enable */
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#define FQSPI_FLASH_CMD_RDSR2 0x07 /* Read status register */
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#define FQSPI_FLASH_CMD_FAST_READ 0x0B /* Fast read data bytes */
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#define FQSPI_FLASH_CMD_4FAST_READ 0x0C /* Fast read data bytes */
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#define FQSPI_FLASH_CMD_DUAL_READ 0xBB /* Dual read data bytes */
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#define FQSPI_FLASH_CMD_4PP 0x12 /* Page program */
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#define FQSPI_FLASH_CMD_4READ 0x13 /* Normal read data bytes */
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#define FQSPI_FLASH_CMD_P4E 0x20 /* Erase 4kb sector */
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#define FQSPI_FLASH_CMD_4P4E 0x21 /* Erase 4kb sector */
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#define FQSPI_FLASH_CMD_QPP 0x32 /* Quad Page program */
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#define FQSPI_FLASH_CMD_4QPP 0x34 /* Quad Page program */
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#define FQSPI_FLASH_CMD_RDCR 0x35 /* Read config register */
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#define FQSPI_FLASH_CMD_BE 0x60 /* Bulk erase */
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#define FQSPI_FLASH_CMD_RDAR 0x65 /* Read Any Register */
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#define FQSPI_FLASH_CMD_DOR 0x3B /* Dual read data bytes*/
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#define FQSPI_FLASH_CMD_QOR 0x6B /* Quad read data bytes */
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#define FQSPI_FLASH_CMD_QWFR 0xE7 /* Quad word fast read data bytes */
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#define FQSPI_FLASH_CMD_4QOR 0x6C /* Quad read data bytes */
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#define FQSPI_FLASH_CMD_WRAR 0x71 /* Write Any Register */
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#define FQSPI_FLASH_CMD_RDID 0x9F /* Read JEDEC ID */
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#define FQSPI_FLASH_CMD_4BAM 0xB7 /* Enter 4 Bytes Mode */
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#define FQSPI_FLASH_CMD_4BE 0xC7 /* Bulk erase */
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#define FQSPI_FLASH_CMD_SE 0xD8 /* Sector erase */
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#define FQSPI_FLASH_CMD_4SE 0xDC /* Sector erase */
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#define FQSPI_FLASH_CMD_4BEX 0xE9 /* Exit 4 Bytes Mode */
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#define FQSPI_FLASH_CMD_QIOR 0xEB /* Quad read data bytes */
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#define FQSPI_FLASH_CMD_4QIOR 0xEC /* Quad read data bytes */
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#define FQSPI_FLASH_CMD_SFDP 0x5A /* Read JEDEC Serial Manu ID */
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#define FQSPI_CMD_ENABLE_RESET 0x66 /* Software Reset Enable */
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#define FQSPI_CMD_RESET 0x99 /* Software Reset */
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#define FQSPI_FLASH_CMD_RDSR3 0x15 /* Read status register 3 */
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/* boya flash */
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#define FQSPI_FLASH_CMD_WRITE_SR2 0x31 /* Write status register 2 */
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#define FQSPI_FLASH_CMD_WRITE_SR3 0x11 /* Write status register 3 */
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#define FQSPI_BUSY_TIMEOUT_US 1000000
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#define FQSPI_NOR_FLASH_STATE_BUSY BIT(0)
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#define FQSPI_FLASH_WP_ENABLE 0x7c /* Write status register 2 */
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#define FQSPI_FLASH_WP_DISABLE 0x00 /* Write status register 2 */
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/* Read some flash information */
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FError FQspiFlashSpecialInstruction(FQspiCtrl *pctrl, u8 cmd, u8 *buf, size_t len);
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/* read flash sfdp-Serial Flash Discoverable Parameter */
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FError FQspiFlashReadSfdp(FQspiCtrl *pctrl, u32 offset, u8 *buf, size_t len);
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/* read flash register */
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FError FQspiFlashReadReg(FQspiCtrl *pctrl, u32 offset, u8 *buf, size_t len);
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/* write flash register */
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FError FQspiFlashWriteReg(FQspiCtrl *pctrl, u8 command, const u8 *buf, size_t len);
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/* read flash data config */
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FError FQspiFlashReadDataConfig(FQspiCtrl *pctrl, u8 command);
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/* read flash data */
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size_t FQspiFlashReadData(FQspiCtrl *pctrl, u32 chip_addr, u8 *buf, size_t len);
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/* write flash data */
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FError FQspiFlashWriteData(FQspiCtrl *pctrl, u8 command, u32 chip_addr, const u8 *buf, size_t len);
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/* flash erase */
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FError FQspiFlashErase(FQspiCtrl *pctrl, u8 command, u32 offset);
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/* flash write enable */
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FError FQspiFlashEnableWrite(FQspiCtrl *pctrl);
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/* flash write disable */
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FError FQspiFlashDisableWrite(FQspiCtrl *pctrl);
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/* wait flash command execution complete */
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FError FQspiFlashWaitForCmd(FQspiCtrl *pctrl);
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/* read flash data use register port */
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FError FQspiFlashPortReadData(FQspiCtrl *pctrl, u8 cmd, u32 chip_addr, u8 *buf, size_t len);
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/* write flash data use register port */
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FError FQspiFlashPortWriteData(FQspiCtrl *pctrl, u8 cmd, u32 chip_addr, u8 *buf, size_t len);
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/* detect flash information */
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FError FQspiFlashDetect(FQspiCtrl *pctrl);
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/* qspi write protect set */
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FError FQspiFlashWProtectSet(FQspiCtrl *pctrl, boolean wprotect, u8 channel);
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#ifdef __cplusplus
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}
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#endif
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#endif
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