ecf2d82159
* Synchronize the code of the rt mart branch to the master branch.
* TTY device
* Add lwP code from rt-smart
* Add vnode in DFS, but DFS will be re-write for rt-smart
* There are three libcpu for rt-smart:
* arm/cortex-a, arm/aarch64
* riscv64
Co-authored-by: Rbb666 <zhangbingru@rt-thread.com>
Co-authored-by: zhkag <zhkag@foxmail.com>
84 lines
1.5 KiB
C
84 lines
1.5 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-10-03 Bernard The first version
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*/
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#ifndef CPUPORT_H__
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#define CPUPORT_H__
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#include <rtconfig.h>
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/* bytes of register width */
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#ifdef ARCH_CPU_64BIT
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#define STORE sd
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#define LOAD ld
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#define REGBYTES 8
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#else
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// error here, not portable
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#error "Not supported XLEN"
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#endif
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/* 33 general register */
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#define CTX_GENERAL_REG_NR 33
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#ifdef ENABLE_FPU
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/* 32 fpu register */
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#define CTX_FPU_REG_NR 32
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#else
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#define CTX_FPU_REG_NR 0
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#endif
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#ifdef ENABLE_VECTOR
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#if defined(ARCH_VECTOR_VLEN_128)
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#define CTX_VECTOR_REGS 64
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#elif defined(ARCH_VECTOR_VLEN_256)
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#define CTX_VECTOR_REGS 128
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#endif
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#define CTX_VECTOR_REG_NR (CTX_VECTOR_REGS + 4)
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#else
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#define CTX_VECTOR_REG_NR 0
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#endif
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/* all context registers */
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#define CTX_REG_NR (CTX_GENERAL_REG_NR + CTX_FPU_REG_NR + CTX_VECTOR_REG_NR)
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#ifdef RT_USING_SMP
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typedef union {
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unsigned long slock;
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struct __arch_tickets {
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unsigned short owner;
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unsigned short next;
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} tickets;
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} rt_hw_spinlock_t;
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#endif
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#ifndef __ASSEMBLY__
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rt_inline void rt_hw_dsb()
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{
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asm volatile("fence":::"memory");
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}
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rt_inline void rt_hw_dmb()
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{
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asm volatile("fence":::"memory");
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}
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rt_inline void rt_hw_isb()
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{
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asm volatile(".long 0x0000100F":::"memory");
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}
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#endif
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#endif
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#ifdef RISCV_U_MODE
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#define RISCV_USER_ENTRY 0xFFFFFFE000000000ULL
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#endif
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