ecf2d82159
* Synchronize the code of the rt mart branch to the master branch.
* TTY device
* Add lwP code from rt-smart
* Add vnode in DFS, but DFS will be re-write for rt-smart
* There are three libcpu for rt-smart:
* arm/cortex-a, arm/aarch64
* riscv64
Co-authored-by: Rbb666 <zhangbingru@rt-thread.com>
Co-authored-by: zhkag <zhkag@foxmail.com>
89 lines
2.4 KiB
C
89 lines
2.4 KiB
C
/*
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*********************************************************************************************************
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* AR100 SYSTEM
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* AR100 Software System Develop Kits
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* interrupt module
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*
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* (c) Copyright 2012-2016, Sunny China
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* All Rights Reserved
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*
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* File : intc_i.h
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* By : Sunny
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* Version : v1.0
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* Date : 2012-5-3
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* Descript: interrupt controller internal header.
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* Update : date auther ver notes
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* 2012-5-3 13:27:40 Sunny 1.0 Create this file.
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*********************************************************************************************************
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*/
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#ifndef __INTC_I_H__
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#define __INTC_I_H__
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#include <hal_interrupt.h>
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#include <sunxi_hal_common.h>
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/*interrput controller registers Offset*/
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typedef struct intc_regs {
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/*offset 0x00 */
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volatile u32 vector;
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volatile u32 base_addr;
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volatile u32 reserved0;
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volatile u32 control;
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/*offset 0x10 */
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volatile u32 pending;
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volatile u32 pending1;
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volatile u32 pending2;
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volatile u32 reserved1[9];
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/*offset 0x40 */
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volatile u32 enable;
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volatile u32 enable1;
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volatile u32 enable2;
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volatile u32 reserved2[1];
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/*offset 0x50 */
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volatile u32 mask;
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volatile u32 mask1;
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volatile u32 mask2;
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volatile u32 reserved3[5];
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/*offset 0x70 */
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volatile u32 fast_forcing;
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volatile u32 reserved4[3];
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/*offset 0x80 */
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volatile u32 priority0;
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volatile u32 priority1;
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volatile u32 reserved5[14];
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/*offset 0xc0 */
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volatile u32 group_config0;
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volatile u32 group_config1;
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volatile u32 group_config2;
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volatile u32 group_config3;
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} intc_regs_t;
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struct int_isr_node {
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__pISR_hdle_t pisr; /*ISR process handler */
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void *parg; /*argument for isr process */
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};
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/*local functions*/
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s32 intc_init(void);
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s32 intc_exit(void);
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s32 intc_set_fiq_triggermode(u32 triggermode);
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s32 intc_enable_interrupt(u32 intno);
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s32 intc_disable_interrupt(u32 intno);
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u32 intc_get_current_interrupt(void);
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s32 intc_set_mask(u32 intno, u32 mask);
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s32 intc_set_group_config(u32 grp_irq_num, u32 mask);
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s32 isr_default(int dummy, void *arg);
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/*pointer of register list*/
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extern struct intc_regs *pintc_regs;
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#endif /*__INTC_I_H__*/
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