f51bce3fed
We currently only support building with CCS and SCons is not using.
bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file.
You may need to regenerate the source file as you like, providing that:
1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The
channel 5 in enabled and connected to IRQ.
2, RTI driver is enabled and compare3 source is selected to counter1
and the compare3 will generate tick in the period of 10ms. This
value is coresponding with RT_TICK_PER_SECOND in rtconfig.h.
In CCS, you need to create a new CCS project and create link folders
pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember
to add the include path to the Build Properties.
99 lines
3.2 KiB
NASM
99 lines
3.2 KiB
NASM
;-------------------------------------------------------------------------------
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; dabort.asm
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;
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; (c) Texas Instruments 2009-2013, All rights reserved.
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;
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.text
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.arm
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;-------------------------------------------------------------------------------
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; Run Memory Test
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.ref custom_dabort
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.def _dabort
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.asmfunc
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_dabort
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stmfd r13!, {r0 - r12, lr}; push registers and link register on to stack
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ldr r12, esmsr3 ; ESM Group3 status register
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ldr r0, [r12]
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tst r0, #0x8 ; check if bit 3 is set, this indicates uncorrectable ECC error on B0TCM
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bne ramErrorFound
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tst r0, #0x20 ; check if bit 5 is set, this indicates uncorrectable ECC error on B1TCM
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bne ramErrorFound
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noRAMerror
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tst r0, #0x80 ; check if bit 7 is set, this indicates uncorrectable ECC error on ATCM
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bne flashErrorFound
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bl custom_dabort ; custom data abort handler required
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; If this custom handler is written in assembly, all registers used in the routine
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; and the link register must be saved on to the stack upon entry, and restored before
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; return from the routine.
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ldmfd r13!, {r0 - r12, lr}; pop registers and link register from stack
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subs pc, lr, #8 ; restore state of CPU when abort occurred, and branch back to instruction that was aborted
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ramErrorFound
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ldr r1, ramctrl ; RAM control register for B0TCM TCRAMW
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ldr r2, [r1]
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tst r2, #0x100 ; check if bit 8 is set in RAMCTRL, this indicates ECC memory write is enabled
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beq ramErrorReal
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mov r2, #0x20
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str r2, [r1, #0x10] ; clear RAM error status register
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ldr r1, ram2ctrl
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str r2, [r1, #0x10] ; clear RAM error status register
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mov r2, #0x28
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str r2, [r12] ; clear ESM group3 flags for uncorrectable RAM ECC errors
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mov r2, #5
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str r2, [r12, #0x18] ; The nERROR pin will become inactive once the LTC counter expires
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ldmfd r13!, {r0 - r12, lr}
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subs pc, lr, #4 ; branch to instruction after the one that caused the abort
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; this is the case because the data abort was caused intentionally
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; and we do not want to cause the same data abort again.
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ramErrorReal
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b ramErrorReal ; branch here forever as continuing operation is not recommended
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flashErrorFound
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ldr r1, flashbase
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ldr r2, [r1, #0x6C] ; read FDIAGCTRL register
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mov r2, r2, lsr #16
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tst r2, #5 ; check if bits 19:16 are 5, this indicates diagnostic mode is enabled
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beq flashErrorReal
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mov r2, #1
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mov r2, r2, lsl #8
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str r2, [r1, #0x1C] ; clear FEDACSTATUS error flag
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mov r2, #0x80
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str r2, [r12] ; clear ESM group3 flag for uncorrectable flash ECC error
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mov r2, #5
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str r2, [r12, #0x18] ; The nERROR pin will become inactive once the LTC counter expires
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ldmfd r13!, {r0 - r12, lr}
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subs pc, lr, #4 ; branch to instruction after the one that caused the abort
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; this is the case because the data abort was caused intentionally
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; and we do not want to cause the same data abort again.
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flashErrorReal
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b flashErrorReal ; branch here forever as continuing operation is not recommended
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esmsr3 .word 0xFFFFF520
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ramctrl .word 0xFFFFF800
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ram2ctrl .word 0xFFFFF900
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ram1errstat .word 0xFFFFF810
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ram2errstat .word 0xFFFFF910
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flashbase .word 0xFFF87000
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.endasmfunc
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