326 lines
8.1 KiB
C
326 lines
8.1 KiB
C
/*
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* Copyright (c) 2021 hpm
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Change Logs:
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* Date Author Notes
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* 2022-01-11 hpmicro First version
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* 2022-07-28 hpmicro Fixed compiling warnings
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*/
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#include <rtthread.h>
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#ifdef BSP_USING_GPIO
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#include <rthw.h>
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#include <rtdevice.h>
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#include "board.h"
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#include "drv_gpio.h"
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#include "hpm_gpio_drv.h"
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#include "hpm_gpiom_drv.h"
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#include "hpm_clock_drv.h"
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typedef struct
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{
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uint32_t gpio_idx;
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uint32_t irq_num;
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} gpio_irq_map_t;
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static const gpio_irq_map_t hpm_gpio_irq_map[] = {
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#ifdef IRQn_GPIO0_A
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{ GPIO_IE_GPIOA, IRQn_GPIO0_A },
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#endif
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#ifdef IRQn_GPIO0_B
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{ GPIO_IE_GPIOB, IRQn_GPIO0_B },
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#endif
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#ifdef IRQn_GPIO0_C
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{ GPIO_IE_GPIOC, IRQn_GPIO0_C },
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#endif
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#ifdef GPIO_IE_GPIOD
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{ GPIO_IE_GPIOD, IRQn_GPIO0_D },
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#endif
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#ifdef IRQn_GPIO0_E
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{ GPIO_IE_GPIOE, IRQn_GPIO0_E },
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#endif
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#ifdef IRQn_GPIO0_F
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{ GPIO_IE_GPIOF, IRQn_GPIO0_F },
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#endif
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#ifdef IRQn_GPIO0_X
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{ GPIO_IE_GPIOX, IRQn_GPIO0_X },
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#endif
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#ifdef IRQn_GPIO0_Y
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{ GPIO_IE_GPIOY, IRQn_GPIO0_Y },
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#endif
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#ifdef IRQn_GPIO0_Z
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{ GPIO_IE_GPIOZ, IRQn_GPIO0_Z },
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#endif
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};
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static struct rt_pin_irq_hdr hpm_gpio_pin_hdr_tbl[IOC_PAD_PZ11];
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static int hpm_get_gpi_irq_num(uint32_t gpio_idx)
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{
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int irq_num = -1;
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for (uint32_t i = 0; i < sizeof(hpm_gpio_irq_map) / sizeof(hpm_gpio_irq_map[0]); i++)
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{
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if (hpm_gpio_irq_map[i].gpio_idx == gpio_idx)
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{
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irq_num = hpm_gpio_irq_map[i].irq_num;
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break;
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}
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}
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return irq_num;
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}
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static void hpm_gpio_isr(uint32_t gpio_index, GPIO_Type *base)
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{
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uint32_t pin_idx = 0;
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for(pin_idx = 0; pin_idx < 32; pin_idx++)
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{
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if (gpio_check_pin_interrupt_flag(base, gpio_index, pin_idx))
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{
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uint32_t pin = gpio_index * 32U + pin_idx;
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gpio_clear_pin_interrupt_flag(base, gpio_index, pin_idx);
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if (hpm_gpio_pin_hdr_tbl[pin].hdr != RT_NULL)
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{
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hpm_gpio_pin_hdr_tbl[pin].hdr(hpm_gpio_pin_hdr_tbl[pin].args);
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}
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}
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}
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}
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#ifdef GPIO_IF_GPIOA
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void gpioa_isr(void)
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{
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hpm_gpio_isr(GPIO_IF_GPIOA, HPM_GPIO0);
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}
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SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_A, gpioa_isr)
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#endif
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#ifdef GPIO_IF_GPIOB
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void gpiob_isr(void)
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{
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hpm_gpio_isr(GPIO_IF_GPIOB, HPM_GPIO0);
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}
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SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_B, gpiob_isr)
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#endif
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#ifdef GPIO_IF_GPIOC
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void gpioc_isr(void)
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{
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hpm_gpio_isr(GPIO_IF_GPIOC, HPM_GPIO0);
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}
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SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_C, gpioc_isr)
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#endif
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#ifdef GPIO_IF_GPIOD
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void gpiod_isr(void)
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{
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hpm_gpio_isr(GPIO_IF_GPIOD, HPM_GPIO0);
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}
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SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_D, gpiod_isr)
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#endif
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#ifdef GPIO_IF_GPIOE
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void gpioe_isr(void)
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{
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hpm_gpio_isr(GPIO_IF_GPIOE, HPM_GPIO0);
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}
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SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_E, gpioe_isr)
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#endif
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#ifdef GPIO_IF_GPIOF
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void gpiof_isr(void)
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{
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hpm_gpio_isr(GPIO_IF_GPIOF, HPM_GPIO0);
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}
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SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_F, gpiof_isr)
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#endif
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#ifdef GPIO_IF_GPIOX
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void gpiox_isr(void)
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{
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hpm_gpio_isr(GPIO_IF_GPIOX, HPM_GPIO0);
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}
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SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_X, gpiox_isr)
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#endif
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#ifdef GPIO_IF_GPIOY
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void gpioy_isr(void)
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{
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hpm_gpio_isr(GPIO_IF_GPIOY, HPM_GPIO0);
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}
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SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_Y, gpioy_isr)
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#endif
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#ifdef GPIO_IF_GPIOZ
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void gpioz_isr(void)
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{
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hpm_gpio_isr(GPIO_IF_GPIOZ, HPM_GPIO0);
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}
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SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_Z, gpioz_isr)
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#endif
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static void hpm_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
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{
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/* TODO: Check the validity of the pin value */
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uint32_t gpio_idx = pin >> 5;
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uint32_t pin_idx = pin & 0x1FU;
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gpiom_set_pin_controller(HPM_GPIOM, gpio_idx, pin_idx, gpiom_soc_gpio0);
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HPM_IOC->PAD[pin].FUNC_CTL = 0;
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switch (gpio_idx)
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{
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case GPIO_DI_GPIOY :
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HPM_PIOC->PAD[pin].FUNC_CTL = 3;
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break;
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case GPIO_DI_GPIOZ :
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HPM_BIOC->PAD[pin].FUNC_CTL = 3;
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break;
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default :
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break;
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}
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switch (mode)
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{
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case PIN_MODE_OUTPUT:
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gpio_set_pin_output(HPM_GPIO0, gpio_idx, pin_idx);
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HPM_IOC->PAD[pin].PAD_CTL &= ~(IOC_PAD_PAD_CTL_PS_MASK | IOC_PAD_PAD_CTL_PE_MASK | IOC_PAD_PAD_CTL_OD_MASK);
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break;
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case PIN_MODE_INPUT:
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gpio_set_pin_input(HPM_GPIO0, gpio_idx, pin_idx);
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HPM_IOC->PAD[pin].PAD_CTL &= ~(IOC_PAD_PAD_CTL_PS_MASK | IOC_PAD_PAD_CTL_PE_MASK);
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break;
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case PIN_MODE_INPUT_PULLDOWN:
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gpio_set_pin_input(HPM_GPIO0, gpio_idx, pin_idx);
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HPM_IOC->PAD[pin].PAD_CTL = (HPM_IOC->PAD[pin].PAD_CTL & ~IOC_PAD_PAD_CTL_PS_MASK) | IOC_PAD_PAD_CTL_PE_SET(1);
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break;
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case PIN_MODE_INPUT_PULLUP:
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gpio_set_pin_input(HPM_GPIO0, gpio_idx, pin_idx);
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HPM_IOC->PAD[pin].PAD_CTL |= IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
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break;
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case PIN_MODE_OUTPUT_OD:
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gpio_set_pin_output(HPM_GPIO0, gpio_idx, pin_idx);
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HPM_IOC->PAD[pin].PAD_CTL = (HPM_IOC->PAD[pin].PAD_CTL & ~(IOC_PAD_PAD_CTL_PS_MASK | IOC_PAD_PAD_CTL_PE_MASK)) | IOC_PAD_PAD_CTL_OD_SET(1);
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break;
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default:
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/* Invalid mode */
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break;
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}
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}
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static int hpm_pin_read(rt_device_t dev, rt_base_t pin)
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{
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/* TODO: Check the validity of the pin value */
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uint32_t gpio_idx = pin >> 5;
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uint32_t pin_idx = pin & 0x1FU;
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return (int) gpio_read_pin(HPM_GPIO0, gpio_idx, pin_idx);
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}
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static void hpm_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
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{
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/* TODO: Check the validity of the pin value */
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uint32_t gpio_idx = pin >> 5;
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uint32_t pin_idx = pin & 0x1FU;
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gpio_write_pin(HPM_GPIO0, gpio_idx, pin_idx, value);
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}
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static rt_err_t hpm_pin_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode,
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void (*hdr)(void *args), void *args)
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{
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rt_base_t level;
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level = rt_hw_interrupt_disable();
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hpm_gpio_pin_hdr_tbl[pin].pin = pin;
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hpm_gpio_pin_hdr_tbl[pin].hdr = hdr;
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hpm_gpio_pin_hdr_tbl[pin].mode = mode;
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hpm_gpio_pin_hdr_tbl[pin].args = args;
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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static rt_err_t hpm_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
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{
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rt_base_t level;
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level = rt_hw_interrupt_disable();
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hpm_gpio_pin_hdr_tbl[pin].pin = -1;
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hpm_gpio_pin_hdr_tbl[pin].hdr = RT_NULL;
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hpm_gpio_pin_hdr_tbl[pin].mode = 0;
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hpm_gpio_pin_hdr_tbl[pin].args = RT_NULL;
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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static rt_err_t hpm_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
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{
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/* TODO: Check the validity of the pin value */
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uint32_t gpio_idx = pin >> 5;
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uint32_t pin_idx = pin & 0x1FU;
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gpio_interrupt_trigger_t trigger;
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if (enabled == PIN_IRQ_ENABLE)
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{
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switch(hpm_gpio_pin_hdr_tbl[pin].mode)
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{
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case PIN_IRQ_MODE_RISING:
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trigger = gpio_interrupt_trigger_edge_rising;
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break;
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case PIN_IRQ_MODE_FALLING:
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trigger = gpio_interrupt_trigger_edge_falling;
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break;
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case PIN_IRQ_MODE_HIGH_LEVEL:
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trigger = gpio_interrupt_trigger_level_high;
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break;
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case PIN_IRQ_MODE_LOW_LEVEL:
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trigger = gpio_interrupt_trigger_level_low;
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break;
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default:
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trigger = gpio_interrupt_trigger_edge_rising;
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break;
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}
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gpio_config_pin_interrupt(HPM_GPIO0, gpio_idx, pin_idx, trigger);
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uint32_t irq_num = hpm_get_gpi_irq_num(gpio_idx);
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gpio_enable_pin_interrupt(HPM_GPIO0, gpio_idx, pin_idx);
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intc_m_enable_irq_with_priority(irq_num, 1);
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}
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else if (enabled == PIN_IRQ_DISABLE)
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{
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gpio_disable_pin_interrupt(HPM_GPIO0, gpio_idx, pin_idx);
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}
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else
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{
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return -RT_EINVAL;
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}
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return RT_EOK;
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}
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const static struct rt_pin_ops hpm_pin_ops = {
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.pin_mode = hpm_pin_mode,
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.pin_write = hpm_pin_write,
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.pin_read = hpm_pin_read,
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.pin_attach_irq = hpm_pin_attach_irq,
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.pin_detach_irq = hpm_pin_detach_irq,
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.pin_irq_enable = hpm_pin_irq_enable};
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int rt_hw_pin_init(void)
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{
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int ret = RT_EOK;
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ret = rt_device_pin_register("pin", &hpm_pin_ops, RT_NULL);
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return ret;
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}
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INIT_BOARD_EXPORT(rt_hw_pin_init);
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#endif /* BSP_USING_GPIO */
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