1387 lines
41 KiB
C
1387 lines
41 KiB
C
/**
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* \file
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*
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* \brief SAM I2S - Inter-IC Sound Controller
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*
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* Copyright (c) 2014-2016 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
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*/
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#ifndef I2S_H_INCLUDED
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#define I2S_H_INCLUDED
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/**
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* \defgroup asfdoc_sam0_i2s_group SAM Inter-IC Sound Controller (I2S) Driver
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*
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* This driver for Atmel® | SMART ARM®-based microcontrollers provides
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* an interface for the configuration and management of the device's Inter-IC
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* Sound Controller functionality.
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*
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* The following driver API modes are covered by this manual:
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* - Polled APIs
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* \if I2S_CALLBACK_MODE
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* - Callback APIs
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* \endif
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*
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* The following peripheral is used by this module:
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* - I<SUP>2</SUP>S (Inter-IC Sound Controller)
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*
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* The following devices can use this module:
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* - Atmel | SMART SAM D21
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* - Atmel | SMART SAM DA1
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*
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* The outline of this documentation is as follows:
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* - \ref asfdoc_sam0_i2s_prerequisites
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* - \ref asfdoc_sam0_i2s_module_overview
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* - \ref asfdoc_sam0_i2s_special_considerations
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* - \ref asfdoc_sam0_i2s_extra_info
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* - \ref asfdoc_sam0_i2s_examples
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* - \ref asfdoc_sam0_i2s_api_overview
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*
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* \section asfdoc_sam0_i2s_prerequisites Prerequisites
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*
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* There are no prerequisites for this module.
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*
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* \section asfdoc_sam0_i2s_module_overview Module Overview
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*
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* The I<SUP>2</SUP>S provides bidirectional, synchronous, digital audio link with
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* external audio devices through these signal pins:
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* - Serial Data (SDm)
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* - Frame Sync (FSn)
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* - Serial Clock (SCKn)
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* - Master Clock (MCKn)
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*
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* The I<SUP>2</SUP>S consists of two Clock Units and two Serializers, which can be
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* separately configured and enabled, to provide varies functionalities as follow:
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* - Communicate to Audio CODECs as Master or Slave, or provides clock and
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* frame sync signals as Controller
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* - Communicate to DAC or ADC through dedicated I<SUP>2</SUP>S serial interface
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* - Communicate to multi-slot or multiple stereo DACs or ADCs, via
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* Time Division Multiplexed (TDM) format
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* - Reading mono or stereo MEMS microphones, using the Pulse Density
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* Modulation (PDM) interface
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*
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* The I<SUP>2</SUP>S supports compact stereo data word, where left channel data bits are
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* in lower half and right channel data bits are in upper half. It reduces the
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* number of data words for stereo audio data and the DMA bandwidth.
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*
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* In master mode, the frame is configured by number of slots and slot size, and
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* allows range covering 16fs to 1024fs MCK, to provide oversampling clock to an
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* external audio CODEC or digital signal processor (DSP).
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*
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* A block diagram of the I<SUP>2</SUP>S can be seen in
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* \ref asfdoc_sam0_i2s_module_block_diagram "the figure below".
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*
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* \anchor asfdoc_sam0_i2s_module_block_diagram
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* \image html i2s_blocks.svg "I2S Block Diagram"
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*
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* This driver for I<SUP>2</SUP>S module provides an interface to:
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* - Initialize and control I<SUP>2</SUP>S module
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* - Configure and control the I<SUP>2</SUP>S Clock Unit and Serializer
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* - Transmit/receive data through I<SUP>2</SUP>S Serializer
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*
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* \subsection asfdoc_sam0_i2s_module_overview_clocks Clocks
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*
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* To use I<SUP>2</SUP>S module, the I<SUP>2</SUP>S bus interface clock (clk_i2s)
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* must be enabled via Power Manager.
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*
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* For each I<SUP>2</SUP>S Clock Unit, a generic clock (gclk_i2s_n) is connnected.
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* When I<SUP>2</SUP>S works in master mode the generic clock is used. It should
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* be prepared before clock unit is used. In master mode the input generic clock
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* will be used as MCK for SCKn and FSn generation, in addition, the MCK could be
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* devided and output to I<SUP>2</SUP>S MCKn pin, as oversampling clock to
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* external audio device.
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*
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* The I<SUP>2</SUP>S Serializer uses clock and control signal from Clock Unit to handle
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* transfer. Select different clock unit with different configurations allows
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* the I<SUP>2</SUP>S to work as master or slave, to work on non-related clocks.
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*
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* When using the driver with ASF, enabling the register interface is normally
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* done by the \c init function.
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* The Generic Clock Controller (GCLK) source for the asynchronous domain is
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* normally configured and set through the _configuration
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* struct_ / _init_ function.
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* If GCLK source != 0 is used, this source has to be configured and enabled
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* through invoking the system_gclk driver function when needed, or modifying
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* conf_clock.h to enable it at the beginning.
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*
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* \subsection asfdoc_sam0_i2s_module_overview_frame Audio Frame Generation
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*
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* Audio sample data for all channels are sent in frames, one frame can consist
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* 1 - 8 slots where each slot can be configured to a size 8-bit, 16-bit, 24-bit,
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* or 32-bit. The audio frame synch clock is generated by the I<SUP>2</SUP>S
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* Clock unit in the master/controller mode. The frame rate (or frame sync
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* frequency) is calculated as follows:
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*
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* FS = SCK / number_of_slots / number_of_bits_in_slot
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*
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* The serial clock (SCK) source is either an external source (slave mode) or
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* generated by the I<SUP>2</SUP>S clock unit (controller or master mode) using
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* the MCK as source.
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*
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* SCK = MCK / sck_div
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* \note SCK generation division value is MCKDIV in register.
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*
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* MCK is either an external source or generated using the GCLK input from a
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* generic clock generator.
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*
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* \subsection asfdoc_sam0_i2s_module_overview_mode Master, Controller, and Slave Modes
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*
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* The I<SUP>2</SUP>S module has three modes: master, controller, and slave.
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*
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* \subsubsection asfdoc_sam0_i2s_module_overview_mode_mst Master
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* In master mode the module will control the data flow on the I<SUP>2</SUP>S bus and can
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* be responsible for clock generation. The Serializers are enabled and will
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* transmit/receive data. On a bus with only master and slave the SCK, and FS
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* clock signal will be outputted on the SCK and FS pin on the master module.
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* MCK can optionally be outputted on the MCK pin, if there is a controller
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* module on the bus the SCK, FS, and optionally the MCK clock is sourced from
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* the same pins. Serial data will be trancieved on the SD pin in both
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* scenarios.
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*
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* \subsubsection asfdoc_sam0_i2s_module_overview_mode_ctl Controller
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* In controller mode the module will generate the clock signals, but the
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* Serializers are disabled and no data will be transmitted/received by the
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* module in this mode. The clock signals is outputted on the SCK, FS and
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* optionally the MCK pin.
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*
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* \subsubsection asfdoc_sam0_i2s_module_overview_mode_slv Slave
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* In slave mode the module will use the SCK and FS clock source from the master
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* or the controller which is received on the SCK and FS pin. The MCK can
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* optionally be sourced externally on the MCK pin. The Serializers are enabled
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* and will tranceive data on the SD pin. All data flow is controlled by the
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* master.
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*
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* \subsubsection asfdoc_sam0_i2s_module_overview_mode_chg Switch Modes
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* The mode switching between master, controller, and slave modes are actually
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* done by modifying the source mode of I<SUP>2</SUP>S pins.
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* The source mode of I<SUP>2</SUP>S pins are selected by writing corresponding
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* bits in CLKCTRLn.
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* Since source mode switching changes the direction of pin, the mode must be
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* changed when the I<SUP>2</SUP>S Clock Unit is stopped.
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*
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* \subsection asfdoc_sam0_i2s_module_overview_data Data Stream Reception/Transmission
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*
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* The I<SUP>2</SUP>S module support several data stream formats:
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* - I<SUP>2</SUP>S format
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* - Time Division Multiplexed (TDM) format
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* - Pulse Density Modulation (PDM) format (reception only)
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*
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* Basically the I<SUP>2</SUP>S module can send several words within each frame,
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* it's more like TDM format. With adjust to the number of data words in a frame,
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* the FS width, the FS to data bits delay, etc., the module is able to handle
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* I<SUP>2</SUP>S compliant data stream.
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*
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* Also the Serializer can receive PDM format data stream, which allows the
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* I<SUP>2</SUP>S module receive 1 PDM data on each SCK edge.
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*
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* \subsubsection asfdoc_sam0_i2s_module_overview_data_i2s I2S Stream Reception/Transmission
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*
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* For 2-channel I<SUP>2</SUP>S compliant data stream format the I<SUP>2</SUP>S
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* module uses the FS line as word select (WS) signal and will send left channel
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* data word on low WS level and right channel data word on high WS level as
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* specified in the I<SUP>2</SUP>S standard. The supported word sizes are 8-,
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* 16-, 18-, 20-, 24-, and 32- bit.
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*
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* Thus for I<SUP>2</SUP>S stream, the following settings should be applied to the module:
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* - Data starting delay after FS transition : one SCK period
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* - FS width : half of frame
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* - Data bits adjust in word : left-adjusted
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* - Bit transmitting order : MSB first
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*
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* Following is an example for I<SUP>2</SUP>S application connections and waveforms. See
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* the figure below.
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*
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* \anchor asfdoc_sam0_i2s_module_i2s_example_diagram
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* \image html i2s_example.svg "I2S Example Diagram"
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*
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* \subsubsection asfdoc_sam0_i2s_module_overview_data_tdm TDM Stream Reception/Transmission
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* In TDM format, the module sends several data words in each frame. For this
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* data stream format most of the configurations could be adjusted:
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* - Main Frame related settings are as follow:
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* - Frame Sync (FS) options:
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* - The active edge of the FS (or if FS is inverted before use)
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* - The width of the FS
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* - The delay between FS to first data bit
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* - Data alignment in slot
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* - The number of slots and slot size can be adjusted, it has been mentioned
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* in \ref asfdoc_sam0_i2s_module_overview_frame
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* - The data word size is controlled by Serializer, it can be chosen among
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* 8, 16, 18, 20, 24, and 32 bits.
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*
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* The general TDM waveform generation is as follows:
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*
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* \anchor asfdoc_sam0_i2s_module_tdm_wave_diagram
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* \image html tdm_wave.svg "TDM Waveform Generation"
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*
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* Some other settings could also be found to set up clock, data formatting and
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* pin multiplexer (MUX).
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* Refer to \ref i2s_clock_unit_config "Clock Unit Configurations"
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* and \ref i2s_serializer_config "Serializer Configurations" for more
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* details.
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*
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* Following is examples for different application use cases.
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*
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* See \ref asfdoc_sam0_i2s_module_tdm_timeslot_example_diagram "here" for
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* the Time Slot Application connection and waveform example.
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*
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* \anchor asfdoc_sam0_i2s_module_tdm_timeslot_example_diagram
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* \image html tdm_timeslot_example.svg "Codec Example Diagram"
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*
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* See \ref asfdoc_sam0_i2s_module_tdm_codec_example_diagram "here" for the
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* Codec Application connection and waveform example.
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*
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* \anchor asfdoc_sam0_i2s_module_tdm_codec_example_diagram
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* \image html tdm_codec_example.svg "Time Slot Example Diagram"
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*
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* \subsubsection asfdoc_sam0_i2s_module_overview_data_pdm PDM Reception
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* The I<SUP>2</SUP>S Serializer integrates PDM reception feature, to use this feature,
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* simply select PDM2 mode in Serializer configuration. In PDM2 mode, it assumes
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* two microphones are input for stereo stream. The left microphone bits will
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* be stored in lower half and right microphone bits in upper half of the data
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* word, like in compact stereo format.
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*
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* See \ref asfdoc_sam0_i2s_module_pdm_example_diagram "following figure" for an
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* example of PDM Microphones Application with both left and right channel
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* microphone connected.
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*
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* \anchor asfdoc_sam0_i2s_module_pdm_example_diagram
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* \image html pdm_example.svg "Time PDM2 Example Diagram"
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*
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* \subsubsection asfdoc_sam0_i2s_module_overview_data_fmt MONO and Compact Data
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* The I<SUP>2</SUP>S Serializer can accept some pre-defined data format and generates
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* the data stream in specified way.
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*
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* When transmitting data, the Serializer can work in MONO mode: assum input
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* is single channel mono data on left channel and copy it to right channel
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* automatically.
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*
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* Also the I<SUP>2</SUP>S Serializer can support compact stereo data word. The data word
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* size of the Serializer can be set to \ref I2S_DATA_SIZE_16BIT_COMPACT
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* "16-bit compact" or \ref I2S_DATA_SIZE_8BIT_COMPACT "8-bit compact", with
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* these option I<SUP>2</SUP>S Serializer will compact left channel data and right channel
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* data together, the left channel data will take lower bytes and right channel
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* data take higher bytes.
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*
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* \subsection asfdoc_sam0_i2s_module_overview_loop Loop-back Mode
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* The I<SUP>2</SUP>S can be configured to loop back the Transmitter to Receiver. In this
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* mode Serializer's input will be connected to another Serializer's output
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* internally.
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*
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* \subsection asfdoc_sam0_i2s_module_overview_sleep Sleep Modes
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* The I<SUP>2</SUP>S will continue to operate in any sleep mode, where the selected source
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* clocks are running.
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*
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* \section asfdoc_sam0_i2s_special_considerations Special Considerations
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*
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* There is no special considerations for I<SUP>2</SUP>S module.
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*
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* \section asfdoc_sam0_i2s_extra_info Extra Information
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*
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* For extra information see \ref asfdoc_sam0_i2s_extra. This includes:
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* - \ref asfdoc_sam0_i2s_extra_acronyms
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* - \ref asfdoc_sam0_i2s_extra_dependencies
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* - \ref asfdoc_sam0_i2s_extra_errata
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* - \ref asfdoc_sam0_i2s_extra_history
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*
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* \section asfdoc_sam0_i2s_examples Examples
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*
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* For a list of examples related to this driver, see
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* \ref asfdoc_sam0_i2s_exqsg.
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*
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*
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* \section asfdoc_sam0_i2s_api_overview API Overview
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* @{
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*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <compiler.h>
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#include <system.h>
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#if I2S_CALLBACK_MODE == true
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# include <system_interrupt.h>
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#if !defined(__DOXYGEN__)
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extern struct i2s_module *_i2s_instances[I2S_INST_NUM];
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#endif
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/** Forward definition of the device instance */
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struct i2s_module;
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/** Type of the callback functions. */
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typedef void (*i2s_serializer_callback_t)
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(struct i2s_module *const module);
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/**
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* \brief I<SUP>2</SUP>S Serializer Callback enum
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*/
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enum i2s_serializer_callback {
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/** Callback for buffer read/write finished */
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I2S_SERIALIZER_CALLBACK_BUFFER_DONE,
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/** Callback for Serializer overrun/underrun */
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I2S_SERIALIZER_CALLBACK_OVER_UNDER_RUN,
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# if !defined(__DOXYGEN__)
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I2S_SERIALIZER_CALLBACK_N
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# endif
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};
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#endif /* #if I2S_CALLBACK_MODE == true */
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/**
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* \name Module Status Flags
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*
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* I<SUP>2</SUP>S status flags, returned by \ref i2s_get_status() and cleared by
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* \ref i2s_clear_status().
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*
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* @{
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*/
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/** Module Serializer x (0~1) Transmit Underrun. */
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#define I2S_STATUS_TRANSMIT_UNDERRUN(x) (1u << ((x)+0))
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/** Module Serializer x (0~1) is ready to accept new data to be transmitted. */
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#define I2S_STATUS_TRANSMIT_READY(x) (1u << ((x)+2))
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/** Module Serializer x (0~1) Receive Overrun. */
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#define I2S_STATUS_RECEIVE_OVERRUN(x) (1u << ((x)+4))
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/** Module Serializer x (0~1) has received a new data. */
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#define I2S_STATUS_RECEIVE_READY(x) (1u << ((x)+6))
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/** Module is busy on synchronization. */
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#define I2S_STATUS_SYNC_BUSY (1u << 8)
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/** @} */
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/**
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* Master Clock (MCK) source selection.
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*/
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enum i2s_master_clock_source {
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/** Master Clock (MCK) is from general clock */
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I2S_MASTER_CLOCK_SOURCE_GCLK,
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/** Master Clock (MCK) is from MCK input pin */
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I2S_MASTER_CLOCK_SOURCE_MCKPIN
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};
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/**
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* Serial Clock (SCK) source selection.
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*/
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enum i2s_serial_clock_source {
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/** Serial Clock (SCK) is divided from Master Clock */
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I2S_SERIAL_CLOCK_SOURCE_MCKDIV,
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/** Serial Clock (SCK) is input from SCK input pin */
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I2S_SERIAL_CLOCK_SOURCE_SCKPIN
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};
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/**
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* Data delay from Frame Sync (FS).
|
|
*/
|
|
enum i2s_data_delay {
|
|
/** Left Justified (no delay) */
|
|
I2S_DATA_DELAY_0,
|
|
/** I<SUP>2</SUP>S data delay (1-bit delay) */
|
|
I2S_DATA_DELAY_1,
|
|
/** Left Justified (no delay) */
|
|
I2S_DATA_DELAY_LEFT_JUSTIFIED = I2S_DATA_DELAY_0,
|
|
/** I<SUP>2</SUP>S data delay (1-bit delay) */
|
|
I2S_DATA_DELAY_I2S = I2S_DATA_DELAY_1
|
|
};
|
|
|
|
/**
|
|
* Frame Sync (FS) source.
|
|
*/
|
|
enum i2s_frame_sync_source {
|
|
/** Frame Sync (FS) is divided from I<SUP>2</SUP>S Serial Clock */
|
|
I2S_FRAME_SYNC_SOURCE_SCKDIV,
|
|
/** Frame Sync (FS) is input from FS input pin */
|
|
I2S_FRAME_SYNC_SOURCE_FSPIN
|
|
};
|
|
|
|
/**
|
|
* Frame Sync (FS) output pulse width.
|
|
*/
|
|
enum i2s_frame_sync_width {
|
|
/** Frame Sync (FS) Pulse is one slot width */
|
|
I2S_FRAME_SYNC_WIDTH_SLOT,
|
|
/** Frame Sync (FS) Pulse is half a frame width */
|
|
I2S_FRAME_SYNC_WIDTH_HALF_FRAME,
|
|
/** Frame Sync (FS) Pulse is one bit width */
|
|
I2S_FRAME_SYNC_WIDTH_BIT,
|
|
/** 1-bit wide Frame Sync (FS) per Data sample, only used when Data transfer
|
|
* is requested */
|
|
I2S_FRAME_SYNC_WIDTH_BURST
|
|
};
|
|
|
|
/**
|
|
* Time Slot Size in number of I<SUP>2</SUP>S serial clocks (bits).
|
|
*/
|
|
enum i2s_slot_size {
|
|
/** 8-bit slot */
|
|
I2S_SLOT_SIZE_8_BIT,
|
|
/** 16-bit slot */
|
|
I2S_SLOT_SIZE_16_BIT,
|
|
/** 24-bit slot */
|
|
I2S_SLOT_SIZE_24_BIT,
|
|
/** 32-bit slot */
|
|
I2S_SLOT_SIZE_32_BIT
|
|
};
|
|
|
|
/**
|
|
* DMA channels usage for I<SUP>2</SUP>S.
|
|
*/
|
|
enum i2s_dma_usage {
|
|
/** Single DMA channel for all I<SUP>2</SUP>S channels */
|
|
I2S_DMA_USE_SINGLE_CHANNEL_FOR_ALL,
|
|
/** One DMA channel per data channel */
|
|
I2S_DMA_USE_ONE_CHANNEL_PER_DATA_CHANNEL
|
|
};
|
|
|
|
/**
|
|
* I<SUP>2</SUP>S data format, to extend mono data to two channels.
|
|
*/
|
|
enum i2s_data_format {
|
|
/** Normal mode, keep data to its right channel */
|
|
I2S_DATA_FORMAT_STEREO,
|
|
/** Assume input is mono data for left channel, the data is duplicated to
|
|
* right channel */
|
|
I2S_DATA_FORMAT_MONO
|
|
};
|
|
|
|
/**
|
|
* I<SUP>2</SUP>S data bit order.
|
|
*/
|
|
enum i2s_bit_order {
|
|
/** Transfer Data Most Significant Bit first
|
|
* (Default for I<SUP>2</SUP>S protocol)
|
|
*/
|
|
I2S_BIT_ORDER_MSB_FIRST,
|
|
/** Transfer Data Least Significant Bit first */
|
|
I2S_BIT_ORDER_LSB_FIRST
|
|
};
|
|
|
|
/**
|
|
* I<SUP>2</SUP>S data bit padding.
|
|
*/
|
|
enum i2s_bit_padding {
|
|
/** Padding with 0 */
|
|
I2S_BIT_PADDING_0,
|
|
/** Padding with 1 */
|
|
I2S_BIT_PADDING_1,
|
|
/** Padding with MSBit */
|
|
I2S_BIT_PADDING_MSB,
|
|
/** Padding with LSBit */
|
|
I2S_BIT_PADDING_LSB,
|
|
};
|
|
|
|
/**
|
|
* I<SUP>2</SUP>S data word adjust.
|
|
*/
|
|
enum i2s_data_adjust {
|
|
/** Data is right adjusted in word */
|
|
I2S_DATA_ADJUST_RIGHT,
|
|
/** Data is left adjusted in word */
|
|
I2S_DATA_ADJUST_LEFT
|
|
};
|
|
|
|
/**
|
|
* I<SUP>2</SUP>S data word size.
|
|
*/
|
|
enum i2s_data_size {
|
|
/** 32-bit */
|
|
I2S_DATA_SIZE_32BIT,
|
|
/** 24-bit */
|
|
I2S_DATA_SIZE_24BIT,
|
|
/** 20-bit */
|
|
I2S_DATA_SIZE_20BIT,
|
|
/** 18-bit */
|
|
I2S_DATA_SIZE_18BIT,
|
|
/** 16-bit */
|
|
I2S_DATA_SIZE_16BIT,
|
|
/** 16-bit compact stereo */
|
|
I2S_DATA_SIZE_16BIT_COMPACT,
|
|
/** 8-bit */
|
|
I2S_DATA_SIZE_8BIT,
|
|
/** 8-bit compact stereo */
|
|
I2S_DATA_SIZE_8BIT_COMPACT
|
|
};
|
|
|
|
/**
|
|
* I<SUP>2</SUP>S data slot adjust.
|
|
*/
|
|
enum i2s_slot_adjust {
|
|
/** Data is right adjusted in slot */
|
|
I2S_SLOT_ADJUST_RIGHT,
|
|
/** Data is left adjusted in slot */
|
|
I2S_SLOT_ADJUST_LEFT
|
|
};
|
|
|
|
/**
|
|
* I<SUP>2</SUP>S data padding.
|
|
*/
|
|
enum i2s_data_padding {
|
|
/** Padding 0 in case of under-run */
|
|
I2S_DATA_PADDING_0,
|
|
/** Padding last data in case of under-run */
|
|
I2S_DATA_PADDING_SAME_AS_LAST,
|
|
/** Padding last data in case of under-run
|
|
* (abbr. \c I2S_DATA_PADDING_SAME_AS_LAST) */
|
|
I2S_DATA_PADDING_LAST = I2S_DATA_PADDING_SAME_AS_LAST,
|
|
/** Padding last data in case of under-run
|
|
* (abbr. \c I2S_DATA_PADDING_SAME_AS_LAST) */
|
|
I2S_DATA_PADDING_SAME = I2S_DATA_PADDING_SAME_AS_LAST
|
|
};
|
|
|
|
/**
|
|
* I<SUP>2</SUP>S line default value when slot disabled.
|
|
*/
|
|
enum i2s_line_default_state {
|
|
/** Output default value is 0 */
|
|
I2S_LINE_DEFAULT_0,
|
|
/** Output default value is 1 */
|
|
I2S_LINE_DEFAULT_1,
|
|
/** Output default value is high impedance */
|
|
I2S_LINE_DEFAULT_HIGH_IMPEDANCE = 3,
|
|
/** Output default value is high impedance
|
|
* (abbr. \c I2S_LINE_DEFAULT_HIGH_IMPEDANCE) */
|
|
I2S_LINE_DEFAULT_HIZ = I2S_LINE_DEFAULT_HIGH_IMPEDANCE
|
|
};
|
|
|
|
/**
|
|
* I<SUP>2</SUP>S Serializer mode.
|
|
*/
|
|
enum i2s_serializer_mode {
|
|
/** Serializer is used to receive data */
|
|
I2S_SERIALIZER_RECEIVE,
|
|
/** Serializer is used to transmit data */
|
|
I2S_SERIALIZER_TRANSMIT,
|
|
/** Serializer is used to receive PDM data on each clock edge */
|
|
I2S_SERIALIZER_PDM2
|
|
};
|
|
|
|
/**
|
|
* I<SUP>2</SUP>S clock unit selection.
|
|
*/
|
|
enum i2s_clock_unit {
|
|
/** Clock Unit channel 0 */
|
|
I2S_CLOCK_UNIT_0,
|
|
/** Clock Unit channel 1 */
|
|
I2S_CLOCK_UNIT_1,
|
|
/** Number of Clock Unit channels */
|
|
I2S_CLOCK_UNIT_N
|
|
};
|
|
|
|
/**
|
|
* I<SUP>2</SUP>S Serializer selection.
|
|
*/
|
|
enum i2s_serializer {
|
|
/** Serializer channel 0 */
|
|
I2S_SERIALIZER_0,
|
|
/** Serializer channel 1 */
|
|
I2S_SERIALIZER_1,
|
|
/** Number of Serializer channels */
|
|
I2S_SERIALIZER_N
|
|
};
|
|
|
|
|
|
/**
|
|
* Configure for I<SUP>2</SUP>S pin.
|
|
*/
|
|
struct i2s_pin_config {
|
|
/** GPIO index to access the pin */
|
|
uint8_t gpio;
|
|
/** Pin function MUX */
|
|
uint8_t mux;
|
|
/** Enable this pin for I<SUP>2</SUP>S module */
|
|
bool enable;
|
|
};
|
|
|
|
/**
|
|
* Configure for I<SUP>2</SUP>S clock (SCK).
|
|
*/
|
|
struct i2s_clock_config {
|
|
/** Divide generic clock to master clock output (1~32, 0,1 means no div) */
|
|
uint8_t mck_out_div;
|
|
/** Divide generic clock to serial clock (1~32, 0,1 means no div) */
|
|
uint8_t sck_div;
|
|
/** Clock source selection */
|
|
enum gclk_generator gclk_src;
|
|
/** Master clock source selection: generated or input from pin */
|
|
enum i2s_master_clock_source mck_src;
|
|
/** Serial clock source selection: generated or input from pin */
|
|
enum i2s_serial_clock_source sck_src;
|
|
/** Invert master clock output */
|
|
bool mck_out_invert;
|
|
/** Invert serial clock output */
|
|
bool sck_out_invert;
|
|
/** Generate MCK clock output */
|
|
bool mck_out_enable;
|
|
};
|
|
|
|
/**
|
|
* Configure for I<SUP>2</SUP>S frame sync (FS).
|
|
*/
|
|
struct i2s_frame_sync_config {
|
|
/** Frame Sync (FS) generated or input from pin */
|
|
enum i2s_frame_sync_source source;
|
|
/** Frame Sync (FS) width */
|
|
enum i2s_frame_sync_width width;
|
|
/** Invert Frame Sync (FS) signal before use */
|
|
bool invert_use;
|
|
/** Invert Frame Sync (FS) signal before output */
|
|
bool invert_out;
|
|
};
|
|
|
|
/**
|
|
* Configure for I<SUP>2</SUP>S frame.
|
|
*/
|
|
struct i2s_frame_config {
|
|
/** Number of slots in a frame (1~8, 0,1 means minimum 1) */
|
|
uint8_t number_slots;
|
|
/** Size of each slot in frame */
|
|
enum i2s_slot_size slot_size;
|
|
/** Data delay from Frame Sync (FS) to first data bit */
|
|
enum i2s_data_delay data_delay;
|
|
/** Frame sync (FS) */
|
|
struct i2s_frame_sync_config frame_sync;
|
|
};
|
|
|
|
/**
|
|
* Configure for I<SUP>2</SUP>S clock unit.
|
|
*/
|
|
struct i2s_clock_unit_config {
|
|
/** Configure clock generation */
|
|
struct i2s_clock_config clock;
|
|
/** Configure frame generation */
|
|
struct i2s_frame_config frame;
|
|
|
|
/** Configure master clock pin */
|
|
struct i2s_pin_config mck_pin;
|
|
/** Configure serial clock pin */
|
|
struct i2s_pin_config sck_pin;
|
|
/** Configure frame sync pin */
|
|
struct i2s_pin_config fs_pin;
|
|
};
|
|
|
|
/**
|
|
* Configure for I<SUP>2</SUP>S Serializer.
|
|
*/
|
|
struct i2s_serializer_config {
|
|
/** Configure Serializer data pin */
|
|
struct i2s_pin_config data_pin;
|
|
|
|
/** Set to \c true to loop-back output to input pin for test */
|
|
bool loop_back;
|
|
|
|
/** Set to \c true to assumes mono input and duplicate it (left channel) to
|
|
* right channel */
|
|
bool mono_mode;
|
|
|
|
/** Disable data slot */
|
|
bool disable_data_slot[8];
|
|
|
|
/** Set to \c true to transfer LSB first, \c false to transfer MSB first */
|
|
bool transfer_lsb_first;
|
|
/** Data Word Formatting Adjust,
|
|
* set to \c true to adjust bits in word to left */
|
|
bool data_adjust_left_in_word;
|
|
/** Data Slot Formatting Adjust,
|
|
* set to \c true to adjust words in slot to left */
|
|
bool data_adjust_left_in_slot;
|
|
|
|
/** Data Word Size */
|
|
enum i2s_data_size data_size;
|
|
/** Data Formatting Bit Extension */
|
|
enum i2s_bit_padding bit_padding;
|
|
/** Data padding when under-run */
|
|
enum i2s_data_padding data_padding;
|
|
|
|
/** DMA usage */
|
|
enum i2s_dma_usage dma_usage;
|
|
|
|
/** Clock unit selection */
|
|
enum i2s_clock_unit clock_unit;
|
|
|
|
/** Line default state where slot is disabled */
|
|
enum i2s_line_default_state line_default_state;
|
|
|
|
/** Serializer Mode */
|
|
enum i2s_serializer_mode mode;
|
|
};
|
|
|
|
/**
|
|
* \brief I<SUP>2</SUP>S Serializer instance struct.
|
|
*/
|
|
struct i2s_serializer_module {
|
|
|
|
#if I2S_CALLBACK_MODE == true
|
|
/** Callbacks list for Serializer */
|
|
i2s_serializer_callback_t callback[I2S_SERIALIZER_CALLBACK_N];
|
|
|
|
/** Job buffer */
|
|
void *job_buffer;
|
|
/** Requested data words to read/write */
|
|
uint32_t requested_words;
|
|
/** Transferred data words for read/write */
|
|
uint32_t transferred_words;
|
|
|
|
/** Callback mask for registered callbacks */
|
|
uint8_t registered_callback_mask;
|
|
/** Callback mask for enabled callbacks */
|
|
uint8_t enabled_callback_mask;
|
|
|
|
/** Status of the ongoing or last transfer job */
|
|
enum status_code job_status;
|
|
#endif
|
|
|
|
/** Serializer mode */
|
|
enum i2s_serializer_mode mode;
|
|
/** Serializer data word size */
|
|
enum i2s_data_size data_size;
|
|
};
|
|
|
|
/**
|
|
* \brief I<SUP>2</SUP>S Software Module instance struct.
|
|
*/
|
|
struct i2s_module {
|
|
/** Module HW register access base */
|
|
I2s *hw;
|
|
|
|
/** Module Serializer used */
|
|
struct i2s_serializer_module serializer[2];
|
|
};
|
|
|
|
/**
|
|
* \brief Determines if the hardware module(s) are currently synchronizing to the bus.
|
|
*
|
|
* Checks to see if the underlying hardware peripheral module(s) are currently
|
|
* synchronizing across multiple clock domains to the hardware bus, This
|
|
* function can be used to delay further operations on a module until such time
|
|
* that it is ready, to prevent blocking delays for synchronization in the
|
|
* user application.
|
|
*
|
|
* \param[in] module_inst Pointer to the software module instance struct
|
|
*
|
|
* \return Synchronization status of the underlying hardware module(s).
|
|
*
|
|
* \retval false If the module has completed synchronization
|
|
* \retval true If the module synchronization is ongoing
|
|
*/
|
|
static inline bool i2s_is_syncing(
|
|
const struct i2s_module *const module_inst)
|
|
{
|
|
/* Sanity check arguments */
|
|
Assert(module_inst);
|
|
Assert(module_inst->hw);
|
|
|
|
return (module_inst->hw->SYNCBUSY.reg > 0);
|
|
}
|
|
|
|
/**
|
|
* \name Driver Initialization
|
|
* @{
|
|
*/
|
|
|
|
enum status_code i2s_init(
|
|
struct i2s_module *const module_inst,
|
|
I2s *hw);
|
|
|
|
/** @} */
|
|
|
|
/**
|
|
* \name Enable/Disable/Reset
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* \brief Enable the I<SUP>2</SUP>S module.
|
|
*
|
|
* Enables a I<SUP>2</SUP>S module that has been previously initialized.
|
|
*
|
|
* \param[in] module_inst Pointer to the software module instance struct
|
|
*/
|
|
static inline void i2s_enable(const struct i2s_module *const module_inst)
|
|
{
|
|
Assert(module_inst);
|
|
Assert(module_inst->hw);
|
|
|
|
while (module_inst->hw->SYNCBUSY.reg & I2S_SYNCBUSY_ENABLE) {
|
|
/* Sync wait */
|
|
}
|
|
module_inst->hw->CTRLA.reg |= I2S_SYNCBUSY_ENABLE;
|
|
}
|
|
|
|
/**
|
|
* \brief Disables the I<SUP>2</SUP>S module.
|
|
*
|
|
* Disables a I<SUP>2</SUP>S module.
|
|
*
|
|
* \param[in] module_inst Pointer to the software module instance struct
|
|
*/
|
|
static inline void i2s_disable(const struct i2s_module *const module_inst)
|
|
{
|
|
Assert(module_inst);
|
|
Assert(module_inst->hw);
|
|
|
|
while (module_inst->hw->SYNCBUSY.reg & I2S_SYNCBUSY_ENABLE) {
|
|
/* Sync wait */
|
|
}
|
|
|
|
module_inst->hw->INTENCLR.reg = I2S_INTENCLR_MASK;
|
|
module_inst->hw->INTFLAG.reg = I2S_INTFLAG_MASK;
|
|
module_inst->hw->CTRLA.reg &= ~I2S_SYNCBUSY_ENABLE;
|
|
}
|
|
|
|
/**
|
|
* \brief Resets the I<SUP>2</SUP>S module.
|
|
*
|
|
* Resets the I<SUP>2</SUP>S module, restoring all hardware module registers to their
|
|
* default values and disabling the module. The I<SUP>2</SUP>S module will not be
|
|
* accessible while the reset is being performed.
|
|
*
|
|
* \param[in] module_inst Pointer to the software module instance struct
|
|
*/
|
|
static inline void i2s_reset(const struct i2s_module *const module_inst)
|
|
{
|
|
Assert(module_inst);
|
|
Assert(module_inst->hw);
|
|
|
|
/* Disable the module if it is running */
|
|
if (module_inst->hw->CTRLA.reg & I2S_CTRLA_ENABLE) {
|
|
i2s_disable(module_inst);
|
|
while (i2s_is_syncing(module_inst)) {
|
|
/* Sync wait */
|
|
}
|
|
}
|
|
/* Reset the HW module */
|
|
module_inst->hw->CTRLA.reg = I2S_CTRLA_SWRST;
|
|
}
|
|
|
|
/** @} */
|
|
|
|
/**
|
|
* \name Clock Unit Initialization and Configuration
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* \brief Initializes config with predefined default values for I<SUP>2</SUP>S clock unit.
|
|
*
|
|
* This function will initialize a given I<SUP>2</SUP>S Clock Unit configuration structure
|
|
* to a set of known default values. This function should be called on any new
|
|
* instance of the configuration structures before being modified by the user
|
|
* application.
|
|
*
|
|
* The default configuration is as follows:
|
|
* - The clock unit does not generate output clocks (MCK, SCK, and FS)
|
|
* - The pins (MCK, SCK, and FS) and MUX configurations are not set
|
|
*
|
|
* \param[out] config Pointer to a I<SUP>2</SUP>S module clock unit configuration struct
|
|
* to set
|
|
*/
|
|
static inline void i2s_clock_unit_get_config_defaults(
|
|
struct i2s_clock_unit_config *const config)
|
|
{
|
|
Assert(config);
|
|
|
|
config->clock.mck_out_enable = false;
|
|
config->clock.gclk_src = GCLK_GENERATOR_0;
|
|
|
|
config->clock.mck_src = I2S_MASTER_CLOCK_SOURCE_GCLK;
|
|
config->clock.mck_out_div = 1;
|
|
config->clock.mck_out_invert = false;
|
|
|
|
config->clock.sck_src = I2S_SERIAL_CLOCK_SOURCE_MCKDIV;
|
|
config->clock.sck_div = 1;
|
|
config->clock.sck_out_invert = false;
|
|
|
|
config->frame.number_slots = 1;
|
|
config->frame.slot_size = I2S_SLOT_SIZE_32_BIT;
|
|
config->frame.data_delay = I2S_DATA_DELAY_I2S;
|
|
|
|
config->frame.frame_sync.source = I2S_FRAME_SYNC_SOURCE_SCKDIV;
|
|
config->frame.frame_sync.width = I2S_FRAME_SYNC_WIDTH_HALF_FRAME;
|
|
config->frame.frame_sync.invert_use = false;
|
|
config->frame.frame_sync.invert_out = false;
|
|
|
|
config->mck_pin.enable = false;
|
|
config->mck_pin.mux = 0;
|
|
config->mck_pin.gpio = 0;
|
|
|
|
config->sck_pin.enable = false;
|
|
config->sck_pin.mux = 0;
|
|
config->sck_pin.gpio = 0;
|
|
|
|
config->fs_pin.enable = false;
|
|
config->fs_pin.mux = 0;
|
|
config->fs_pin.gpio = 0;
|
|
}
|
|
|
|
enum status_code i2s_clock_unit_set_config(
|
|
struct i2s_module *const module_inst,
|
|
const enum i2s_clock_unit clock_unit,
|
|
const struct i2s_clock_unit_config *config);
|
|
|
|
/** @} */
|
|
|
|
|
|
/**
|
|
* \name Clock Unit Enable/Disable
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* \brief Enable the Specified Clock Unit of I<SUP>2</SUP>S module.
|
|
*
|
|
* Enables a Clock Unit in I<SUP>2</SUP>S module that has been previously initialized.
|
|
*
|
|
* \param[in] module_inst Pointer to the software module instance struct
|
|
* \param[in] clock_unit I<SUP>2</SUP>S Clock Unit to enable
|
|
*/
|
|
static inline void i2s_clock_unit_enable(
|
|
const struct i2s_module *const module_inst,
|
|
const enum i2s_clock_unit clock_unit)
|
|
{
|
|
uint32_t cken_bit;
|
|
|
|
Assert(module_inst);
|
|
Assert(module_inst->hw);
|
|
|
|
cken_bit = I2S_CTRLA_CKEN0 << clock_unit;
|
|
|
|
while (module_inst->hw->SYNCBUSY.reg & cken_bit) {
|
|
/* Sync wait */
|
|
}
|
|
module_inst->hw->CTRLA.reg |= cken_bit;
|
|
}
|
|
|
|
/**
|
|
* \brief Disable the Specified Clock Unit of I<SUP>2</SUP>S module.
|
|
*
|
|
* Disables a Clock Unit in I<SUP>2</SUP>S module that has been previously initialized.
|
|
*
|
|
* \param[in] module_inst Pointer to the software module instance struct
|
|
* \param[in] clock_unit I<SUP>2</SUP>S Clock Unit to disable
|
|
*/
|
|
static inline void i2s_clock_unit_disable(
|
|
const struct i2s_module *const module_inst,
|
|
const enum i2s_clock_unit clock_unit)
|
|
{
|
|
uint32_t cken_bit;
|
|
|
|
Assert(module_inst);
|
|
Assert(module_inst->hw);
|
|
|
|
cken_bit = I2S_CTRLA_CKEN0 << clock_unit;
|
|
|
|
while (module_inst->hw->SYNCBUSY.reg & cken_bit) {
|
|
/* Sync wait */
|
|
}
|
|
module_inst->hw->CTRLA.reg &= ~cken_bit;
|
|
}
|
|
|
|
/** @} */
|
|
|
|
|
|
/**
|
|
* \name Serializer Initialization and Configuration
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* \brief Initializes config with predefined default values for I<SUP>2</SUP>S Serializer.
|
|
*
|
|
* This function will initialize a given I<SUP>2</SUP>S Clock Unit configuration structure
|
|
* to a set of known default values. This function should be called on any new
|
|
* instance of the configuration structures before being modified by the user
|
|
* application.
|
|
*
|
|
* The default configuration is as follows:
|
|
* - Output data does not internally loopback to input line
|
|
* - Does not extend mono data (left channel) to right channel
|
|
* - None of the data slot is disabled
|
|
* - MSB of I<SUP>2</SUP>S data is transferred first
|
|
* - In data word data is adjusted right
|
|
* - In slot data word is adjusted left
|
|
* - The data size is 16-bit width
|
|
* - I<SUP>2</SUP>S will padd 0 to not defined bits
|
|
* - I<SUP>2</SUP>S will padd 0 to not defined words
|
|
* - I<SUP>2</SUP>S will use single DMA channel for all data channels
|
|
* - I<SUP>2</SUP>S will use clock unit 0 to serve as clock
|
|
* - The default data line state is 0, when there is no data
|
|
* - I<SUP>2</SUP>S will transmit data to output line
|
|
* - The data pin and MUX configuration are not set
|
|
*
|
|
* \param[out] config Pointer to a I<SUP>2</SUP>S module Serializer configuration struct
|
|
* to set
|
|
*/
|
|
static inline void i2s_serializer_get_config_defaults(
|
|
struct i2s_serializer_config *const config)
|
|
{
|
|
config->loop_back = false;
|
|
|
|
config->mono_mode = false;
|
|
|
|
config->disable_data_slot[0] = false;
|
|
config->disable_data_slot[1] = false;
|
|
config->disable_data_slot[2] = false;
|
|
config->disable_data_slot[3] = false;
|
|
config->disable_data_slot[4] = false;
|
|
config->disable_data_slot[5] = false;
|
|
config->disable_data_slot[6] = false;
|
|
config->disable_data_slot[7] = false;
|
|
|
|
config->transfer_lsb_first = false;
|
|
config->data_adjust_left_in_word = false;
|
|
config->data_adjust_left_in_slot = true;
|
|
|
|
config->data_size = I2S_DATA_SIZE_16BIT;
|
|
|
|
config->bit_padding = I2S_BIT_PADDING_0;
|
|
config->data_padding = I2S_DATA_PADDING_0;
|
|
|
|
config->dma_usage = I2S_DMA_USE_SINGLE_CHANNEL_FOR_ALL;
|
|
|
|
config->clock_unit = I2S_CLOCK_UNIT_0;
|
|
|
|
config->line_default_state = I2S_LINE_DEFAULT_0;
|
|
|
|
config->mode = I2S_SERIALIZER_TRANSMIT;
|
|
|
|
config->data_pin.enable = false;
|
|
config->data_pin.gpio = 0;
|
|
config->data_pin.mux = 0;
|
|
}
|
|
|
|
enum status_code i2s_serializer_set_config(
|
|
struct i2s_module *const module_inst,
|
|
const enum i2s_serializer serializer,
|
|
const struct i2s_serializer_config *config);
|
|
/** @} */
|
|
|
|
/**
|
|
* \name Serializer Enable/Disable
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* \brief Enable the Specified Serializer of I<SUP>2</SUP>S module.
|
|
*
|
|
* Enables a Serializer in I<SUP>2</SUP>S module that has been previously initialized.
|
|
*
|
|
* \param[in] module_inst Pointer to the software module instance struct
|
|
* \param[in] serializer I<SUP>2</SUP>S Serializer to enable
|
|
*/
|
|
static inline void i2s_serializer_enable(
|
|
const struct i2s_module *const module_inst,
|
|
const enum i2s_serializer serializer)
|
|
{
|
|
uint32_t seren_bit;
|
|
|
|
Assert(module_inst);
|
|
Assert(module_inst->hw);
|
|
|
|
seren_bit = I2S_CTRLA_SEREN0 << serializer;
|
|
|
|
while (module_inst->hw->SYNCBUSY.reg & seren_bit) {
|
|
/* Sync wait */
|
|
}
|
|
module_inst->hw->CTRLA.reg |= seren_bit;
|
|
}
|
|
|
|
/**
|
|
* \brief Disable the Specified Serializer of I<SUP>2</SUP>S module.
|
|
*
|
|
* Disables a Serializer in I<SUP>2</SUP>S module that has been previously initialized.
|
|
*
|
|
* \param[in] module_inst Pointer to the software module instance struct
|
|
* \param[in] serializer I<SUP>2</SUP>S Serializer to disable
|
|
*/
|
|
static inline void i2s_serializer_disable(
|
|
const struct i2s_module *const module_inst,
|
|
const enum i2s_serializer serializer)
|
|
{
|
|
uint32_t seren_bit;
|
|
|
|
Assert(module_inst);
|
|
Assert(module_inst->hw);
|
|
|
|
seren_bit = I2S_CTRLA_SEREN0 << serializer;
|
|
|
|
while (module_inst->hw->SYNCBUSY.reg & seren_bit) {
|
|
/* Sync wait */
|
|
}
|
|
module_inst->hw->CTRLA.reg &= ~seren_bit;
|
|
}
|
|
/** @} */
|
|
|
|
/**
|
|
* \name Status Management
|
|
* @{
|
|
*/
|
|
|
|
uint32_t i2s_get_status(
|
|
const struct i2s_module *const module_inst);
|
|
|
|
void i2s_clear_status(
|
|
const struct i2s_module *const module_inst,
|
|
uint32_t status);
|
|
|
|
|
|
enum status_code i2s_enable_status_interrupt(
|
|
struct i2s_module *const module_inst,
|
|
uint32_t status);
|
|
|
|
void i2s_disable_status_interrupt(
|
|
struct i2s_module *const module_inst,
|
|
uint32_t status);
|
|
|
|
/** @}*/
|
|
|
|
/**
|
|
* \name Data Read/Write
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* \brief Write a data word to the specified Serializer of I<SUP>2</SUP>S module
|
|
*
|
|
* \param[in] module_inst Pointer to the software module instance struct
|
|
* \param[in] serializer The Serializer to write to
|
|
* \param[in] data The data to write
|
|
*
|
|
*/
|
|
static inline void i2s_serializer_write_wait(
|
|
const struct i2s_module *const module_inst,
|
|
enum i2s_serializer serializer,
|
|
uint32_t data)
|
|
{
|
|
uint32_t sync_bit, ready_bit;
|
|
|
|
Assert(module_inst);
|
|
Assert(module_inst->hw);
|
|
|
|
ready_bit = I2S_INTFLAG_TXRDY0 << serializer;
|
|
while (!(module_inst->hw->INTFLAG.reg & ready_bit)) {
|
|
/* Wait until ready to transmit */
|
|
}
|
|
sync_bit = I2S_SYNCBUSY_DATA0 << serializer;
|
|
while (module_inst->hw->SYNCBUSY.reg & sync_bit) {
|
|
/* Wait sync */
|
|
}
|
|
/* Write data */
|
|
module_inst->hw->DATA[serializer].reg = data;
|
|
module_inst->hw->INTFLAG.reg = ready_bit;
|
|
}
|
|
|
|
/**
|
|
* \brief Read a data word from the specified Serializer of I<SUP>2</SUP>S module
|
|
*
|
|
* \param[in] module_inst Pointer to the software module instance struct
|
|
* \param[in] serializer The Serializer to read
|
|
*/
|
|
static inline uint32_t i2s_serializer_read_wait(
|
|
const struct i2s_module *const module_inst,
|
|
enum i2s_serializer serializer)
|
|
{
|
|
uint32_t sync_bit, ready_bit;
|
|
uint32_t data;
|
|
|
|
Assert(module_inst);
|
|
Assert(module_inst->hw);
|
|
|
|
ready_bit = I2S_INTFLAG_RXRDY0 << serializer;
|
|
while (!(module_inst->hw->INTFLAG.reg & ready_bit)) {
|
|
/* Wait until ready to transmit */
|
|
}
|
|
sync_bit = I2S_SYNCBUSY_DATA0 << serializer;
|
|
while (module_inst->hw->SYNCBUSY.reg & sync_bit) {
|
|
/* Wait sync */
|
|
}
|
|
/* Read data */
|
|
data = module_inst->hw->DATA[serializer].reg;
|
|
module_inst->hw->INTFLAG.reg = ready_bit;
|
|
return data;
|
|
}
|
|
|
|
enum status_code i2s_serializer_write_buffer_wait(
|
|
const struct i2s_module *const module_inst,
|
|
enum i2s_serializer serializer,
|
|
void *buffer, uint32_t size);
|
|
|
|
enum status_code i2s_serializer_read_buffer_wait(
|
|
const struct i2s_module *const module_inst,
|
|
enum i2s_serializer serializer,
|
|
void *buffer, uint32_t size);
|
|
|
|
/** @} */
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
/** @} */
|
|
|
|
|
|
/**
|
|
* \page asfdoc_sam0_i2s_extra Extra Information for I2S Driver
|
|
*
|
|
* \section asfdoc_sam0_i2s_extra_acronyms Acronyms
|
|
* Below is a table listing the acronyms used in this module, along with their
|
|
* intended meanings.
|
|
*
|
|
* <table>
|
|
* <tr>
|
|
* <th>Acronym</th>
|
|
* <th>Description</th>
|
|
* </tr>
|
|
* <tr>
|
|
* <td>I<SUP>2</SUP>S, IIS</td>
|
|
* <td>Inter-IC Sound Controller</td>
|
|
* </tr>
|
|
* <tr>
|
|
* <td>MCK</td>
|
|
* <td>Master Clock</td>
|
|
* </tr>
|
|
* <tr>
|
|
* <td>SCK</td>
|
|
* <td>Serial Clock</td>
|
|
* </tr>
|
|
* <tr>
|
|
* <td>FS</td>
|
|
* <td>Frame Sync</td>
|
|
* </tr>
|
|
* <tr>
|
|
* <td>SD</td>
|
|
* <td>Serial Data</td>
|
|
* </tr>
|
|
* <tr>
|
|
* <td>ADC</td>
|
|
* <td>Analog-to-Digital Converter</td>
|
|
* </tr>
|
|
* <tr>
|
|
* <td>DAC</td>
|
|
* <td>Digital-to-Analog Converter</td>
|
|
* </tr>
|
|
* <tr>
|
|
* <td>TDM</td>
|
|
* <td>Time Division Multiplexed</td>
|
|
* </tr>
|
|
* <tr>
|
|
* <td>PDM</td>
|
|
* <td>Pulse Density Modulation</td>
|
|
* </tr>
|
|
* <tr>
|
|
* <td>LSB</td>
|
|
* <td>Least Significant Bit</td>
|
|
* </tr>
|
|
* <tr>
|
|
* <td>MSB</td>
|
|
* <td>Most Significant Bit</td>
|
|
* </tr>
|
|
* <tr>
|
|
* <td>DSP</td>
|
|
* <td>Digital Signal Processor</td>
|
|
* </tr>
|
|
* </table>
|
|
*
|
|
*
|
|
* \section asfdoc_sam0_i2s_extra_dependencies Dependencies
|
|
* This driver has the following dependencies:
|
|
*
|
|
* - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver"
|
|
*
|
|
*
|
|
* \section asfdoc_sam0_i2s_extra_errata Errata
|
|
* There are no errata related to this driver.
|
|
*
|
|
*
|
|
* \section asfdoc_sam0_i2s_extra_history Module History
|
|
* An overview of the module history is presented in the table below, with
|
|
* details on the enhancements and fixes made to the module since its first
|
|
* release. The current version of this corresponds to the newest version in
|
|
* the table.
|
|
*
|
|
* <table>
|
|
* <tr>
|
|
* <th>Changelog</th>
|
|
* </tr>
|
|
* <tr>
|
|
* <td>Initial Release</td>
|
|
* </tr>
|
|
* </table>
|
|
*/
|
|
|
|
/**
|
|
* \page asfdoc_sam0_i2s_exqsg Examples for I2S Driver
|
|
*
|
|
* This is a list of the available Quick Start guides (QSGs) and example
|
|
* applications for \ref asfdoc_sam0_i2s_group. QSGs are simple examples with
|
|
* step-by-step instructions to configure and use this driver in a selection of
|
|
* use cases. Note that QSGs can be compiled as a standalone application or be
|
|
* added to the user application.
|
|
*
|
|
* - \subpage asfdoc_sam0_i2s_basic_use_case
|
|
* \if I2S_CALLBACK_MODE
|
|
* - \subpage asfdoc_sam0_i2s_callback_use_case
|
|
* \endif
|
|
* - \subpage asfdoc_sam0_i2s_dma_use_case
|
|
*
|
|
* \page asfdoc_sam0_i2s_document_revision_history Document Revision History
|
|
*
|
|
* <table>
|
|
* <tr>
|
|
* <th>Doc. Rev.</th>
|
|
* <th>Date</th>
|
|
* <th>Comments</th>
|
|
* </tr>
|
|
* <tr>
|
|
* <td>42255B</td>
|
|
* <td>12/2015</td>
|
|
* <td>Added support for SAM DA1</td>
|
|
* </tr>
|
|
* <tr>
|
|
* <td>42255A</td>
|
|
* <td>01/2014</td>
|
|
* <td>Initial release</td>
|
|
* </tr>
|
|
* </table>
|
|
*/
|
|
|
|
#endif /* #ifndef I2S_H_INCLUDED */
|