260 lines
4.7 KiB
C
260 lines
4.7 KiB
C
#ifndef __PLAT_INTERRUPT_H__
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#define __PLAT_INTERRUPT_H__
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#include "rthw.h"
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#include <rtconfig.h>
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#if defined(BSP_USING_MMU)
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#include "mmu.h"
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#define NONCACHEABLE BIT31
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#else
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#define NONCACHEABLE 0
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#endif
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typedef enum
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{
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/* SYS_AHBIPRST, SYS_BA + 0x060 */
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CHIPRST,
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AHBIPRST_Reserved_1,
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CPURST,
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EBIRST,
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PDMA0RST,
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PDMA1RST,
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SDICRST,
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GPIORST,
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I2SRST,
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AHBIPRST_Reserved_9,
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VCAP0RST,
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VCAP1RST,
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AHBIPRST_Reserved_12,
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AHBIPRST_Reserved_13,
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AHBIPRST_Reserved_14,
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AHBIPRST_Reserved_15,
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EMAC0RST,
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EMAC1RST,
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USBHRST,
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USBDRST,
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FMIRST,
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AHBIPRST_Reserved_21,
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AHBIPRST_Reserved_22,
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CRYPTORST,
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SDHRST,
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AHBIPRST_Reserved_25,
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AHBIPRST_Reserved_26,
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AHBIPRST_Reserved_27,
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AHBIPRST_Reserved_28,
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AHBIPRST_Reserved_29,
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AHBIPRST_Reserved_30,
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AHBIPRST_Reserved_31,
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/* SYS_APBIPRST0, SYS_BA + 0x064 */
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APBIPRST0_Reserved_0,
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APBIPRST0_Reserved_1,
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APBIPRST0_Reserved_2,
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APBIPRST0_Reserved_3,
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AICRST,
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APBIPRST0_Reserved_5,
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APBIPRST0_Reserved_6,
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APBIPRST0_Reserved_7,
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TIMER0RST,
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TIMER1RST,
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TIMER2RST,
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TIMER3RST,
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TIMER4RST,
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TIMER5RST,
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APBIPRST0_Reserved_14,
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APBIPRST0_Reserved_15,
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UART0RST,
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UART1RST,
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UART2RST,
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UART3RST,
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UART4RST,
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UART5RST,
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UART6RST,
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UART7RST,
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UART8RST,
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UART9RST,
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APBIPRST0_Reserved_26,
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APBIPRST0_Reserved_27,
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APBIPRST0_Reserved_28,
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APBIPRST0_Reserved_29,
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APBIPRST0_Reserved_30,
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APBIPRST0_Reserved_31,
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/* SYS_APBIPRST1, SYS_BA + 0x068 */
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I2C0RST,
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I2C1RST,
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I2C2RST,
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I2C3RST,
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QSPI0RST,
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SPI0RST,
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SPI1RST,
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APBIPRST1_Reserved_7,
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CAN0RST,
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CAN1RST,
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CAN2RST,
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CAN3RST,
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SMC0RST,
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SMC1RST,
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APBIPRST1_Reserved_14,
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APBIPRST1_Reserved_15,
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APBIPRST1_Reserved_16,
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APBIPRST1_Reserved_17,
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APBIPRST1_Reserved_18,
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APBIPRST1_Reserved_19,
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APBIPRST1_Reserved_20,
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APBIPRST1_Reserved_21,
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APBIPRST1_Reserved_22,
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APBIPRST1_Reserved_23,
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ADCRST,
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APBIPRST1_Reserved_25,
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PWM0RST,
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PWM1RST,
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APBIPRST1_Reserved_28,
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APBIPRST1_Reserved_29,
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APBIPRST1_Reserved_30,
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APBIPRST1_Reserved_31,
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SYS_IPRST_CNT
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} E_SYS_IPRST;
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typedef enum
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{
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/* CLK_HCLKEN, CLK_BA + 0x010 */
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CPUCKEN,
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HCLKCKEN,
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HCLK1CKEN,
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HCLK3CKEN,
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HCLK4CKEN,
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PCLK0CKEN,
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PCLK1CKEN,
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TICCKEN,
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SRAMCKEN,
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EBICKEN,
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SDICCKEN,
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GPIOCKEN,
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PDMA0CKEN,
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PDMA1CKEN,
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PCLK2CKEN,
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CKOCKEN,
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EMAC0CKEN,
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EMAC1CKEN,
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USBHCKEN,
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USBDCKEN,
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FMICKEN,
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NANDCKEN,
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SD0CKEN,
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CRYPTOCKEN,
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I2SCKEN,
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HCLKEN_Reserved_25,
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VCAP0CKEN,
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SENSORCKEN,
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HCLKEN_Reserved_28,
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HCLKEN_Reserved_29,
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SD1CKEN,
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VCAP1CKEN,
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CLK_HCLKEN_END,
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/* CLK_BA+0x014 */
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/* CLK_PCLKEN0 CLK_BA+0x018 */
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CLK_PCLKEN0_BEGIN = CLK_HCLKEN_END + 32,
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WDTCKEN = CLK_PCLKEN0_BEGIN,
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WWDTCKEN,
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RTCCKEN,
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PCLKEN0_Reserved_3,
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PCLKEN0_Reserved_4,
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PCLKEN0_Reserved_5,
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PCLKEN0_Reserved_6,
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PCLKEN0_Reserved_7,
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TIMER0CKEN,
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TIMER1CKEN,
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TIMER2CKEN,
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TIMER3CKEN,
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TIMER4CKEN,
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TIMER5CKEN,
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PCLKEN0_Reserved_14,
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PCLKEN0_Reserved_15,
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UART0CKEN,
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UART1CKEN,
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UART2CKEN,
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UART3CKEN,
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UART4CKEN,
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UART5CKEN,
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UART6CKEN,
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UART7CKEN,
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UART8CKEN,
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UART9CKEN,
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PCLKEN0_Reserved_26,
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PCLKEN0_Reserved_27,
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PCLKEN0_Reserved_28,
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PCLKEN0_Reserved_29,
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PCLKEN0_Reserved_30,
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PCLKEN0_Reserved_31,
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/* CLK_PCLKEN1, CLK_BA + 0x01C */
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I2C0CKEN,
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I2C1CKEN,
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I2C2CKEN,
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I2C3CKEN,
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QSPI0CKEN,
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SPI0CKEN,
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SPI1CKEN,
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PCLKEN1_Reserved_7,
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CAN0CKEN,
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CAN1CKEN,
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CAN2CKEN,
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CAN3CKEN,
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SMC0CKEN,
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SMC1CKEN,
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PCLKEN1_Reserved_14,
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PCLKEN1_Reserved_15,
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PCLKEN1_Reserved_16,
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PCLKEN1_Reserved_17,
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PCLKEN1_Reserved_18,
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PCLKEN1_Reserved_19,
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PCLKEN1_Reserved_20,
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PCLKEN1_Reserved_21,
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PCLKEN1_Reserved_22,
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PCLKEN1_Reserved_23,
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ADCCKEN,
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PCLKEN1_Reserved_25,
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PWM0CKEN,
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PWM1CKEN,
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PCLKEN1_Reserved_28,
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PCLKEN1_Reserved_29,
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PCLKEN1_Reserved_30,
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PCLKEN1_Reserved_31,
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SYS_IPCLK_CNT
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} E_SYS_IPCLK;
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void rt_hw_interrupt_init(void);
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void rt_hw_interrupt_set_priority(int vector, int priority);
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void rt_hw_interrupt_set_type(int vector, int type);
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rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, void *param, const char *name);
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void rt_hw_systick_init(void);
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void nu_clock_base_init(void);
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void nu_systick_udelay(uint32_t delay_us);
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void nu_sys_ip_reset(E_SYS_IPRST eIPRstIdx);
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void nu_sys_ipclk_enable(E_SYS_IPCLK eIPClkIdx);
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void nu_sys_ipclk_disable(E_SYS_IPCLK eIPClkIdx);
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#endif
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