777 lines
22 KiB
C
777 lines
22 KiB
C
/**************************************************************************//**
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*
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* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-1-13 Wayne First version
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*
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******************************************************************************/
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#include <rtthread.h>
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#if defined(NU_PKG_USING_SPINAND)
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#define LOG_TAG "spinand_flash"
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#define DBG_ENABLE
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#define DBG_SECTION_NAME LOG_TAG
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#define DBG_LEVEL DBG_INFO
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#define DBG_COLOR
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#include <rtdbg.h>
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#include "spinand.h"
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const struct nu_spinand_info g_spinandflash_list[] =
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{
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/* Winbond */
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/* Only tested */
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{
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0xEFAA21, 2048, 64, 0x6b, 0xff, 0xff, 0xff, 0x1, 1024, 64, 0, "Winbond 128MB: 2048+64@64@1024",
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#if defined(RT_USING_DFS_UFFS)
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{
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/* For storing Seal-byte at 0x37. Need 15-Bytes */
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0x04, 0x04, 0x14, 0x04, 0x24, 0x04, 0x34, 0x03, 0xFF, 0x00
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},
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{
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/* For storing Seal-byte at 0x37 and not report latest ECC part in Spare-3 */
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0x08, 0x08, 0x18, 0x08, 0x28, 0x08, /*0x38, 0x08,*/ 0xFF, 0x00
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}
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#else
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{
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0x04, 0x04, 0x14, 0x04, 0x24, 0x04, 0x34, 0x04, 0xFF, 0x00
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},
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{
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0x08, 0x08, 0x18, 0x08, 0x28, 0x08, 0x38, 0x08, 0xFF, 0x00
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}
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#endif
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},
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{
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0xEFBF22, 2048, 64, 0x6b, 0xff, 0xff, 0xff, 0x1, 2048, 64, 0, "Winbond 256MB: 2048+64@64@2048",
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#if defined(RT_USING_DFS_UFFS)
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{
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/* For storing Seal-byte at 0x39. Need 15-Bytes */
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0x08, 0x04, 0x18, 0x04, 0x28, 0x04, 0x38, 0x03, 0xFF, 0x00
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},
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{
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/* For storing Seal-byte at 0x39 and not report latest ECC part in Spare-3 */
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0x0C, 0x04, 0x1C, 0x04, 0x2C, 0x04, /*0x3C, 0x04,*/ 0xFF, 0x00
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}
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#else
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{
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0x08, 0x04, 0x18, 0x04, 0x28, 0x04, 0x38, 0x04, 0xFF, 0x00
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},
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{
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0x0C, 0x04, 0x1C, 0x04, 0x2C, 0x04, 0x3C, 0x04, 0xFF, 0x00
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}
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#endif
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},
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#if 0
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{ 0xEFAA22, 2048, 64, 0x6b, 0xff, 0xff, 0xff, 0x1, 2048, 64, 0, "Winbond 256MB: 2048+64@64@1024" },
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{ 0xEFAB21, 2048, 64, 0x6b, 0xff, 0xff, 0xff, 0x1, 1024, 64, 1, "Winbond 256MB: 2048+64@64@1024, MCP" },
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/* Not test and supporting yet. */
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/* MXIC */
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{ 0x00C212, 2048, 64, 0x6b, 0x05, 0x01, 0x40, 0x1, 1024, 64, 0, "MXIC 128MB: 2048+64@64@1024" },
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/* XTX */
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{ 0x0BE20B, 2048, 64, 0x6b, 0xff, 0xff, 0xff, 0x1, 2048, 64, 0, "XTX 256MB: 2048+64@64@2048" },
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{ 0x0BF20B, 2048, 64, 0x6b, 0xff, 0xff, 0xff, 0x1, 2048, 64, 0, "XTX 256MB: 2048+64@64@2048" },
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{ 0x0BE10B, 2048, 64, 0x6b, 0xff, 0xff, 0xff, 0x1, 1024, 64, 0, "XTX 256MB: 2048+64@64@1024" },
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{ 0x0BF10B, 2048, 64, 0x6b, 0xff, 0xff, 0xff, 0x1, 1024, 64, 0, "XTX 256MB: 2048+64@64@1024" },
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/* ATO */
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{ 0x9B129B, 2048, 64, 0x6b, 0x0f, 0x1f, 0x01, 0x1, 1024, 64, 0, "ATO 128MB: 2048+64@64@1024" },
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/* Micro */
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{ 0x2C242C, 2048, 128, 0x6b, 0x0f, 0x1f, 0x01, 0x1, 2048, 64, 0, "Micro 256MB: 2048+128@64@2048" },
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/* GigaDevice */
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{ 0xB148C8, 2048, 128, 0x6b, 0x0f, 0x1f, 0x01, 0x1, 1024, 64, 0, "GD 128MB: 2048+128@64@1024" },
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/* Unknown */
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{ 0x00C8D1, 2048, 128, 0x6b, 0x0f, 0x1f, 0x01, 0x1, 1024, 64, 0, "Unknown 128MB: 2048+128@64@1024" },
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{ 0x00C851, 2048, 128, 0x6b, 0x0f, 0x1f, 0x01, 0x1, 1024, 64, 0, "Unknown 128MB: 2048+128@64@1024" },
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{ 0x98E240, 2048, 128, 0x6b, 0x0f, 0x1f, 0x01, 0x1, 1024, 64, 0, "Unknown 128MB: 2048+128@64@1024" }
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#endif
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};
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#define SPINAND_LIST_ELEMENT_NUM ( sizeof(g_spinandflash_list)/sizeof(struct nu_spinand_info) )
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/*
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========================================================
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For 0xEFAA21 description:
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Data Area(2048-Byte)
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-----------------------------
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|Sect-0|Sect-1|Sect-2|Sect-3|
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|(512B)|(512B)|(512B)|(512B)|
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-----------------------------
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Spare Area(64-Byte)
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---------------------------------
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|Spare-0|Spare-1|Spare-2|Spare-3|
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| (16B) | (16B) | (16B) | (16B) |
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---------------------------------
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----------------- Spare-0 -------------------
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/ \
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-------------------------------------------------
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| BBM | UD2 | UD1 | ECC Sect-0 | ECC Spare |
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| 0 1 | 2 3 | 4 5 6 7 | 8 9 A B C D | E F |
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-------------------------------------------------
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| NO ECC | ECC PROTECTED | ECC 4-D |
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BBM: Bad block marker.
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UD1: User Data 1.
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UD2: User Data 2.
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ECC Sect-n: ECC for sector-n.
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ECC Spare: ECC for spare 4-D.
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---------------- Spare-1 -------------------
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/ \
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-----------------------------------------------
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| UD2 | UD1 | ECC Sect-1 | ECC Spare |
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| 0 1 2 3 | 4 5 6 7 | 8 9 A B C D | E F |
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-----------------------------------------------
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| NO ECC | ECC PROTECTED | ECC 14-1D |
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---------------- Spare-2 -------------------
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/ \
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-----------------------------------------------
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| UD2 | UD1 | ECC Sect-2 | ECC Spare |
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| 0 1 2 3 | 4 5 6 7 | 8 9 A B C D | E F |
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-----------------------------------------------
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| NO ECC | ECC PROTECTED | ECC 24-2D |
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---------------- Spare-3 -------------------
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/ \
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-----------------------------------------------
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| UD2 | UD1 | ECC Sect-3 | ECC Spare |
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| 0 1 2 3 | 4 5 6 7 | 8 9 A B C D | E F |
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-----------------------------------------------
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| NO ECC | ECC PROTECTED | ECC 34-3D |
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========================================================
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========================================================
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For 0xEFBF22 description:
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Data Area(2048-Byte)
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-----------------------------
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|Sect-0|Sect-1|Sect-2|Sect-3|
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|(512B)|(512B)|(512B)|(512B)|
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-----------------------------
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Spare Area(64-Byte)
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---------------------------------
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|Spare-0|Spare-1|Spare-2|Spare-3|
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| (16B) | (16B) | (16B) | (16B) |
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---------------------------------
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----------------- Spare-0 -------------------
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/ \
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-----------------------------------------
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| BBM | UD2 | UD1 | ECC UD1 |
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| 0 1 | 2 3 4 5 6 7 | 8 9 A B | C D E F |
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-----------------------------------------
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| NO ECC | ECC PROTECTED |
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BBM: Bad block marker.
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UD1: User Data 1.
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UD2: User Data 2.
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ECC UD1: ECC for UD1.
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---------------- Spare-1 -------------------
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/ \
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---------------------------------------
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| UD2 | UD1 | ECC UD1 |
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| 0 1 2 3 4 5 6 7 | 8 9 A B | C D E F |
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---------------------------------------
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| NO ECC | ECC PROTECTED |
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---------------- Spare-2 -------------------
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/ \
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---------------------------------------
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| UD2 | UD1 | ECC UD1 |
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| 0 1 2 3 4 5 6 7 | 8 9 A B | C D E F |
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---------------------------------------
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| NO ECC | ECC PROTECTED |
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---------------- Spare-3 -------------------
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/ \
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---------------------------------------
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| UD2 | UD1 | ECC UD1 |
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| 0 1 2 3 4 5 6 7 | 8 9 A B | C D E F |
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---------------------------------------
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| NO ECC | ECC PROTECTED |
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========================================================
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*/
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rt_uint8_t spinand_flash_data_layout[SPINAND_SPARE_LAYOUT_SIZE];
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rt_uint8_t spinand_flash_ecc_layout[SPINAND_SPARE_LAYOUT_SIZE];
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static rt_err_t spinand_info_read(struct rt_qspi_device *qspi);
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static rt_err_t spinand_die_select(struct rt_qspi_device *qspi, uint8_t select_die)
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{
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uint8_t au8Cmd[2] = { 0xC2, 0x0 };
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au8Cmd[1] = select_die;
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return nu_qspi_send(qspi, &au8Cmd[0], sizeof(au8Cmd));
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}
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static uint8_t spinand_isbusy(struct rt_qspi_device *qspi)
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{
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#define BUSY_CKECKING_TIMEOUT_MS 3000
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volatile uint8_t SR = 0xFF;
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rt_err_t result;
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uint8_t au8Cmd[2] = { 0x0F, 0xC0 };
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uint32_t u32CheckingDuration = rt_tick_from_millisecond(BUSY_CKECKING_TIMEOUT_MS);
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uint32_t u32Start = rt_tick_get();
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do
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{
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result = nu_qspi_send_then_recv(qspi, &au8Cmd[0], sizeof(au8Cmd), (void *)&SR, 1);
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if (result != RT_EOK)
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goto timeout_spinand_isbusy;
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if ((rt_tick_get() - u32Start) >= u32CheckingDuration)
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{
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goto timeout_spinand_isbusy;
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}
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}
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while ((SR & 0x1) != 0x00);
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return 0;
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timeout_spinand_isbusy:
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LOG_E("Error: spinand timeout.");
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return 1;
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}
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static rt_err_t spinand_program_dataload(
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struct rt_qspi_device *qspi,
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uint8_t u8AddrH,
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uint8_t u8AddrL,
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uint8_t *pu8DataBuff,
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uint32_t u32DataCount,
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uint8_t *pu8SpareBuff,
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uint32_t u32SpareCount)
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{
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uint8_t u8WECmd = 0x06;
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rt_err_t result = RT_EOK;
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struct rt_qspi_message qspi_messages[2] = {0};
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/* 1-bit mode */
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qspi_messages[0].instruction.content = 0x32;
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qspi_messages[0].instruction.qspi_lines = 1;
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qspi_messages[0].address.content = (u8AddrH << 8) | (u8AddrL);
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qspi_messages[0].address.size = 2 * 8;
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qspi_messages[0].address.qspi_lines = 1;
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/* 4-bit mode */
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qspi_messages[0].qspi_data_lines = 4;
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qspi_messages[0].parent.cs_take = 1;
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qspi_messages[0].parent.cs_release = 0;
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qspi_messages[0].parent.send_buf = pu8DataBuff;
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qspi_messages[0].parent.length = u32DataCount;
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qspi_messages[0].parent.next = &qspi_messages[1].parent;
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qspi_messages[1].qspi_data_lines = 4;
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qspi_messages[1].parent.cs_take = 0;
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qspi_messages[1].parent.cs_release = 1;
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qspi_messages[1].parent.send_buf = pu8SpareBuff;
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qspi_messages[1].parent.length = u32SpareCount;
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if ((result = nu_qspi_send(qspi, &u8WECmd, sizeof(u8WECmd))) != RT_EOK)
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goto exit_spinand_program_dataload;
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result = nu_qspi_transfer_message(qspi, (struct rt_qspi_message *)&qspi_messages[0]);
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exit_spinand_program_dataload:
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return result;
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}
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static uint8_t spinand_status_register_read(struct rt_qspi_device *qspi, uint8_t u8SRSel)
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{
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uint8_t u8SR = 0;
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uint8_t au8Cmd[2];
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switch (u8SRSel)
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{
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case 0x01:
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au8Cmd[0] = 0x05;
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au8Cmd[1] = 0xA0;
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break;
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case 0x02:
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au8Cmd[0] = 0x0F;
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au8Cmd[1] = 0xB0;
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break;
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case 0x03:
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au8Cmd[0] = 0x05;
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au8Cmd[1] = 0xC0;
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break;
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default:
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RT_ASSERT(0);
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break;
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}
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if (nu_qspi_send_then_recv(qspi, &au8Cmd[0], sizeof(au8Cmd), &u8SR, 1) != RT_EOK)
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RT_ASSERT(0);
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return u8SR;
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}
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static rt_err_t spinand_status_register_write(struct rt_qspi_device *qspi, uint8_t u8SRSel, uint8_t u8Value)
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{
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rt_err_t result = RT_EOK;
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uint8_t au8Cmd[3];
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switch (u8SRSel)
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{
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case 0x01:
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au8Cmd[0] = 0x01;
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au8Cmd[1] = 0xA0;
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break;
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case 0x02:
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au8Cmd[0] = 0x01;
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au8Cmd[1] = 0xB0;
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break;
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case 0x03:
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au8Cmd[0] = 0x01;
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au8Cmd[1] = 0xC0;
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break;
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default:
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result = RT_EINVAL;
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goto exit_spinand_status_register_write;
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}
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au8Cmd[2] = u8Value;
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if ((result = nu_qspi_send(qspi, &au8Cmd[0], sizeof(au8Cmd))) != RT_EOK)
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goto exit_spinand_status_register_write;
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if (spinand_isbusy(qspi))
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{
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result = RT_EIO;
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goto exit_spinand_status_register_write;
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}
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exit_spinand_status_register_write:
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return result;
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}
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static rt_err_t spinand_program_execute(struct rt_qspi_device *qspi, uint8_t u8Addr2, uint8_t u8Addr1, uint8_t u8Addr0)
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{
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rt_err_t result;
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uint8_t au8Cmd[4], u8SR;
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au8Cmd[0] = 0x10 ;
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au8Cmd[1] = u8Addr2;
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au8Cmd[2] = u8Addr1;
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au8Cmd[3] = u8Addr0;
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if ((result = nu_qspi_send(qspi, &au8Cmd, sizeof(au8Cmd))) != RT_EOK)
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goto exit_spinand_program_execute;
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if (spinand_isbusy(qspi))
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{
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result = -RT_MTD_EIO;
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goto exit_spinand_program_execute;
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}
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u8SR = (spinand_status_register_read(SPINAND_FLASH_QSPI, 3) & 0x0C) >> 2;
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if (u8SR == 1)
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{
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result = -RT_MTD_EIO;
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LOG_E("Error write status!");
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}
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exit_spinand_program_execute:
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return result;
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}
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static rt_err_t spinand_normal_read(struct rt_qspi_device *qspi, uint8_t u8AddrH, uint8_t u8AddrL, uint8_t *pu8Buff, uint32_t u32Count)
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{
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uint8_t au8Cmd[4];
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au8Cmd[0] = 0x03;
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au8Cmd[1] = u8AddrH;
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au8Cmd[2] = u8AddrL;
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au8Cmd[3] = 0x00;
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return nu_qspi_send_then_recv(qspi, &au8Cmd[0], sizeof(au8Cmd), pu8Buff, u32Count);
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}
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static rt_err_t spinand_protect_set(struct rt_qspi_device *qspi, uint8_t u8Protect)
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{
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/* Read status register 1 */
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uint8_t u8SR = spinand_status_register_read(qspi, 1);
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if (u8Protect)
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{
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/* protect */
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u8SR |= 0x7C;
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}
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else
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{
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/* unprotect */
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u8SR &= 0x83;
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}
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return spinand_status_register_write(qspi, 1, u8SR);
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}
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static uint8_t spinand_program_erase_isfail(struct rt_qspi_device *qspi)
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{
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/* Read status register 3 */
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uint8_t u8SR = spinand_status_register_read(qspi, 3);
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return (u8SR & 0x0C) >> 2; /* Check P-Fail, E-Fail bit */
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}
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static uint8_t spinand_hwecc_status_get(struct rt_qspi_device *qspi)
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{
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/* Read status register 3 */
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uint8_t u8SR = spinand_status_register_read(qspi, 3);
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return (u8SR & 0x30) >> 4; /* ECC-1, ECC0 bit */
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}
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static rt_err_t spinand_hwecc_set(struct rt_qspi_device *qspi, uint8_t u8Enable)
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{
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uint8_t u8SR = spinand_status_register_read(qspi, 2); // Read status register 2
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if (u8Enable)
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{
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u8SR |= 0x10; // Enable ECC-E bit
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}
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else
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{
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u8SR &= 0xEF; // Disable ECC-E bit
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}
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|
|
|
return spinand_status_register_write(qspi, 2, u8SR);
|
|
}
|
|
|
|
static uint8_t spinand_hwecc_get(struct rt_qspi_device *qspi)
|
|
{
|
|
/* Read status register 2 */
|
|
uint8_t u8SR = spinand_status_register_read(qspi, 2);
|
|
return (u8SR & 0x10) >> 4;
|
|
}
|
|
|
|
static rt_err_t spinand_read_dataload(struct rt_qspi_device *qspi, uint8_t u8Addr2, uint8_t u8Addr1, uint8_t u8Addr0)
|
|
{
|
|
rt_err_t result = RT_EOK;
|
|
uint8_t au8Cmd[4];
|
|
uint8_t u8SR;
|
|
|
|
au8Cmd[0] = 0x13 ;
|
|
au8Cmd[1] = u8Addr2;
|
|
au8Cmd[2] = u8Addr1;
|
|
au8Cmd[3] = u8Addr0;
|
|
|
|
if ((result = nu_qspi_send(qspi, &au8Cmd[0], sizeof(au8Cmd))) != RT_EOK)
|
|
goto exit_spinand_read_dataload;
|
|
|
|
if (spinand_isbusy(qspi))
|
|
{
|
|
result = -RT_EIO;
|
|
goto exit_spinand_read_dataload;
|
|
}
|
|
|
|
u8SR = spinand_hwecc_status_get(SPINAND_FLASH_QSPI);
|
|
if ((u8SR != 0x00) && (u8SR != 0x01))
|
|
{
|
|
result = -RT_MTD_EECC;
|
|
LOG_E("Error ECC status error[0x%x].", u8SR);
|
|
}
|
|
|
|
exit_spinand_read_dataload:
|
|
|
|
return result;
|
|
}
|
|
|
|
static uint8_t spinand_block_isbad(struct rt_qspi_device *qspi, uint32_t u32PageAddr)
|
|
{
|
|
rt_err_t result;
|
|
uint8_t read_buf;
|
|
|
|
again_spinand_block_isbad:
|
|
|
|
result = spinand_read_dataload(qspi, (u32PageAddr >> 16) & 0xFF, (u32PageAddr >> 8) & 0xFF, u32PageAddr & 0xFF); // Read the first page of a block
|
|
RT_ASSERT(result == RT_EOK);
|
|
|
|
result = spinand_normal_read(qspi, (SPINAND_FLASH_PAGE_SIZE >> 8) & 0xff, SPINAND_FLASH_PAGE_SIZE & 0xff, &read_buf, 1); // Read bad block mark at 0x800 update at v.1.0.8
|
|
RT_ASSERT(result == RT_EOK);
|
|
|
|
if (read_buf != 0xFF)
|
|
{
|
|
// update at v.1.0.7
|
|
return 1;
|
|
}
|
|
|
|
if (((u32PageAddr % (SPINAND_FLASH_PAGE_PER_BLOCK_NUM * SPINAND_FLASH_PAGE_SIZE)) == 0))
|
|
{
|
|
/* Need check second page again. */
|
|
u32PageAddr++;
|
|
goto again_spinand_block_isbad;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static rt_err_t spinand_buffermode_set(struct rt_qspi_device *qspi, uint8_t u8Enable)
|
|
{
|
|
uint8_t u8SR = spinand_status_register_read(qspi, 2); // Read status register 2
|
|
|
|
if (u8Enable)
|
|
{
|
|
u8SR |= 0x08; // Enable BUF bit
|
|
}
|
|
else
|
|
{
|
|
u8SR &= 0xF7; // Disable BUF bit
|
|
}
|
|
return spinand_status_register_write(qspi, 2, u8SR);
|
|
}
|
|
|
|
static rt_err_t spinand_block_erase(struct rt_qspi_device *qspi, uint8_t u8Addr2, uint8_t u8Addr1, uint8_t u8Addr0)
|
|
{
|
|
rt_err_t result;
|
|
uint8_t u8WECmd = 0x06;
|
|
uint8_t au8EraseCmd[4], u8SR;
|
|
|
|
au8EraseCmd[0] = 0xD8;
|
|
au8EraseCmd[1] = u8Addr2;
|
|
au8EraseCmd[2] = u8Addr1;
|
|
au8EraseCmd[3] = u8Addr0;
|
|
|
|
if ((result = nu_qspi_send(qspi, &u8WECmd, sizeof(u8WECmd))) != RT_EOK)
|
|
goto exit_spinand_block_erase;
|
|
|
|
if ((result = nu_qspi_send(qspi, &au8EraseCmd[0], sizeof(au8EraseCmd))) != RT_EOK)
|
|
goto exit_spinand_block_erase;
|
|
|
|
if (spinand_isbusy(qspi))
|
|
return -RT_EIO;
|
|
|
|
u8SR = spinand_program_erase_isfail(SPINAND_FLASH_QSPI);
|
|
if (u8SR != 0)
|
|
{
|
|
/* Fail to erase */
|
|
LOG_E("Fail to erase. Will mark it bad.");
|
|
result = -RT_ERROR;
|
|
goto exit_spinand_block_erase;
|
|
}
|
|
|
|
exit_spinand_block_erase:
|
|
|
|
return result;
|
|
}
|
|
|
|
static rt_err_t spinand_block_markbad(struct rt_qspi_device *qspi, uint32_t u32PageAddr)
|
|
{
|
|
rt_err_t result = RT_EOK;
|
|
|
|
uint8_t u8BadBlockMarker = 0xF0;
|
|
|
|
result = spinand_block_erase(qspi, (u32PageAddr >> 16) & 0xFF, (u32PageAddr >> 8) & 0xFF, u32PageAddr & 0xFF);
|
|
if (result != RT_EOK)
|
|
return result;
|
|
|
|
result = spinand_program_dataload(qspi, (SPINAND_FLASH_PAGE_SIZE >> 8) & 0xff, SPINAND_FLASH_PAGE_SIZE & 0xff, &u8BadBlockMarker, 1, 0, 0);
|
|
if (result != RT_EOK)
|
|
return result;
|
|
|
|
return spinand_program_execute(qspi, (u32PageAddr >> 16) & 0xFF, (u32PageAddr >> 8) & 0xFF, u32PageAddr & 0xFF);
|
|
}
|
|
|
|
static rt_err_t spinand_read_quadoutput(
|
|
struct rt_qspi_device *qspi,
|
|
uint8_t u8AddrH,
|
|
uint8_t u8AddrL,
|
|
uint8_t *pu8DataBuff,
|
|
uint32_t u32DataCount
|
|
)
|
|
{
|
|
struct rt_qspi_message qspi_messages = {0};
|
|
|
|
/* 1-bit mode */
|
|
qspi_messages.instruction.content = SPINAND_FLASH_QUADREAD_CMDID;
|
|
qspi_messages.instruction.qspi_lines = 1;
|
|
|
|
qspi_messages.address.content = (u8AddrH << 8) | (u8AddrL);
|
|
qspi_messages.address.size = 2 * 8;
|
|
qspi_messages.address.qspi_lines = 1;
|
|
|
|
qspi_messages.dummy_cycles = SPINAND_FLASH_DUMMYBYTE * 8; //In bit
|
|
|
|
/* 4-bit mode */
|
|
qspi_messages.qspi_data_lines = 4;
|
|
qspi_messages.parent.cs_take = 1;
|
|
qspi_messages.parent.cs_release = 1;
|
|
qspi_messages.parent.recv_buf = pu8DataBuff;
|
|
qspi_messages.parent.length = u32DataCount;
|
|
qspi_messages.parent.next = RT_NULL;
|
|
|
|
return nu_qspi_transfer_message(qspi, (struct rt_qspi_message *) &qspi_messages);
|
|
}
|
|
|
|
static rt_err_t spinand_jedecid_get(struct rt_qspi_device *qspi, uint32_t *pu32ID)
|
|
{
|
|
uint32_t u32JedecId = 0;
|
|
uint32_t u32JedecId_real = 0;
|
|
uint8_t u8Cmd = 0x9F;
|
|
|
|
if (nu_qspi_send_then_recv(qspi, &u8Cmd, 1, &u32JedecId, 4) != RT_EOK)
|
|
{
|
|
return -RT_ERROR;
|
|
}
|
|
|
|
/* Reverse order. */
|
|
nu_set32_be((uint8_t *)&u32JedecId_real, u32JedecId);
|
|
|
|
/* Only keep 3-bytes. */
|
|
u32JedecId_real &= 0x00ffffff;
|
|
|
|
*pu32ID = u32JedecId_real;
|
|
|
|
return RT_EOK;
|
|
}
|
|
|
|
static rt_err_t spinand_reset(struct rt_qspi_device *qspi)
|
|
{
|
|
rt_err_t result;
|
|
uint8_t u8Cmd = 0xFF;
|
|
|
|
if ((result = nu_qspi_send(qspi, &u8Cmd, 1)) != RT_EOK)
|
|
goto exit_spinand_reset;
|
|
|
|
if (spinand_isbusy(qspi))
|
|
{
|
|
result = RT_EIO;
|
|
goto exit_spinand_reset;
|
|
}
|
|
|
|
exit_spinand_reset:
|
|
|
|
return result;
|
|
}
|
|
|
|
rt_err_t spinand_flash_init(struct rt_qspi_device *qspi)
|
|
{
|
|
rt_err_t result;
|
|
|
|
if ((result = spinand_reset(qspi)) != RT_EOK)
|
|
goto exit_spinand_init;
|
|
|
|
if ((result = spinand_info_read(qspi)) != RT_EOK)
|
|
goto exit_spinand_init;
|
|
|
|
/* Un-protect */
|
|
if ((result = spinand_protect_set(qspi, 0)) != RT_EOK)
|
|
goto exit_spinand_init;
|
|
|
|
/* Enable BUF mode */
|
|
if ((result = spinand_buffermode_set(qspi, 1)) != RT_EOK)
|
|
goto exit_spinand_init;
|
|
|
|
/* Enable HWECC */
|
|
if ((result = spinand_hwecc_set(qspi, 1)) != RT_EOK)
|
|
goto exit_spinand_init;
|
|
|
|
/* Check HWECC */
|
|
if (!(spinand_hwecc_get(qspi)))
|
|
goto exit_spinand_init;
|
|
|
|
if (SPINAND_FLASH_MCP == 1)
|
|
{
|
|
/* Select die. */
|
|
if ((result = spinand_die_select(qspi, SPINAND_DIE_ID1)) != RT_EOK)
|
|
goto exit_spinand_init;
|
|
|
|
/* Unprotect */
|
|
if ((result = spinand_protect_set(qspi, 0)) != RT_EOK)
|
|
goto exit_spinand_init;
|
|
}
|
|
|
|
LOG_I("Enabled BUF, HWECC. Unprotected.");
|
|
|
|
exit_spinand_init:
|
|
|
|
return -result;
|
|
}
|
|
|
|
struct spinand_ops spinand_ops_wb =
|
|
{
|
|
.block_erase = spinand_block_erase,
|
|
.block_isbad = spinand_block_isbad,
|
|
.block_markbad = spinand_block_markbad,
|
|
.die_select = spinand_die_select,
|
|
.jedecid_get = spinand_jedecid_get,
|
|
.program_dataload = spinand_program_dataload,
|
|
.program_execute = spinand_program_execute,
|
|
.read_dataload = spinand_read_dataload,
|
|
.read_quadoutput = spinand_read_quadoutput
|
|
};
|
|
|
|
static rt_err_t spinand_info_read(struct rt_qspi_device *qspi)
|
|
{
|
|
int i;
|
|
uint32_t u32JedecId = 0;
|
|
|
|
if (spinand_jedecid_get(qspi, &u32JedecId) != RT_EOK)
|
|
goto exit_spinand_info_read;
|
|
|
|
for (i = 0 ; i < SPINAND_LIST_ELEMENT_NUM; i++)
|
|
{
|
|
if (u32JedecId == g_spinandflash_list[i].u32JEDECID) /* Match JEDECID? */
|
|
{
|
|
rt_memcpy((void *)&spinand_flash_data_layout[0], (void *)&g_spinandflash_list[i].au8DataLayout[0], SPINAND_SPARE_LAYOUT_SIZE);
|
|
rt_memcpy((void *)&spinand_flash_ecc_layout[0], (void *)&g_spinandflash_list[i].au8EccLayout[0], SPINAND_SPARE_LAYOUT_SIZE);
|
|
|
|
rt_memcpy(SPINAND_FLASH_INFO, &g_spinandflash_list[i], sizeof(struct nu_spinand_info));
|
|
LOG_I("Found: [%08X] %s.", u32JedecId, SPINAND_FLASH_DESCRIPTION);
|
|
|
|
switch (u32JedecId & 0xff0000)
|
|
{
|
|
case 0xEF0000: /* Winbond */
|
|
SPINAND_FLASH_OPS = &spinand_ops_wb;
|
|
break;
|
|
|
|
default:
|
|
goto exit_spinand_info_read;
|
|
}
|
|
|
|
return RT_EOK;
|
|
}
|
|
}
|
|
|
|
exit_spinand_info_read:
|
|
|
|
LOG_E("Can't find the flash[%08X] in supported list.", u32JedecId);
|
|
return -RT_ERROR;
|
|
}
|
|
|
|
#endif
|