622 lines
17 KiB
C
622 lines
17 KiB
C
/**************************************************************************//**
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*
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* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-01-28 klcheng First version
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*
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******************************************************************************/
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#include <rtconfig.h>
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#if defined(BSP_USING_UUART)
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#include <rtdevice.h>
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#include <rthw.h>
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#include "NuMicro.h"
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#if defined(RT_SERIAL_USING_DMA)
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#include <drv_pdma.h>
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#endif
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/* Private define ---------------------------------------------------------------*/
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enum
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{
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UUART_START = -1,
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#if defined(BSP_USING_UUART0)
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UUART0_IDX,
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#endif
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#if defined(BSP_USING_UUART1)
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UUART1_IDX,
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#endif
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UUART_CNT
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};
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/* Private typedef --------------------------------------------------------------*/
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struct nu_uuart
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{
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rt_serial_t dev;
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char *name;
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UUART_T *uuart_base;
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uint32_t uuart_rst;
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IRQn_Type uuart_irq_n;
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#if defined(RT_SERIAL_USING_DMA)
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uint32_t dma_flag;
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int16_t pdma_perp_tx;
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int8_t pdma_chanid_tx;
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int16_t pdma_perp_rx;
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int8_t pdma_chanid_rx;
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int32_t rx_write_offset;
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int32_t rxdma_trigger_len;
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#endif
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};
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typedef struct nu_uuart *nu_uuart_t;
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/* Private functions ------------------------------------------------------------*/
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static rt_err_t nu_uuart_configure(struct rt_serial_device *serial, struct serial_configure *cfg);
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static rt_err_t nu_uuart_control(struct rt_serial_device *serial, int cmd, void *arg);
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static int nu_uuart_send(struct rt_serial_device *serial, char c);
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static int nu_uuart_receive(struct rt_serial_device *serial);
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static void nu_uuart_isr(nu_uuart_t serial);
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#if defined(RT_SERIAL_USING_DMA)
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static rt_size_t nu_uuart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction);
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static void nu_pdma_uuart_rx_cb(void *pvOwner, uint32_t u32Events);
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static void nu_pdma_uuart_tx_cb(void *pvOwner, uint32_t u32Events);
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#endif
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/* Public functions ------------------------------------------------------------*/
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/* Private variables ------------------------------------------------------------*/
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static const struct rt_uart_ops nu_uuart_ops =
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{
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.configure = nu_uuart_configure,
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.control = nu_uuart_control,
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.putc = nu_uuart_send,
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.getc = nu_uuart_receive,
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#if defined(RT_SERIAL_USING_DMA)
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.dma_transmit = nu_uuart_dma_transmit
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#else
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.dma_transmit = RT_NULL
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#endif
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};
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static const struct serial_configure nu_uuart_default_config =
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RT_SERIAL_CONFIG_DEFAULT;
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static struct nu_uuart nu_uuart_arr [] =
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{
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#if defined(BSP_USING_UUART0)
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{
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.name = "uuart0",
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.uuart_base = UUART0,
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.uuart_rst = USCI0_RST,
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.uuart_irq_n = USCI01_IRQn,
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#if defined(RT_SERIAL_USING_DMA)
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#if defined(BSP_USING_UUART0_TX_DMA)
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.pdma_perp_tx = PDMA_USCI0_TX,
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#else
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.pdma_perp_tx = NU_PDMA_UNUSED,
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#endif
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#if defined(BSP_USING_UUART0_RX_DMA)
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.pdma_perp_rx = PDMA_USCI0_RX,
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.rx_write_offset = 0,
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#else
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.pdma_perp_rx = NU_PDMA_UNUSED,
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#endif
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#endif
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},
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#endif
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#if defined(BSP_USING_UUART1)
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{
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.name = "uuart1",
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.uuart_base = UUART1,
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.uuart_rst = USCI1_RST,
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.uuart_irq_n = USCI01_IRQn,
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#if defined(RT_SERIAL_USING_DMA)
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#if defined(BSP_USING_UUART1_TX_DMA)
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.pdma_perp_tx = PDMA_USCI1_TX,
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#else
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.pdma_perp_tx = NU_PDMA_UNUSED,
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#endif
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#if defined(BSP_USING_UUART1_RX_DMA)
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.pdma_perp_rx = PDMA_USCI1_RX,
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.rx_write_offset = 0,
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#else
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.pdma_perp_rx = NU_PDMA_UNUSED,
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#endif
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#endif
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},
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#endif
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{0}
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}; /* uuart nu_uuart */
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/* Interrupt Handle Function ----------------------------------------------------*/
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#if defined(BSP_USING_UUART0) || defined(BSP_USING_UUART1)
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/* USCI0 interrupt entry */
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void USCI01_IRQHandler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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#if defined(BSP_USING_UUART0)
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nu_uuart_isr(&nu_uuart_arr[UUART0_IDX]);
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#endif
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#if defined(BSP_USING_UUART1)
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nu_uuart_isr(&nu_uuart_arr[UUART1_IDX]);
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#endif
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/* leave interrupt */
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rt_interrupt_leave();
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}
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#endif
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/**
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* All UUART interrupt service routine
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*/
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static void nu_uuart_isr(nu_uuart_t serial)
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{
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/* Get base address of uuart register */
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UUART_T *uuart_base = ((nu_uuart_t)serial)->uuart_base;
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/* Get interrupt event */
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uint32_t u32IntSts = uuart_base->PROTSTS;
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uint32_t u32FIFOSts = uuart_base->BUFSTS;
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if (u32IntSts & (UUART_PROTSTS_PARITYERR_Msk | UUART_PROTSTS_FRMERR_Msk | UUART_PROTSTS_BREAK_Msk))
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{
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uuart_base->PROTSTS |= (UUART_PROTSTS_PARITYERR_Msk | UUART_PROTSTS_FRMERR_Msk | UUART_PROTSTS_BREAK_Msk);
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return;
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}
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/* Handle RX event */
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if (u32IntSts & UUART_PROTSTS_RXENDIF_Msk)
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{
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rt_hw_serial_isr(&serial->dev, RT_SERIAL_EVENT_RX_IND);
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}
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uuart_base->PROTSTS = u32IntSts;
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uuart_base->BUFSTS = u32FIFOSts;
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}
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/**
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* Configure uuart port
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*/
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static rt_err_t nu_uuart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
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{
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rt_err_t ret = RT_EOK;
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uint32_t uuart_word_len = 0;
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uint32_t uuart_stop_bit = 0;
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uint32_t uuart_parity = 0;
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/* Get base address of uuart register */
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UUART_T *uuart_base = ((nu_uuart_t)serial)->uuart_base;
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/* Check baud rate */
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RT_ASSERT(cfg->baud_rate != 0);
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/* Check word len */
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switch (cfg->data_bits)
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{
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case DATA_BITS_5:
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rt_kprintf("Unsupported data length");
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goto exit_nu_uuart_configure;
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case DATA_BITS_6:
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uuart_word_len = UUART_WORD_LEN_6;
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break;
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case DATA_BITS_7:
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uuart_word_len = UUART_WORD_LEN_7;
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break;
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case DATA_BITS_8:
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uuart_word_len = UUART_WORD_LEN_8;
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break;
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default:
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rt_kprintf("Unsupported data length");
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ret = RT_EINVAL;
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goto exit_nu_uuart_configure;
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}
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/* Check stop bit */
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switch (cfg->stop_bits)
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{
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case STOP_BITS_1:
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uuart_stop_bit = UUART_STOP_BIT_1;
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break;
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case STOP_BITS_2:
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uuart_stop_bit = UUART_STOP_BIT_2;
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break;
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default:
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rt_kprintf("Unsupported stop bit");
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ret = RT_EINVAL;
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goto exit_nu_uuart_configure;
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}
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/* Check parity */
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switch (cfg->parity)
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{
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case PARITY_NONE:
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uuart_parity = UUART_PARITY_NONE;
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break;
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case PARITY_ODD:
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uuart_parity = UUART_PARITY_ODD;
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break;
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case PARITY_EVEN:
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uuart_parity = UUART_PARITY_EVEN;
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break;
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default:
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rt_kprintf("Unsupported parity");
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ret = RT_EINVAL;
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goto exit_nu_uuart_configure;
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}
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/* Reset this module */
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SYS_ResetModule(((nu_uuart_t)serial)->uuart_rst);
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/* Open UUart and set UUART baud rate */
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UUART_Open(uuart_base, cfg->baud_rate);
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/* Set line configuration. */
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UUART_SetLine_Config(uuart_base, 0, uuart_word_len, uuart_parity, uuart_stop_bit);
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/* Enable NVIC interrupt. */
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NVIC_EnableIRQ(((nu_uuart_t)serial)->uuart_irq_n);
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exit_nu_uuart_configure:
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if (ret != RT_EOK)
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UUART_Close(uuart_base);
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return -(ret);
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}
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#if defined(RT_SERIAL_USING_DMA)
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static rt_err_t nu_pdma_uuart_rx_config(struct rt_serial_device *serial, uint8_t *pu8Buf, int32_t i32TriggerLen)
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{
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rt_err_t result = RT_EOK;
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/* Get base address of uuart register */
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UUART_T *uuart_base = ((nu_uuart_t)serial)->uuart_base;
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result = nu_pdma_callback_register(((nu_uuart_t)serial)->pdma_chanid_rx,
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nu_pdma_uuart_rx_cb,
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(void *)serial,
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NU_PDMA_EVENT_TRANSFER_DONE | NU_PDMA_EVENT_TIMEOUT);
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if (result != RT_EOK)
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{
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goto exit_nu_pdma_uuart_rx_config;
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}
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result = nu_pdma_transfer(((nu_uuart_t)serial)->pdma_chanid_rx,
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8,
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(uint32_t)&uuart_base->RXDAT,
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(uint32_t)pu8Buf,
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i32TriggerLen,
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1000); //Idle-timeout, 1ms
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if (result != RT_EOK)
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{
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goto exit_nu_pdma_uuart_rx_config;
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}
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//UUART PDMA reset
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UUART_PDMA_ENABLE(uuart_base, UUART_PDMACTL_PDMARST_Msk);
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/* Enable Receive Line interrupt & Start DMA RX transfer. */
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UUART_EnableInt(uuart_base, UUART_RLS_INT_MASK);
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UUART_PDMA_ENABLE(uuart_base, UUART_PDMACTL_RXPDMAEN_Msk | UUART_PDMACTL_PDMAEN_Msk);
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exit_nu_pdma_uuart_rx_config:
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return result;
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}
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static void nu_pdma_uuart_rx_cb(void *pvOwner, uint32_t u32Events)
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{
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rt_size_t recv_len = 0;
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rt_size_t transferred_rxbyte = 0;
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struct rt_serial_device *serial = (struct rt_serial_device *)pvOwner;
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nu_uuart_t puuart = (nu_uuart_t)serial;
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RT_ASSERT(serial != RT_NULL);
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/* Get base address of uuart register */
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UUART_T *uuart_base = puuart->uuart_base;
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transferred_rxbyte = nu_pdma_transferred_byte_get(puuart->pdma_chanid_rx, puuart->rxdma_trigger_len);
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if (u32Events & (NU_PDMA_EVENT_TRANSFER_DONE | NU_PDMA_EVENT_TIMEOUT))
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{
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if (u32Events & NU_PDMA_EVENT_TRANSFER_DONE)
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{
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if (serial->config.bufsz != 0)
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{
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struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
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nu_pdma_uuart_rx_config(serial, &rx_fifo->buffer[0], puuart->rxdma_trigger_len); // Config & trigger next
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}
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transferred_rxbyte = puuart->rxdma_trigger_len;
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}
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else if ((u32Events & NU_PDMA_EVENT_TIMEOUT) && !UUART_GET_RX_EMPTY(uuart_base))
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{
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return;
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}
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recv_len = transferred_rxbyte - puuart->rx_write_offset;
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puuart->rx_write_offset = transferred_rxbyte % puuart->rxdma_trigger_len;
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}
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if ((serial->config.bufsz == 0) && (u32Events & NU_PDMA_EVENT_TRANSFER_DONE))
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{
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recv_len = puuart->rxdma_trigger_len;
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}
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if (recv_len)
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{
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rt_hw_serial_isr(&puuart->dev, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
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}
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}
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static rt_err_t nu_pdma_uuart_tx_config(struct rt_serial_device *serial)
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{
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rt_err_t result = RT_EOK;
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RT_ASSERT(serial != RT_NULL);
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result = nu_pdma_callback_register(((nu_uuart_t)serial)->pdma_chanid_tx,
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nu_pdma_uuart_tx_cb,
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(void *)serial,
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NU_PDMA_EVENT_TRANSFER_DONE);
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return result;
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}
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static void nu_pdma_uuart_tx_cb(void *pvOwner, uint32_t u32Events)
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{
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nu_uuart_t puuart = (nu_uuart_t)pvOwner;
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RT_ASSERT(puuart != RT_NULL);
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// Stop DMA TX transfer
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UUART_PDMA_DISABLE(puuart->uuart_base, UUART_PDMACTL_TXPDMAEN_Msk);
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if (u32Events & NU_PDMA_EVENT_TRANSFER_DONE)
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{
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rt_hw_serial_isr(&puuart->dev, RT_SERIAL_EVENT_TX_DMADONE);
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}
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}
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/**
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* UUart DMA transfer
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*/
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static rt_size_t nu_uuart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
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{
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rt_err_t result = RT_EOK;
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RT_ASSERT(serial != RT_NULL);
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RT_ASSERT(buf != RT_NULL);
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/* Get base address of uuart register */
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UUART_T *uuart_base = ((nu_uuart_t)serial)->uuart_base;
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if (direction == RT_SERIAL_DMA_TX)
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{
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result = nu_pdma_transfer(((nu_uuart_t)serial)->pdma_chanid_tx,
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8,
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(uint32_t)buf,
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(uint32_t)&uuart_base->TXDAT,
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size,
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0); // wait-forever
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// Start DMA TX transfer
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UUART_PDMA_ENABLE(uuart_base, UUART_PDMACTL_TXPDMAEN_Msk | UUART_PDMACTL_PDMAEN_Msk);
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}
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else if (direction == RT_SERIAL_DMA_RX)
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{
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// If config.bufsz = 0, serial will trigger once.
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((nu_uuart_t)serial)->rxdma_trigger_len = size;
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((nu_uuart_t)serial)->rx_write_offset = 0;
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result = nu_pdma_uuart_rx_config(serial, buf, size);
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}
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else
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{
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result = RT_ERROR;
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}
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return result;
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}
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static int nu_hw_uuart_dma_allocate(nu_uuart_t puuart)
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{
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RT_ASSERT(puuart != RT_NULL);
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/* Allocate UUART_TX nu_dma channel */
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if (puuart->pdma_perp_tx != NU_PDMA_UNUSED)
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{
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puuart->pdma_chanid_tx = nu_pdma_channel_allocate(puuart->pdma_perp_tx);
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if (puuart->pdma_chanid_tx >= 0)
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{
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puuart->dma_flag |= RT_DEVICE_FLAG_DMA_TX;
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}
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}
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/* Allocate UUART_RX nu_dma channel */
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if (puuart->pdma_perp_rx != NU_PDMA_UNUSED)
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{
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puuart->pdma_chanid_rx = nu_pdma_channel_allocate(puuart->pdma_perp_rx);
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if (puuart->pdma_chanid_rx >= 0)
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{
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puuart->dma_flag |= RT_DEVICE_FLAG_DMA_RX;
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}
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}
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return RT_EOK;
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}
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#endif
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/**
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* UUart interrupt control
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*/
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static rt_err_t nu_uuart_control(struct rt_serial_device *serial, int cmd, void *arg)
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{
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rt_err_t result = RT_EOK;
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rt_uint32_t flag = 0;
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rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
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RT_ASSERT(serial != RT_NULL);
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/* Get base address of uuart register */
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UUART_T *uuart_base = ((nu_uuart_t)serial)->uuart_base;
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switch (cmd)
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{
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case RT_DEVICE_CTRL_CLR_INT:
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if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) /* Disable INT-RX */
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{
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flag = UUART_RXEND_INT_MASK;
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UUART_DisableInt(uuart_base, flag);
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}
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else if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) /* Disable DMA-RX */
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{
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/* Disable Receive Line interrupt & Stop DMA RX transfer. */
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flag = UUART_RLS_INT_MASK;
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nu_pdma_channel_terminate(((nu_uuart_t)serial)->pdma_chanid_rx);
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UUART_PDMA_DISABLE(uuart_base, UUART_PDMACTL_RXPDMAEN_Msk);
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UUART_DisableInt(uuart_base, flag);
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}
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break;
|
|
|
|
case RT_DEVICE_CTRL_SET_INT:
|
|
if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) /* Enable INT-RX */
|
|
{
|
|
flag = UUART_RXEND_INT_MASK;
|
|
UUART_EnableInt(uuart_base, flag);
|
|
}
|
|
break;
|
|
|
|
#if defined(RT_SERIAL_USING_DMA)
|
|
case RT_DEVICE_CTRL_CONFIG:
|
|
if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) /* Configure and trigger DMA-RX */
|
|
{
|
|
struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
|
|
((nu_uuart_t)serial)->rxdma_trigger_len = serial->config.bufsz;
|
|
((nu_uuart_t)serial)->rx_write_offset = 0;
|
|
result = nu_pdma_uuart_rx_config(serial, &rx_fifo->buffer[0], ((nu_uuart_t)serial)->rxdma_trigger_len); // Config & trigger
|
|
}
|
|
else if (ctrl_arg == RT_DEVICE_FLAG_DMA_TX) /* Configure DMA-TX */
|
|
{
|
|
result = nu_pdma_uuart_tx_config(serial);
|
|
}
|
|
break;
|
|
#endif
|
|
|
|
case RT_DEVICE_CTRL_CLOSE:
|
|
/* Disable NVIC interrupt. */
|
|
NVIC_DisableIRQ(((nu_uuart_t)serial)->uuart_irq_n);
|
|
|
|
#if defined(RT_SERIAL_USING_DMA)
|
|
nu_pdma_channel_terminate(((nu_uuart_t)serial)->pdma_chanid_tx);
|
|
nu_pdma_channel_terminate(((nu_uuart_t)serial)->pdma_chanid_rx);
|
|
#endif
|
|
|
|
/* Reset this module */
|
|
SYS_ResetModule(((nu_uuart_t)serial)->uuart_rst);
|
|
|
|
/* Close UUART port */
|
|
UUART_Close(uuart_base);
|
|
|
|
break;
|
|
default:
|
|
result = -RT_EINVAL;
|
|
break;
|
|
}
|
|
return result;
|
|
}
|
|
|
|
/**
|
|
* UUart put char
|
|
*/
|
|
static int nu_uuart_send(struct rt_serial_device *serial, char c)
|
|
{
|
|
RT_ASSERT(serial != RT_NULL);
|
|
|
|
/* Get base address of uuart register */
|
|
UUART_T *uuart_base = ((nu_uuart_t)serial)->uuart_base;
|
|
|
|
/* Waiting if TX-FIFO is full. */
|
|
while (UUART_IS_TX_FULL(uuart_base)) {};
|
|
|
|
/* Put char into TX-FIFO */
|
|
UUART_WRITE(uuart_base, c);
|
|
|
|
return 1;
|
|
}
|
|
|
|
/**
|
|
* UUart get char
|
|
*/
|
|
static int nu_uuart_receive(struct rt_serial_device *serial)
|
|
{
|
|
RT_ASSERT(serial != RT_NULL);
|
|
|
|
/* Get base address of uuart register */
|
|
UUART_T *uuart_base = ((nu_uuart_t)serial)->uuart_base;
|
|
|
|
/* Return failure if RX-FIFO is empty. */
|
|
if (UUART_GET_RX_EMPTY(uuart_base) != 0)
|
|
{
|
|
return -1;
|
|
}
|
|
|
|
/* Get char from RX-FIFO */
|
|
return UUART_READ(uuart_base);
|
|
}
|
|
|
|
/**
|
|
* Hardware UUART Initialization
|
|
*/
|
|
static int rt_hw_uuart_init(void)
|
|
{
|
|
int i;
|
|
rt_uint32_t flag;
|
|
rt_err_t ret = RT_EOK;
|
|
|
|
for (i = (UUART_START + 1); i < UUART_CNT; i++)
|
|
{
|
|
flag = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX;
|
|
|
|
nu_uuart_arr[i].dev.ops = &nu_uuart_ops;
|
|
nu_uuart_arr[i].dev.config = nu_uuart_default_config;
|
|
|
|
#if defined(RT_SERIAL_USING_DMA)
|
|
nu_uuart_arr[i].dma_flag = 0;
|
|
nu_hw_uuart_dma_allocate(&nu_uuart_arr[i]);
|
|
flag |= nu_uuart_arr[i].dma_flag;
|
|
#endif
|
|
|
|
ret = rt_hw_serial_register(&nu_uuart_arr[i].dev, nu_uuart_arr[i].name, flag, NULL);
|
|
RT_ASSERT(ret == RT_EOK);
|
|
}
|
|
|
|
return (int)ret;
|
|
}
|
|
|
|
INIT_DEVICE_EXPORT(rt_hw_uuart_init);
|
|
|
|
#endif //#if defined(BSP_USING_UUART)
|