367 lines
9.8 KiB
C
367 lines
9.8 KiB
C
/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-3-08 GuEe-GUI the first version
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include <rtdevice.h>
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#include <board.h>
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/*
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* The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
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* LCR is written whilst busy. If it is, then a busy detect interrupt is
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* raised, the LCR needs to be rewritten and the uart status register read.
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*/
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#define UART_RX 0 /* In: Receive buffer */
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#define UART_TX 0 /* Out: Transmit buffer */
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#define UART_DLL 0 /* Out: Divisor Latch Low */
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#define UART_DLM 1 /* Out: Divisor Latch High */
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#define UART_IER 1 /* Out: Interrupt Enable Register */
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#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
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#define UART_SSR 0x22 /* In: Software Reset Register */
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#define UART_USR 0x1f /* UART Status Register */
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#define UART_LCR 3 /* Out: Line Control Register */
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#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
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#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
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#define UART_LCR_PARITY 0x8 /* Parity Enable */
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#define UART_LCR_STOP 0x4 /* Stop bits: 0=1 bit, 1=2 bits */
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#define UART_LCR_WLEN8 0x3 /* Wordlength: 8 bits */
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#define UART_MCR 4 /* Out: Modem Control Register */
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#define UART_MCR_RTS 0x02 /* RTS complement */
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#define UART_LSR 5 /* In: Line Status Register */
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#define UART_LSR_BI 0x10 /* Break interrupt indicator */
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#define UART_LSR_DR 0x01 /* Receiver data ready */
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#define UART_IIR 2 /* In: Interrupt ID Register */
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#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
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#define UART_IIR_BUSY 0x07 /* DesignWare APB Busy Detect */
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#define UART_IIR_RX_TIMEOUT 0x0c /* OMAP RX Timeout interrupt */
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#define UART_FCR 2 /* Out: FIFO Control Register */
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#define UART_FCR_EN_FIFO 0x01 /* Enable the FIFO */
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#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
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#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
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#define UART_REG_SHIFT 0x2 /* Register Shift*/
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#define UART_INPUT_CLK 24000000
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struct hw_uart_device
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{
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rt_ubase_t hw_base;
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rt_uint32_t irqno;
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#ifdef RT_USING_SMP
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struct rt_spinlock spinlock;
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#endif
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};
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#define BSP_DEFINE_UART_DEVICE(no) \
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static struct hw_uart_device _uart##no##_device = \
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{ \
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UART##no##_MMIO_BASE, \
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UART##no##_IRQ \
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}; \
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static struct rt_serial_device _serial##no;
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#ifdef RT_USING_UART0
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BSP_DEFINE_UART_DEVICE(0);
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#endif
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#ifdef RT_USING_UART1
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BSP_DEFINE_UART_DEVICE(1);
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#endif
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#ifdef RT_USING_UART2
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BSP_DEFINE_UART_DEVICE(2);
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#endif
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#ifdef RT_USING_UART3
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BSP_DEFINE_UART_DEVICE(3);
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#endif
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#ifdef RT_USING_UART4
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BSP_DEFINE_UART_DEVICE(4);
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#endif
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#ifdef RT_USING_UART5
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BSP_DEFINE_UART_DEVICE(5);
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#endif
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#ifdef RT_USING_UART6
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BSP_DEFINE_UART_DEVICE(6);
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#endif
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#ifdef RT_USING_UART7
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BSP_DEFINE_UART_DEVICE(7);
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#endif
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#ifdef RT_USING_UART8
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BSP_DEFINE_UART_DEVICE(8);
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#endif
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#ifdef RT_USING_UART9
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BSP_DEFINE_UART_DEVICE(9);
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#endif
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rt_inline rt_uint32_t dw8250_read32(rt_ubase_t addr, rt_ubase_t offset)
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{
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return *((volatile rt_uint32_t *)(addr + (offset << UART_REG_SHIFT)));
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}
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rt_inline void dw8250_write32(rt_ubase_t addr, rt_ubase_t offset, rt_uint32_t value)
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{
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*((volatile rt_uint32_t *)(addr + (offset << UART_REG_SHIFT))) = value;
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if (offset == UART_LCR)
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{
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int tries = 1000;
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/* Make sure LCR write wasn't ignored */
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while (tries--)
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{
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unsigned int lcr = dw8250_read32(addr, UART_LCR);
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if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
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{
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return;
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}
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dw8250_write32(addr, UART_FCR, UART_FCR_EN_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
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dw8250_read32(addr, UART_RX);
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*((volatile rt_uint32_t *)(addr + (offset << UART_REG_SHIFT))) = value;
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}
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}
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}
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static rt_err_t dw8250_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
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{
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rt_base_t base, rate;
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struct hw_uart_device *uart;
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RT_ASSERT(serial != RT_NULL);
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uart = (struct hw_uart_device *)serial->parent.user_data;
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base = uart->hw_base;
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#ifdef RT_USING_SMP
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rt_spin_lock_init(&uart->spinlock);
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#endif
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/* Resset UART */
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dw8250_write32(base, UART_SSR, 1);
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dw8250_write32(base, UART_SSR, 0);
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dw8250_write32(base, UART_IER, !UART_IER_RDI);
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dw8250_write32(base, UART_FCR, UART_FCR_EN_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
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/* Disable flow ctrl */
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dw8250_write32(base, UART_MCR, 0);
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/* Clear RTS */
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dw8250_write32(base, UART_MCR, dw8250_read32(base, UART_MCR) | UART_MCR_RTS);
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rate = UART_INPUT_CLK / 16 / serial->config.baud_rate;
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/* Enable access DLL & DLH */
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dw8250_write32(base, UART_LCR, dw8250_read32(base, UART_LCR) | UART_LCR_DLAB);
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dw8250_write32(base, UART_DLL, (rate & 0xff));
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dw8250_write32(base, UART_DLM, (rate & 0xff00) >> 8);
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/* Clear DLAB bit */
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dw8250_write32(base, UART_LCR, dw8250_read32(base, UART_LCR) & (~UART_LCR_DLAB));
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dw8250_write32(base, UART_LCR, (dw8250_read32(base, UART_LCR) & (~UART_LCR_WLEN8)) | UART_LCR_WLEN8);
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dw8250_write32(base, UART_LCR, dw8250_read32(base, UART_LCR) & (~UART_LCR_STOP));
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dw8250_write32(base, UART_LCR, dw8250_read32(base, UART_LCR) & (~UART_LCR_PARITY));
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dw8250_write32(base, UART_IER, UART_IER_RDI);
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return RT_EOK;
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}
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static rt_err_t dw8250_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
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{
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struct hw_uart_device *uart;
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RT_ASSERT(serial != RT_NULL);
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uart = (struct hw_uart_device *)serial->parent.user_data;
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switch (cmd)
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{
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case RT_DEVICE_CTRL_CLR_INT:
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/* Disable rx irq */
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dw8250_write32(uart->hw_base, UART_IER, !UART_IER_RDI);
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rt_hw_interrupt_mask(uart->irqno);
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break;
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case RT_DEVICE_CTRL_SET_INT:
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/* Enable rx irq */
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dw8250_write32(uart->hw_base, UART_IER, UART_IER_RDI);
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rt_hw_interrupt_umask(uart->irqno);
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break;
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}
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return RT_EOK;
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}
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static int dw8250_uart_putc(struct rt_serial_device *serial, char c)
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{
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rt_base_t base;
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struct hw_uart_device *uart;
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RT_ASSERT(serial != RT_NULL);
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uart = (struct hw_uart_device *)serial->parent.user_data;
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base = uart->hw_base;
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while ((dw8250_read32(base, UART_USR) & 0x2) == 0)
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{
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}
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dw8250_write32(base, UART_TX, c);
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return 1;
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}
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static int dw8250_uart_getc(struct rt_serial_device *serial)
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{
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int ch = -1;
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rt_base_t base;
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struct hw_uart_device *uart;
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RT_ASSERT(serial != RT_NULL);
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uart = (struct hw_uart_device *)serial->parent.user_data;
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base = uart->hw_base;
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if ((dw8250_read32(base, UART_LSR) & 0x1))
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{
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ch = dw8250_read32(base, UART_RX) & 0xff;
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}
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return ch;
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}
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static const struct rt_uart_ops _uart_ops =
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{
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dw8250_uart_configure,
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dw8250_uart_control,
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dw8250_uart_putc,
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dw8250_uart_getc,
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};
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static void rt_hw_uart_isr(int irqno, void *param)
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{
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unsigned int iir, status;
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struct rt_serial_device *serial = (struct rt_serial_device *)param;
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struct hw_uart_device *uart = (struct hw_uart_device *)serial->parent.user_data;
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iir = dw8250_read32(uart->hw_base, UART_IIR);
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/* If don't do this in non-DMA mode then the "RX TIMEOUT" interrupt will fire forever. */
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if ((iir & 0x3f) == UART_IIR_RX_TIMEOUT)
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{
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#ifdef RT_USING_SMP
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rt_base_t level = rt_spin_lock_irqsave(&uart->spinlock);
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#endif
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status = dw8250_read32(uart->hw_base, UART_LSR);
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if (!(status & (UART_LSR_DR | UART_LSR_BI)))
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{
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dw8250_read32(uart->hw_base, UART_RX);
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}
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#ifdef RT_USING_SMP
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rt_spin_unlock_irqrestore(&uart->spinlock, level);
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#endif
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}
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if (!(iir & UART_IIR_NO_INT))
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{
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rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
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}
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if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY)
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{
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/* Clear the USR */
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dw8250_read32(uart->hw_base, UART_USR);
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return;
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}
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}
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int rt_hw_uart_init(void)
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{
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rt_uint32_t value;
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struct hw_uart_device* uart;
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struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
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RT_UNUSED(value);
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config.baud_rate = 1500000;
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#define BSP_INSTALL_UART_DEVICE(no) \
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uart = &_uart##no##_device; \
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_serial##no.ops = &_uart_ops; \
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_serial##no.config = config; \
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rt_hw_serial_register(&_serial##no, "uart" #no, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); \
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rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial##no, "uart" #no);
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#ifdef RT_USING_UART0
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BSP_INSTALL_UART_DEVICE(0);
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#endif
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#ifdef RT_USING_UART1
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BSP_INSTALL_UART_DEVICE(1);
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#endif
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#ifdef RT_USING_UART2
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BSP_INSTALL_UART_DEVICE(2);
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#endif
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#ifdef RT_USING_UART3
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BSP_INSTALL_UART_DEVICE(3);
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#endif
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#ifdef RT_USING_UART4
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HWREG32(CRU_BASE + 0x370) = 0xFFFF0000 | (0x600) |(HWREG32(CRU_BASE + 0x370) & 0xF0FF);
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value = HWREG32(0xFDC60000 + 0x48);
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value &= ~((7 << 8) | (7 << 4));
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value |= 0xFFFF0000 | (4 << 8) | (4 << 4);
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HWREG32(0xFDC60000 + 0x48) = value;
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HWREG32(0xFDC60000 + 0x30C) = 0xFFFF0000 | (1 << 14) | HWREG32(0xFDC60000 + 0x30C);
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BSP_INSTALL_UART_DEVICE(4);
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#endif
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#ifdef RT_USING_UART5
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BSP_INSTALL_UART_DEVICE(5);
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#endif
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#ifdef RT_USING_UART6
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BSP_INSTALL_UART_DEVICE(6);
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#endif
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#ifdef RT_USING_UART7
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BSP_INSTALL_UART_DEVICE(7);
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#endif
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#ifdef RT_USING_UART8
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BSP_INSTALL_UART_DEVICE(8);
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#endif
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#ifdef RT_USING_UART9
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BSP_INSTALL_UART_DEVICE(9);
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#endif
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return 0;
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}
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