395 lines
13 KiB
C
395 lines
13 KiB
C
/*
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_adc.h"
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.adc_12b1msps_sar"
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#endif
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Get instance number for ADC module.
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*
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* @param base ADC peripheral base address
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*/
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static uint32_t ADC_GetInstance(ADC_Type *base);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*! @brief Pointers to ADC bases for each instance. */
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static ADC_Type *const s_adcBases[] = ADC_BASE_PTRS;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/*! @brief Pointers to ADC clocks for each instance. */
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static const clock_ip_name_t s_adcClocks[] = ADC_CLOCKS;
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/*******************************************************************************
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* Code
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******************************************************************************/
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static uint32_t ADC_GetInstance(ADC_Type *base)
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{
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uint32_t instance;
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < ARRAY_SIZE(s_adcBases); instance++)
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{
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if (s_adcBases[instance] == base)
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{
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break;
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}
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}
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assert(instance < ARRAY_SIZE(s_adcBases));
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return instance;
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}
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/*!
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* brief Initialize the ADC module.
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*
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* param base ADC peripheral base address.
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* param config Pointer to "adc_config_t" structure.
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*/
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void ADC_Init(ADC_Type *base, const adc_config_t *config)
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{
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assert(NULL != config);
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uint32_t tmp32;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Enable the clock. */
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CLOCK_EnableClock(s_adcClocks[ADC_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* ADCx_CFG */
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tmp32 = base->CFG & (ADC_CFG_AVGS_MASK | ADC_CFG_ADTRG_MASK); /* Reserve AVGS and ADTRG bits. */
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tmp32 |= ADC_CFG_REFSEL(config->referenceVoltageSource) | ADC_CFG_ADSTS(config->samplePeriodMode) |
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ADC_CFG_ADICLK(config->clockSource) | ADC_CFG_ADIV(config->clockDriver) | ADC_CFG_MODE(config->resolution);
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if (config->enableOverWrite)
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{
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tmp32 |= ADC_CFG_OVWREN_MASK;
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}
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if (config->enableLongSample)
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{
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tmp32 |= ADC_CFG_ADLSMP_MASK;
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}
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if (config->enableLowPower)
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{
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tmp32 |= ADC_CFG_ADLPC_MASK;
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}
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if (config->enableHighSpeed)
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{
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tmp32 |= ADC_CFG_ADHSC_MASK;
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}
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base->CFG = tmp32;
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/* ADCx_GC */
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tmp32 = base->GC & ~(ADC_GC_ADCO_MASK | ADC_GC_ADACKEN_MASK);
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if (config->enableContinuousConversion)
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{
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tmp32 |= ADC_GC_ADCO_MASK;
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}
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if (config->enableAsynchronousClockOutput)
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{
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tmp32 |= ADC_GC_ADACKEN_MASK;
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}
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base->GC = tmp32;
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}
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/*!
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* brief De-initializes the ADC module.
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*
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* param base ADC peripheral base address.
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*/
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void ADC_Deinit(ADC_Type *base)
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{
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Disable the clock. */
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CLOCK_DisableClock(s_adcClocks[ADC_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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/*!
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* brief Gets an available pre-defined settings for the converter's configuration.
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*
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* This function initializes the converter configuration structure with available settings. The default values are:
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* code
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* config->enableAsynchronousClockOutput = true;
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* config->enableOverWrite = false;
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* config->enableContinuousConversion = false;
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* config->enableHighSpeed = false;
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* config->enableLowPower = false;
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* config->enableLongSample = false;
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* config->referenceVoltageSource = kADC_ReferenceVoltageSourceAlt0;
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* config->samplePeriodMode = kADC_SamplePeriod2or12Clocks;
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* config->clockSource = kADC_ClockSourceAD;
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* config->clockDriver = kADC_ClockDriver1;
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* config->resolution = kADC_Resolution12Bit;
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* endcode
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* param base ADC peripheral base address.
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* param config Pointer to the configuration structure.
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*/
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void ADC_GetDefaultConfig(adc_config_t *config)
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{
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assert(NULL != config);
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/* Initializes the configure structure to zero. */
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memset(config, 0, sizeof(*config));
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config->enableAsynchronousClockOutput = true;
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config->enableOverWrite = false;
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config->enableContinuousConversion = false;
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config->enableHighSpeed = false;
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config->enableLowPower = false;
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config->enableLongSample = false;
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config->referenceVoltageSource = kADC_ReferenceVoltageSourceAlt0;
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config->samplePeriodMode = kADC_SamplePeriod2or12Clocks;
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config->clockSource = kADC_ClockSourceAD;
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config->clockDriver = kADC_ClockDriver1;
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config->resolution = kADC_Resolution12Bit;
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}
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/*!
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* brief Configures the conversion channel.
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*
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* This operation triggers the conversion when in software trigger mode. When in hardware trigger mode, this API
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* configures the channel while the external trigger source helps to trigger the conversion.
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*
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* Note that the "Channel Group" has a detailed description.
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* To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC has more than one
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* group of status and control registers, one for each conversion. The channel group parameter indicates which group of
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* registers are used, for example channel group 0 is for Group A registers and channel group 1 is for Group B
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* registers. The
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* channel groups are used in a "ping-pong" approach to control the ADC operation. At any point, only one of
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* the channel groups is actively controlling ADC conversions. The channel group 0 is used for both software and
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* hardware
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* trigger modes. Channel groups 1 and greater indicate potentially multiple channel group registers for
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* use only in hardware trigger mode. See the chip configuration information in the appropriate MCU reference manual
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* about the
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* number of SC1n registers (channel groups) specific to this device. None of the channel groups 1 or greater are used
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* for software trigger operation. Therefore, writing to these channel groups does not initiate a new conversion.
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* Updating the channel group 0 while a different channel group is actively controlling a conversion is allowed and
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* vice versa. Writing any of the channel group registers while that specific channel group is actively controlling a
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* conversion aborts the current conversion.
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*
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* param base ADC peripheral base address.
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* param channelGroup Channel group index.
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* param config Pointer to the "adc_channel_config_t" structure for the conversion channel.
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*/
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void ADC_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc_channel_config_t *config)
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{
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assert(NULL != config);
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assert(channelGroup < ADC_HC_COUNT);
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uint32_t tmp32;
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tmp32 = ADC_HC_ADCH(config->channelNumber);
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if (config->enableInterruptOnConversionCompleted)
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{
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tmp32 |= ADC_HC_AIEN_MASK;
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}
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base->HC[channelGroup] = tmp32;
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}
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/*
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*To complete calibration, the user must follow the below procedure:
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* 1. Configure ADC_CFG with actual operating values for maximum accuracy.
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* 2. Configure the ADC_GC values along with CAL bit.
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* 3. Check the status of CALF bit in ADC_GS and the CAL bit in ADC_GC.
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* 4. When CAL bit becomes '0' then check the CALF status and COCO[0] bit status.
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*/
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/*!
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* brief Automates the hardware calibration.
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*
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* This auto calibration helps to adjust the plus/minus side gain automatically.
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* Execute the calibration before using the converter. Note that the software trigger should be used
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* during calibration.
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*
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* param base ADC peripheral base address.
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*
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* return Execution status.
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* retval kStatus_Success Calibration is done successfully.
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* retval kStatus_Fail Calibration has failed.
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*/
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status_t ADC_DoAutoCalibration(ADC_Type *base)
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{
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status_t status = kStatus_Success;
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#if !(defined(FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) && FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE)
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bool bHWTrigger = false;
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/* The calibration would be failed when in hardwar mode.
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* Remember the hardware trigger state here and restore it later if the hardware trigger is enabled.*/
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if (0U != (ADC_CFG_ADTRG_MASK & base->CFG))
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{
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bHWTrigger = true;
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ADC_EnableHardwareTrigger(base, false);
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}
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#endif
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/* Clear the CALF and launch the calibration. */
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base->GS = ADC_GS_CALF_MASK; /* Clear the CALF. */
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base->GC |= ADC_GC_CAL_MASK; /* Launch the calibration. */
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/* Check the status of CALF bit in ADC_GS and the CAL bit in ADC_GC. */
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while (0U != (base->GC & ADC_GC_CAL_MASK))
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{
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/* Check the CALF when the calibration is active. */
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if (0U != (ADC_GetStatusFlags(base) & kADC_CalibrationFailedFlag))
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{
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status = kStatus_Fail;
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break;
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}
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}
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/* When CAL bit becomes '0' then check the CALF status and COCO[0] bit status. */
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if (0U == ADC_GetChannelStatusFlags(base, 0U)) /* Check the COCO[0] bit status. */
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{
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status = kStatus_Fail;
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}
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if (0U != (ADC_GetStatusFlags(base) & kADC_CalibrationFailedFlag)) /* Check the CALF status. */
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{
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status = kStatus_Fail;
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}
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/* Clear conversion done flag. */
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ADC_GetChannelConversionValue(base, 0U);
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#if !(defined(FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) && FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE)
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/* Restore original trigger mode. */
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if (true == bHWTrigger)
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{
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ADC_EnableHardwareTrigger(base, true);
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}
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#endif
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return status;
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}
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/*!
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* brief Set user defined offset.
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*
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* param base ADC peripheral base address.
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* param config Pointer to "adc_offest_config_t" structure.
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*/
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void ADC_SetOffsetConfig(ADC_Type *base, const adc_offest_config_t *config)
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{
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assert(NULL != config);
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uint32_t tmp32;
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tmp32 = ADC_OFS_OFS(config->offsetValue);
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if (config->enableSigned)
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{
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tmp32 |= ADC_OFS_SIGN_MASK;
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}
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base->OFS = tmp32;
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}
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/*!
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* brief Configures the hardware compare mode.
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*
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* The hardware compare mode provides a way to process the conversion result automatically by using hardware. Only the
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* result
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* in the compare range is available. To compare the range, see "adc_hardware_compare_mode_t" or the appopriate
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* reference
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* manual for more information.
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*
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* param base ADC peripheral base address.
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* param Pointer to "adc_hardware_compare_config_t" structure.
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*
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*/
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void ADC_SetHardwareCompareConfig(ADC_Type *base, const adc_hardware_compare_config_t *config)
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{
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uint32_t tmp32;
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tmp32 = base->GC & ~(ADC_GC_ACFE_MASK | ADC_GC_ACFGT_MASK | ADC_GC_ACREN_MASK);
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if (NULL == config) /* Pass "NULL" to disable the feature. */
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{
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base->GC = tmp32;
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return;
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}
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/* Enable the feature. */
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tmp32 |= ADC_GC_ACFE_MASK;
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/* Select the hardware compare working mode. */
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switch (config->hardwareCompareMode)
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{
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case kADC_HardwareCompareMode0:
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break;
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case kADC_HardwareCompareMode1:
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tmp32 |= ADC_GC_ACFGT_MASK;
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break;
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case kADC_HardwareCompareMode2:
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tmp32 |= ADC_GC_ACREN_MASK;
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break;
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case kADC_HardwareCompareMode3:
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tmp32 |= ADC_GC_ACFGT_MASK | ADC_GC_ACREN_MASK;
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break;
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default:
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break;
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}
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base->GC = tmp32;
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/* Load the compare values. */
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tmp32 = ADC_CV_CV1(config->value1) | ADC_CV_CV2(config->value2);
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base->CV = tmp32;
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}
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/*!
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* brief Configures the hardware average mode.
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*
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* The hardware average mode provides a way to process the conversion result automatically by using hardware. The
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* multiple
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* conversion results are accumulated and averaged internally making them easier to read.
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*
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* param base ADC peripheral base address.
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* param mode Setting the hardware average mode. See "adc_hardware_average_mode_t".
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*/
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void ADC_SetHardwareAverageConfig(ADC_Type *base, adc_hardware_average_mode_t mode)
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{
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uint32_t tmp32;
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if (mode == kADC_HardwareAverageDiasable)
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{
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base->GC &= ~ADC_GC_AVGE_MASK;
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}
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else
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{
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tmp32 = base->CFG & ~ADC_CFG_AVGS_MASK;
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tmp32 |= ADC_CFG_AVGS(mode);
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base->CFG = tmp32;
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base->GC |= ADC_GC_AVGE_MASK; /* Enable the hardware compare. */
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}
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}
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/*!
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* brief Clears the converter's status falgs.
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*
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* param base ADC peripheral base address.
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* param mask Mask value for the cleared flags. See "adc_status_flags_t".
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*/
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void ADC_ClearStatusFlags(ADC_Type *base, uint32_t mask)
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{
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uint32_t tmp32 = 0;
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if (0U != (mask & kADC_CalibrationFailedFlag))
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{
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tmp32 |= ADC_GS_CALF_MASK;
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}
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if (0U != (mask & kADC_ConversionActiveFlag))
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{
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tmp32 |= ADC_GS_ADACT_MASK;
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}
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base->GS = tmp32;
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}
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