282 lines
8.2 KiB
C
282 lines
8.2 KiB
C
/******************************************************************************************************************************************
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* 文件名称: system_SWM320.c
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* 功能说明: SWM320单片机的时钟设置
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* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1
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* 注意事项:
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* 版本日期: V1.1.0 2017年10月25日
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* 升级记录:
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*
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*
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*******************************************************************************************************************************************
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* @attention
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
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* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
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* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
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* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
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* -ECTION WITH THEIR PRODUCTS.
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*
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* COPYRIGHT 2012 Synwit Technology
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*******************************************************************************************************************************************/
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#include <stdint.h>
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#include "SWM320.h"
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/******************************************************************************************************************************************
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* 系统时钟设定
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*****************************************************************************************************************************************/
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#define SYS_CLK_20MHz 0 //0 内部高频20MHz RC振荡器
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#define SYS_CLK_40MHz 1 //1 内部高频40MHz RC振荡器
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#define SYS_CLK_32KHz 2 //2 内部低频32KHz RC振荡器
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#define SYS_CLK_XTAL 3 //3 外部晶体振荡器（2-30MHz）
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#define SYS_CLK_PLL 4 //4 片内锁相环输出
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#define SYS_CLK SYS_CLK_PLL
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#define SYS_CLK_DIV_1 0
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#define SYS_CLK_DIV_2 1
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#define SYS_CLK_DIV SYS_CLK_DIV_1
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#define __HSI (20000000UL) //高速内部时钟
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#define __LSI (32000UL) //低速内部时钟
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#define __HSE (20000000UL) //高速外部时钟
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/********************************** PLL 设定 **********************************************
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* VCO输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV
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* PLL输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV / OUTDIV = VCO输出频率 / OUTDIV
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* 注意：VCO输出频率需要在 [600MHz, 1200MHz] 之间
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*****************************************************************************************/
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#define SYS_PLL_SRC SYS_CLK_20MHz //可取值SYS_CLK_20MHz、SYS_CLK_XTAL
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#define PLL_IN_DIV 5
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#define PLL_FB_DIV 60
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#define PLL_OUT_DIV8 0
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#define PLL_OUT_DIV4 1
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#define PLL_OUT_DIV2 2
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#define PLL_OUT_DIV PLL_OUT_DIV8
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uint32_t SystemCoreClock = __HSI; //System Clock Frequency (Core Clock)
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uint32_t CyclesPerUs = (__HSI / 1000000); //Cycles per micro second
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/******************************************************************************************************************************************
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* 函数名称:
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* 功能说明: This function is used to update the variable SystemCoreClock and must be called whenever the core clock is changed
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* 输 入:
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* 输 出:
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* 注意事项:
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******************************************************************************************************************************************/
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void SystemCoreClockUpdate(void)
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{
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if (SYS->CLKSEL & SYS_CLKSEL_SYS_Msk) //SYS_CLK <= HFCK
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{
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if (SYS->CLKSEL & SYS_CLKSEL_HFCK_Msk) //HFCK <= XTAL
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{
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SystemCoreClock = __HSE;
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}
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else //HFCK <= HRC
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{
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if (SYS->HRCCR & SYS_HRCCR_DBL_Msk) //HRC = 40MHz
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{
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SystemCoreClock = __HSI * 2;
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}
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else //HRC = 20MHz
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{
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SystemCoreClock = __HSI;
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}
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}
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}
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else //SYS_CLK <= LFCK
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{
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if (SYS->CLKSEL & SYS_CLKSEL_LFCK_Msk) //LFCK <= PLL
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{
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if (SYS->PLLCR & SYS_PLLCR_INSEL_Msk) //PLL_SRC <= HRC
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{
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SystemCoreClock = __HSI;
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}
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else //PLL_SRC <= XTAL
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{
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SystemCoreClock = __HSE;
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}
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SystemCoreClock = SystemCoreClock / PLL_IN_DIV * PLL_FB_DIV * 4 / (2 << (2 - PLL_OUT_DIV));
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}
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else //LFCK <= LRC
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{
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SystemCoreClock = __LSI;
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}
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}
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if (SYS->CLKDIV & SYS_CLKDIV_SYS_Msk)
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SystemCoreClock /= 2;
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CyclesPerUs = SystemCoreClock / 1000000;
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}
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/******************************************************************************************************************************************
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* 函数名称:
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* 功能说明: The necessary initializaiton of systerm
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* 输 入:
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* 输 出:
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* 注意事项:
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******************************************************************************************************************************************/
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void SystemInit(void)
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{
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SYS->CLKEN |= (1 << SYS_CLKEN_ANAC_Pos);
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Flash_Param_at_xMHz(120);
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switch (SYS_CLK)
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{
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case SYS_CLK_20MHz: //0 内部高频20MHz RC振荡器
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switchCLK_20MHz();
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break;
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case SYS_CLK_40MHz: //1 内部高频40MHz RC振荡器
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switchCLK_40MHz();
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break;
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case SYS_CLK_32KHz: //2 内部低频32KHz RC振荡器
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switchCLK_32KHz();
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break;
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case SYS_CLK_XTAL: //3 外部晶体振荡器（2-30MHz）
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switchCLK_XTAL();
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break;
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case SYS_CLK_PLL: //4 片内锁相环输出
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switchCLK_PLL();
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break;
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}
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SYS->CLKDIV &= ~SYS_CLKDIV_SYS_Msk;
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SYS->CLKDIV |= (SYS_CLK_DIV << SYS_CLKDIV_SYS_Pos);
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SystemCoreClockUpdate();
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if (SystemCoreClock > 80000000)
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{
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Flash_Param_at_xMHz(120);
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}
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else if (SystemCoreClock > 40000000)
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{
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Flash_Param_at_xMHz(80);
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}
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else if (SystemCoreClock > 30000000)
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{
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Flash_Param_at_xMHz(40);
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}
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else
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{
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Flash_Param_at_xMHz(30);
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}
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}
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static void delay_3ms(void)
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{
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uint32_t i;
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if (((SYS->CLKSEL & SYS_CLKSEL_SYS_Msk) == 0) &&
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((SYS->CLKSEL & SYS_CLKSEL_LFCK_Msk) == 0)) //32KHz
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{
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for (i = 0; i < 20; i++)
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__NOP();
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}
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else
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{
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for (i = 0; i < 20000; i++)
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__NOP();
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}
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}
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void switchCLK_20MHz(void)
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{
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SYS->HRCCR = (0 << SYS_HRCCR_OFF_Pos) |
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(0 << SYS_HRCCR_DBL_Pos); //HRC = 20MHz
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delay_3ms();
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SYS->CLKSEL &= ~SYS_CLKSEL_HFCK_Msk; //HFCK <= HRC
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SYS->CLKSEL |= (1 << SYS_CLKSEL_SYS_Pos); //SYS_CLK <= HFCK
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}
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void switchCLK_40MHz(void)
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{
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SYS->HRCCR = (0 << SYS_HRCCR_OFF_Pos) |
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(1 << SYS_HRCCR_DBL_Pos); //HRC = 40MHz
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delay_3ms();
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SYS->CLKSEL &= ~SYS_CLKSEL_HFCK_Msk; //HFCK <= HRC
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SYS->CLKSEL |= (1 << SYS_CLKSEL_SYS_Pos); //SYS_CLK <= HFCK
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}
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void switchCLK_32KHz(void)
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{
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SYS->CLKEN |= (1 << SYS_CLKEN_RTCBKP_Pos);
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SYS->LRCCR &= ~(1 << SYS_LRCCR_OFF_Pos);
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delay_3ms();
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SYS->CLKSEL &= ~SYS_CLKSEL_LFCK_Msk; //LFCK <= LRC
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SYS->CLKSEL &= ~SYS_CLKSEL_SYS_Msk; //SYS_CLK <= LFCK
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}
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void switchCLK_XTAL(void)
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{
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SYS->XTALCR = (1 << SYS_XTALCR_EN_Pos);
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delay_3ms();
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delay_3ms();
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SYS->CLKSEL |= (1 << SYS_CLKSEL_HFCK_Pos); //HFCK <= XTAL
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SYS->CLKSEL |= (1 << SYS_CLKSEL_SYS_Pos); //SYS_CLK <= HFCK
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}
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void switchCLK_PLL(void)
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{
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PLLInit();
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SYS->PLLCR |= (1 << SYS_PLLCR_OUTEN_Pos);
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SYS->CLKSEL |= (1 << SYS_CLKSEL_LFCK_Pos); //LFCK <= PLL
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SYS->CLKSEL &= ~SYS_CLKSEL_SYS_Msk; //SYS_CLK <= LFCK
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}
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void PLLInit(void)
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{
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if (SYS_PLL_SRC == SYS_CLK_20MHz)
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{
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SYS->HRCCR = (0 << SYS_HRCCR_OFF_Pos) |
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(0 << SYS_HRCCR_DBL_Pos); //HRC = 20MHz
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delay_3ms();
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SYS->PLLCR |= (1 << SYS_PLLCR_INSEL_Pos); //PLL_SRC <= HRC
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}
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else if (SYS_PLL_SRC == SYS_CLK_XTAL)
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{
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SYS->XTALCR = (1 << SYS_XTALCR_EN_Pos);
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delay_3ms();
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delay_3ms();
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SYS->PLLCR &= ~(1 << SYS_PLLCR_INSEL_Pos); //PLL_SRC <= XTAL
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}
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SYS->PLLDIV &= ~(SYS_PLLDIV_INDIV_Msk |
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SYS_PLLDIV_FBDIV_Msk |
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SYS_PLLDIV_OUTDIV_Msk);
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SYS->PLLDIV |= (PLL_IN_DIV << SYS_PLLDIV_INDIV_Pos) |
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(PLL_FB_DIV << SYS_PLLDIV_FBDIV_Pos) |
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(PLL_OUT_DIV << SYS_PLLDIV_OUTDIV_Pos);
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SYS->PLLCR &= ~(1 << SYS_PLLCR_OFF_Pos);
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while (SYS->PLLLOCK == 0)
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; //等待PLL锁定
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}
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