397 lines
26 KiB
C
397 lines
26 KiB
C
/*!
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\file gd32f3x0_tsi.h
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\brief definitions for the TSI
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\version 2017-06-06, V1.0.0, firmware for GD32F3x0
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\version 2019-06-01, V2.0.0, firmware for GD32F3x0
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*/
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/*
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Copyright (c) 2019, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32F3X0_TSI_H
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#define GD32F3X0_TSI_H
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#include "gd32f3x0.h"
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/* TSI definitions */
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#define TSI TSI_BASE /*!< TSI base address */
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/* registers definitions */
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#define TSI_CTL0 REG32(TSI + 0x00000000U)/*!< TSI control register0 */
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#define TSI_INTEN REG32(TSI + 0x00000004U)/*!< TSI interrupt enable register */
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#define TSI_INTC REG32(TSI + 0x00000008U)/*!< TSI interrupt flag clear register */
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#define TSI_INTF REG32(TSI + 0x0000000CU)/*!< TSI interrupt flag register */
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#define TSI_PHM REG32(TSI + 0x00000010U)/*!< TSI pin hysteresis mode register */
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#define TSI_ASW REG32(TSI + 0x00000018U)/*!< TSI analog switch register */
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#define TSI_SAMPCFG REG32(TSI + 0x00000020U)/*!< TSI sample configuration register */
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#define TSI_CHCFG REG32(TSI + 0x00000028U)/*!< TSI channel configuration register */
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#define TSI_GCTL REG32(TSI + 0x00000030U)/*!< TSI group control register */
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#define TSI_G0CYCN REG32(TSI + 0x00000034U)/*!< TSI group 0 cycle number register */
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#define TSI_G1CYCN REG32(TSI + 0x00000038U)/*!< TSI group 1 cycle number register */
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#define TSI_G2CYCN REG32(TSI + 0x0000003CU)/*!< TSI group 2 cycle number register */
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#define TSI_G3CYCN REG32(TSI + 0x00000040U)/*!< TSI group 3 cycle number register */
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#define TSI_G4CYCN REG32(TSI + 0x00000044U)/*!< TSI group 4 cycle number register */
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#define TSI_G5CYCN REG32(TSI + 0x00000048U)/*!< TSI group 5 cycle number register */
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#define TSI_CTL1 REG32(TSI + 0x00000300U)/*!< TSI control registers1 */
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/* bits definitions */
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/* TSI_CTL0 */
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#define TSI_CTL0_TSIEN BIT(0) /*!< TSI enable */
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#define TSI_CTL0_TSIS BIT(1) /*!< TSI start */
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#define TSI_CTL0_TRGMOD BIT(2) /*!< trigger mode selection */
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#define TSI_CTL0_EGSEL BIT(3) /*!< edge selection */
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#define TSI_CTL0_PINMOD BIT(4) /*!< pin mode */
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#define TSI_CTL0_MCN BITS(5,7) /*!< max cycle number of a sequence */
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#define TSI_CTL0_CTCDIV BITS(12,14) /*!< CTCLK clock division factor */
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#define TSI_CTL0_ECDIV BIT(15) /*!< ECCLK clock division factor */
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#define TSI_CTL0_ECEN BIT(16) /*!< extend charge state enable */
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#define TSI_CTL0_ECDT BITS(17,23) /*!< extend charge State maximum duration time */
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#define TSI_CTL0_CTDT BITS(24,27) /*!< charge transfer state duration time */
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#define TSI_CTL0_CDT BITS(28,31) /*!< charge state duration time */
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/* TSI_INTEN */
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#define TSI_INTEN_CTCFIE BIT(0) /*!< charge transfer complete flag interrupt enable */
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#define TSI_INTEN_MNERRIE BIT(1) /*!< max cycle number error interrupt enable */
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/* TSI_INTC */
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#define TSI_INTC_CCTCF BIT(0) /*!< clear charge transfer complete flag */
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#define TSI_INTC_CMNERR BIT(1) /*!< clear max cycle number error */
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/* TSI_INTF */
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#define TSI_INTF_CTCF BIT(0) /*!< charge transfer complete flag */
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#define TSI_INTF_MNERR BIT(1) /*!< max cycle number error */
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/* TSI_PHM */
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#define TSI_PHM_G0P0 BIT(0) /*!< pin G0P0 Schmitt trigger hysteresis state */
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#define TSI_PHM_G0P1 BIT(1) /*!< pin G0P1 Schmitt trigger hysteresis state */
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#define TSI_PHM_G0P2 BIT(2) /*!< pin G0P2 Schmitt trigger hysteresis state */
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#define TSI_PHM_G0P3 BIT(3) /*!< pin G0P3 Schmitt trigger hysteresis state */
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#define TSI_PHM_G1P0 BIT(4) /*!< pin G1P0 Schmitt trigger hysteresis state */
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#define TSI_PHM_G1P1 BIT(5) /*!< pin G1P1 Schmitt trigger hysteresis state */
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#define TSI_PHM_G1P2 BIT(6) /*!< pin G1P2 Schmitt trigger hysteresis state */
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#define TSI_PHM_G1P3 BIT(7) /*!< pin G1P3 Schmitt trigger hysteresis state */
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#define TSI_PHM_G2P0 BIT(8) /*!< pin G2P0 Schmitt trigger hysteresis state */
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#define TSI_PHM_G2P1 BIT(9) /*!< pin G2P1 Schmitt trigger hysteresis state */
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#define TSI_PHM_G2P2 BIT(10) /*!< pin G2P2 Schmitt trigger hysteresis state */
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#define TSI_PHM_G2P3 BIT(11) /*!< pin G2P3 Schmitt trigger hysteresis state */
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#define TSI_PHM_G3P0 BIT(12) /*!< pin G3P0 Schmitt trigger hysteresis state */
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#define TSI_PHM_G3P1 BIT(13) /*!< pin G3P1 Schmitt trigger hysteresis state */
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#define TSI_PHM_G3P2 BIT(14) /*!< pin G3P2 Schmitt trigger hysteresis state */
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#define TSI_PHM_G3P3 BIT(15) /*!< pin G3P3 Schmitt trigger hysteresis state */
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#define TSI_PHM_G4P0 BIT(16) /*!< pin G4P0 Schmitt trigger hysteresis state */
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#define TSI_PHM_G4P1 BIT(17) /*!< pin G4P1 Schmitt trigger hysteresis state */
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#define TSI_PHM_G4P2 BIT(18) /*!< pin G4P2 Schmitt trigger hysteresis state */
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#define TSI_PHM_G4P3 BIT(19) /*!< pin G4P3 Schmitt trigger hysteresis state */
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#define TSI_PHM_G5P0 BIT(20) /*!< pin G5P0 Schmitt trigger hysteresis state */
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#define TSI_PHM_G5P1 BIT(21) /*!< pin G5P1 Schmitt trigger hysteresis state */
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#define TSI_PHM_G5P2 BIT(22) /*!< pin G5P2 Schmitt trigger hysteresis state */
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#define TSI_PHM_G5P3 BIT(23) /*!< pin G5P3 Schmitt trigger hysteresis state */
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/* TSI_ASW */
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#define TSI_ASW_G0P0 BIT(0) /*!< pin G0P0 analog switch state */
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#define TSI_ASW_G0P1 BIT(1) /*!< pin G0P1 analog switch state */
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#define TSI_ASW_G0P2 BIT(2) /*!< pin G0P2 analog switch state */
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#define TSI_ASW_G0P3 BIT(3) /*!< pin G0P3 analog switch state */
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#define TSI_ASW_G1P0 BIT(4) /*!< pin G1P0 analog switch state */
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#define TSI_ASW_G1P1 BIT(5) /*!< pin G1P1 analog switch state */
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#define TSI_ASW_G1P2 BIT(6) /*!< pin G1P2 analog switch state */
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#define TSI_ASW_G1P3 BIT(7) /*!< pin G1P3 analog switch state */
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#define TSI_ASW_G2P0 BIT(8) /*!< pin G2P0 analog switch state */
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#define TSI_ASW_G2P1 BIT(9) /*!< pin G2P1 analog switch state */
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#define TSI_ASW_G2P2 BIT(10) /*!< pin G2P2 analog switch state */
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#define TSI_ASW_G2P3 BIT(11) /*!< pin G2P3 analog switch state */
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#define TSI_ASW_G3P0 BIT(12) /*!< pin G3P0 analog switch state */
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#define TSI_ASW_G3P1 BIT(13) /*!< pin G3P1 analog switch state */
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#define TSI_ASW_G3P2 BIT(14) /*!< pin G3P2 analog switch state */
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#define TSI_ASW_G3P3 BIT(15) /*!< pin G3P3 analog switch state */
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#define TSI_ASW_G4P0 BIT(16) /*!< pin G4P0 analog switch state */
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#define TSI_ASW_G4P1 BIT(17) /*!< pin G4P1 analog switch state */
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#define TSI_ASW_G4P2 BIT(18) /*!< pin G4P2 analog switch state */
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#define TSI_ASW_G4P3 BIT(19) /*!< pin G4P3 analog switch state */
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#define TSI_ASW_G5P0 BIT(20) /*!< pin G5P0 analog switch state */
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#define TSI_ASW_G5P1 BIT(21) /*!< pin G5P1 analog switch state */
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#define TSI_ASW_G5P2 BIT(22) /*!< pin G5P2 analog switch state */
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#define TSI_ASW_G5P3 BIT(23) /*!< pin G5P3 analog switch state */
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/* TSI_SAMPCFG */
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#define TSI_SAMPCFG_G0P0 BIT(0) /*!< pin G0P0 sample pin mode */
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#define TSI_SAMPCFG_G0P1 BIT(1) /*!< pin G0P1 sample pin mode */
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#define TSI_SAMPCFG_G0P2 BIT(2) /*!< pin G0P2 sample pin mode */
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#define TSI_SAMPCFG_G0P3 BIT(3) /*!< pin G0P3 sample pin mode */
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#define TSI_SAMPCFG_G1P0 BIT(4) /*!< pin G1P0 sample pin mode */
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#define TSI_SAMPCFG_G1P1 BIT(5) /*!< pin G1P1 sample pin mode */
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#define TSI_SAMPCFG_G1P2 BIT(6) /*!< pin G1P2 sample pin mode */
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#define TSI_SAMPCFG_G1P3 BIT(7) /*!< pin G1P3 sample pin mode */
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#define TSI_SAMPCFG_G2P0 BIT(8) /*!< pin G2P0 sample pin mode */
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#define TSI_SAMPCFG_G2P1 BIT(9) /*!< pin G2P1 sample pin mode */
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#define TSI_SAMPCFG_G2P2 BIT(10) /*!< pin G2P2 sample pin mode */
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#define TSI_SAMPCFG_G2P3 BIT(11) /*!< pin G2P3 sample pin mode */
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#define TSI_SAMPCFG_G3P0 BIT(12) /*!< pin G3P0 sample pin mode */
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#define TSI_SAMPCFG_G3P1 BIT(13) /*!< pin G3P1 sample pin mode */
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#define TSI_SAMPCFG_G3P2 BIT(14) /*!< pin G3P2 sample pin mode */
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#define TSI_SAMPCFG_G3P3 BIT(15) /*!< pin G3P3 sample pin mode */
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#define TSI_SAMPCFG_G4P0 BIT(16) /*!< pin G4P0 sample pin mode */
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#define TSI_SAMPCFG_G4P1 BIT(17) /*!< pin G4P1 sample pin mode */
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#define TSI_SAMPCFG_G4P2 BIT(18) /*!< pin G4P2 sample pin mode */
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#define TSI_SAMPCFG_G4P3 BIT(19) /*!< pin G4P3 sample pin mode */
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#define TSI_SAMPCFG_G5P0 BIT(20) /*!< pin G5P0 sample pin mode */
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#define TSI_SAMPCFG_G5P1 BIT(21) /*!< pin G5P1 sample pin mode */
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#define TSI_SAMPCFG_G5P2 BIT(22) /*!< pin G5P2 sample pin mode */
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#define TSI_SAMPCFG_G5P3 BIT(23) /*!< pin G5P3 sample pin mode */
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/* TSI_CHCFG */
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#define TSI_CHCFG_G0P0 BIT(0) /*!< pin G0P0 channel pin mode */
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#define TSI_CHCFG_G0P1 BIT(1) /*!< pin G0P1 channel pin mode */
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#define TSI_CHCFG_G0P2 BIT(2) /*!< pin G0P2 channel pin mode */
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#define TSI_CHCFG_G0P3 BIT(3) /*!< pin G0P3 channel pin mode */
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#define TSI_CHCFG_G1P0 BIT(4) /*!< pin G1P0 channel pin mode */
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#define TSI_CHCFG_G1P1 BIT(5) /*!< pin G1P1 channel pin mode */
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#define TSI_CHCFG_G1P2 BIT(6) /*!< pin G1P2 channel pin mode */
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#define TSI_CHCFG_G1P3 BIT(7) /*!< pin G1P3 channel pin mode */
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#define TSI_CHCFG_G2P0 BIT(8) /*!< pin G2P0 channel pin mode */
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#define TSI_CHCFG_G2P1 BIT(9) /*!< pin G2P1 channel pin mode */
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#define TSI_CHCFG_G2P2 BIT(10) /*!< pin G2P2 channel pin mode */
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#define TSI_CHCFG_G2P3 BIT(11) /*!< pin G2P3 channel pin mode */
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#define TSI_CHCFG_G3P0 BIT(12) /*!< pin G3P0 channel pin mode */
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#define TSI_CHCFG_G3P1 BIT(13) /*!< pin G3P1 channel pin mode */
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#define TSI_CHCFG_G3P2 BIT(14) /*!< pin G3P2 channel pin mode */
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#define TSI_CHCFG_G3P3 BIT(15) /*!< pin G3P3 channel pin mode */
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#define TSI_CHCFG_G4P0 BIT(16) /*!< pin G4P0 channel pin mode */
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#define TSI_CHCFG_G4P1 BIT(17) /*!< pin G4P1 channel pin mode */
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#define TSI_CHCFG_G4P2 BIT(18) /*!< pin G4P2 channel pin mode */
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#define TSI_CHCFG_G4P3 BIT(19) /*!< pin G4P3 channel pin mode */
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#define TSI_CHCFG_G5P0 BIT(20) /*!< pin G5P0 channel pin mode */
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#define TSI_CHCFG_G5P1 BIT(21) /*!< pin G5P1 channel pin mode */
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#define TSI_CHCFG_G5P2 BIT(22) /*!< pin G5P2 channel pin mode */
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#define TSI_CHCFG_G5P3 BIT(23) /*!< pin G5P3 channel pin mode */
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/* TSI_GCTL */
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#define TSI_GCTL_GE0 BIT(0) /*!< group0 enable */
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#define TSI_GCTL_GE1 BIT(1) /*!< group1 enable */
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#define TSI_GCTL_GE2 BIT(2) /*!< group2 enable */
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#define TSI_GCTL_GE3 BIT(3) /*!< group3 enable */
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#define TSI_GCTL_GE4 BIT(4) /*!< group4 enable */
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#define TSI_GCTL_GE5 BIT(5) /*!< group5 enable */
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#define TSI_GCTL_GC0 BIT(16) /*!< group0 complete */
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#define TSI_GCTL_GC1 BIT(17) /*!< group1 complete */
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#define TSI_GCTL_GC2 BIT(18) /*!< group2 complete */
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#define TSI_GCTL_GC3 BIT(19) /*!< group3 complete */
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#define TSI_GCTL_GC4 BIT(20) /*!< group4 complete */
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#define TSI_GCTL_GC5 BIT(21) /*!< group5 complete */
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/* TSI_CTL1 */
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#define TSI_CTL1_CTCDIV BIT(24) /*!< CTCLK clock division factor */
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#define TSI_CTL1_ECDIV BITS(28,29) /*!< ECCLK clock division factor */
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/* constants definitions */
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/* TSI interrupt enable bit */
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#define TSI_INT_CCTCF TSI_INTEN_CTCFIE /*!< charge transfer complete flag interrupt enable */
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#define TSI_INT_MNERR TSI_INTEN_MNERRIE /*!< max cycle number error interrupt enable */
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/* I2C interrupt flags */
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#define TSI_INT_FLAG_CTCF TSI_INTF_CTCF /*!< charge transfer complete flag */
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#define TSI_INT_FLAG_MNERR TSI_INTF_MNERR /*!< max cycle number error */
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/* I2C interrupt clear flags */
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#define TSI_INT_FLAG_CTCF_CLR TSI_INTC_CCTCF /*!< clear charge transfer complete flag */
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#define TSI_INT_FLAG_MNERR_CLR TSI_INTC_CMNERR /*!< clear max cycle number error */
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/* I2C flags */
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#define TSI_FLAG_CTCF TSI_INTF_CTCF /*!< charge transfer complete flag */
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#define TSI_FLAG_MNERR TSI_INTF_MNERR /*!< max cycle number error */
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/* I2C clear flags */
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#define TSI_FLAG_CTCF_CLR TSI_INTC_CCTCF /*!< clear charge transfer complete flag */
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#define TSI_FLAG_MNERR_CLR TSI_INTC_CMNERR /*!< clear max cycle number error */
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/* CTCLK clock division factor */
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#define TSI_CTCDIV_DIV1 ((uint32_t)0x00000000U) /*!< fCTCLK = fHCLK */
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#define TSI_CTCDIV_DIV2 ((uint32_t)0x00000001U) /*!< fCTCLK = fHCLK/2 */
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#define TSI_CTCDIV_DIV4 ((uint32_t)0x00000002U) /*!< fCTCLK = fHCLK/4 */
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#define TSI_CTCDIV_DIV8 ((uint32_t)0x00000003U) /*!< fCTCLK = fHCLK/8 */
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#define TSI_CTCDIV_DIV16 ((uint32_t)0x00000004U) /*!< fCTCLK = fHCLK/16 */
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#define TSI_CTCDIV_DIV32 ((uint32_t)0x00000005U) /*!< fCTCLK = fHCLK/32 */
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#define TSI_CTCDIV_DIV64 ((uint32_t)0x00000006U) /*!< fCTCLK = fHCLK/64 */
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#define TSI_CTCDIV_DIV128 ((uint32_t)0x00000007U) /*!< fCTCLK = fHCLK/128 */
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#define TSI_CTCDIV_DIV256 ((uint32_t)0x00000008U) /*!< fCTCLK = fHCLK/256 */
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#define TSI_CTCDIV_DIV512 ((uint32_t)0x00000009U) /*!< fCTCLK = fHCLK/512 */
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#define TSI_CTCDIV_DIV1024 ((uint32_t)0x0000000AU) /*!< fCTCLK = fHCLK/1024 */
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#define TSI_CTCDIV_DIV2048 ((uint32_t)0x0000000BU) /*!< fCTCLK = fHCLK/2048 */
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#define TSI_CTCDIV_DIV4096 ((uint32_t)0x0000000CU) /*!< fCTCLK = fHCLK/4096 */
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#define TSI_CTCDIV_DIV8192 ((uint32_t)0x0000000DU) /*!< fCTCLK = fHCLK/8192 */
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#define TSI_CTCDIV_DIV16384 ((uint32_t)0x0000000EU) /*!< fCTCLK = fHCLK/16384 */
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#define TSI_CTCDIV_DIV32768 ((uint32_t)0x0000000FU) /*!< fCTCLK = fHCLK/32768 */
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/* charge transfer state duration Time */
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#define CTL_CTDT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24U))
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#define TSI_TRANSFER_1CTCLK CTL_CTDT(0) /*!< the duration time of transfer state is 1 CTCLK */
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#define TSI_TRANSFER_2CTCLK CTL_CTDT(1) /*!< the duration time of transfer state is 2 CTCLK */
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#define TSI_TRANSFER_3CTCLK CTL_CTDT(2) /*!< the duration time of transfer state is 3 CTCLK */
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#define TSI_TRANSFER_4CTCLK CTL_CTDT(3) /*!< the duration time of transfer state is 4 CTCLK */
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#define TSI_TRANSFER_5CTCLK CTL_CTDT(4) /*!< the duration time of transfer state is 5 CTCLK */
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#define TSI_TRANSFER_6CTCLK CTL_CTDT(5) /*!< the duration time of transfer state is 6 CTCLK */
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#define TSI_TRANSFER_7CTCLK CTL_CTDT(6) /*!< the duration time of transfer state is 7 CTCLK */
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#define TSI_TRANSFER_8CTCLK CTL_CTDT(7) /*!< the duration time of transfer state is 8 CTCLK */
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#define TSI_TRANSFER_9CTCLK CTL_CTDT(8) /*!< the duration time of transfer state is 9 CTCLK */
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#define TSI_TRANSFER_10CTCLK CTL_CTDT(9) /*!< the duration time of transfer state is 10 CTCLK */
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#define TSI_TRANSFER_11CTCLK CTL_CTDT(10) /*!< the duration time of transfer state is 11 CTCLK */
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#define TSI_TRANSFER_12CTCLK CTL_CTDT(11) /*!< the duration time of transfer state is 12 CTCLK */
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#define TSI_TRANSFER_13CTCLK CTL_CTDT(12) /*!< the duration time of transfer state is 13 CTCLK */
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#define TSI_TRANSFER_14CTCLK CTL_CTDT(13) /*!< the duration time of transfer state is 14 CTCLK */
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#define TSI_TRANSFER_15CTCLK CTL_CTDT(14) /*!< the duration time of transfer state is 15 CTCLK */
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#define TSI_TRANSFER_16CTCLK CTL_CTDT(15) /*!< the duration time of transfer state is 16 CTCLK */
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/* charge state duration time */
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#define CTL_CDT(regval) (BITS(28,31) & ((uint32_t)(regval) << 28U))
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#define TSI_CHARGE_1CTCLK CTL_CDT(0) /*!< the duration time of charge state is 1 CTCLK */
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#define TSI_CHARGE_2CTCLK CTL_CDT(1) /*!< the duration time of charge state is 2 CTCLK */
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#define TSI_CHARGE_3CTCLK CTL_CDT(2) /*!< the duration time of charge state is 3 CTCLK */
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#define TSI_CHARGE_4CTCLK CTL_CDT(3) /*!< the duration time of charge state is 4 CTCLK */
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#define TSI_CHARGE_5CTCLK CTL_CDT(4) /*!< the duration time of charge state is 5 CTCLK */
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#define TSI_CHARGE_6CTCLK CTL_CDT(5) /*!< the duration time of charge state is 6 CTCLK */
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#define TSI_CHARGE_7CTCLK CTL_CDT(6) /*!< the duration time of charge state is 7 CTCLK */
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#define TSI_CHARGE_8CTCLK CTL_CDT(7) /*!< the duration time of charge state is 8 CTCLK */
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#define TSI_CHARGE_9CTCLK CTL_CDT(8) /*!< the duration time of charge state is 9 CTCLK */
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#define TSI_CHARGE_10CTCLK CTL_CDT(9) /*!< the duration time of charge state is 10 CTCLK */
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#define TSI_CHARGE_11CTCLK CTL_CDT(10) /*!< the duration time of charge state is 11 CTCLK */
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#define TSI_CHARGE_12CTCLK CTL_CDT(11) /*!< the duration time of charge state is 12 CTCLK */
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#define TSI_CHARGE_13CTCLK CTL_CDT(12) /*!< the duration time of charge state is 13 CTCLK */
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#define TSI_CHARGE_14CTCLK CTL_CDT(13) /*!< the duration time of charge state is 14 CTCLK */
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#define TSI_CHARGE_15CTCLK CTL_CDT(14) /*!< the duration time of charge state is 15 CTCLK */
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#define TSI_CHARGE_16CTCLK CTL_CDT(15) /*!< the duration time of charge state is 16 CTCLK */
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/* max cycle number of a sequence */
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#define CTL_MCN(regval) (BITS(5,7) & ((uint32_t)(regval) << 5U))
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#define TSI_MAXNUM255 CTL_MCN(0) /*!< the max cycle number of a sequence is 255 */
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#define TSI_MAXNUM511 CTL_MCN(1) /*!< the max cycle number of a sequence is 511 */
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#define TSI_MAXNUM1023 CTL_MCN(2) /*!< the max cycle number of a sequence is 1023 */
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#define TSI_MAXNUM2047 CTL_MCN(3) /*!< the max cycle number of a sequence is 2047 */
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#define TSI_MAXNUM4095 CTL_MCN(4) /*!< the max cycle number of a sequence is 4095 */
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#define TSI_MAXNUM8191 CTL_MCN(5) /*!< the max cycle number of a sequence is 8191 */
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#define TSI_MAXNUM16383 CTL_MCN(6) /*!< the max cycle number of a sequence is 16383 */
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/* ECCLK clock division factor */
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#define TSI_EXTEND_DIV1 ((uint32_t)0x00000000U) /*!< fECCLK = fHCLK */
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#define TSI_EXTEND_DIV2 ((uint32_t)0x00000001U) /*!< fECCLK = fHCLK/2 */
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#define TSI_EXTEND_DIV3 ((uint32_t)0x00000002U) /*!< fECCLK = fHCLK/3 */
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#define TSI_EXTEND_DIV4 ((uint32_t)0x00000003U) /*!< fECCLK = fHCLK/4 */
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#define TSI_EXTEND_DIV5 ((uint32_t)0x00000004U) /*!< fECCLK = fHCLK/5 */
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#define TSI_EXTEND_DIV6 ((uint32_t)0x00000005U) /*!< fECCLK = fHCLK/6 */
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#define TSI_EXTEND_DIV7 ((uint32_t)0x00000006U) /*!< fECCLK = fHCLK/7 */
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#define TSI_EXTEND_DIV8 ((uint32_t)0x00000007U) /*!< fECCLK = fHCLK/8 */
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/* extend charge state maximum duration time */
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#define TSI_EXTENDMAX(regval) (BITS(17,23) & ((uint32_t)(regval) << 17U)) /* value range 1..128,extend charge state maximum duration time */
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/* hardware trigger mode */
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#define TSI_FALLING_TRIGGER 0x00U /*!< falling edge trigger TSI charge transfer sequence */
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#define TSI_RISING_TRIGGER 0x01U /*!< rising edge trigger TSI charge transfer sequence */
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/* pin mode */
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#define TSI_OUTPUT_LOW 0x00U /*!< TSI pin will output low when IDLE */
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#define TSI_INPUT_FLOATING 0x01U /*!< TSI pin will keep input_floating when IDLE */
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/* function declarations */
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/* reset TSI peripheral */
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void tsi_deinit(void);
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/* initialize TSI plus prescaler,charge plus,transfer plus,max cycle number */
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void tsi_init(uint32_t prescaler,uint32_t charge_duration,uint32_t transfer_duration,uint32_t max_number);
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/* enable TSI module */
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void tsi_enable(void);
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/* disable TSI module */
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void tsi_disable(void);
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/* enable sample pin */
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void tsi_sample_pin_enable(uint32_t sample);
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/* disable sample pin */
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void tsi_sample_pin_disable(uint32_t sample);
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/* enable channel pin */
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void tsi_channel_pin_enable(uint32_t channel);
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/* disable channel pin */
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void tsi_channel_pin_disable(uint32_t channel);
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/* configure TSI triggering by software */
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void tsi_sofeware_mode_config(void);
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/* start a charge-transfer sequence when TSI is in software trigger mode */
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void tsi_software_start(void);
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/* stop a charge-transfer sequence when TSI is in software trigger mode */
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void tsi_software_stop(void);
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/* configure TSI triggering by hardware */
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void tsi_hardware_mode_config(uint8_t trigger_edge);
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/* configure TSI pin mode when charge-transfer sequence is IDLE */
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void tsi_pin_mode_config(uint8_t pin_mode);
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/* configure extend charge state */
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void tsi_extend_charge_config(ControlStatus extend,uint8_t prescaler,uint32_t max_duration);
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/* configure charge plus and transfer plus */
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void tsi_plus_config(uint32_t prescaler,uint32_t charge_duration,uint32_t transfer_duration);
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/* configure the max cycle number of a charge-transfer sequence */
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void tsi_max_number_config(uint32_t max_number);
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/* switch on hysteresis pin */
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void tsi_hysteresis_on(uint32_t group_pin);
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/* switch off hysteresis pin */
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void tsi_hysteresis_off(uint32_t group_pin);
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/* switch on analog pin */
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void tsi_analog_on(uint32_t group_pin);
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/* switch off analog pin */
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void tsi_analog_off(uint32_t group_pin);
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/* enable TSI interrupt */
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void tsi_interrupt_enable(uint32_t source);
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/* disable TSI interrupt */
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void tsi_interrupt_disable(uint32_t source);
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/* clear interrupt flag */
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void tsi_interrupt_flag_clear(uint32_t flag);
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/* get TSI interrupt flag */
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FlagStatus tsi_interrupt_flag_get(uint32_t flag);
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/* clear flag */
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void tsi_flag_clear(uint32_t flag);
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/* get flag */
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FlagStatus tsi_flag_get(uint32_t flag);
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/* enbale group */
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void tsi_group_enable(uint32_t group);
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/* disbale group */
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void tsi_group_disable(uint32_t group);
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/* get group complete status */
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FlagStatus tsi_group_status_get(uint32_t group);
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/* get the cycle number for group0 as soon as a charge-transfer sequence completes */
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uint16_t tsi_group0_cycle_get(void);
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/* get the cycle number for group1 as soon as a charge-transfer sequence completes */
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uint16_t tsi_group1_cycle_get(void);
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/* get the cycle number for group2 as soon as a charge-transfer sequence completes */
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uint16_t tsi_group2_cycle_get(void);
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/* get the cycle number for group3 as soon as a charge-transfer sequence completes */
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uint16_t tsi_group3_cycle_get(void);
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/* get the cycle number for group4 as soon as a charge-transfer sequence completes */
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uint16_t tsi_group4_cycle_get(void);
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/* get the cycle number for group5 as soon as a charge-transfer sequence completes */
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uint16_t tsi_group5_cycle_get(void);
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#endif /* GD32F3X0_TSI_H */
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