42539 lines
2.4 MiB
42539 lines
2.4 MiB
/*
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** ###################################################################
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** Processors: MIMXRT1052CVJ5B
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** MIMXRT1052CVL5B
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** MIMXRT1052DVJ6B
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** MIMXRT1052DVL6B
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**
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** Compilers: Freescale C/C++ for Embedded ARM
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** GNU C Compiler
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** IAR ANSI C/C++ Compiler for ARM
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** Keil ARM C/C++ Compiler
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** MCUXpresso Compiler
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**
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** Reference manual: IMXRT1050RM Rev.2.1, 12/2018
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** Version: rev. 1.2, 2018-11-27
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** Build: b181205
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**
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** Abstract:
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** CMSIS Peripheral Access Layer for MIMXRT1052
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**
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** Copyright 1997-2016 Freescale Semiconductor, Inc.
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** Copyright 2016-2018 NXP
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** All rights reserved.
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**
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** SPDX-License-Identifier: BSD-3-Clause
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**
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** http: www.nxp.com
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** mail: support@nxp.com
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**
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** Revisions:
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** - rev. 0.1 (2017-01-10)
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** Initial version.
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** - rev. 1.0 (2018-09-21)
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** Update interrupt vector table and dma request source.
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** Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1.
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** Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS.
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** - rev. 1.1 (2018-11-16)
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** Update header files to align with IMXRT1050RM Rev.1.
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** - rev. 1.2 (2018-11-27)
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** Update header files to align with IMXRT1050RM Rev.2.1.
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**
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** ###################################################################
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*/
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/*!
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* @file MIMXRT1052.h
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* @version 1.2
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* @date 2018-11-27
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* @brief CMSIS Peripheral Access Layer for MIMXRT1052
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*
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* CMSIS Peripheral Access Layer for MIMXRT1052
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*/
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#ifndef _MIMXRT1052_H_
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#define _MIMXRT1052_H_ /**< Symbol preventing repeated inclusion */
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/** Memory map major version (memory maps with equal major version number are
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* compatible) */
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#define MCU_MEM_MAP_VERSION 0x0100U
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/** Memory map minor version */
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#define MCU_MEM_MAP_VERSION_MINOR 0x0002U
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/* ----------------------------------------------------------------------------
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-- Interrupt vector numbers
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup Interrupt_vector_numbers Interrupt vector numbers
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* @{
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*/
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/** Interrupt Number Definitions */
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#define NUMBER_OF_INT_VECTORS 168 /**< Number of interrupts in the Vector table */
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typedef enum IRQn {
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/* Auxiliary constants */
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NotAvail_IRQn = -128, /**< Not available device specific interrupt */
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/* Core interrupts */
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NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
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HardFault_IRQn = -13, /**< Cortex-M7 SV Hard Fault Interrupt */
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MemoryManagement_IRQn = -12, /**< Cortex-M7 Memory Management Interrupt */
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BusFault_IRQn = -11, /**< Cortex-M7 Bus Fault Interrupt */
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UsageFault_IRQn = -10, /**< Cortex-M7 Usage Fault Interrupt */
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SVCall_IRQn = -5, /**< Cortex-M7 SV Call Interrupt */
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DebugMonitor_IRQn = -4, /**< Cortex-M7 Debug Monitor Interrupt */
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PendSV_IRQn = -2, /**< Cortex-M7 Pend SV Interrupt */
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SysTick_IRQn = -1, /**< Cortex-M7 System Tick Interrupt */
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/* Device specific interrupts */
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DMA0_DMA16_IRQn = 0, /**< DMA channel 0/16 transfer complete */
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DMA1_DMA17_IRQn = 1, /**< DMA channel 1/17 transfer complete */
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DMA2_DMA18_IRQn = 2, /**< DMA channel 2/18 transfer complete */
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DMA3_DMA19_IRQn = 3, /**< DMA channel 3/19 transfer complete */
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DMA4_DMA20_IRQn = 4, /**< DMA channel 4/20 transfer complete */
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DMA5_DMA21_IRQn = 5, /**< DMA channel 5/21 transfer complete */
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DMA6_DMA22_IRQn = 6, /**< DMA channel 6/22 transfer complete */
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DMA7_DMA23_IRQn = 7, /**< DMA channel 7/23 transfer complete */
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DMA8_DMA24_IRQn = 8, /**< DMA channel 8/24 transfer complete */
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DMA9_DMA25_IRQn = 9, /**< DMA channel 9/25 transfer complete */
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DMA10_DMA26_IRQn = 10, /**< DMA channel 10/26 transfer complete */
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DMA11_DMA27_IRQn = 11, /**< DMA channel 11/27 transfer complete */
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DMA12_DMA28_IRQn = 12, /**< DMA channel 12/28 transfer complete */
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DMA13_DMA29_IRQn = 13, /**< DMA channel 13/29 transfer complete */
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DMA14_DMA30_IRQn = 14, /**< DMA channel 14/30 transfer complete */
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DMA15_DMA31_IRQn = 15, /**< DMA channel 15/31 transfer complete */
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DMA_ERROR_IRQn = 16, /**< DMA error interrupt channels 0-15 / 16-31 */
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CTI0_ERROR_IRQn = 17, /**< CTI0_Error */
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CTI1_ERROR_IRQn = 18, /**< CTI1_Error */
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CORE_IRQn = 19, /**< CorePlatform exception IRQ */
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LPUART1_IRQn = 20, /**< LPUART1 TX interrupt and RX interrupt */
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LPUART2_IRQn = 21, /**< LPUART2 TX interrupt and RX interrupt */
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LPUART3_IRQn = 22, /**< LPUART3 TX interrupt and RX interrupt */
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LPUART4_IRQn = 23, /**< LPUART4 TX interrupt and RX interrupt */
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LPUART5_IRQn = 24, /**< LPUART5 TX interrupt and RX interrupt */
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LPUART6_IRQn = 25, /**< LPUART6 TX interrupt and RX interrupt */
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LPUART7_IRQn = 26, /**< LPUART7 TX interrupt and RX interrupt */
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LPUART8_IRQn = 27, /**< LPUART8 TX interrupt and RX interrupt */
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LPI2C1_IRQn = 28, /**< LPI2C1 interrupt */
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LPI2C2_IRQn = 29, /**< LPI2C2 interrupt */
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LPI2C3_IRQn = 30, /**< LPI2C3 interrupt */
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LPI2C4_IRQn = 31, /**< LPI2C4 interrupt */
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LPSPI1_IRQn = 32, /**< LPSPI1 single interrupt vector for all sources */
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LPSPI2_IRQn = 33, /**< LPSPI2 single interrupt vector for all sources */
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LPSPI3_IRQn = 34, /**< LPSPI3 single interrupt vector for all sources */
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LPSPI4_IRQn = 35, /**< LPSPI4 single interrupt vector for all sources */
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CAN1_IRQn = 36, /**< CAN1 interrupt */
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CAN2_IRQn = 37, /**< CAN2 interrupt */
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FLEXRAM_IRQn = 38, /**< FlexRAM address out of range Or access hit IRQ */
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KPP_IRQn = 39, /**< Keypad nterrupt */
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TSC_DIG_IRQn = 40, /**< TSC interrupt */
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GPR_IRQ_IRQn = 41, /**< GPR interrupt */
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LCDIF_IRQn = 42, /**< LCDIF interrupt */
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CSI_IRQn = 43, /**< CSI interrupt */
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PXP_IRQn = 44, /**< PXP interrupt */
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WDOG2_IRQn = 45, /**< WDOG2 interrupt */
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SNVS_HP_WRAPPER_IRQn = 46, /**< SRTC Consolidated Interrupt. Non TZ */
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SNVS_HP_WRAPPER_TZ_IRQn = 47, /**< SRTC Security Interrupt. TZ */
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SNVS_LP_WRAPPER_IRQn = 48, /**< ON-OFF button press shorter than 5 secs (pulse event) */
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CSU_IRQn = 49, /**< CSU interrupt */
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DCP_IRQn = 50, /**< DCP_IRQ interrupt */
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DCP_VMI_IRQn = 51, /**< DCP_VMI_IRQ interrupt */
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Reserved68_IRQn = 52, /**< Reserved interrupt */
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TRNG_IRQn = 53, /**< TRNG interrupt */
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SJC_IRQn = 54, /**< SJC interrupt */
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BEE_IRQn = 55, /**< BEE interrupt */
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SAI1_IRQn = 56, /**< SAI1 interrupt */
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SAI2_IRQn = 57, /**< SAI1 interrupt */
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SAI3_RX_IRQn = 58, /**< SAI3 interrupt */
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SAI3_TX_IRQn = 59, /**< SAI3 interrupt */
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SPDIF_IRQn = 60, /**< SPDIF interrupt */
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PMU_EVENT_IRQn = 61, /**< Brown-out event interrupt */
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Reserved78_IRQn = 62, /**< Reserved interrupt */
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TEMP_LOW_HIGH_IRQn = 63, /**< TempSensor low/high interrupt */
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TEMP_PANIC_IRQn = 64, /**< TempSensor panic interrupt */
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USB_PHY1_IRQn = 65, /**< USBPHY (UTMI0), Interrupt */
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USB_PHY2_IRQn = 66, /**< USBPHY (UTMI0), Interrupt */
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ADC1_IRQn = 67, /**< ADC1 interrupt */
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ADC2_IRQn = 68, /**< ADC2 interrupt */
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DCDC_IRQn = 69, /**< DCDC interrupt */
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Reserved86_IRQn = 70, /**< Reserved interrupt */
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Reserved87_IRQn = 71, /**< Reserved interrupt */
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GPIO1_INT0_IRQn = 72, /**< Active HIGH Interrupt from INT0 from GPIO */
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GPIO1_INT1_IRQn = 73, /**< Active HIGH Interrupt from INT1 from GPIO */
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GPIO1_INT2_IRQn = 74, /**< Active HIGH Interrupt from INT2 from GPIO */
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GPIO1_INT3_IRQn = 75, /**< Active HIGH Interrupt from INT3 from GPIO */
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GPIO1_INT4_IRQn = 76, /**< Active HIGH Interrupt from INT4 from GPIO */
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GPIO1_INT5_IRQn = 77, /**< Active HIGH Interrupt from INT5 from GPIO */
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GPIO1_INT6_IRQn = 78, /**< Active HIGH Interrupt from INT6 from GPIO */
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GPIO1_INT7_IRQn = 79, /**< Active HIGH Interrupt from INT7 from GPIO */
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GPIO1_Combined_0_15_IRQn = 80, /**< Combined interrupt indication for GPIO1 signal 0 throughout 15 */
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GPIO1_Combined_16_31_IRQn = 81, /**< Combined interrupt indication for GPIO1 signal 16 throughout 31 */
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GPIO2_Combined_0_15_IRQn = 82, /**< Combined interrupt indication for GPIO2 signal 0 throughout 15 */
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GPIO2_Combined_16_31_IRQn = 83, /**< Combined interrupt indication for GPIO2 signal 16 throughout 31 */
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GPIO3_Combined_0_15_IRQn = 84, /**< Combined interrupt indication for GPIO3 signal 0 throughout 15 */
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GPIO3_Combined_16_31_IRQn = 85, /**< Combined interrupt indication for GPIO3 signal 16 throughout 31 */
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GPIO4_Combined_0_15_IRQn = 86, /**< Combined interrupt indication for GPIO4 signal 0 throughout 15 */
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GPIO4_Combined_16_31_IRQn = 87, /**< Combined interrupt indication for GPIO4 signal 16 throughout 31 */
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GPIO5_Combined_0_15_IRQn = 88, /**< Combined interrupt indication for GPIO5 signal 0 throughout 15 */
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GPIO5_Combined_16_31_IRQn = 89, /**< Combined interrupt indication for GPIO5 signal 16 throughout 31 */
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FLEXIO1_IRQn = 90, /**< FLEXIO1 interrupt */
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FLEXIO2_IRQn = 91, /**< FLEXIO2 interrupt */
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WDOG1_IRQn = 92, /**< WDOG1 interrupt */
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RTWDOG_IRQn = 93, /**< RTWDOG interrupt */
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EWM_IRQn = 94, /**< EWM interrupt */
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CCM_1_IRQn = 95, /**< CCM IRQ1 interrupt */
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CCM_2_IRQn = 96, /**< CCM IRQ2 interrupt */
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GPC_IRQn = 97, /**< GPC interrupt */
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SRC_IRQn = 98, /**< SRC interrupt */
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Reserved115_IRQn = 99, /**< Reserved interrupt */
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GPT1_IRQn = 100, /**< GPT1 interrupt */
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GPT2_IRQn = 101, /**< GPT2 interrupt */
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PWM1_0_IRQn = 102, /**< PWM1 capture 0, compare 0, or reload 0 interrupt */
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PWM1_1_IRQn = 103, /**< PWM1 capture 1, compare 1, or reload 0 interrupt */
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PWM1_2_IRQn = 104, /**< PWM1 capture 2, compare 2, or reload 0 interrupt */
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PWM1_3_IRQn = 105, /**< PWM1 capture 3, compare 3, or reload 0 interrupt */
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PWM1_FAULT_IRQn = 106, /**< PWM1 fault or reload error interrupt */
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Reserved123_IRQn = 107, /**< Reserved interrupt */
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FLEXSPI_IRQn = 108, /**< FlexSPI0 interrupt */
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SEMC_IRQn = 109, /**< Reserved interrupt */
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USDHC1_IRQn = 110, /**< USDHC1 interrupt */
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USDHC2_IRQn = 111, /**< USDHC2 interrupt */
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USB_OTG2_IRQn = 112, /**< USBO2 USB OTG2 */
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USB_OTG1_IRQn = 113, /**< USBO2 USB OTG1 */
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ENET_IRQn = 114, /**< ENET interrupt */
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ENET_1588_Timer_IRQn = 115, /**< ENET_1588_Timer interrupt */
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XBAR1_IRQ_0_1_IRQn = 116, /**< XBAR1 interrupt */
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XBAR1_IRQ_2_3_IRQn = 117, /**< XBAR1 interrupt */
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ADC_ETC_IRQ0_IRQn = 118, /**< ADCETC IRQ0 interrupt */
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ADC_ETC_IRQ1_IRQn = 119, /**< ADCETC IRQ1 interrupt */
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ADC_ETC_IRQ2_IRQn = 120, /**< ADCETC IRQ2 interrupt */
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ADC_ETC_ERROR_IRQ_IRQn = 121, /**< ADCETC Error IRQ interrupt */
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PIT_IRQn = 122, /**< PIT interrupt */
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ACMP1_IRQn = 123, /**< ACMP interrupt */
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ACMP2_IRQn = 124, /**< ACMP interrupt */
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ACMP3_IRQn = 125, /**< ACMP interrupt */
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ACMP4_IRQn = 126, /**< ACMP interrupt */
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Reserved143_IRQn = 127, /**< Reserved interrupt */
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Reserved144_IRQn = 128, /**< Reserved interrupt */
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ENC1_IRQn = 129, /**< ENC1 interrupt */
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ENC2_IRQn = 130, /**< ENC2 interrupt */
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ENC3_IRQn = 131, /**< ENC3 interrupt */
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ENC4_IRQn = 132, /**< ENC4 interrupt */
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TMR1_IRQn = 133, /**< TMR1 interrupt */
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TMR2_IRQn = 134, /**< TMR2 interrupt */
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TMR3_IRQn = 135, /**< TMR3 interrupt */
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TMR4_IRQn = 136, /**< TMR4 interrupt */
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PWM2_0_IRQn = 137, /**< PWM2 capture 0, compare 0, or reload 0 interrupt */
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PWM2_1_IRQn = 138, /**< PWM2 capture 1, compare 1, or reload 0 interrupt */
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PWM2_2_IRQn = 139, /**< PWM2 capture 2, compare 2, or reload 0 interrupt */
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PWM2_3_IRQn = 140, /**< PWM2 capture 3, compare 3, or reload 0 interrupt */
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PWM2_FAULT_IRQn = 141, /**< PWM2 fault or reload error interrupt */
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PWM3_0_IRQn = 142, /**< PWM3 capture 0, compare 0, or reload 0 interrupt */
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PWM3_1_IRQn = 143, /**< PWM3 capture 1, compare 1, or reload 0 interrupt */
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PWM3_2_IRQn = 144, /**< PWM3 capture 2, compare 2, or reload 0 interrupt */
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PWM3_3_IRQn = 145, /**< PWM3 capture 3, compare 3, or reload 0 interrupt */
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PWM3_FAULT_IRQn = 146, /**< PWM3 fault or reload error interrupt */
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PWM4_0_IRQn = 147, /**< PWM4 capture 0, compare 0, or reload 0 interrupt */
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PWM4_1_IRQn = 148, /**< PWM4 capture 1, compare 1, or reload 0 interrupt */
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PWM4_2_IRQn = 149, /**< PWM4 capture 2, compare 2, or reload 0 interrupt */
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PWM4_3_IRQn = 150, /**< PWM4 capture 3, compare 3, or reload 0 interrupt */
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PWM4_FAULT_IRQn = 151 /**< PWM4 fault or reload error interrupt */
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} IRQn_Type;
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/*!
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* @}
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*/ /* end of group Interrupt_vector_numbers */
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/* ----------------------------------------------------------------------------
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-- Cortex M7 Core Configuration
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup Cortex_Core_Configuration Cortex M7 Core Configuration
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* @{
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*/
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#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
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#define __ICACHE_PRESENT 1 /**< Defines if an ICACHE is present or not */
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#define __DCACHE_PRESENT 1 /**< Defines if an DCACHE is present or not */
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#define __DTCM_PRESENT 1 /**< Defines if an DTCM is present or not */
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#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
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#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
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#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
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#include "core_cm7.h" /* Core Peripheral Access Layer */
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#include "system_MIMXRT1052.h" /* Device specific configuration file */
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/*!
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* @}
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*/ /* end of group Cortex_Core_Configuration */
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/* ----------------------------------------------------------------------------
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-- Mapping Information
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup Mapping_Information Mapping Information
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* @{
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*/
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/** Mapping Information */
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/*!
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* @addtogroup edma_request
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* @{
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*/
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*!
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* @brief Structure for the DMA hardware request
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*
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* Defines the structure for the DMA hardware request collections. The user can configure the
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* hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
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* of the hardware request varies according to the to SoC.
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*/
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typedef enum _dma_request_source
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{
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kDmaRequestMuxFlexIO1Request0Request1 = 0|0x100U, /**< FlexIO1 Request0 and Request1 */
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kDmaRequestMuxFlexIO2Request0Request1 = 1|0x100U, /**< FlexIO2 Request0 and Request1 */
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kDmaRequestMuxLPUART1Tx = 2|0x100U, /**< LPUART1 Transmit */
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kDmaRequestMuxLPUART1Rx = 3|0x100U, /**< LPUART1 Receive */
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kDmaRequestMuxLPUART3Tx = 4|0x100U, /**< LPUART3 Transmit */
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kDmaRequestMuxLPUART3Rx = 5|0x100U, /**< LPUART3 Receive */
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kDmaRequestMuxLPUART5Tx = 6|0x100U, /**< LPUART5 Transmit */
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kDmaRequestMuxLPUART5Rx = 7|0x100U, /**< LPUART5 Receive */
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kDmaRequestMuxLPUART7Tx = 8|0x100U, /**< LPUART7 Transmit */
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kDmaRequestMuxLPUART7Rx = 9|0x100U, /**< LPUART7 Receive */
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kDmaRequestMuxCSI = 12|0x100U, /**< CSI */
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kDmaRequestMuxLPSPI1Rx = 13|0x100U, /**< LPSPI1 Receive */
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kDmaRequestMuxLPSPI1Tx = 14|0x100U, /**< LPSPI1 Transmit */
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kDmaRequestMuxLPSPI3Rx = 15|0x100U, /**< LPSPI3 Receive */
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kDmaRequestMuxLPSPI3Tx = 16|0x100U, /**< LPSPI3 Transmit */
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kDmaRequestMuxLPI2C1 = 17|0x100U, /**< LPI2C1 */
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kDmaRequestMuxLPI2C3 = 18|0x100U, /**< LPI2C3 */
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kDmaRequestMuxSai1Rx = 19|0x100U, /**< SAI1 Receive */
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kDmaRequestMuxSai1Tx = 20|0x100U, /**< SAI1 Transmit */
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kDmaRequestMuxSai2Rx = 21|0x100U, /**< SAI2 Receive */
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kDmaRequestMuxSai2Tx = 22|0x100U, /**< SAI2 Transmit */
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kDmaRequestMuxADC_ETC = 23|0x100U, /**< ADC_ETC */
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kDmaRequestMuxADC1 = 24|0x100U, /**< ADC1 */
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kDmaRequestMuxACMP1 = 25|0x100U, /**< ACMP1 */
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kDmaRequestMuxACMP3 = 26|0x100U, /**< ACMP3 */
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kDmaRequestMuxFlexSPIRx = 28|0x100U, /**< FlexSPI Receive */
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kDmaRequestMuxFlexSPITx = 29|0x100U, /**< FlexSPI Transmit */
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kDmaRequestMuxXBAR1Request0 = 30|0x100U, /**< XBAR1 Request 0 */
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kDmaRequestMuxXBAR1Request1 = 31|0x100U, /**< XBAR1 Request 1 */
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kDmaRequestMuxFlexPWM1CaptureSub0 = 32|0x100U, /**< FlexPWM1 Capture sub-module0 */
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kDmaRequestMuxFlexPWM1CaptureSub1 = 33|0x100U, /**< FlexPWM1 Capture sub-module1 */
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kDmaRequestMuxFlexPWM1CaptureSub2 = 34|0x100U, /**< FlexPWM1 Capture sub-module2 */
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kDmaRequestMuxFlexPWM1CaptureSub3 = 35|0x100U, /**< FlexPWM1 Capture sub-module3 */
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kDmaRequestMuxFlexPWM1ValueSub0 = 36|0x100U, /**< FlexPWM1 Value sub-module0 */
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kDmaRequestMuxFlexPWM1ValueSub1 = 37|0x100U, /**< FlexPWM1 Value sub-module1 */
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kDmaRequestMuxFlexPWM1ValueSub2 = 38|0x100U, /**< FlexPWM1 Value sub-module2 */
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kDmaRequestMuxFlexPWM1ValueSub3 = 39|0x100U, /**< FlexPWM1 Value sub-module3 */
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kDmaRequestMuxFlexPWM3CaptureSub0 = 40|0x100U, /**< FlexPWM3 Capture sub-module0 */
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kDmaRequestMuxFlexPWM3CaptureSub1 = 41|0x100U, /**< FlexPWM3 Capture sub-module1 */
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kDmaRequestMuxFlexPWM3CaptureSub2 = 42|0x100U, /**< FlexPWM3 Capture sub-module2 */
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kDmaRequestMuxFlexPWM3CaptureSub3 = 43|0x100U, /**< FlexPWM3 Capture sub-module3 */
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kDmaRequestMuxFlexPWM3ValueSub0 = 44|0x100U, /**< FlexPWM3 Value sub-module0 */
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kDmaRequestMuxFlexPWM3ValueSub1 = 45|0x100U, /**< FlexPWM3 Value sub-module1 */
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kDmaRequestMuxFlexPWM3ValueSub2 = 46|0x100U, /**< FlexPWM3 Value sub-module2 */
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kDmaRequestMuxFlexPWM3ValueSub3 = 47|0x100U, /**< FlexPWM3 Value sub-module3 */
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kDmaRequestMuxQTIMER1CaptTimer0 = 48|0x100U, /**< TMR1 Capture timer 0 */
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kDmaRequestMuxQTIMER1CaptTimer1 = 49|0x100U, /**< TMR1 Capture timer 1 */
|
|
kDmaRequestMuxQTIMER1CaptTimer2 = 50|0x100U, /**< TMR1 Capture timer 2 */
|
|
kDmaRequestMuxQTIMER1CaptTimer3 = 51|0x100U, /**< TMR1 Capture timer 3 */
|
|
kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1 = 52|0x100U, /**< TMR1 cmpld1 in timer 0 or cmpld2 in timer 1 */
|
|
kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0 = 53|0x100U, /**< TMR1 cmpld1 in timer 1 or cmpld2 in timer 0 */
|
|
kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3 = 54|0x100U, /**< TMR1 cmpld1 in timer 2 or cmpld2 in timer 3 */
|
|
kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2 = 55|0x100U, /**< TMR1 cmpld1 in timer 3 or cmpld2 in timer 2 */
|
|
kDmaRequestMuxQTIMER3CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 56|0x100U, /**< TMR3 capture timer 0, cmpld1 in timer 0 or cmpld2 in timer 1 */
|
|
kDmaRequestMuxQTIMER3CaptTimer1Cmpld1Timer1Cmpld2Timer0 = 57|0x100U, /**< TMR3 capture timer 1, cmpld1 in timer 1 or cmpld2 in timer 0 */
|
|
kDmaRequestMuxQTIMER3CaptTimer2Cmpld1Timer2Cmpld2Timer3 = 58|0x100U, /**< TMR3 capture timer 2, cmpld1 in timer 2 or cmpld2 in timer 3 */
|
|
kDmaRequestMuxQTIMER3CaptTimer3Cmpld1Timer3Cmpld2Timer2 = 59|0x100U, /**< TMR3 capture timer 3, cmpld1 in timer 3 or cmpld2 in timer 2 */
|
|
kDmaRequestMuxFlexIO1Request2Request3 = 64|0x100U, /**< FlexIO1 Request2 and Request3 */
|
|
kDmaRequestMuxFlexIO2Request2Request3 = 65|0x100U, /**< FlexIO2 Request2 and Request3 */
|
|
kDmaRequestMuxLPUART2Tx = 66|0x100U, /**< LPUART2 Transmit */
|
|
kDmaRequestMuxLPUART2Rx = 67|0x100U, /**< LPUART2 Receive */
|
|
kDmaRequestMuxLPUART4Tx = 68|0x100U, /**< LPUART4 Transmit */
|
|
kDmaRequestMuxLPUART4Rx = 69|0x100U, /**< LPUART4 Receive */
|
|
kDmaRequestMuxLPUART6Tx = 70|0x100U, /**< LPUART6 Transmit */
|
|
kDmaRequestMuxLPUART6Rx = 71|0x100U, /**< LPUART6 Receive */
|
|
kDmaRequestMuxLPUART8Tx = 72|0x100U, /**< LPUART8 Transmit */
|
|
kDmaRequestMuxLPUART8Rx = 73|0x100U, /**< LPUART8 Receive */
|
|
kDmaRequestMuxPxp = 75|0x100U, /**< PXP */
|
|
kDmaRequestMuxLCDIF = 76|0x100U, /**< LCDIF */
|
|
kDmaRequestMuxLPSPI2Rx = 77|0x100U, /**< LPSPI2 Receive */
|
|
kDmaRequestMuxLPSPI2Tx = 78|0x100U, /**< LPSPI2 Transmit */
|
|
kDmaRequestMuxLPSPI4Rx = 79|0x100U, /**< LPSPI4 Receive */
|
|
kDmaRequestMuxLPSPI4Tx = 80|0x100U, /**< LPSPI4 Transmit */
|
|
kDmaRequestMuxLPI2C2 = 81|0x100U, /**< LPI2C2 */
|
|
kDmaRequestMuxLPI2C4 = 82|0x100U, /**< LPI2C4 */
|
|
kDmaRequestMuxSai3Rx = 83|0x100U, /**< SAI3 Receive */
|
|
kDmaRequestMuxSai3Tx = 84|0x100U, /**< SAI3 Transmit */
|
|
kDmaRequestMuxSpdifRx = 85|0x100U, /**< SPDIF Receive */
|
|
kDmaRequestMuxSpdifTx = 86|0x100U, /**< SPDIF Transmit */
|
|
kDmaRequestMuxADC2 = 88|0x100U, /**< ADC2 */
|
|
kDmaRequestMuxACMP2 = 89|0x100U, /**< ACMP2 */
|
|
kDmaRequestMuxACMP4 = 90|0x100U, /**< ACMP4 */
|
|
kDmaRequestMuxEnetTimer0 = 92|0x100U, /**< ENET Timer0 */
|
|
kDmaRequestMuxEnetTimer1 = 93|0x100U, /**< ENET Timer1 */
|
|
kDmaRequestMuxXBAR1Request2 = 94|0x100U, /**< XBAR1 Request 2 */
|
|
kDmaRequestMuxXBAR1Request3 = 95|0x100U, /**< XBAR1 Request 3 */
|
|
kDmaRequestMuxFlexPWM2CaptureSub0 = 96|0x100U, /**< FlexPWM2 Capture sub-module0 */
|
|
kDmaRequestMuxFlexPWM2CaptureSub1 = 97|0x100U, /**< FlexPWM2 Capture sub-module1 */
|
|
kDmaRequestMuxFlexPWM2CaptureSub2 = 98|0x100U, /**< FlexPWM2 Capture sub-module2 */
|
|
kDmaRequestMuxFlexPWM2CaptureSub3 = 99|0x100U, /**< FlexPWM2 Capture sub-module3 */
|
|
kDmaRequestMuxFlexPWM2ValueSub0 = 100|0x100U, /**< FlexPWM2 Value sub-module0 */
|
|
kDmaRequestMuxFlexPWM2ValueSub1 = 101|0x100U, /**< FlexPWM2 Value sub-module1 */
|
|
kDmaRequestMuxFlexPWM2ValueSub2 = 102|0x100U, /**< FlexPWM2 Value sub-module2 */
|
|
kDmaRequestMuxFlexPWM2ValueSub3 = 103|0x100U, /**< FlexPWM2 Value sub-module3 */
|
|
kDmaRequestMuxFlexPWM4CaptureSub0 = 104|0x100U, /**< FlexPWM4 Capture sub-module0 */
|
|
kDmaRequestMuxFlexPWM4CaptureSub1 = 105|0x100U, /**< FlexPWM4 Capture sub-module1 */
|
|
kDmaRequestMuxFlexPWM4CaptureSub2 = 106|0x100U, /**< FlexPWM4 Capture sub-module2 */
|
|
kDmaRequestMuxFlexPWM4CaptureSub3 = 107|0x100U, /**< FlexPWM4 Capture sub-module3 */
|
|
kDmaRequestMuxFlexPWM4ValueSub0 = 108|0x100U, /**< FlexPWM4 Value sub-module0 */
|
|
kDmaRequestMuxFlexPWM4ValueSub1 = 109|0x100U, /**< FlexPWM4 Value sub-module1 */
|
|
kDmaRequestMuxFlexPWM4ValueSub2 = 110|0x100U, /**< FlexPWM4 Value sub-module2 */
|
|
kDmaRequestMuxFlexPWM4ValueSub3 = 111|0x100U, /**< FlexPWM4 Value sub-module3 */
|
|
kDmaRequestMuxQTIMER2CaptTimer0 = 112|0x100U, /**< TMR2 Capture timer 0 */
|
|
kDmaRequestMuxQTIMER2CaptTimer1 = 113|0x100U, /**< TMR2 Capture timer 1 */
|
|
kDmaRequestMuxQTIMER2CaptTimer2 = 114|0x100U, /**< TMR2 Capture timer 2 */
|
|
kDmaRequestMuxQTIMER2CaptTimer3 = 115|0x100U, /**< TMR2 Capture timer 3 */
|
|
kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1 = 116|0x100U, /**< TMR2 cmpld1 in timer 0 or cmpld2 in timer 1 */
|
|
kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0 = 117|0x100U, /**< TMR2 cmpld1 in timer 1 or cmpld2 in timer 0 */
|
|
kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3 = 118|0x100U, /**< TMR2 cmpld1 in timer 2 or cmpld2 in timer 3 */
|
|
kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2 = 119|0x100U, /**< TMR2 cmpld1 in timer 3 or cmpld2 in timer 2 */
|
|
kDmaRequestMuxQTIMER4CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 120|0x100U, /**< TMR4 capture timer 0, cmpld1 in timer 0 or cmpld2 in timer 1 */
|
|
kDmaRequestMuxQTIMER4CaptTimer1Cmpld1Timer1Cmpld2Timer0 = 121|0x100U, /**< TMR4 capture timer 1, cmpld1 in timer 1 or cmpld2 in timer 0 */
|
|
kDmaRequestMuxQTIMER4CaptTimer2Cmpld1Timer2Cmpld2Timer3 = 122|0x100U, /**< TMR4 capture timer 2, cmpld1 in timer 2 or cmpld2 in timer 3 */
|
|
kDmaRequestMuxQTIMER4CaptTimer3Cmpld1Timer3Cmpld2Timer2 = 123|0x100U, /**< TMR4 capture timer 3, cmpld1 in timer 3 or cmpld2 in timer 2 */
|
|
} dma_request_source_t;
|
|
|
|
/* @} */
|
|
|
|
/*!
|
|
* @addtogroup iomuxc_pads
|
|
* @{ */
|
|
|
|
/*******************************************************************************
|
|
* Definitions
|
|
*******************************************************************************/
|
|
|
|
/*!
|
|
* @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD
|
|
*
|
|
* Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections.
|
|
*/
|
|
typedef enum _iomuxc_sw_mux_ctl_pad
|
|
{
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00 = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01 = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02 = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03 = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 = 6U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 = 7U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 = 8U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09 = 9U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10 = 10U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11 = 11U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12 = 12U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13 = 13U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14 = 14U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15 = 15U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16 = 16U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17 = 17U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18 = 18U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19 = 19U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20 = 20U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21 = 21U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 = 22U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 = 23U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 = 24U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 = 25U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 = 26U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27 = 27U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28 = 28U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29 = 29U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30 = 30U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31 = 31U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 = 32U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33 = 33U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34 = 34U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35 = 35U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36 = 36U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37 = 37U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38 = 38U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39 = 39U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40 = 40U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41 = 41U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00 = 42U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01 = 43U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02 = 44U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03 = 45U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04 = 46U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05 = 47U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06 = 48U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07 = 49U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08 = 50U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09 = 51U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10 = 52U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11 = 53U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12 = 54U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13 = 55U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14 = 56U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15 = 57U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00 = 58U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01 = 59U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02 = 60U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03 = 61U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04 = 62U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05 = 63U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06 = 64U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07 = 65U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08 = 66U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09 = 67U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10 = 68U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11 = 69U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12 = 70U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13 = 71U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14 = 72U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15 = 73U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00 = 74U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01 = 75U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02 = 76U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 = 77U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_04 = 78U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_05 = 79U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_06 = 80U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_07 = 81U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_08 = 82U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_09 = 83U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10 = 84U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11 = 85U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12 = 86U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_13 = 87U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_14 = 88U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_15 = 89U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00 = 90U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01 = 91U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02 = 92U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03 = 93U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04 = 94U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05 = 95U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06 = 96U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07 = 97U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08 = 98U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09 = 99U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10 = 100U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11 = 101U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12 = 102U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13 = 103U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_14 = 104U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_15 = 105U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 = 106U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01 = 107U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02 = 108U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03 = 109U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04 = 110U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05 = 111U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 = 112U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 = 113U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 = 114U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 = 115U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 = 116U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 = 117U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06 = 118U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07 = 119U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08 = 120U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09 = 121U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10 = 122U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11 = 123U, /**< IOMUXC SW_MUX_CTL_PAD index */
|
|
} iomuxc_sw_mux_ctl_pad_t;
|
|
|
|
/* @} */
|
|
|
|
/*!
|
|
* @addtogroup iomuxc_pads
|
|
* @{ */
|
|
|
|
/*******************************************************************************
|
|
* Definitions
|
|
*******************************************************************************/
|
|
|
|
/*!
|
|
* @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD
|
|
*
|
|
* Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections.
|
|
*/
|
|
typedef enum _iomuxc_sw_pad_ctl_pad
|
|
{
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00 = 0U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01 = 1U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02 = 2U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03 = 3U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04 = 4U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05 = 5U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06 = 6U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07 = 7U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08 = 8U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09 = 9U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10 = 10U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11 = 11U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12 = 12U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13 = 13U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14 = 14U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15 = 15U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16 = 16U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17 = 17U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18 = 18U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19 = 19U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20 = 20U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21 = 21U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22 = 22U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23 = 23U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24 = 24U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25 = 25U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26 = 26U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27 = 27U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28 = 28U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29 = 29U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30 = 30U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31 = 31U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 = 32U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33 = 33U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34 = 34U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35 = 35U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36 = 36U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37 = 37U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38 = 38U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39 = 39U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40 = 40U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41 = 41U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00 = 42U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01 = 43U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02 = 44U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03 = 45U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04 = 46U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05 = 47U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06 = 48U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07 = 49U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08 = 50U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09 = 51U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10 = 52U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11 = 53U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12 = 54U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13 = 55U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14 = 56U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15 = 57U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00 = 58U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01 = 59U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02 = 60U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03 = 61U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04 = 62U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05 = 63U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06 = 64U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07 = 65U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08 = 66U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09 = 67U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10 = 68U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11 = 69U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12 = 70U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13 = 71U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14 = 72U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15 = 73U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00 = 74U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01 = 75U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02 = 76U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 = 77U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_04 = 78U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_05 = 79U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_06 = 80U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_07 = 81U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_08 = 82U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_09 = 83U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10 = 84U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11 = 85U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12 = 86U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_13 = 87U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_14 = 88U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_15 = 89U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00 = 90U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01 = 91U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02 = 92U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03 = 93U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04 = 94U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05 = 95U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06 = 96U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07 = 97U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08 = 98U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09 = 99U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10 = 100U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11 = 101U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12 = 102U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13 = 103U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_14 = 104U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_15 = 105U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 = 106U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01 = 107U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02 = 108U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03 = 109U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04 = 110U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05 = 111U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 = 112U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 = 113U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 = 114U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 = 115U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 = 116U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 = 117U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06 = 118U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07 = 119U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08 = 120U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09 = 121U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10 = 122U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11 = 123U, /**< IOMUXC SW_PAD_CTL_PAD index */
|
|
} iomuxc_sw_pad_ctl_pad_t;
|
|
|
|
/* @} */
|
|
|
|
/*!
|
|
* @brief Enumeration for the IOMUXC select input
|
|
*
|
|
* Defines the enumeration for the IOMUXC select input collections.
|
|
*/
|
|
typedef enum _iomuxc_select_input
|
|
{
|
|
kIOMUXC_ANATOP_USB_OTG1_ID_SELECT_INPUT = 0U, /**< IOMUXC select input index */
|
|
kIOMUXC_ANATOP_USB_OTG2_ID_SELECT_INPUT = 1U, /**< IOMUXC select input index */
|
|
kIOMUXC_CCM_PMIC_READY_SELECT_INPUT = 2U, /**< IOMUXC select input index */
|
|
kIOMUXC_CSI_DATA02_SELECT_INPUT = 3U, /**< IOMUXC select input index */
|
|
kIOMUXC_CSI_DATA03_SELECT_INPUT = 4U, /**< IOMUXC select input index */
|
|
kIOMUXC_CSI_DATA04_SELECT_INPUT = 5U, /**< IOMUXC select input index */
|
|
kIOMUXC_CSI_DATA05_SELECT_INPUT = 6U, /**< IOMUXC select input index */
|
|
kIOMUXC_CSI_DATA06_SELECT_INPUT = 7U, /**< IOMUXC select input index */
|
|
kIOMUXC_CSI_DATA07_SELECT_INPUT = 8U, /**< IOMUXC select input index */
|
|
kIOMUXC_CSI_DATA08_SELECT_INPUT = 9U, /**< IOMUXC select input index */
|
|
kIOMUXC_CSI_DATA09_SELECT_INPUT = 10U, /**< IOMUXC select input index */
|
|
kIOMUXC_CSI_HSYNC_SELECT_INPUT = 11U, /**< IOMUXC select input index */
|
|
kIOMUXC_CSI_PIXCLK_SELECT_INPUT = 12U, /**< IOMUXC select input index */
|
|
kIOMUXC_CSI_VSYNC_SELECT_INPUT = 13U, /**< IOMUXC select input index */
|
|
kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT = 14U, /**< IOMUXC select input index */
|
|
kIOMUXC_ENET_MDIO_SELECT_INPUT = 15U, /**< IOMUXC select input index */
|
|
kIOMUXC_ENET0_RXDATA_SELECT_INPUT = 16U, /**< IOMUXC select input index */
|
|
kIOMUXC_ENET1_RXDATA_SELECT_INPUT = 17U, /**< IOMUXC select input index */
|
|
kIOMUXC_ENET_RXEN_SELECT_INPUT = 18U, /**< IOMUXC select input index */
|
|
kIOMUXC_ENET_RXERR_SELECT_INPUT = 19U, /**< IOMUXC select input index */
|
|
kIOMUXC_ENET0_TIMER_SELECT_INPUT = 20U, /**< IOMUXC select input index */
|
|
kIOMUXC_ENET_TXCLK_SELECT_INPUT = 21U, /**< IOMUXC select input index */
|
|
kIOMUXC_FLEXCAN1_RX_SELECT_INPUT = 22U, /**< IOMUXC select input index */
|
|
kIOMUXC_FLEXCAN2_RX_SELECT_INPUT = 23U, /**< IOMUXC select input index */
|
|
kIOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT = 24U, /**< IOMUXC select input index */
|
|
kIOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT = 25U, /**< IOMUXC select input index */
|
|
kIOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT = 26U, /**< IOMUXC select input index */
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kIOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT = 27U, /**< IOMUXC select input index */
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kIOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT = 28U, /**< IOMUXC select input index */
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kIOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT = 29U, /**< IOMUXC select input index */
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kIOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT = 30U, /**< IOMUXC select input index */
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kIOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT = 31U, /**< IOMUXC select input index */
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kIOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT = 32U, /**< IOMUXC select input index */
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kIOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT = 33U, /**< IOMUXC select input index */
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kIOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT = 34U, /**< IOMUXC select input index */
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kIOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT = 35U, /**< IOMUXC select input index */
|
|
kIOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT = 36U, /**< IOMUXC select input index */
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kIOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT = 37U, /**< IOMUXC select input index */
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kIOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT = 38U, /**< IOMUXC select input index */
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|
kIOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT = 39U, /**< IOMUXC select input index */
|
|
kIOMUXC_FLEXPWM4_PWMA0_SELECT_INPUT = 40U, /**< IOMUXC select input index */
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kIOMUXC_FLEXPWM4_PWMA1_SELECT_INPUT = 41U, /**< IOMUXC select input index */
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|
kIOMUXC_FLEXPWM4_PWMA2_SELECT_INPUT = 42U, /**< IOMUXC select input index */
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|
kIOMUXC_FLEXPWM4_PWMA3_SELECT_INPUT = 43U, /**< IOMUXC select input index */
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|
kIOMUXC_FLEXSPIA_DQS_SELECT_INPUT = 44U, /**< IOMUXC select input index */
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|
kIOMUXC_FLEXSPIA_DATA0_SELECT_INPUT = 45U, /**< IOMUXC select input index */
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|
kIOMUXC_FLEXSPIA_DATA1_SELECT_INPUT = 46U, /**< IOMUXC select input index */
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kIOMUXC_FLEXSPIA_DATA2_SELECT_INPUT = 47U, /**< IOMUXC select input index */
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|
kIOMUXC_FLEXSPIA_DATA3_SELECT_INPUT = 48U, /**< IOMUXC select input index */
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|
kIOMUXC_FLEXSPIB_DATA0_SELECT_INPUT = 49U, /**< IOMUXC select input index */
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kIOMUXC_FLEXSPIB_DATA1_SELECT_INPUT = 50U, /**< IOMUXC select input index */
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|
kIOMUXC_FLEXSPIB_DATA2_SELECT_INPUT = 51U, /**< IOMUXC select input index */
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|
kIOMUXC_FLEXSPIB_DATA3_SELECT_INPUT = 52U, /**< IOMUXC select input index */
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|
kIOMUXC_FLEXSPIA_SCK_SELECT_INPUT = 53U, /**< IOMUXC select input index */
|
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kIOMUXC_LPI2C1_SCL_SELECT_INPUT = 54U, /**< IOMUXC select input index */
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kIOMUXC_LPI2C1_SDA_SELECT_INPUT = 55U, /**< IOMUXC select input index */
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kIOMUXC_LPI2C2_SCL_SELECT_INPUT = 56U, /**< IOMUXC select input index */
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|
kIOMUXC_LPI2C2_SDA_SELECT_INPUT = 57U, /**< IOMUXC select input index */
|
|
kIOMUXC_LPI2C3_SCL_SELECT_INPUT = 58U, /**< IOMUXC select input index */
|
|
kIOMUXC_LPI2C3_SDA_SELECT_INPUT = 59U, /**< IOMUXC select input index */
|
|
kIOMUXC_LPI2C4_SCL_SELECT_INPUT = 60U, /**< IOMUXC select input index */
|
|
kIOMUXC_LPI2C4_SDA_SELECT_INPUT = 61U, /**< IOMUXC select input index */
|
|
kIOMUXC_LPSPI1_PCS0_SELECT_INPUT = 62U, /**< IOMUXC select input index */
|
|
kIOMUXC_LPSPI1_SCK_SELECT_INPUT = 63U, /**< IOMUXC select input index */
|
|
kIOMUXC_LPSPI1_SDI_SELECT_INPUT = 64U, /**< IOMUXC select input index */
|
|
kIOMUXC_LPSPI1_SDO_SELECT_INPUT = 65U, /**< IOMUXC select input index */
|
|
kIOMUXC_LPSPI2_PCS0_SELECT_INPUT = 66U, /**< IOMUXC select input index */
|
|
kIOMUXC_LPSPI2_SCK_SELECT_INPUT = 67U, /**< IOMUXC select input index */
|
|
kIOMUXC_LPSPI2_SDI_SELECT_INPUT = 68U, /**< IOMUXC select input index */
|
|
kIOMUXC_LPSPI2_SDO_SELECT_INPUT = 69U, /**< IOMUXC select input index */
|
|
kIOMUXC_LPSPI3_PCS0_SELECT_INPUT = 70U, /**< IOMUXC select input index */
|
|
kIOMUXC_LPSPI3_SCK_SELECT_INPUT = 71U, /**< IOMUXC select input index */
|
|
kIOMUXC_LPSPI3_SDI_SELECT_INPUT = 72U, /**< IOMUXC select input index */
|
|
kIOMUXC_LPSPI3_SDO_SELECT_INPUT = 73U, /**< IOMUXC select input index */
|
|
kIOMUXC_LPSPI4_PCS0_SELECT_INPUT = 74U, /**< IOMUXC select input index */
|
|
kIOMUXC_LPSPI4_SCK_SELECT_INPUT = 75U, /**< IOMUXC select input index */
|
|
kIOMUXC_LPSPI4_SDI_SELECT_INPUT = 76U, /**< IOMUXC select input index */
|
|
kIOMUXC_LPSPI4_SDO_SELECT_INPUT = 77U, /**< IOMUXC select input index */
|
|
kIOMUXC_LPUART2_RX_SELECT_INPUT = 78U, /**< IOMUXC select input index */
|
|
kIOMUXC_LPUART2_TX_SELECT_INPUT = 79U, /**< IOMUXC select input index */
|
|
kIOMUXC_LPUART3_CTS_B_SELECT_INPUT = 80U, /**< IOMUXC select input index */
|
|
kIOMUXC_LPUART3_RX_SELECT_INPUT = 81U, /**< IOMUXC select input index */
|
|
kIOMUXC_LPUART3_TX_SELECT_INPUT = 82U, /**< IOMUXC select input index */
|
|
kIOMUXC_LPUART4_RX_SELECT_INPUT = 83U, /**< IOMUXC select input index */
|
|
kIOMUXC_LPUART4_TX_SELECT_INPUT = 84U, /**< IOMUXC select input index */
|
|
kIOMUXC_LPUART5_RX_SELECT_INPUT = 85U, /**< IOMUXC select input index */
|
|
kIOMUXC_LPUART5_TX_SELECT_INPUT = 86U, /**< IOMUXC select input index */
|
|
kIOMUXC_LPUART6_RX_SELECT_INPUT = 87U, /**< IOMUXC select input index */
|
|
kIOMUXC_LPUART6_TX_SELECT_INPUT = 88U, /**< IOMUXC select input index */
|
|
kIOMUXC_LPUART7_RX_SELECT_INPUT = 89U, /**< IOMUXC select input index */
|
|
kIOMUXC_LPUART7_TX_SELECT_INPUT = 90U, /**< IOMUXC select input index */
|
|
kIOMUXC_LPUART8_RX_SELECT_INPUT = 91U, /**< IOMUXC select input index */
|
|
kIOMUXC_LPUART8_TX_SELECT_INPUT = 92U, /**< IOMUXC select input index */
|
|
kIOMUXC_NMI_SELECT_INPUT = 93U, /**< IOMUXC select input index */
|
|
kIOMUXC_QTIMER2_TIMER0_SELECT_INPUT = 94U, /**< IOMUXC select input index */
|
|
kIOMUXC_QTIMER2_TIMER1_SELECT_INPUT = 95U, /**< IOMUXC select input index */
|
|
kIOMUXC_QTIMER2_TIMER2_SELECT_INPUT = 96U, /**< IOMUXC select input index */
|
|
kIOMUXC_QTIMER2_TIMER3_SELECT_INPUT = 97U, /**< IOMUXC select input index */
|
|
kIOMUXC_QTIMER3_TIMER0_SELECT_INPUT = 98U, /**< IOMUXC select input index */
|
|
kIOMUXC_QTIMER3_TIMER1_SELECT_INPUT = 99U, /**< IOMUXC select input index */
|
|
kIOMUXC_QTIMER3_TIMER2_SELECT_INPUT = 100U, /**< IOMUXC select input index */
|
|
kIOMUXC_QTIMER3_TIMER3_SELECT_INPUT = 101U, /**< IOMUXC select input index */
|
|
kIOMUXC_SAI1_MCLK2_SELECT_INPUT = 102U, /**< IOMUXC select input index */
|
|
kIOMUXC_SAI1_RX_BCLK_SELECT_INPUT = 103U, /**< IOMUXC select input index */
|
|
kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT = 104U, /**< IOMUXC select input index */
|
|
kIOMUXC_SAI1_RX_DATA1_SELECT_INPUT = 105U, /**< IOMUXC select input index */
|
|
kIOMUXC_SAI1_RX_DATA2_SELECT_INPUT = 106U, /**< IOMUXC select input index */
|
|
kIOMUXC_SAI1_RX_DATA3_SELECT_INPUT = 107U, /**< IOMUXC select input index */
|
|
kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT = 108U, /**< IOMUXC select input index */
|
|
kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT = 109U, /**< IOMUXC select input index */
|
|
kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT = 110U, /**< IOMUXC select input index */
|
|
kIOMUXC_SAI2_MCLK2_SELECT_INPUT = 111U, /**< IOMUXC select input index */
|
|
kIOMUXC_SAI2_RX_BCLK_SELECT_INPUT = 112U, /**< IOMUXC select input index */
|
|
kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT = 113U, /**< IOMUXC select input index */
|
|
kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT = 114U, /**< IOMUXC select input index */
|
|
kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT = 115U, /**< IOMUXC select input index */
|
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kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT = 116U, /**< IOMUXC select input index */
|
|
kIOMUXC_SPDIF_IN_SELECT_INPUT = 117U, /**< IOMUXC select input index */
|
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kIOMUXC_USB_OTG2_OC_SELECT_INPUT = 118U, /**< IOMUXC select input index */
|
|
kIOMUXC_USB_OTG1_OC_SELECT_INPUT = 119U, /**< IOMUXC select input index */
|
|
kIOMUXC_USDHC1_CD_B_SELECT_INPUT = 120U, /**< IOMUXC select input index */
|
|
kIOMUXC_USDHC1_WP_SELECT_INPUT = 121U, /**< IOMUXC select input index */
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kIOMUXC_USDHC2_CLK_SELECT_INPUT = 122U, /**< IOMUXC select input index */
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kIOMUXC_USDHC2_CD_B_SELECT_INPUT = 123U, /**< IOMUXC select input index */
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kIOMUXC_USDHC2_CMD_SELECT_INPUT = 124U, /**< IOMUXC select input index */
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kIOMUXC_USDHC2_DATA0_SELECT_INPUT = 125U, /**< IOMUXC select input index */
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kIOMUXC_USDHC2_DATA1_SELECT_INPUT = 126U, /**< IOMUXC select input index */
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kIOMUXC_USDHC2_DATA2_SELECT_INPUT = 127U, /**< IOMUXC select input index */
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kIOMUXC_USDHC2_DATA3_SELECT_INPUT = 128U, /**< IOMUXC select input index */
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kIOMUXC_USDHC2_DATA4_SELECT_INPUT = 129U, /**< IOMUXC select input index */
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kIOMUXC_USDHC2_DATA5_SELECT_INPUT = 130U, /**< IOMUXC select input index */
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kIOMUXC_USDHC2_DATA6_SELECT_INPUT = 131U, /**< IOMUXC select input index */
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kIOMUXC_USDHC2_DATA7_SELECT_INPUT = 132U, /**< IOMUXC select input index */
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kIOMUXC_USDHC2_WP_SELECT_INPUT = 133U, /**< IOMUXC select input index */
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kIOMUXC_XBAR1_IN02_SELECT_INPUT = 134U, /**< IOMUXC select input index */
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kIOMUXC_XBAR1_IN03_SELECT_INPUT = 135U, /**< IOMUXC select input index */
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kIOMUXC_XBAR1_IN04_SELECT_INPUT = 136U, /**< IOMUXC select input index */
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kIOMUXC_XBAR1_IN05_SELECT_INPUT = 137U, /**< IOMUXC select input index */
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kIOMUXC_XBAR1_IN06_SELECT_INPUT = 138U, /**< IOMUXC select input index */
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kIOMUXC_XBAR1_IN07_SELECT_INPUT = 139U, /**< IOMUXC select input index */
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kIOMUXC_XBAR1_IN08_SELECT_INPUT = 140U, /**< IOMUXC select input index */
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kIOMUXC_XBAR1_IN09_SELECT_INPUT = 141U, /**< IOMUXC select input index */
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kIOMUXC_XBAR1_IN17_SELECT_INPUT = 142U, /**< IOMUXC select input index */
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kIOMUXC_XBAR1_IN18_SELECT_INPUT = 143U, /**< IOMUXC select input index */
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kIOMUXC_XBAR1_IN20_SELECT_INPUT = 144U, /**< IOMUXC select input index */
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kIOMUXC_XBAR1_IN22_SELECT_INPUT = 145U, /**< IOMUXC select input index */
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kIOMUXC_XBAR1_IN23_SELECT_INPUT = 146U, /**< IOMUXC select input index */
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kIOMUXC_XBAR1_IN24_SELECT_INPUT = 147U, /**< IOMUXC select input index */
|
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kIOMUXC_XBAR1_IN14_SELECT_INPUT = 148U, /**< IOMUXC select input index */
|
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kIOMUXC_XBAR1_IN15_SELECT_INPUT = 149U, /**< IOMUXC select input index */
|
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kIOMUXC_XBAR1_IN16_SELECT_INPUT = 150U, /**< IOMUXC select input index */
|
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kIOMUXC_XBAR1_IN25_SELECT_INPUT = 151U, /**< IOMUXC select input index */
|
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kIOMUXC_XBAR1_IN19_SELECT_INPUT = 152U, /**< IOMUXC select input index */
|
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kIOMUXC_XBAR1_IN21_SELECT_INPUT = 153U, /**< IOMUXC select input index */
|
|
} iomuxc_select_input_t;
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|
|
|
typedef enum _xbar_input_signal
|
|
{
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kXBARA1_InputLogicLow = 0|0x100U, /**< LOGIC_LOW output assigned to XBARA1_IN0 input. */
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kXBARA1_InputLogicHigh = 1|0x100U, /**< LOGIC_HIGH output assigned to XBARA1_IN1 input. */
|
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kXBARA1_InputIomuxXbarIn02 = 2|0x100U, /**< IOMUX_XBAR_IN02 output assigned to XBARA1_IN2 input. */
|
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kXBARA1_InputIomuxXbarIn03 = 3|0x100U, /**< IOMUX_XBAR_IN03 output assigned to XBARA1_IN3 input. */
|
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kXBARA1_InputIomuxXbarInout04 = 4|0x100U, /**< IOMUX_XBAR_INOUT04 output assigned to XBARA1_IN4 input. */
|
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kXBARA1_InputIomuxXbarInout05 = 5|0x100U, /**< IOMUX_XBAR_INOUT05 output assigned to XBARA1_IN5 input. */
|
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kXBARA1_InputIomuxXbarInout06 = 6|0x100U, /**< IOMUX_XBAR_INOUT06 output assigned to XBARA1_IN6 input. */
|
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kXBARA1_InputIomuxXbarInout07 = 7|0x100U, /**< IOMUX_XBAR_INOUT07 output assigned to XBARA1_IN7 input. */
|
|
kXBARA1_InputIomuxXbarInout08 = 8|0x100U, /**< IOMUX_XBAR_INOUT08 output assigned to XBARA1_IN8 input. */
|
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kXBARA1_InputIomuxXbarInout09 = 9|0x100U, /**< IOMUX_XBAR_INOUT09 output assigned to XBARA1_IN9 input. */
|
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kXBARA1_InputIomuxXbarInout10 = 10|0x100U, /**< IOMUX_XBAR_INOUT10 output assigned to XBARA1_IN10 input. */
|
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kXBARA1_InputIomuxXbarInout11 = 11|0x100U, /**< IOMUX_XBAR_INOUT11 output assigned to XBARA1_IN11 input. */
|
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kXBARA1_InputIomuxXbarInout12 = 12|0x100U, /**< IOMUX_XBAR_INOUT12 output assigned to XBARA1_IN12 input. */
|
|
kXBARA1_InputIomuxXbarInout13 = 13|0x100U, /**< IOMUX_XBAR_INOUT13 output assigned to XBARA1_IN13 input. */
|
|
kXBARA1_InputIomuxXbarInout14 = 14|0x100U, /**< IOMUX_XBAR_INOUT14 output assigned to XBARA1_IN14 input. */
|
|
kXBARA1_InputIomuxXbarInout15 = 15|0x100U, /**< IOMUX_XBAR_INOUT15 output assigned to XBARA1_IN15 input. */
|
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kXBARA1_InputIomuxXbarInout16 = 16|0x100U, /**< IOMUX_XBAR_INOUT16 output assigned to XBARA1_IN16 input. */
|
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kXBARA1_InputIomuxXbarInout17 = 17|0x100U, /**< IOMUX_XBAR_INOUT17 output assigned to XBARA1_IN17 input. */
|
|
kXBARA1_InputIomuxXbarInout18 = 18|0x100U, /**< IOMUX_XBAR_INOUT18 output assigned to XBARA1_IN18 input. */
|
|
kXBARA1_InputIomuxXbarInout19 = 19|0x100U, /**< IOMUX_XBAR_INOUT19 output assigned to XBARA1_IN19 input. */
|
|
kXBARA1_InputIomuxXbarIn20 = 20|0x100U, /**< IOMUX_XBAR_IN20 output assigned to XBARA1_IN20 input. */
|
|
kXBARA1_InputIomuxXbarIn21 = 21|0x100U, /**< IOMUX_XBAR_IN21 output assigned to XBARA1_IN21 input. */
|
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kXBARA1_InputIomuxXbarIn22 = 22|0x100U, /**< IOMUX_XBAR_IN22 output assigned to XBARA1_IN22 input. */
|
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kXBARA1_InputIomuxXbarIn23 = 23|0x100U, /**< IOMUX_XBAR_IN23 output assigned to XBARA1_IN23 input. */
|
|
kXBARA1_InputIomuxXbarIn24 = 24|0x100U, /**< IOMUX_XBAR_IN24 output assigned to XBARA1_IN24 input. */
|
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kXBARA1_InputIomuxXbarIn25 = 25|0x100U, /**< IOMUX_XBAR_IN25 output assigned to XBARA1_IN25 input. */
|
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kXBARA1_InputAcmp1Out = 26|0x100U, /**< ACMP1_OUT output assigned to XBARA1_IN26 input. */
|
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kXBARA1_InputAcmp2Out = 27|0x100U, /**< ACMP2_OUT output assigned to XBARA1_IN27 input. */
|
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kXBARA1_InputAcmp3Out = 28|0x100U, /**< ACMP3_OUT output assigned to XBARA1_IN28 input. */
|
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kXBARA1_InputAcmp4Out = 29|0x100U, /**< ACMP4_OUT output assigned to XBARA1_IN29 input. */
|
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kXBARA1_InputRESERVED30 = 30|0x100U, /**< XBARA1_IN30 input is reserved. */
|
|
kXBARA1_InputRESERVED31 = 31|0x100U, /**< XBARA1_IN31 input is reserved. */
|
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kXBARA1_InputQtimer3Tmr0Output = 32|0x100U, /**< QTIMER3_TMR0_OUTPUT output assigned to XBARA1_IN32 input. */
|
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kXBARA1_InputQtimer3Tmr1Output = 33|0x100U, /**< QTIMER3_TMR1_OUTPUT output assigned to XBARA1_IN33 input. */
|
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kXBARA1_InputQtimer3Tmr2Output = 34|0x100U, /**< QTIMER3_TMR2_OUTPUT output assigned to XBARA1_IN34 input. */
|
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kXBARA1_InputQtimer3Tmr3Output = 35|0x100U, /**< QTIMER3_TMR3_OUTPUT output assigned to XBARA1_IN35 input. */
|
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kXBARA1_InputQtimer4Tmr0Output = 36|0x100U, /**< QTIMER4_TMR0_OUTPUT output assigned to XBARA1_IN36 input. */
|
|
kXBARA1_InputQtimer4Tmr1Output = 37|0x100U, /**< QTIMER4_TMR1_OUTPUT output assigned to XBARA1_IN37 input. */
|
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kXBARA1_InputQtimer4Tmr2Output = 38|0x100U, /**< QTIMER4_TMR2_OUTPUT output assigned to XBARA1_IN38 input. */
|
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kXBARA1_InputQtimer4Tmr3Output = 39|0x100U, /**< QTIMER4_TMR3_OUTPUT output assigned to XBARA1_IN39 input. */
|
|
kXBARA1_InputFlexpwm1Pwm1OutTrig01 = 40|0x100U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN40 input. */
|
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kXBARA1_InputFlexpwm1Pwm2OutTrig01 = 41|0x100U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN41 input. */
|
|
kXBARA1_InputFlexpwm1Pwm3OutTrig01 = 42|0x100U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN42 input. */
|
|
kXBARA1_InputFlexpwm1Pwm4OutTrig01 = 43|0x100U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN43 input. */
|
|
kXBARA1_InputFlexpwm2Pwm1OutTrig01 = 44|0x100U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN44 input. */
|
|
kXBARA1_InputFlexpwm2Pwm2OutTrig01 = 45|0x100U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN45 input. */
|
|
kXBARA1_InputFlexpwm2Pwm3OutTrig01 = 46|0x100U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN46 input. */
|
|
kXBARA1_InputFlexpwm2Pwm4OutTrig01 = 47|0x100U, /**< FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN47 input. */
|
|
kXBARA1_InputFlexpwm3Pwm1OutTrig01 = 48|0x100U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN48 input. */
|
|
kXBARA1_InputFlexpwm3Pwm2OutTrig01 = 49|0x100U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN49 input. */
|
|
kXBARA1_InputFlexpwm3Pwm3OutTrig01 = 50|0x100U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN50 input. */
|
|
kXBARA1_InputFlexpwm3Pwm4OutTrig01 = 51|0x100U, /**< FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN51 input. */
|
|
kXBARA1_InputFlexpwm4Pwm1OutTrig01 = 52|0x100U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN52 input. */
|
|
kXBARA1_InputFlexpwm4Pwm2OutTrig01 = 53|0x100U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN53 input. */
|
|
kXBARA1_InputFlexpwm4Pwm3OutTrig01 = 54|0x100U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN54 input. */
|
|
kXBARA1_InputFlexpwm4Pwm4OutTrig01 = 55|0x100U, /**< FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN55 input. */
|
|
kXBARA1_InputPitTrigger0 = 56|0x100U, /**< PIT_TRIGGER0 output assigned to XBARA1_IN56 input. */
|
|
kXBARA1_InputPitTrigger1 = 57|0x100U, /**< PIT_TRIGGER1 output assigned to XBARA1_IN57 input. */
|
|
kXBARA1_InputPitTrigger2 = 58|0x100U, /**< PIT_TRIGGER2 output assigned to XBARA1_IN58 input. */
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kXBARA1_InputPitTrigger3 = 59|0x100U, /**< PIT_TRIGGER3 output assigned to XBARA1_IN59 input. */
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kXBARA1_InputEnc1PosMatch = 60|0x100U, /**< ENC1_POS_MATCH output assigned to XBARA1_IN60 input. */
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kXBARA1_InputEnc2PosMatch = 61|0x100U, /**< ENC2_POS_MATCH output assigned to XBARA1_IN61 input. */
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kXBARA1_InputEnc3PosMatch = 62|0x100U, /**< ENC3_POS_MATCH output assigned to XBARA1_IN62 input. */
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kXBARA1_InputEnc4PosMatch = 63|0x100U, /**< ENC4_POS_MATCH output assigned to XBARA1_IN63 input. */
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kXBARA1_InputDmaDone0 = 64|0x100U, /**< DMA_DONE0 output assigned to XBARA1_IN64 input. */
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kXBARA1_InputDmaDone1 = 65|0x100U, /**< DMA_DONE1 output assigned to XBARA1_IN65 input. */
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kXBARA1_InputDmaDone2 = 66|0x100U, /**< DMA_DONE2 output assigned to XBARA1_IN66 input. */
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kXBARA1_InputDmaDone3 = 67|0x100U, /**< DMA_DONE3 output assigned to XBARA1_IN67 input. */
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kXBARA1_InputDmaDone4 = 68|0x100U, /**< DMA_DONE4 output assigned to XBARA1_IN68 input. */
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kXBARA1_InputDmaDone5 = 69|0x100U, /**< DMA_DONE5 output assigned to XBARA1_IN69 input. */
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kXBARA1_InputDmaDone6 = 70|0x100U, /**< DMA_DONE6 output assigned to XBARA1_IN70 input. */
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kXBARA1_InputDmaDone7 = 71|0x100U, /**< DMA_DONE7 output assigned to XBARA1_IN71 input. */
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kXBARA1_InputAoi1Out0 = 72|0x100U, /**< AOI1_OUT0 output assigned to XBARA1_IN72 input. */
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kXBARA1_InputAoi1Out1 = 73|0x100U, /**< AOI1_OUT1 output assigned to XBARA1_IN73 input. */
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kXBARA1_InputAoi1Out2 = 74|0x100U, /**< AOI1_OUT2 output assigned to XBARA1_IN74 input. */
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kXBARA1_InputAoi1Out3 = 75|0x100U, /**< AOI1_OUT3 output assigned to XBARA1_IN75 input. */
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kXBARA1_InputAoi2Out0 = 76|0x100U, /**< AOI2_OUT0 output assigned to XBARA1_IN76 input. */
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kXBARA1_InputAoi2Out1 = 77|0x100U, /**< AOI2_OUT1 output assigned to XBARA1_IN77 input. */
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kXBARA1_InputAoi2Out2 = 78|0x100U, /**< AOI2_OUT2 output assigned to XBARA1_IN78 input. */
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kXBARA1_InputAoi2Out3 = 79|0x100U, /**< AOI2_OUT3 output assigned to XBARA1_IN79 input. */
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kXBARA1_InputAdcEtcXbar0Coco0 = 80|0x100U, /**< ADC_ETC_XBAR0_COCO0 output assigned to XBARA1_IN80 input. */
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kXBARA1_InputAdcEtcXbar0Coco1 = 81|0x100U, /**< ADC_ETC_XBAR0_COCO1 output assigned to XBARA1_IN81 input. */
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kXBARA1_InputAdcEtcXbar0Coco2 = 82|0x100U, /**< ADC_ETC_XBAR0_COCO2 output assigned to XBARA1_IN82 input. */
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kXBARA1_InputAdcEtcXbar0Coco3 = 83|0x100U, /**< ADC_ETC_XBAR0_COCO3 output assigned to XBARA1_IN83 input. */
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kXBARA1_InputAdcEtcXbar1Coco0 = 84|0x100U, /**< ADC_ETC_XBAR1_COCO0 output assigned to XBARA1_IN84 input. */
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kXBARA1_InputAdcEtcXbar1Coco1 = 85|0x100U, /**< ADC_ETC_XBAR1_COCO1 output assigned to XBARA1_IN85 input. */
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kXBARA1_InputAdcEtcXbar1Coco2 = 86|0x100U, /**< ADC_ETC_XBAR1_COCO2 output assigned to XBARA1_IN86 input. */
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kXBARA1_InputAdcEtcXbar1Coco3 = 87|0x100U, /**< ADC_ETC_XBAR1_COCO3 output assigned to XBARA1_IN87 input. */
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kXBARB2_InputLogicLow = 0|0x200U, /**< LOGIC_LOW output assigned to XBARB2_IN0 input. */
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kXBARB2_InputLogicHigh = 1|0x200U, /**< LOGIC_HIGH output assigned to XBARB2_IN1 input. */
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kXBARB2_InputRESERVED2 = 2|0x200U, /**< XBARB2_IN2 input is reserved. */
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kXBARB2_InputRESERVED3 = 3|0x200U, /**< XBARB2_IN3 input is reserved. */
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kXBARB2_InputRESERVED4 = 4|0x200U, /**< XBARB2_IN4 input is reserved. */
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kXBARB2_InputRESERVED5 = 5|0x200U, /**< XBARB2_IN5 input is reserved. */
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kXBARB2_InputAcmp1Out = 6|0x200U, /**< ACMP1_OUT output assigned to XBARB2_IN6 input. */
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kXBARB2_InputAcmp2Out = 7|0x200U, /**< ACMP2_OUT output assigned to XBARB2_IN7 input. */
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kXBARB2_InputAcmp3Out = 8|0x200U, /**< ACMP3_OUT output assigned to XBARB2_IN8 input. */
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kXBARB2_InputAcmp4Out = 9|0x200U, /**< ACMP4_OUT output assigned to XBARB2_IN9 input. */
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kXBARB2_InputRESERVED10 = 10|0x200U, /**< XBARB2_IN10 input is reserved. */
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kXBARB2_InputRESERVED11 = 11|0x200U, /**< XBARB2_IN11 input is reserved. */
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kXBARB2_InputQtimer3Tmr0Output = 12|0x200U, /**< QTIMER3_TMR0_OUTPUT output assigned to XBARB2_IN12 input. */
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kXBARB2_InputQtimer3Tmr1Output = 13|0x200U, /**< QTIMER3_TMR1_OUTPUT output assigned to XBARB2_IN13 input. */
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kXBARB2_InputQtimer3Tmr2Output = 14|0x200U, /**< QTIMER3_TMR2_OUTPUT output assigned to XBARB2_IN14 input. */
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kXBARB2_InputQtimer3Tmr3Output = 15|0x200U, /**< QTIMER3_TMR3_OUTPUT output assigned to XBARB2_IN15 input. */
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kXBARB2_InputQtimer4Tmr0Output = 16|0x200U, /**< QTIMER4_TMR0_OUTPUT output assigned to XBARB2_IN16 input. */
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kXBARB2_InputQtimer4Tmr1Output = 17|0x200U, /**< QTIMER4_TMR1_OUTPUT output assigned to XBARB2_IN17 input. */
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kXBARB2_InputQtimer4Tmr2Output = 18|0x200U, /**< QTIMER4_TMR2_OUTPUT output assigned to XBARB2_IN18 input. */
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kXBARB2_InputQtimer4Tmr3Output = 19|0x200U, /**< QTIMER4_TMR3_OUTPUT output assigned to XBARB2_IN19 input. */
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kXBARB2_InputFlexpwm1Pwm1OutTrig01 = 20|0x200U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN20 input. */
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kXBARB2_InputFlexpwm1Pwm2OutTrig01 = 21|0x200U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN21 input. */
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kXBARB2_InputFlexpwm1Pwm3OutTrig01 = 22|0x200U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN22 input. */
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kXBARB2_InputFlexpwm1Pwm4OutTrig01 = 23|0x200U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN23 input. */
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kXBARB2_InputFlexpwm2Pwm1OutTrig01 = 24|0x200U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN24 input. */
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kXBARB2_InputFlexpwm2Pwm2OutTrig01 = 25|0x200U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN25 input. */
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kXBARB2_InputFlexpwm2Pwm3OutTrig01 = 26|0x200U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN26 input. */
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kXBARB2_InputFlexpwm2Pwm4OutTrig01 = 27|0x200U, /**< FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN27 input. */
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kXBARB2_InputFlexpwm3Pwm1OutTrig01 = 28|0x200U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN28 input. */
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kXBARB2_InputFlexpwm3Pwm2OutTrig01 = 29|0x200U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN29 input. */
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kXBARB2_InputFlexpwm3Pwm3OutTrig01 = 30|0x200U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN30 input. */
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kXBARB2_InputFlexpwm3Pwm4OutTrig01 = 31|0x200U, /**< FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN31 input. */
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kXBARB2_InputFlexpwm4Pwm1OutTrig01 = 32|0x200U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN32 input. */
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kXBARB2_InputFlexpwm4Pwm2OutTrig01 = 33|0x200U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN33 input. */
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kXBARB2_InputFlexpwm4Pwm3OutTrig01 = 34|0x200U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN34 input. */
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kXBARB2_InputFlexpwm4Pwm4OutTrig01 = 35|0x200U, /**< FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN35 input. */
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kXBARB2_InputPitTrigger0 = 36|0x200U, /**< PIT_TRIGGER0 output assigned to XBARB2_IN36 input. */
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kXBARB2_InputPitTrigger1 = 37|0x200U, /**< PIT_TRIGGER1 output assigned to XBARB2_IN37 input. */
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kXBARB2_InputAdcEtcXbar0Coco0 = 38|0x200U, /**< ADC_ETC_XBAR0_COCO0 output assigned to XBARB2_IN38 input. */
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kXBARB2_InputAdcEtcXbar0Coco1 = 39|0x200U, /**< ADC_ETC_XBAR0_COCO1 output assigned to XBARB2_IN39 input. */
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kXBARB2_InputAdcEtcXbar0Coco2 = 40|0x200U, /**< ADC_ETC_XBAR0_COCO2 output assigned to XBARB2_IN40 input. */
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kXBARB2_InputAdcEtcXbar0Coco3 = 41|0x200U, /**< ADC_ETC_XBAR0_COCO3 output assigned to XBARB2_IN41 input. */
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kXBARB2_InputAdcEtcXbar1Coco0 = 42|0x200U, /**< ADC_ETC_XBAR1_COCO0 output assigned to XBARB2_IN42 input. */
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kXBARB2_InputAdcEtcXbar1Coco1 = 43|0x200U, /**< ADC_ETC_XBAR1_COCO1 output assigned to XBARB2_IN43 input. */
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kXBARB2_InputAdcEtcXbar1Coco2 = 44|0x200U, /**< ADC_ETC_XBAR1_COCO2 output assigned to XBARB2_IN44 input. */
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kXBARB2_InputAdcEtcXbar1Coco3 = 45|0x200U, /**< ADC_ETC_XBAR1_COCO3 output assigned to XBARB2_IN45 input. */
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kXBARB2_InputEnc1PosMatch = 46|0x200U, /**< ENC1_POS_MATCH output assigned to XBARB2_IN46 input. */
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kXBARB2_InputEnc2PosMatch = 47|0x200U, /**< ENC2_POS_MATCH output assigned to XBARB2_IN47 input. */
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kXBARB2_InputEnc3PosMatch = 48|0x200U, /**< ENC3_POS_MATCH output assigned to XBARB2_IN48 input. */
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kXBARB2_InputEnc4PosMatch = 49|0x200U, /**< ENC4_POS_MATCH output assigned to XBARB2_IN49 input. */
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kXBARB2_InputDmaDone0 = 50|0x200U, /**< DMA_DONE0 output assigned to XBARB2_IN50 input. */
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kXBARB2_InputDmaDone1 = 51|0x200U, /**< DMA_DONE1 output assigned to XBARB2_IN51 input. */
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kXBARB2_InputDmaDone2 = 52|0x200U, /**< DMA_DONE2 output assigned to XBARB2_IN52 input. */
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kXBARB2_InputDmaDone3 = 53|0x200U, /**< DMA_DONE3 output assigned to XBARB2_IN53 input. */
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kXBARB2_InputDmaDone4 = 54|0x200U, /**< DMA_DONE4 output assigned to XBARB2_IN54 input. */
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kXBARB2_InputDmaDone5 = 55|0x200U, /**< DMA_DONE5 output assigned to XBARB2_IN55 input. */
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kXBARB2_InputDmaDone6 = 56|0x200U, /**< DMA_DONE6 output assigned to XBARB2_IN56 input. */
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kXBARB2_InputDmaDone7 = 57|0x200U, /**< DMA_DONE7 output assigned to XBARB2_IN57 input. */
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kXBARB3_InputLogicLow = 0|0x300U, /**< LOGIC_LOW output assigned to XBARB3_IN0 input. */
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kXBARB3_InputLogicHigh = 1|0x300U, /**< LOGIC_HIGH output assigned to XBARB3_IN1 input. */
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kXBARB3_InputRESERVED2 = 2|0x300U, /**< XBARB3_IN2 input is reserved. */
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kXBARB3_InputRESERVED3 = 3|0x300U, /**< XBARB3_IN3 input is reserved. */
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kXBARB3_InputRESERVED4 = 4|0x300U, /**< XBARB3_IN4 input is reserved. */
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kXBARB3_InputRESERVED5 = 5|0x300U, /**< XBARB3_IN5 input is reserved. */
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kXBARB3_InputAcmp1Out = 6|0x300U, /**< ACMP1_OUT output assigned to XBARB3_IN6 input. */
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kXBARB3_InputAcmp2Out = 7|0x300U, /**< ACMP2_OUT output assigned to XBARB3_IN7 input. */
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kXBARB3_InputAcmp3Out = 8|0x300U, /**< ACMP3_OUT output assigned to XBARB3_IN8 input. */
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kXBARB3_InputAcmp4Out = 9|0x300U, /**< ACMP4_OUT output assigned to XBARB3_IN9 input. */
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kXBARB3_InputRESERVED10 = 10|0x300U, /**< XBARB3_IN10 input is reserved. */
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kXBARB3_InputRESERVED11 = 11|0x300U, /**< XBARB3_IN11 input is reserved. */
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kXBARB3_InputQtimer3Tmr0Output = 12|0x300U, /**< QTIMER3_TMR0_OUTPUT output assigned to XBARB3_IN12 input. */
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kXBARB3_InputQtimer3Tmr1Output = 13|0x300U, /**< QTIMER3_TMR1_OUTPUT output assigned to XBARB3_IN13 input. */
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kXBARB3_InputQtimer3Tmr2Output = 14|0x300U, /**< QTIMER3_TMR2_OUTPUT output assigned to XBARB3_IN14 input. */
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kXBARB3_InputQtimer3Tmr3Output = 15|0x300U, /**< QTIMER3_TMR3_OUTPUT output assigned to XBARB3_IN15 input. */
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kXBARB3_InputQtimer4Tmr0Output = 16|0x300U, /**< QTIMER4_TMR0_OUTPUT output assigned to XBARB3_IN16 input. */
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kXBARB3_InputQtimer4Tmr1Output = 17|0x300U, /**< QTIMER4_TMR1_OUTPUT output assigned to XBARB3_IN17 input. */
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kXBARB3_InputQtimer4Tmr2Output = 18|0x300U, /**< QTIMER4_TMR2_OUTPUT output assigned to XBARB3_IN18 input. */
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kXBARB3_InputQtimer4Tmr3Output = 19|0x300U, /**< QTIMER4_TMR3_OUTPUT output assigned to XBARB3_IN19 input. */
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kXBARB3_InputFlexpwm1Pwm1OutTrig01 = 20|0x300U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN20 input. */
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kXBARB3_InputFlexpwm1Pwm2OutTrig01 = 21|0x300U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN21 input. */
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kXBARB3_InputFlexpwm1Pwm3OutTrig01 = 22|0x300U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN22 input. */
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kXBARB3_InputFlexpwm1Pwm4OutTrig01 = 23|0x300U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN23 input. */
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kXBARB3_InputFlexpwm2Pwm1OutTrig01 = 24|0x300U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN24 input. */
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kXBARB3_InputFlexpwm2Pwm2OutTrig01 = 25|0x300U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN25 input. */
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kXBARB3_InputFlexpwm2Pwm3OutTrig01 = 26|0x300U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN26 input. */
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kXBARB3_InputFlexpwm2Pwm4OutTrig01 = 27|0x300U, /**< FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN27 input. */
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kXBARB3_InputFlexpwm3Pwm1OutTrig01 = 28|0x300U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN28 input. */
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kXBARB3_InputFlexpwm3Pwm2OutTrig01 = 29|0x300U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN29 input. */
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kXBARB3_InputFlexpwm3Pwm3OutTrig01 = 30|0x300U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN30 input. */
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kXBARB3_InputFlexpwm3Pwm4OutTrig01 = 31|0x300U, /**< FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN31 input. */
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kXBARB3_InputFlexpwm4Pwm1OutTrig01 = 32|0x300U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN32 input. */
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kXBARB3_InputFlexpwm4Pwm2OutTrig01 = 33|0x300U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN33 input. */
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kXBARB3_InputFlexpwm4Pwm3OutTrig01 = 34|0x300U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN34 input. */
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kXBARB3_InputFlexpwm4Pwm4OutTrig01 = 35|0x300U, /**< FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN35 input. */
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kXBARB3_InputPitTrigger0 = 36|0x300U, /**< PIT_TRIGGER0 output assigned to XBARB3_IN36 input. */
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kXBARB3_InputPitTrigger1 = 37|0x300U, /**< PIT_TRIGGER1 output assigned to XBARB3_IN37 input. */
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kXBARB3_InputAdcEtcXbar0Coco0 = 38|0x300U, /**< ADC_ETC_XBAR0_COCO0 output assigned to XBARB3_IN38 input. */
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kXBARB3_InputAdcEtcXbar0Coco1 = 39|0x300U, /**< ADC_ETC_XBAR0_COCO1 output assigned to XBARB3_IN39 input. */
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kXBARB3_InputAdcEtcXbar0Coco2 = 40|0x300U, /**< ADC_ETC_XBAR0_COCO2 output assigned to XBARB3_IN40 input. */
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kXBARB3_InputAdcEtcXbar0Coco3 = 41|0x300U, /**< ADC_ETC_XBAR0_COCO3 output assigned to XBARB3_IN41 input. */
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kXBARB3_InputAdcEtcXbar1Coco0 = 42|0x300U, /**< ADC_ETC_XBAR1_COCO0 output assigned to XBARB3_IN42 input. */
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kXBARB3_InputAdcEtcXbar1Coco1 = 43|0x300U, /**< ADC_ETC_XBAR1_COCO1 output assigned to XBARB3_IN43 input. */
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kXBARB3_InputAdcEtcXbar1Coco2 = 44|0x300U, /**< ADC_ETC_XBAR1_COCO2 output assigned to XBARB3_IN44 input. */
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kXBARB3_InputAdcEtcXbar1Coco3 = 45|0x300U, /**< ADC_ETC_XBAR1_COCO3 output assigned to XBARB3_IN45 input. */
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kXBARB3_InputEnc1PosMatch = 46|0x300U, /**< ENC1_POS_MATCH output assigned to XBARB3_IN46 input. */
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kXBARB3_InputEnc2PosMatch = 47|0x300U, /**< ENC2_POS_MATCH output assigned to XBARB3_IN47 input. */
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kXBARB3_InputEnc3PosMatch = 48|0x300U, /**< ENC3_POS_MATCH output assigned to XBARB3_IN48 input. */
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kXBARB3_InputEnc4PosMatch = 49|0x300U, /**< ENC4_POS_MATCH output assigned to XBARB3_IN49 input. */
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kXBARB3_InputDmaDone0 = 50|0x300U, /**< DMA_DONE0 output assigned to XBARB3_IN50 input. */
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kXBARB3_InputDmaDone1 = 51|0x300U, /**< DMA_DONE1 output assigned to XBARB3_IN51 input. */
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kXBARB3_InputDmaDone2 = 52|0x300U, /**< DMA_DONE2 output assigned to XBARB3_IN52 input. */
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kXBARB3_InputDmaDone3 = 53|0x300U, /**< DMA_DONE3 output assigned to XBARB3_IN53 input. */
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kXBARB3_InputDmaDone4 = 54|0x300U, /**< DMA_DONE4 output assigned to XBARB3_IN54 input. */
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kXBARB3_InputDmaDone5 = 55|0x300U, /**< DMA_DONE5 output assigned to XBARB3_IN55 input. */
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kXBARB3_InputDmaDone6 = 56|0x300U, /**< DMA_DONE6 output assigned to XBARB3_IN56 input. */
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kXBARB3_InputDmaDone7 = 57|0x300U, /**< DMA_DONE7 output assigned to XBARB3_IN57 input. */
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} xbar_input_signal_t;
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typedef enum _xbar_output_signal
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{
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kXBARA1_OutputDmaChMuxReq30 = 0|0x100U, /**< XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ30 */
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kXBARA1_OutputDmaChMuxReq31 = 1|0x100U, /**< XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ31 */
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kXBARA1_OutputDmaChMuxReq94 = 2|0x100U, /**< XBARA1_OUT2 output assigned to DMA_CH_MUX_REQ94 */
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kXBARA1_OutputDmaChMuxReq95 = 3|0x100U, /**< XBARA1_OUT3 output assigned to DMA_CH_MUX_REQ95 */
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kXBARA1_OutputIomuxXbarInout04 = 4|0x100U, /**< XBARA1_OUT4 output assigned to IOMUX_XBAR_INOUT04 */
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kXBARA1_OutputIomuxXbarInout05 = 5|0x100U, /**< XBARA1_OUT5 output assigned to IOMUX_XBAR_INOUT05 */
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kXBARA1_OutputIomuxXbarInout06 = 6|0x100U, /**< XBARA1_OUT6 output assigned to IOMUX_XBAR_INOUT06 */
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kXBARA1_OutputIomuxXbarInout07 = 7|0x100U, /**< XBARA1_OUT7 output assigned to IOMUX_XBAR_INOUT07 */
|
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kXBARA1_OutputIomuxXbarInout08 = 8|0x100U, /**< XBARA1_OUT8 output assigned to IOMUX_XBAR_INOUT08 */
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kXBARA1_OutputIomuxXbarInout09 = 9|0x100U, /**< XBARA1_OUT9 output assigned to IOMUX_XBAR_INOUT09 */
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kXBARA1_OutputIomuxXbarInout10 = 10|0x100U, /**< XBARA1_OUT10 output assigned to IOMUX_XBAR_INOUT10 */
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kXBARA1_OutputIomuxXbarInout11 = 11|0x100U, /**< XBARA1_OUT11 output assigned to IOMUX_XBAR_INOUT11 */
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kXBARA1_OutputIomuxXbarInout12 = 12|0x100U, /**< XBARA1_OUT12 output assigned to IOMUX_XBAR_INOUT12 */
|
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kXBARA1_OutputIomuxXbarInout13 = 13|0x100U, /**< XBARA1_OUT13 output assigned to IOMUX_XBAR_INOUT13 */
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kXBARA1_OutputIomuxXbarInout14 = 14|0x100U, /**< XBARA1_OUT14 output assigned to IOMUX_XBAR_INOUT14 */
|
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kXBARA1_OutputIomuxXbarInout15 = 15|0x100U, /**< XBARA1_OUT15 output assigned to IOMUX_XBAR_INOUT15 */
|
|
kXBARA1_OutputIomuxXbarInout16 = 16|0x100U, /**< XBARA1_OUT16 output assigned to IOMUX_XBAR_INOUT16 */
|
|
kXBARA1_OutputIomuxXbarInout17 = 17|0x100U, /**< XBARA1_OUT17 output assigned to IOMUX_XBAR_INOUT17 */
|
|
kXBARA1_OutputIomuxXbarInout18 = 18|0x100U, /**< XBARA1_OUT18 output assigned to IOMUX_XBAR_INOUT18 */
|
|
kXBARA1_OutputIomuxXbarInout19 = 19|0x100U, /**< XBARA1_OUT19 output assigned to IOMUX_XBAR_INOUT19 */
|
|
kXBARA1_OutputAcmp1Sample = 20|0x100U, /**< XBARA1_OUT20 output assigned to ACMP1_SAMPLE */
|
|
kXBARA1_OutputAcmp2Sample = 21|0x100U, /**< XBARA1_OUT21 output assigned to ACMP2_SAMPLE */
|
|
kXBARA1_OutputAcmp3Sample = 22|0x100U, /**< XBARA1_OUT22 output assigned to ACMP3_SAMPLE */
|
|
kXBARA1_OutputAcmp4Sample = 23|0x100U, /**< XBARA1_OUT23 output assigned to ACMP4_SAMPLE */
|
|
kXBARA1_OutputRESERVED24 = 24|0x100U, /**< XBARA1_OUT24 output is reserved. */
|
|
kXBARA1_OutputRESERVED25 = 25|0x100U, /**< XBARA1_OUT25 output is reserved. */
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kXBARA1_OutputFlexpwm1Exta0 = 26|0x100U, /**< XBARA1_OUT26 output assigned to FLEXPWM1_EXTA0 */
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kXBARA1_OutputFlexpwm1Exta1 = 27|0x100U, /**< XBARA1_OUT27 output assigned to FLEXPWM1_EXTA1 */
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|
kXBARA1_OutputFlexpwm1Exta2 = 28|0x100U, /**< XBARA1_OUT28 output assigned to FLEXPWM1_EXTA2 */
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|
kXBARA1_OutputFlexpwm1Exta3 = 29|0x100U, /**< XBARA1_OUT29 output assigned to FLEXPWM1_EXTA3 */
|
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kXBARA1_OutputFlexpwm1ExtSync0 = 30|0x100U, /**< XBARA1_OUT30 output assigned to FLEXPWM1_EXT_SYNC0 */
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kXBARA1_OutputFlexpwm1ExtSync1 = 31|0x100U, /**< XBARA1_OUT31 output assigned to FLEXPWM1_EXT_SYNC1 */
|
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kXBARA1_OutputFlexpwm1ExtSync2 = 32|0x100U, /**< XBARA1_OUT32 output assigned to FLEXPWM1_EXT_SYNC2 */
|
|
kXBARA1_OutputFlexpwm1ExtSync3 = 33|0x100U, /**< XBARA1_OUT33 output assigned to FLEXPWM1_EXT_SYNC3 */
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kXBARA1_OutputFlexpwm1ExtClk = 34|0x100U, /**< XBARA1_OUT34 output assigned to FLEXPWM1_EXT_CLK */
|
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kXBARA1_OutputFlexpwm1Fault0 = 35|0x100U, /**< XBARA1_OUT35 output assigned to FLEXPWM1_FAULT0 */
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kXBARA1_OutputFlexpwm1Fault1 = 36|0x100U, /**< XBARA1_OUT36 output assigned to FLEXPWM1_FAULT1 */
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kXBARA1_OutputFlexpwm1234Fault2 = 37|0x100U, /**< XBARA1_OUT37 output assigned to FLEXPWM1_2_3_4_FAULT2 */
|
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kXBARA1_OutputFlexpwm1234Fault3 = 38|0x100U, /**< XBARA1_OUT38 output assigned to FLEXPWM1_2_3_4_FAULT3 */
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kXBARA1_OutputFlexpwm1ExtForce = 39|0x100U, /**< XBARA1_OUT39 output assigned to FLEXPWM1_EXT_FORCE */
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kXBARA1_OutputFlexpwm234Exta0 = 40|0x100U, /**< XBARA1_OUT40 output assigned to FLEXPWM2_3_4_EXTA0 */
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kXBARA1_OutputFlexpwm234Exta1 = 41|0x100U, /**< XBARA1_OUT41 output assigned to FLEXPWM2_3_4_EXTA1 */
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kXBARA1_OutputFlexpwm234Exta2 = 42|0x100U, /**< XBARA1_OUT42 output assigned to FLEXPWM2_3_4_EXTA2 */
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kXBARA1_OutputFlexpwm234Exta3 = 43|0x100U, /**< XBARA1_OUT43 output assigned to FLEXPWM2_3_4_EXTA3 */
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kXBARA1_OutputFlexpwm2ExtSync0 = 44|0x100U, /**< XBARA1_OUT44 output assigned to FLEXPWM2_EXT_SYNC0 */
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kXBARA1_OutputFlexpwm2ExtSync1 = 45|0x100U, /**< XBARA1_OUT45 output assigned to FLEXPWM2_EXT_SYNC1 */
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kXBARA1_OutputFlexpwm2ExtSync2 = 46|0x100U, /**< XBARA1_OUT46 output assigned to FLEXPWM2_EXT_SYNC2 */
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kXBARA1_OutputFlexpwm2ExtSync3 = 47|0x100U, /**< XBARA1_OUT47 output assigned to FLEXPWM2_EXT_SYNC3 */
|
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kXBARA1_OutputFlexpwm234ExtClk = 48|0x100U, /**< XBARA1_OUT48 output assigned to FLEXPWM2_3_4_EXT_CLK */
|
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kXBARA1_OutputFlexpwm2Fault0 = 49|0x100U, /**< XBARA1_OUT49 output assigned to FLEXPWM2_FAULT0 */
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|
kXBARA1_OutputFlexpwm2Fault1 = 50|0x100U, /**< XBARA1_OUT50 output assigned to FLEXPWM2_FAULT1 */
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|
kXBARA1_OutputFlexpwm2ExtForce = 51|0x100U, /**< XBARA1_OUT51 output assigned to FLEXPWM2_EXT_FORCE */
|
|
kXBARA1_OutputFlexpwm3ExtSync0 = 52|0x100U, /**< XBARA1_OUT52 output assigned to FLEXPWM3_EXT_SYNC0 */
|
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kXBARA1_OutputFlexpwm3ExtSync1 = 53|0x100U, /**< XBARA1_OUT53 output assigned to FLEXPWM3_EXT_SYNC1 */
|
|
kXBARA1_OutputFlexpwm3ExtSync2 = 54|0x100U, /**< XBARA1_OUT54 output assigned to FLEXPWM3_EXT_SYNC2 */
|
|
kXBARA1_OutputFlexpwm3ExtSync3 = 55|0x100U, /**< XBARA1_OUT55 output assigned to FLEXPWM3_EXT_SYNC3 */
|
|
kXBARA1_OutputFlexpwm3Fault0 = 56|0x100U, /**< XBARA1_OUT56 output assigned to FLEXPWM3_FAULT0 */
|
|
kXBARA1_OutputFlexpwm3Fault1 = 57|0x100U, /**< XBARA1_OUT57 output assigned to FLEXPWM3_FAULT1 */
|
|
kXBARA1_OutputFlexpwm3ExtForce = 58|0x100U, /**< XBARA1_OUT58 output assigned to FLEXPWM3_EXT_FORCE */
|
|
kXBARA1_OutputFlexpwm4ExtSync0 = 59|0x100U, /**< XBARA1_OUT59 output assigned to FLEXPWM4_EXT_SYNC0 */
|
|
kXBARA1_OutputFlexpwm4ExtSync1 = 60|0x100U, /**< XBARA1_OUT60 output assigned to FLEXPWM4_EXT_SYNC1 */
|
|
kXBARA1_OutputFlexpwm4ExtSync2 = 61|0x100U, /**< XBARA1_OUT61 output assigned to FLEXPWM4_EXT_SYNC2 */
|
|
kXBARA1_OutputFlexpwm4ExtSync3 = 62|0x100U, /**< XBARA1_OUT62 output assigned to FLEXPWM4_EXT_SYNC3 */
|
|
kXBARA1_OutputFlexpwm4Fault0 = 63|0x100U, /**< XBARA1_OUT63 output assigned to FLEXPWM4_FAULT0 */
|
|
kXBARA1_OutputFlexpwm4Fault1 = 64|0x100U, /**< XBARA1_OUT64 output assigned to FLEXPWM4_FAULT1 */
|
|
kXBARA1_OutputFlexpwm4ExtForce = 65|0x100U, /**< XBARA1_OUT65 output assigned to FLEXPWM4_EXT_FORCE */
|
|
kXBARA1_OutputEnc1PhaseAInput = 66|0x100U, /**< XBARA1_OUT66 output assigned to ENC1_PHASE_A_INPUT */
|
|
kXBARA1_OutputEnc1PhaseBInput = 67|0x100U, /**< XBARA1_OUT67 output assigned to ENC1_PHASE_B_INPUT */
|
|
kXBARA1_OutputEnc1Index = 68|0x100U, /**< XBARA1_OUT68 output assigned to ENC1_INDEX */
|
|
kXBARA1_OutputEnc1Home = 69|0x100U, /**< XBARA1_OUT69 output assigned to ENC1_HOME */
|
|
kXBARA1_OutputEnc1Trigger = 70|0x100U, /**< XBARA1_OUT70 output assigned to ENC1_TRIGGER */
|
|
kXBARA1_OutputEnc2PhaseAInput = 71|0x100U, /**< XBARA1_OUT71 output assigned to ENC2_PHASE_A_INPUT */
|
|
kXBARA1_OutputEnc2PhaseBInput = 72|0x100U, /**< XBARA1_OUT72 output assigned to ENC2_PHASE_B_INPUT */
|
|
kXBARA1_OutputEnc2Index = 73|0x100U, /**< XBARA1_OUT73 output assigned to ENC2_INDEX */
|
|
kXBARA1_OutputEnc2Home = 74|0x100U, /**< XBARA1_OUT74 output assigned to ENC2_HOME */
|
|
kXBARA1_OutputEnc2Trigger = 75|0x100U, /**< XBARA1_OUT75 output assigned to ENC2_TRIGGER */
|
|
kXBARA1_OutputEnc3PhaseAInput = 76|0x100U, /**< XBARA1_OUT76 output assigned to ENC3_PHASE_A_INPUT */
|
|
kXBARA1_OutputEnc3PhaseBInput = 77|0x100U, /**< XBARA1_OUT77 output assigned to ENC3_PHASE_B_INPUT */
|
|
kXBARA1_OutputEnc3Index = 78|0x100U, /**< XBARA1_OUT78 output assigned to ENC3_INDEX */
|
|
kXBARA1_OutputEnc3Home = 79|0x100U, /**< XBARA1_OUT79 output assigned to ENC3_HOME */
|
|
kXBARA1_OutputEnc3Trigger = 80|0x100U, /**< XBARA1_OUT80 output assigned to ENC3_TRIGGER */
|
|
kXBARA1_OutputEnc4PhaseAInput = 81|0x100U, /**< XBARA1_OUT81 output assigned to ENC4_PHASE_A_INPUT */
|
|
kXBARA1_OutputEnc4PhaseBInput = 82|0x100U, /**< XBARA1_OUT82 output assigned to ENC4_PHASE_B_INPUT */
|
|
kXBARA1_OutputEnc4Index = 83|0x100U, /**< XBARA1_OUT83 output assigned to ENC4_INDEX */
|
|
kXBARA1_OutputEnc4Home = 84|0x100U, /**< XBARA1_OUT84 output assigned to ENC4_HOME */
|
|
kXBARA1_OutputEnc4Trigger = 85|0x100U, /**< XBARA1_OUT85 output assigned to ENC4_TRIGGER */
|
|
kXBARA1_OutputQtimer1Tmr0Input = 86|0x100U, /**< XBARA1_OUT86 output assigned to QTIMER1_TMR0_INPUT */
|
|
kXBARA1_OutputQtimer1Tmr1Input = 87|0x100U, /**< XBARA1_OUT87 output assigned to QTIMER1_TMR1_INPUT */
|
|
kXBARA1_OutputQtimer1Tmr2Input = 88|0x100U, /**< XBARA1_OUT88 output assigned to QTIMER1_TMR2_INPUT */
|
|
kXBARA1_OutputQtimer1Tmr3Input = 89|0x100U, /**< XBARA1_OUT89 output assigned to QTIMER1_TMR3_INPUT */
|
|
kXBARA1_OutputQtimer2Tmr0Input = 90|0x100U, /**< XBARA1_OUT90 output assigned to QTIMER2_TMR0_INPUT */
|
|
kXBARA1_OutputQtimer2Tmr1Input = 91|0x100U, /**< XBARA1_OUT91 output assigned to QTIMER2_TMR1_INPUT */
|
|
kXBARA1_OutputQtimer2Tmr2Input = 92|0x100U, /**< XBARA1_OUT92 output assigned to QTIMER2_TMR2_INPUT */
|
|
kXBARA1_OutputQtimer2Tmr3Input = 93|0x100U, /**< XBARA1_OUT93 output assigned to QTIMER2_TMR3_INPUT */
|
|
kXBARA1_OutputQtimer3Tmr0Input = 94|0x100U, /**< XBARA1_OUT94 output assigned to QTIMER3_TMR0_INPUT */
|
|
kXBARA1_OutputQtimer3Tmr1Input = 95|0x100U, /**< XBARA1_OUT95 output assigned to QTIMER3_TMR1_INPUT */
|
|
kXBARA1_OutputQtimer3Tmr2Input = 96|0x100U, /**< XBARA1_OUT96 output assigned to QTIMER3_TMR2_INPUT */
|
|
kXBARA1_OutputQtimer3Tmr3Input = 97|0x100U, /**< XBARA1_OUT97 output assigned to QTIMER3_TMR3_INPUT */
|
|
kXBARA1_OutputQtimer4Tmr0Input = 98|0x100U, /**< XBARA1_OUT98 output assigned to QTIMER4_TMR0_INPUT */
|
|
kXBARA1_OutputQtimer4Tmr1Input = 99|0x100U, /**< XBARA1_OUT99 output assigned to QTIMER4_TMR1_INPUT */
|
|
kXBARA1_OutputQtimer4Tmr2Input = 100|0x100U, /**< XBARA1_OUT100 output assigned to QTIMER4_TMR2_INPUT */
|
|
kXBARA1_OutputQtimer4Tmr3Input = 101|0x100U, /**< XBARA1_OUT101 output assigned to QTIMER4_TMR3_INPUT */
|
|
kXBARA1_OutputEwmEwmIn = 102|0x100U, /**< XBARA1_OUT102 output assigned to EWM_EWM_IN */
|
|
kXBARA1_OutputAdcEtcXbar0Trig0 = 103|0x100U, /**< XBARA1_OUT103 output assigned to ADC_ETC_XBAR0_TRIG0 */
|
|
kXBARA1_OutputAdcEtcXbar0Trig1 = 104|0x100U, /**< XBARA1_OUT104 output assigned to ADC_ETC_XBAR0_TRIG1 */
|
|
kXBARA1_OutputAdcEtcXbar0Trig2 = 105|0x100U, /**< XBARA1_OUT105 output assigned to ADC_ETC_XBAR0_TRIG2 */
|
|
kXBARA1_OutputAdcEtcXbar0Trig3 = 106|0x100U, /**< XBARA1_OUT106 output assigned to ADC_ETC_XBAR0_TRIG3 */
|
|
kXBARA1_OutputAdcEtcXbar1Trig0 = 107|0x100U, /**< XBARA1_OUT107 output assigned to ADC_ETC_XBAR1_TRIG0 */
|
|
kXBARA1_OutputAdcEtcXbar1Trig1 = 108|0x100U, /**< XBARA1_OUT108 output assigned to ADC_ETC_XBAR1_TRIG1 */
|
|
kXBARA1_OutputAdcEtcXbar1Trig2 = 109|0x100U, /**< XBARA1_OUT109 output assigned to ADC_ETC_XBAR1_TRIG2 */
|
|
kXBARA1_OutputAdcEtcXbar1Trig3 = 110|0x100U, /**< XBARA1_OUT110 output assigned to ADC_ETC_XBAR1_TRIG3 */
|
|
kXBARA1_OutputLpi2c1TrgInput = 111|0x100U, /**< XBARA1_OUT111 output assigned to LPI2C1_TRG_INPUT */
|
|
kXBARA1_OutputLpi2c2TrgInput = 112|0x100U, /**< XBARA1_OUT112 output assigned to LPI2C2_TRG_INPUT */
|
|
kXBARA1_OutputLpi2c3TrgInput = 113|0x100U, /**< XBARA1_OUT113 output assigned to LPI2C3_TRG_INPUT */
|
|
kXBARA1_OutputLpi2c4TrgInput = 114|0x100U, /**< XBARA1_OUT114 output assigned to LPI2C4_TRG_INPUT */
|
|
kXBARA1_OutputLpspi1TrgInput = 115|0x100U, /**< XBARA1_OUT115 output assigned to LPSPI1_TRG_INPUT */
|
|
kXBARA1_OutputLpspi2TrgInput = 116|0x100U, /**< XBARA1_OUT116 output assigned to LPSPI2_TRG_INPUT */
|
|
kXBARA1_OutputLpspi3TrgInput = 117|0x100U, /**< XBARA1_OUT117 output assigned to LPSPI3_TRG_INPUT */
|
|
kXBARA1_OutputLpspi4TrgInput = 118|0x100U, /**< XBARA1_OUT118 output assigned to LPSPI4_TRG_INPUT */
|
|
kXBARA1_OutputLpuart1TrgInput = 119|0x100U, /**< XBARA1_OUT119 output assigned to LPUART1_TRG_INPUT */
|
|
kXBARA1_OutputLpuart2TrgInput = 120|0x100U, /**< XBARA1_OUT120 output assigned to LPUART2_TRG_INPUT */
|
|
kXBARA1_OutputLpuart3TrgInput = 121|0x100U, /**< XBARA1_OUT121 output assigned to LPUART3_TRG_INPUT */
|
|
kXBARA1_OutputLpuart4TrgInput = 122|0x100U, /**< XBARA1_OUT122 output assigned to LPUART4_TRG_INPUT */
|
|
kXBARA1_OutputLpuart5TrgInput = 123|0x100U, /**< XBARA1_OUT123 output assigned to LPUART5_TRG_INPUT */
|
|
kXBARA1_OutputLpuart6TrgInput = 124|0x100U, /**< XBARA1_OUT124 output assigned to LPUART6_TRG_INPUT */
|
|
kXBARA1_OutputLpuart7TrgInput = 125|0x100U, /**< XBARA1_OUT125 output assigned to LPUART7_TRG_INPUT */
|
|
kXBARA1_OutputLpuart8TrgInput = 126|0x100U, /**< XBARA1_OUT126 output assigned to LPUART8_TRG_INPUT */
|
|
kXBARA1_OutputFlexio1TriggerIn0 = 127|0x100U, /**< XBARA1_OUT127 output assigned to FLEXIO1_TRIGGER_IN0 */
|
|
kXBARA1_OutputFlexio1TriggerIn1 = 128|0x100U, /**< XBARA1_OUT128 output assigned to FLEXIO1_TRIGGER_IN1 */
|
|
kXBARA1_OutputFlexio2TriggerIn0 = 129|0x100U, /**< XBARA1_OUT129 output assigned to FLEXIO2_TRIGGER_IN0 */
|
|
kXBARA1_OutputFlexio2TriggerIn1 = 130|0x100U, /**< XBARA1_OUT130 output assigned to FLEXIO2_TRIGGER_IN1 */
|
|
kXBARB2_OutputAoi1In00 = 0|0x200U, /**< XBARB2_OUT0 output assigned to AOI1_IN00 */
|
|
kXBARB2_OutputAoi1In01 = 1|0x200U, /**< XBARB2_OUT1 output assigned to AOI1_IN01 */
|
|
kXBARB2_OutputAoi1In02 = 2|0x200U, /**< XBARB2_OUT2 output assigned to AOI1_IN02 */
|
|
kXBARB2_OutputAoi1In03 = 3|0x200U, /**< XBARB2_OUT3 output assigned to AOI1_IN03 */
|
|
kXBARB2_OutputAoi1In04 = 4|0x200U, /**< XBARB2_OUT4 output assigned to AOI1_IN04 */
|
|
kXBARB2_OutputAoi1In05 = 5|0x200U, /**< XBARB2_OUT5 output assigned to AOI1_IN05 */
|
|
kXBARB2_OutputAoi1In06 = 6|0x200U, /**< XBARB2_OUT6 output assigned to AOI1_IN06 */
|
|
kXBARB2_OutputAoi1In07 = 7|0x200U, /**< XBARB2_OUT7 output assigned to AOI1_IN07 */
|
|
kXBARB2_OutputAoi1In08 = 8|0x200U, /**< XBARB2_OUT8 output assigned to AOI1_IN08 */
|
|
kXBARB2_OutputAoi1In09 = 9|0x200U, /**< XBARB2_OUT9 output assigned to AOI1_IN09 */
|
|
kXBARB2_OutputAoi1In10 = 10|0x200U, /**< XBARB2_OUT10 output assigned to AOI1_IN10 */
|
|
kXBARB2_OutputAoi1In11 = 11|0x200U, /**< XBARB2_OUT11 output assigned to AOI1_IN11 */
|
|
kXBARB2_OutputAoi1In12 = 12|0x200U, /**< XBARB2_OUT12 output assigned to AOI1_IN12 */
|
|
kXBARB2_OutputAoi1In13 = 13|0x200U, /**< XBARB2_OUT13 output assigned to AOI1_IN13 */
|
|
kXBARB2_OutputAoi1In14 = 14|0x200U, /**< XBARB2_OUT14 output assigned to AOI1_IN14 */
|
|
kXBARB2_OutputAoi1In15 = 15|0x200U, /**< XBARB2_OUT15 output assigned to AOI1_IN15 */
|
|
kXBARB3_OutputAoi2In00 = 0|0x300U, /**< XBARB3_OUT0 output assigned to AOI2_IN00 */
|
|
kXBARB3_OutputAoi2In01 = 1|0x300U, /**< XBARB3_OUT1 output assigned to AOI2_IN01 */
|
|
kXBARB3_OutputAoi2In02 = 2|0x300U, /**< XBARB3_OUT2 output assigned to AOI2_IN02 */
|
|
kXBARB3_OutputAoi2In03 = 3|0x300U, /**< XBARB3_OUT3 output assigned to AOI2_IN03 */
|
|
kXBARB3_OutputAoi2In04 = 4|0x300U, /**< XBARB3_OUT4 output assigned to AOI2_IN04 */
|
|
kXBARB3_OutputAoi2In05 = 5|0x300U, /**< XBARB3_OUT5 output assigned to AOI2_IN05 */
|
|
kXBARB3_OutputAoi2In06 = 6|0x300U, /**< XBARB3_OUT6 output assigned to AOI2_IN06 */
|
|
kXBARB3_OutputAoi2In07 = 7|0x300U, /**< XBARB3_OUT7 output assigned to AOI2_IN07 */
|
|
kXBARB3_OutputAoi2In08 = 8|0x300U, /**< XBARB3_OUT8 output assigned to AOI2_IN08 */
|
|
kXBARB3_OutputAoi2In09 = 9|0x300U, /**< XBARB3_OUT9 output assigned to AOI2_IN09 */
|
|
kXBARB3_OutputAoi2In10 = 10|0x300U, /**< XBARB3_OUT10 output assigned to AOI2_IN10 */
|
|
kXBARB3_OutputAoi2In11 = 11|0x300U, /**< XBARB3_OUT11 output assigned to AOI2_IN11 */
|
|
kXBARB3_OutputAoi2In12 = 12|0x300U, /**< XBARB3_OUT12 output assigned to AOI2_IN12 */
|
|
kXBARB3_OutputAoi2In13 = 13|0x300U, /**< XBARB3_OUT13 output assigned to AOI2_IN13 */
|
|
kXBARB3_OutputAoi2In14 = 14|0x300U, /**< XBARB3_OUT14 output assigned to AOI2_IN14 */
|
|
kXBARB3_OutputAoi2In15 = 15|0x300U, /**< XBARB3_OUT15 output assigned to AOI2_IN15 */
|
|
} xbar_output_signal_t;
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group Mapping_Information */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- Device Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup Peripheral_access_layer Device Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
|
|
/*
|
|
** Start of section using anonymous unions
|
|
*/
|
|
|
|
#if defined(__ARMCC_VERSION)
|
|
#if (__ARMCC_VERSION >= 6010050)
|
|
#pragma clang diagnostic push
|
|
#else
|
|
#pragma push
|
|
#pragma anon_unions
|
|
#endif
|
|
#elif defined(__CWCC__)
|
|
#pragma push
|
|
#pragma cpp_extensions on
|
|
#elif defined(__GNUC__)
|
|
/* anonymous unions are enabled by default */
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#elif defined(__IAR_SYSTEMS_ICC__)
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#pragma language=extended
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#else
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#error Not supported compiler type
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#endif
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/* ----------------------------------------------------------------------------
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-- ADC Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
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* @{
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*/
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/** ADC - Register Layout Typedef */
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typedef struct {
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__IO uint32_t HC[8]; /**< Control register for hardware triggers, array offset: 0x0, array step: 0x4 */
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__I uint32_t HS; /**< Status register for HW triggers, offset: 0x20 */
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__I uint32_t R[8]; /**< Data result register for HW triggers, array offset: 0x24, array step: 0x4 */
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__IO uint32_t CFG; /**< Configuration register, offset: 0x44 */
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__IO uint32_t GC; /**< General control register, offset: 0x48 */
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__IO uint32_t GS; /**< General status register, offset: 0x4C */
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__IO uint32_t CV; /**< Compare value register, offset: 0x50 */
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__IO uint32_t OFS; /**< Offset correction value register, offset: 0x54 */
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__IO uint32_t CAL; /**< Calibration value register, offset: 0x58 */
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} ADC_Type;
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/* ----------------------------------------------------------------------------
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-- ADC Register Masks
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup ADC_Register_Masks ADC Register Masks
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* @{
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*/
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/*! @name HC - Control register for hardware triggers */
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/*! @{ */
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#define ADC_HC_ADCH_MASK (0x1FU)
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#define ADC_HC_ADCH_SHIFT (0U)
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/*! ADCH - Input Channel Select
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* 0b10000..External channel selection from ADC_ETC
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* 0b11000..Reserved.
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* 0b11001..VREFSH = internal channel, for ADC self-test, hard connected to VRH internally
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* 0b11010..Reserved.
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* 0b11011..Reserved.
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* 0b11111..Conversion Disabled. Hardware Triggers will not initiate any conversion.
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*/
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#define ADC_HC_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK)
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#define ADC_HC_AIEN_MASK (0x80U)
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#define ADC_HC_AIEN_SHIFT (7U)
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/*! AIEN - Conversion Complete Interrupt Enable/Disable Control
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* 0b1..Conversion complete interrupt enabled
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* 0b0..Conversion complete interrupt disabled
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*/
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#define ADC_HC_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK)
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/*! @} */
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/* The count of ADC_HC */
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#define ADC_HC_COUNT (8U)
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/*! @name HS - Status register for HW triggers */
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/*! @{ */
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#define ADC_HS_COCO0_MASK (0x1U)
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#define ADC_HS_COCO0_SHIFT (0U)
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#define ADC_HS_COCO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO0_SHIFT)) & ADC_HS_COCO0_MASK)
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/*! @} */
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/*! @name R - Data result register for HW triggers */
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/*! @{ */
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#define ADC_R_CDATA_MASK (0xFFFU)
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#define ADC_R_CDATA_SHIFT (0U)
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#define ADC_R_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_CDATA_SHIFT)) & ADC_R_CDATA_MASK)
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/*! @} */
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/* The count of ADC_R */
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#define ADC_R_COUNT (8U)
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/*! @name CFG - Configuration register */
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/*! @{ */
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#define ADC_CFG_ADICLK_MASK (0x3U)
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#define ADC_CFG_ADICLK_SHIFT (0U)
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/*! ADICLK - Input Clock Select
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* 0b00..IPG clock
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* 0b01..IPG clock divided by 2
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* 0b10..Reserved
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* 0b11..Asynchronous clock (ADACK)
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*/
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#define ADC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK)
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#define ADC_CFG_MODE_MASK (0xCU)
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#define ADC_CFG_MODE_SHIFT (2U)
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/*! MODE - Conversion Mode Selection
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* 0b00..8-bit conversion
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* 0b01..10-bit conversion
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* 0b10..12-bit conversion
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* 0b11..Reserved
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*/
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#define ADC_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_MODE_SHIFT)) & ADC_CFG_MODE_MASK)
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#define ADC_CFG_ADLSMP_MASK (0x10U)
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#define ADC_CFG_ADLSMP_SHIFT (4U)
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/*! ADLSMP - Long Sample Time Configuration
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* 0b0..Short sample mode.
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* 0b1..Long sample mode.
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*/
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#define ADC_CFG_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLSMP_SHIFT)) & ADC_CFG_ADLSMP_MASK)
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#define ADC_CFG_ADIV_MASK (0x60U)
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#define ADC_CFG_ADIV_SHIFT (5U)
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/*! ADIV - Clock Divide Select
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* 0b00..Input clock
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* 0b01..Input clock / 2
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* 0b10..Input clock / 4
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* 0b11..Input clock / 8
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*/
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#define ADC_CFG_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADIV_SHIFT)) & ADC_CFG_ADIV_MASK)
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#define ADC_CFG_ADLPC_MASK (0x80U)
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#define ADC_CFG_ADLPC_SHIFT (7U)
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/*! ADLPC - Low-Power Configuration
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* 0b0..ADC hard block not in low power mode.
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* 0b1..ADC hard block in low power mode.
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*/
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#define ADC_CFG_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLPC_SHIFT)) & ADC_CFG_ADLPC_MASK)
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#define ADC_CFG_ADSTS_MASK (0x300U)
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#define ADC_CFG_ADSTS_SHIFT (8U)
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/*! ADSTS
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* 0b00..Sample period (ADC clocks) = 2 if ADLSMP=0b Sample period (ADC clocks) = 12 if ADLSMP=1b
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* 0b01..Sample period (ADC clocks) = 4 if ADLSMP=0b Sample period (ADC clocks) = 16 if ADLSMP=1b
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* 0b10..Sample period (ADC clocks) = 6 if ADLSMP=0b Sample period (ADC clocks) = 20 if ADLSMP=1b
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* 0b11..Sample period (ADC clocks) = 8 if ADLSMP=0b Sample period (ADC clocks) = 24 if ADLSMP=1b
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*/
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#define ADC_CFG_ADSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADSTS_SHIFT)) & ADC_CFG_ADSTS_MASK)
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#define ADC_CFG_ADHSC_MASK (0x400U)
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#define ADC_CFG_ADHSC_SHIFT (10U)
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/*! ADHSC - High Speed Configuration
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* 0b0..Normal conversion selected.
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* 0b1..High speed conversion selected.
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*/
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#define ADC_CFG_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADHSC_SHIFT)) & ADC_CFG_ADHSC_MASK)
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#define ADC_CFG_REFSEL_MASK (0x1800U)
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#define ADC_CFG_REFSEL_SHIFT (11U)
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/*! REFSEL - Voltage Reference Selection
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* 0b00..Selects VREFH/VREFL as reference voltage.
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* 0b01..Reserved
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* 0b10..Reserved
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* 0b11..Reserved
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*/
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#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
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#define ADC_CFG_ADTRG_MASK (0x2000U)
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#define ADC_CFG_ADTRG_SHIFT (13U)
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/*! ADTRG - Conversion Trigger Select
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* 0b0..Software trigger selected
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* 0b1..Hardware trigger selected
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*/
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#define ADC_CFG_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK)
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#define ADC_CFG_AVGS_MASK (0xC000U)
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#define ADC_CFG_AVGS_SHIFT (14U)
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/*! AVGS - Hardware Average select
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|
* 0b00..4 samples averaged
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* 0b01..8 samples averaged
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* 0b10..16 samples averaged
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* 0b11..32 samples averaged
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*/
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#define ADC_CFG_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_AVGS_SHIFT)) & ADC_CFG_AVGS_MASK)
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#define ADC_CFG_OVWREN_MASK (0x10000U)
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#define ADC_CFG_OVWREN_SHIFT (16U)
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/*! OVWREN - Data Overwrite Enable
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* 0b1..Enable the overwriting.
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* 0b0..Disable the overwriting. Existing Data in Data result register will not be overwritten by subsequent converted data.
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*/
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#define ADC_CFG_OVWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK)
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/*! @} */
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/*! @name GC - General control register */
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/*! @{ */
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#define ADC_GC_ADACKEN_MASK (0x1U)
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#define ADC_GC_ADACKEN_SHIFT (0U)
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/*! ADACKEN - Asynchronous clock output enable
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* 0b0..Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active.
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* 0b1..Asynchronous clock and clock output enabled regardless of the state of the ADC
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*/
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#define ADC_GC_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK)
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#define ADC_GC_DMAEN_MASK (0x2U)
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#define ADC_GC_DMAEN_SHIFT (1U)
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/*! DMAEN - DMA Enable
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* 0b0..DMA disabled (default)
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* 0b1..DMA enabled
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*/
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#define ADC_GC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_DMAEN_SHIFT)) & ADC_GC_DMAEN_MASK)
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#define ADC_GC_ACREN_MASK (0x4U)
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#define ADC_GC_ACREN_SHIFT (2U)
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/*! ACREN - Compare Function Range Enable
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* 0b0..Range function disabled. Only the compare value 1 of ADC_CV register (CV1) is compared.
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* 0b1..Range function enabled. Both compare values of ADC_CV registers (CV1 and CV2) are compared.
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*/
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#define ADC_GC_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK)
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#define ADC_GC_ACFGT_MASK (0x8U)
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#define ADC_GC_ACFGT_SHIFT (3U)
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/*! ACFGT - Compare Function Greater Than Enable
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* 0b0..Configures "Less Than Threshold, Outside Range Not Inclusive and Inside Range Not Inclusive" functionality based on the values placed in the ADC_CV register.
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* 0b1..Configures "Greater Than Or Equal To Threshold, Outside Range Inclusive and Inside Range Inclusive" functionality based on the values placed in the ADC_CV registers.
|
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*/
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#define ADC_GC_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFGT_SHIFT)) & ADC_GC_ACFGT_MASK)
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#define ADC_GC_ACFE_MASK (0x10U)
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#define ADC_GC_ACFE_SHIFT (4U)
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/*! ACFE - Compare Function Enable
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* 0b0..Compare function disabled
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* 0b1..Compare function enabled
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*/
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#define ADC_GC_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFE_SHIFT)) & ADC_GC_ACFE_MASK)
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#define ADC_GC_AVGE_MASK (0x20U)
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#define ADC_GC_AVGE_SHIFT (5U)
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/*! AVGE - Hardware average enable
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* 0b0..Hardware average function disabled
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* 0b1..Hardware average function enabled
|
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*/
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#define ADC_GC_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_AVGE_SHIFT)) & ADC_GC_AVGE_MASK)
|
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#define ADC_GC_ADCO_MASK (0x40U)
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#define ADC_GC_ADCO_SHIFT (6U)
|
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/*! ADCO - Continuous Conversion Enable
|
|
* 0b0..One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion.
|
|
* 0b1..Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion.
|
|
*/
|
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#define ADC_GC_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADCO_SHIFT)) & ADC_GC_ADCO_MASK)
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#define ADC_GC_CAL_MASK (0x80U)
|
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#define ADC_GC_CAL_SHIFT (7U)
|
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#define ADC_GC_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_CAL_SHIFT)) & ADC_GC_CAL_MASK)
|
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/*! @} */
|
|
|
|
/*! @name GS - General status register */
|
|
/*! @{ */
|
|
#define ADC_GS_ADACT_MASK (0x1U)
|
|
#define ADC_GS_ADACT_SHIFT (0U)
|
|
/*! ADACT - Conversion Active
|
|
* 0b0..Conversion not in progress.
|
|
* 0b1..Conversion in progress.
|
|
*/
|
|
#define ADC_GS_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK)
|
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#define ADC_GS_CALF_MASK (0x2U)
|
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#define ADC_GS_CALF_SHIFT (1U)
|
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/*! CALF - Calibration Failed Flag
|
|
* 0b0..Calibration completed normally.
|
|
* 0b1..Calibration failed. ADC accuracy specifications are not guaranteed.
|
|
*/
|
|
#define ADC_GS_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_CALF_SHIFT)) & ADC_GS_CALF_MASK)
|
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#define ADC_GS_AWKST_MASK (0x4U)
|
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#define ADC_GS_AWKST_SHIFT (2U)
|
|
/*! AWKST - Asynchronous wakeup interrupt status
|
|
* 0b1..Asynchronous wake up interrupt occurred in stop mode.
|
|
* 0b0..No asynchronous interrupt.
|
|
*/
|
|
#define ADC_GS_AWKST(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK)
|
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/*! @} */
|
|
|
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/*! @name CV - Compare value register */
|
|
/*! @{ */
|
|
#define ADC_CV_CV1_MASK (0xFFFU)
|
|
#define ADC_CV_CV1_SHIFT (0U)
|
|
#define ADC_CV_CV1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV1_SHIFT)) & ADC_CV_CV1_MASK)
|
|
#define ADC_CV_CV2_MASK (0xFFF0000U)
|
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#define ADC_CV_CV2_SHIFT (16U)
|
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#define ADC_CV_CV2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV2_SHIFT)) & ADC_CV_CV2_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name OFS - Offset correction value register */
|
|
/*! @{ */
|
|
#define ADC_OFS_OFS_MASK (0xFFFU)
|
|
#define ADC_OFS_OFS_SHIFT (0U)
|
|
#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
|
|
#define ADC_OFS_SIGN_MASK (0x1000U)
|
|
#define ADC_OFS_SIGN_SHIFT (12U)
|
|
/*! SIGN - Sign bit
|
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* 0b0..The offset value is added with the raw result
|
|
* 0b1..The offset value is subtracted from the raw converted value
|
|
*/
|
|
#define ADC_OFS_SIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK)
|
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/*! @} */
|
|
|
|
/*! @name CAL - Calibration value register */
|
|
/*! @{ */
|
|
#define ADC_CAL_CAL_CODE_MASK (0xFU)
|
|
#define ADC_CAL_CAL_CODE_SHIFT (0U)
|
|
#define ADC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_CAL_CODE_SHIFT)) & ADC_CAL_CAL_CODE_MASK)
|
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/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group ADC_Register_Masks */
|
|
|
|
|
|
/* ADC - Peripheral instance base addresses */
|
|
/** Peripheral ADC1 base address */
|
|
#define ADC1_BASE (0x400C4000u)
|
|
/** Peripheral ADC1 base pointer */
|
|
#define ADC1 ((ADC_Type *)ADC1_BASE)
|
|
/** Peripheral ADC2 base address */
|
|
#define ADC2_BASE (0x400C8000u)
|
|
/** Peripheral ADC2 base pointer */
|
|
#define ADC2 ((ADC_Type *)ADC2_BASE)
|
|
/** Array initializer of ADC peripheral base addresses */
|
|
#define ADC_BASE_ADDRS { 0u, ADC1_BASE, ADC2_BASE }
|
|
/** Array initializer of ADC peripheral base pointers */
|
|
#define ADC_BASE_PTRS { (ADC_Type *)0u, ADC1, ADC2 }
|
|
/** Interrupt vectors for the ADC peripheral type */
|
|
#define ADC_IRQS { NotAvail_IRQn, ADC1_IRQn, ADC2_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group ADC_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- ADC_ETC Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup ADC_ETC_Peripheral_Access_Layer ADC_ETC Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** ADC_ETC - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t CTRL; /**< ADC_ETC Global Control Register, offset: 0x0 */
|
|
__IO uint32_t DONE0_1_IRQ; /**< ETC DONE0 and DONE1 IRQ State Register, offset: 0x4 */
|
|
__IO uint32_t DONE2_ERR_IRQ; /**< ETC DONE_2 and DONE_ERR IRQ State Register, offset: 0x8 */
|
|
__IO uint32_t DMA_CTRL; /**< ETC DMA control Register, offset: 0xC */
|
|
struct { /* offset: 0x10, array step: 0x28 */
|
|
__IO uint32_t TRIGn_CTRL; /**< ETC_TRIG0 Control Register..ETC_TRIG7 Control Register, array offset: 0x10, array step: 0x28 */
|
|
__IO uint32_t TRIGn_COUNTER; /**< ETC_TRIG0 Counter Register..ETC_TRIG7 Counter Register, array offset: 0x14, array step: 0x28 */
|
|
__IO uint32_t TRIGn_CHAIN_1_0; /**< ETC_TRIG Chain 0/1 Register, array offset: 0x18, array step: 0x28 */
|
|
__IO uint32_t TRIGn_CHAIN_3_2; /**< ETC_TRIG Chain 2/3 Register, array offset: 0x1C, array step: 0x28 */
|
|
__IO uint32_t TRIGn_CHAIN_5_4; /**< ETC_TRIG Chain 4/5 Register, array offset: 0x20, array step: 0x28 */
|
|
__IO uint32_t TRIGn_CHAIN_7_6; /**< ETC_TRIG Chain 6/7 Register, array offset: 0x24, array step: 0x28 */
|
|
__I uint32_t TRIGn_RESULT_1_0; /**< ETC_TRIG Result Data 1/0 Register, array offset: 0x28, array step: 0x28 */
|
|
__I uint32_t TRIGn_RESULT_3_2; /**< ETC_TRIG Result Data 3/2 Register, array offset: 0x2C, array step: 0x28 */
|
|
__I uint32_t TRIGn_RESULT_5_4; /**< ETC_TRIG Result Data 5/4 Register, array offset: 0x30, array step: 0x28 */
|
|
__I uint32_t TRIGn_RESULT_7_6; /**< ETC_TRIG Result Data 7/6 Register, array offset: 0x34, array step: 0x28 */
|
|
} TRIG[8];
|
|
} ADC_ETC_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- ADC_ETC Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup ADC_ETC_Register_Masks ADC_ETC Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name CTRL - ADC_ETC Global Control Register */
|
|
/*! @{ */
|
|
#define ADC_ETC_CTRL_TRIG_ENABLE_MASK (0xFFU)
|
|
#define ADC_ETC_CTRL_TRIG_ENABLE_SHIFT (0U)
|
|
#define ADC_ETC_CTRL_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK)
|
|
#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK (0x100U)
|
|
#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT (8U)
|
|
#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK)
|
|
#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK (0xE00U)
|
|
#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT (9U)
|
|
#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK)
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#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK (0x1000U)
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#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT (12U)
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#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK)
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#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK (0xE000U)
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#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT (13U)
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#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK)
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#define ADC_ETC_CTRL_PRE_DIVIDER_MASK (0xFF0000U)
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#define ADC_ETC_CTRL_PRE_DIVIDER_SHIFT (16U)
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#define ADC_ETC_CTRL_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK)
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#define ADC_ETC_CTRL_DMA_MODE_SEL_MASK (0x20000000U)
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#define ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT (29U)
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#define ADC_ETC_CTRL_DMA_MODE_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT)) & ADC_ETC_CTRL_DMA_MODE_SEL_MASK)
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#define ADC_ETC_CTRL_TSC_BYPASS_MASK (0x40000000U)
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#define ADC_ETC_CTRL_TSC_BYPASS_SHIFT (30U)
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#define ADC_ETC_CTRL_TSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TSC_BYPASS_SHIFT)) & ADC_ETC_CTRL_TSC_BYPASS_MASK)
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#define ADC_ETC_CTRL_SOFTRST_MASK (0x80000000U)
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#define ADC_ETC_CTRL_SOFTRST_SHIFT (31U)
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#define ADC_ETC_CTRL_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK)
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/*! @} */
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/*! @name DONE0_1_IRQ - ETC DONE0 and DONE1 IRQ State Register */
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/*! @{ */
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#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK (0x1U)
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#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT (0U)
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#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK)
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#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK (0x2U)
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#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT (1U)
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#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK)
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#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK (0x4U)
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#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT (2U)
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#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK)
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#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK (0x8U)
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#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT (3U)
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#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK)
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#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK (0x10U)
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#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT (4U)
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#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK)
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#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK (0x20U)
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#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT (5U)
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#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK)
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#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK (0x40U)
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#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT (6U)
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#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK)
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#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK (0x80U)
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#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT (7U)
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#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK)
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#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK (0x10000U)
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#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT (16U)
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#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK)
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#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK (0x20000U)
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#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT (17U)
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#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK)
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#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK (0x40000U)
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#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT (18U)
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#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK)
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#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK (0x80000U)
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#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT (19U)
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#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK)
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#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK (0x100000U)
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#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT (20U)
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#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK)
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#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK (0x200000U)
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#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT (21U)
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#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK)
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#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK (0x400000U)
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#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT (22U)
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#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK)
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#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK (0x800000U)
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#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT (23U)
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#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK)
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/*! @} */
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/*! @name DONE2_ERR_IRQ - ETC DONE_2 and DONE_ERR IRQ State Register */
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/*! @{ */
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK (0x1U)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT (0U)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK (0x2U)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT (1U)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK (0x4U)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT (2U)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK (0x8U)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT (3U)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK (0x10U)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT (4U)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK (0x20U)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT (5U)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK (0x40U)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT (6U)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK (0x80U)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT (7U)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK (0x10000U)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT (16U)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK (0x20000U)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT (17U)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK (0x40000U)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT (18U)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK (0x80000U)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT (19U)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK (0x100000U)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT (20U)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK (0x200000U)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT (21U)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK (0x400000U)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT (22U)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK (0x800000U)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT (23U)
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK)
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/*! @} */
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/*! @name DMA_CTRL - ETC DMA control Register */
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/*! @{ */
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#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U)
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#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT (0U)
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#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK)
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#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK (0x2U)
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#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT (1U)
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#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK)
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#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK (0x4U)
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#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT (2U)
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#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK)
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#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK (0x8U)
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#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT (3U)
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#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK)
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#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK (0x10U)
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#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT (4U)
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#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK)
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#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK (0x20U)
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#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT (5U)
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#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK)
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#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK (0x40U)
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#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT (6U)
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#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK)
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#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK (0x80U)
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#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT (7U)
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#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK)
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#define ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK (0x10000U)
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#define ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT (16U)
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#define ADC_ETC_DMA_CTRL_TRIG0_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK)
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#define ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK (0x20000U)
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#define ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT (17U)
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#define ADC_ETC_DMA_CTRL_TRIG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK)
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#define ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK (0x40000U)
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#define ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT (18U)
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#define ADC_ETC_DMA_CTRL_TRIG2_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK)
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#define ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK (0x80000U)
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#define ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT (19U)
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#define ADC_ETC_DMA_CTRL_TRIG3_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK)
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#define ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK (0x100000U)
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#define ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT (20U)
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#define ADC_ETC_DMA_CTRL_TRIG4_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK)
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#define ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK (0x200000U)
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#define ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT (21U)
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#define ADC_ETC_DMA_CTRL_TRIG5_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK)
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#define ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK (0x400000U)
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#define ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT (22U)
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#define ADC_ETC_DMA_CTRL_TRIG6_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK)
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#define ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK (0x800000U)
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#define ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT (23U)
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#define ADC_ETC_DMA_CTRL_TRIG7_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK)
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/*! @} */
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/*! @name TRIGn_CTRL - ETC_TRIG0 Control Register..ETC_TRIG7 Control Register */
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/*! @{ */
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#define ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK (0x1U)
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#define ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT (0U)
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#define ADC_ETC_TRIGn_CTRL_SW_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK)
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#define ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK (0x10U)
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#define ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT (4U)
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#define ADC_ETC_TRIGn_CTRL_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK)
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#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK (0x700U)
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#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT (8U)
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#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK)
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#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK (0x7000U)
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#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT (12U)
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#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK)
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#define ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK (0x10000U)
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#define ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT (16U)
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#define ADC_ETC_TRIGn_CTRL_SYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK)
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/*! @} */
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/* The count of ADC_ETC_TRIGn_CTRL */
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#define ADC_ETC_TRIGn_CTRL_COUNT (8U)
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/*! @name TRIGn_COUNTER - ETC_TRIG0 Counter Register..ETC_TRIG7 Counter Register */
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/*! @{ */
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#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK (0xFFFFU)
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#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT (0U)
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#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK)
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#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U)
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#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U)
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#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK)
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/*! @} */
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/* The count of ADC_ETC_TRIGn_COUNTER */
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#define ADC_ETC_TRIGn_COUNTER_COUNT (8U)
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/*! @name TRIGn_CHAIN_1_0 - ETC_TRIG Chain 0/1 Register */
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/*! @{ */
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#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK (0xFU)
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#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT (0U)
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#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK)
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#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK (0xFF0U)
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#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT (4U)
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#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK)
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#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK (0x1000U)
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#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT (12U)
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#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK)
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#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK (0x6000U)
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#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT (13U)
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#define ADC_ETC_TRIGn_CHAIN_1_0_IE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK)
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#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK (0xF0000U)
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#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT (16U)
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#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK)
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#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK (0xFF00000U)
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#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT (20U)
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#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK)
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#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK (0x10000000U)
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#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT (28U)
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#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK)
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#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK (0x60000000U)
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#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT (29U)
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#define ADC_ETC_TRIGn_CHAIN_1_0_IE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK)
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/*! @} */
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/* The count of ADC_ETC_TRIGn_CHAIN_1_0 */
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#define ADC_ETC_TRIGn_CHAIN_1_0_COUNT (8U)
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/*! @name TRIGn_CHAIN_3_2 - ETC_TRIG Chain 2/3 Register */
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/*! @{ */
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#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK (0xFU)
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#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT (0U)
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#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK)
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#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK (0xFF0U)
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#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT (4U)
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#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK)
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#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK (0x1000U)
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#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT (12U)
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#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK)
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#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK (0x6000U)
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#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT (13U)
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#define ADC_ETC_TRIGn_CHAIN_3_2_IE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK)
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#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK (0xF0000U)
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#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT (16U)
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#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK)
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#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK (0xFF00000U)
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#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT (20U)
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#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK)
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#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK (0x10000000U)
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#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT (28U)
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#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK)
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#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK (0x60000000U)
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#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT (29U)
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#define ADC_ETC_TRIGn_CHAIN_3_2_IE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK)
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/*! @} */
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/* The count of ADC_ETC_TRIGn_CHAIN_3_2 */
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#define ADC_ETC_TRIGn_CHAIN_3_2_COUNT (8U)
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/*! @name TRIGn_CHAIN_5_4 - ETC_TRIG Chain 4/5 Register */
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/*! @{ */
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#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK (0xFU)
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#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT (0U)
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#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK)
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#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK (0xFF0U)
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#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT (4U)
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#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK)
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#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK (0x1000U)
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#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT (12U)
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#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK)
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#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK (0x6000U)
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#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT (13U)
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#define ADC_ETC_TRIGn_CHAIN_5_4_IE4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK)
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#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK (0xF0000U)
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#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT (16U)
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#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK)
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#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK (0xFF00000U)
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#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT (20U)
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#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK)
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#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK (0x10000000U)
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#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT (28U)
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#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK)
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#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK (0x60000000U)
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#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT (29U)
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#define ADC_ETC_TRIGn_CHAIN_5_4_IE5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK)
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/*! @} */
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/* The count of ADC_ETC_TRIGn_CHAIN_5_4 */
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#define ADC_ETC_TRIGn_CHAIN_5_4_COUNT (8U)
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/*! @name TRIGn_CHAIN_7_6 - ETC_TRIG Chain 6/7 Register */
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/*! @{ */
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#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK (0xFU)
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#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT (0U)
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#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK)
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#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK (0xFF0U)
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#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT (4U)
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#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK)
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#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK (0x1000U)
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#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT (12U)
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#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK)
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#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK (0x6000U)
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#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT (13U)
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#define ADC_ETC_TRIGn_CHAIN_7_6_IE6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK)
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#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK (0xF0000U)
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#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT (16U)
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#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK)
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#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK (0xFF00000U)
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#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT (20U)
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#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK)
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#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK (0x10000000U)
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#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT (28U)
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#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK)
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#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK (0x60000000U)
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#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT (29U)
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#define ADC_ETC_TRIGn_CHAIN_7_6_IE7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK)
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/*! @} */
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/* The count of ADC_ETC_TRIGn_CHAIN_7_6 */
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#define ADC_ETC_TRIGn_CHAIN_7_6_COUNT (8U)
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/*! @name TRIGn_RESULT_1_0 - ETC_TRIG Result Data 1/0 Register */
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/*! @{ */
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#define ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK (0xFFFU)
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#define ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT (0U)
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#define ADC_ETC_TRIGn_RESULT_1_0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK)
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#define ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK (0xFFF0000U)
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#define ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT (16U)
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#define ADC_ETC_TRIGn_RESULT_1_0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK)
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/*! @} */
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/* The count of ADC_ETC_TRIGn_RESULT_1_0 */
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#define ADC_ETC_TRIGn_RESULT_1_0_COUNT (8U)
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/*! @name TRIGn_RESULT_3_2 - ETC_TRIG Result Data 3/2 Register */
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/*! @{ */
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#define ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK (0xFFFU)
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#define ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT (0U)
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#define ADC_ETC_TRIGn_RESULT_3_2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK)
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#define ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK (0xFFF0000U)
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#define ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT (16U)
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#define ADC_ETC_TRIGn_RESULT_3_2_DATA3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of ADC_ETC_TRIGn_RESULT_3_2 */
|
|
#define ADC_ETC_TRIGn_RESULT_3_2_COUNT (8U)
|
|
|
|
/*! @name TRIGn_RESULT_5_4 - ETC_TRIG Result Data 5/4 Register */
|
|
/*! @{ */
|
|
#define ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK (0xFFFU)
|
|
#define ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT (0U)
|
|
#define ADC_ETC_TRIGn_RESULT_5_4_DATA4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK)
|
|
#define ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK (0xFFF0000U)
|
|
#define ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT (16U)
|
|
#define ADC_ETC_TRIGn_RESULT_5_4_DATA5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of ADC_ETC_TRIGn_RESULT_5_4 */
|
|
#define ADC_ETC_TRIGn_RESULT_5_4_COUNT (8U)
|
|
|
|
/*! @name TRIGn_RESULT_7_6 - ETC_TRIG Result Data 7/6 Register */
|
|
/*! @{ */
|
|
#define ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK (0xFFFU)
|
|
#define ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT (0U)
|
|
#define ADC_ETC_TRIGn_RESULT_7_6_DATA6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK)
|
|
#define ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK (0xFFF0000U)
|
|
#define ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT (16U)
|
|
#define ADC_ETC_TRIGn_RESULT_7_6_DATA7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of ADC_ETC_TRIGn_RESULT_7_6 */
|
|
#define ADC_ETC_TRIGn_RESULT_7_6_COUNT (8U)
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group ADC_ETC_Register_Masks */
|
|
|
|
|
|
/* ADC_ETC - Peripheral instance base addresses */
|
|
/** Peripheral ADC_ETC base address */
|
|
#define ADC_ETC_BASE (0x403B0000u)
|
|
/** Peripheral ADC_ETC base pointer */
|
|
#define ADC_ETC ((ADC_ETC_Type *)ADC_ETC_BASE)
|
|
/** Array initializer of ADC_ETC peripheral base addresses */
|
|
#define ADC_ETC_BASE_ADDRS { ADC_ETC_BASE }
|
|
/** Array initializer of ADC_ETC peripheral base pointers */
|
|
#define ADC_ETC_BASE_PTRS { ADC_ETC }
|
|
/** Interrupt vectors for the ADC_ETC peripheral type */
|
|
#define ADC_ETC_IRQS { { ADC_ETC_IRQ0_IRQn, ADC_ETC_IRQ1_IRQn, ADC_ETC_IRQ2_IRQn } }
|
|
#define ADC_ETC_FAULT_IRQS { ADC_ETC_ERROR_IRQ_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group ADC_ETC_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- AIPSTZ Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup AIPSTZ_Peripheral_Access_Layer AIPSTZ Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** AIPSTZ - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */
|
|
uint8_t RESERVED_0[60];
|
|
__IO uint32_t OPACR; /**< Off-Platform Peripheral Access Control Registers, offset: 0x40 */
|
|
__IO uint32_t OPACR1; /**< Off-Platform Peripheral Access Control Registers, offset: 0x44 */
|
|
__IO uint32_t OPACR2; /**< Off-Platform Peripheral Access Control Registers, offset: 0x48 */
|
|
__IO uint32_t OPACR3; /**< Off-Platform Peripheral Access Control Registers, offset: 0x4C */
|
|
__IO uint32_t OPACR4; /**< Off-Platform Peripheral Access Control Registers, offset: 0x50 */
|
|
} AIPSTZ_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- AIPSTZ Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup AIPSTZ_Register_Masks AIPSTZ Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name MPR - Master Priviledge Registers */
|
|
/*! @{ */
|
|
#define AIPSTZ_MPR_MPROT5_MASK (0xF00U)
|
|
#define AIPSTZ_MPR_MPROT5_SHIFT (8U)
|
|
/*! MPROT5
|
|
* 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
|
|
* 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
|
|
* 0bxx0x..This master is not trusted for write accesses.
|
|
* 0bxx1x..This master is trusted for write accesses.
|
|
* 0bx0xx..This master is not trusted for read accesses.
|
|
* 0bx1xx..This master is trusted for read accesses.
|
|
* 0b1xxx..Write accesses from this master are allowed to be buffered
|
|
*/
|
|
#define AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK)
|
|
#define AIPSTZ_MPR_MPROT3_MASK (0xF0000U)
|
|
#define AIPSTZ_MPR_MPROT3_SHIFT (16U)
|
|
/*! MPROT3
|
|
* 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
|
|
* 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
|
|
* 0bxx0x..This master is not trusted for write accesses.
|
|
* 0bxx1x..This master is trusted for write accesses.
|
|
* 0bx0xx..This master is not trusted for read accesses.
|
|
* 0bx1xx..This master is trusted for read accesses.
|
|
* 0b1xxx..Write accesses from this master are allowed to be buffered
|
|
*/
|
|
#define AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK)
|
|
#define AIPSTZ_MPR_MPROT2_MASK (0xF00000U)
|
|
#define AIPSTZ_MPR_MPROT2_SHIFT (20U)
|
|
/*! MPROT2
|
|
* 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
|
|
* 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
|
|
* 0bxx0x..This master is not trusted for write accesses.
|
|
* 0bxx1x..This master is trusted for write accesses.
|
|
* 0bx0xx..This master is not trusted for read accesses.
|
|
* 0bx1xx..This master is trusted for read accesses.
|
|
* 0b1xxx..Write accesses from this master are allowed to be buffered
|
|
*/
|
|
#define AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK)
|
|
#define AIPSTZ_MPR_MPROT1_MASK (0xF000000U)
|
|
#define AIPSTZ_MPR_MPROT1_SHIFT (24U)
|
|
/*! MPROT1
|
|
* 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
|
|
* 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
|
|
* 0bxx0x..This master is not trusted for write accesses.
|
|
* 0bxx1x..This master is trusted for write accesses.
|
|
* 0bx0xx..This master is not trusted for read accesses.
|
|
* 0bx1xx..This master is trusted for read accesses.
|
|
* 0b1xxx..Write accesses from this master are allowed to be buffered
|
|
*/
|
|
#define AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK)
|
|
#define AIPSTZ_MPR_MPROT0_MASK (0xF0000000U)
|
|
#define AIPSTZ_MPR_MPROT0_SHIFT (28U)
|
|
/*! MPROT0
|
|
* 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
|
|
* 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
|
|
* 0bxx0x..This master is not trusted for write accesses.
|
|
* 0bxx1x..This master is trusted for write accesses.
|
|
* 0bx0xx..This master is not trusted for read accesses.
|
|
* 0bx1xx..This master is trusted for read accesses.
|
|
* 0b1xxx..Write accesses from this master are allowed to be buffered
|
|
*/
|
|
#define AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name OPACR - Off-Platform Peripheral Access Control Registers */
|
|
/*! @{ */
|
|
#define AIPSTZ_OPACR_OPAC7_MASK (0xFU)
|
|
#define AIPSTZ_OPACR_OPAC7_SHIFT (0U)
|
|
/*! OPAC7
|
|
* 0bxxx0..Accesses from an untrusted master are allowed.
|
|
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bxx0x..This peripheral allows write accesses.
|
|
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
|
|
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
|
|
*/
|
|
#define AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK)
|
|
#define AIPSTZ_OPACR_OPAC6_MASK (0xF0U)
|
|
#define AIPSTZ_OPACR_OPAC6_SHIFT (4U)
|
|
/*! OPAC6
|
|
* 0bxxx0..Accesses from an untrusted master are allowed.
|
|
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bxx0x..This peripheral allows write accesses.
|
|
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
|
|
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
|
|
*/
|
|
#define AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK)
|
|
#define AIPSTZ_OPACR_OPAC5_MASK (0xF00U)
|
|
#define AIPSTZ_OPACR_OPAC5_SHIFT (8U)
|
|
/*! OPAC5
|
|
* 0bxxx0..Accesses from an untrusted master are allowed.
|
|
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bxx0x..This peripheral allows write accesses.
|
|
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
|
|
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
|
|
*/
|
|
#define AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK)
|
|
#define AIPSTZ_OPACR_OPAC4_MASK (0xF000U)
|
|
#define AIPSTZ_OPACR_OPAC4_SHIFT (12U)
|
|
/*! OPAC4
|
|
* 0bxxx0..Accesses from an untrusted master are allowed.
|
|
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bxx0x..This peripheral allows write accesses.
|
|
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
|
|
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
|
|
*/
|
|
#define AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK)
|
|
#define AIPSTZ_OPACR_OPAC3_MASK (0xF0000U)
|
|
#define AIPSTZ_OPACR_OPAC3_SHIFT (16U)
|
|
/*! OPAC3
|
|
* 0bxxx0..Accesses from an untrusted master are allowed.
|
|
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bxx0x..This peripheral allows write accesses.
|
|
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
|
|
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
|
|
*/
|
|
#define AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK)
|
|
#define AIPSTZ_OPACR_OPAC2_MASK (0xF00000U)
|
|
#define AIPSTZ_OPACR_OPAC2_SHIFT (20U)
|
|
/*! OPAC2
|
|
* 0bxxx0..Accesses from an untrusted master are allowed.
|
|
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bxx0x..This peripheral allows write accesses.
|
|
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
|
|
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
|
|
*/
|
|
#define AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK)
|
|
#define AIPSTZ_OPACR_OPAC1_MASK (0xF000000U)
|
|
#define AIPSTZ_OPACR_OPAC1_SHIFT (24U)
|
|
/*! OPAC1
|
|
* 0bxxx0..Accesses from an untrusted master are allowed.
|
|
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bxx0x..This peripheral allows write accesses.
|
|
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
|
|
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
|
|
*/
|
|
#define AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK)
|
|
#define AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U)
|
|
#define AIPSTZ_OPACR_OPAC0_SHIFT (28U)
|
|
/*! OPAC0
|
|
* 0bxxx0..Accesses from an untrusted master are allowed.
|
|
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bxx0x..This peripheral allows write accesses.
|
|
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
|
|
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
|
|
*/
|
|
#define AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name OPACR1 - Off-Platform Peripheral Access Control Registers */
|
|
/*! @{ */
|
|
#define AIPSTZ_OPACR1_OPAC15_MASK (0xFU)
|
|
#define AIPSTZ_OPACR1_OPAC15_SHIFT (0U)
|
|
/*! OPAC15
|
|
* 0bxxx0..Accesses from an untrusted master are allowed.
|
|
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bxx0x..This peripheral allows write accesses.
|
|
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
|
|
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
|
|
*/
|
|
#define AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK)
|
|
#define AIPSTZ_OPACR1_OPAC14_MASK (0xF0U)
|
|
#define AIPSTZ_OPACR1_OPAC14_SHIFT (4U)
|
|
/*! OPAC14
|
|
* 0bxxx0..Accesses from an untrusted master are allowed.
|
|
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bxx0x..This peripheral allows write accesses.
|
|
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
|
|
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
|
|
*/
|
|
#define AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK)
|
|
#define AIPSTZ_OPACR1_OPAC13_MASK (0xF00U)
|
|
#define AIPSTZ_OPACR1_OPAC13_SHIFT (8U)
|
|
/*! OPAC13
|
|
* 0bxxx0..Accesses from an untrusted master are allowed.
|
|
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bxx0x..This peripheral allows write accesses.
|
|
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
|
|
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
|
|
*/
|
|
#define AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK)
|
|
#define AIPSTZ_OPACR1_OPAC12_MASK (0xF000U)
|
|
#define AIPSTZ_OPACR1_OPAC12_SHIFT (12U)
|
|
/*! OPAC12
|
|
* 0bxxx0..Accesses from an untrusted master are allowed.
|
|
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bxx0x..This peripheral allows write accesses.
|
|
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
|
|
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
|
|
*/
|
|
#define AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK)
|
|
#define AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U)
|
|
#define AIPSTZ_OPACR1_OPAC11_SHIFT (16U)
|
|
/*! OPAC11
|
|
* 0bxxx0..Accesses from an untrusted master are allowed.
|
|
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bxx0x..This peripheral allows write accesses.
|
|
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
|
|
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
|
|
*/
|
|
#define AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK)
|
|
#define AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U)
|
|
#define AIPSTZ_OPACR1_OPAC10_SHIFT (20U)
|
|
/*! OPAC10
|
|
* 0bxxx0..Accesses from an untrusted master are allowed.
|
|
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bxx0x..This peripheral allows write accesses.
|
|
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
|
|
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
|
|
*/
|
|
#define AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK)
|
|
#define AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U)
|
|
#define AIPSTZ_OPACR1_OPAC9_SHIFT (24U)
|
|
/*! OPAC9
|
|
* 0bxxx0..Accesses from an untrusted master are allowed.
|
|
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bxx0x..This peripheral allows write accesses.
|
|
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
|
|
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
|
|
*/
|
|
#define AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK)
|
|
#define AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U)
|
|
#define AIPSTZ_OPACR1_OPAC8_SHIFT (28U)
|
|
/*! OPAC8
|
|
* 0bxxx0..Accesses from an untrusted master are allowed.
|
|
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bxx0x..This peripheral allows write accesses.
|
|
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
|
|
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
|
|
*/
|
|
#define AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name OPACR2 - Off-Platform Peripheral Access Control Registers */
|
|
/*! @{ */
|
|
#define AIPSTZ_OPACR2_OPAC23_MASK (0xFU)
|
|
#define AIPSTZ_OPACR2_OPAC23_SHIFT (0U)
|
|
/*! OPAC23
|
|
* 0bxxx0..Accesses from an untrusted master are allowed.
|
|
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bxx0x..This peripheral allows write accesses.
|
|
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
|
|
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
|
|
*/
|
|
#define AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK)
|
|
#define AIPSTZ_OPACR2_OPAC22_MASK (0xF0U)
|
|
#define AIPSTZ_OPACR2_OPAC22_SHIFT (4U)
|
|
/*! OPAC22
|
|
* 0bxxx0..Accesses from an untrusted master are allowed.
|
|
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bxx0x..This peripheral allows write accesses.
|
|
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
|
|
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
|
|
*/
|
|
#define AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK)
|
|
#define AIPSTZ_OPACR2_OPAC21_MASK (0xF00U)
|
|
#define AIPSTZ_OPACR2_OPAC21_SHIFT (8U)
|
|
/*! OPAC21
|
|
* 0bxxx0..Accesses from an untrusted master are allowed.
|
|
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bxx0x..This peripheral allows write accesses.
|
|
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
|
|
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
|
|
*/
|
|
#define AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK)
|
|
#define AIPSTZ_OPACR2_OPAC20_MASK (0xF000U)
|
|
#define AIPSTZ_OPACR2_OPAC20_SHIFT (12U)
|
|
/*! OPAC20
|
|
* 0bxxx0..Accesses from an untrusted master are allowed.
|
|
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bxx0x..This peripheral allows write accesses.
|
|
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
|
|
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
|
|
*/
|
|
#define AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK)
|
|
#define AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U)
|
|
#define AIPSTZ_OPACR2_OPAC19_SHIFT (16U)
|
|
/*! OPAC19
|
|
* 0bxxx0..Accesses from an untrusted master are allowed.
|
|
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bxx0x..This peripheral allows write accesses.
|
|
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
|
|
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
|
|
*/
|
|
#define AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK)
|
|
#define AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U)
|
|
#define AIPSTZ_OPACR2_OPAC18_SHIFT (20U)
|
|
/*! OPAC18
|
|
* 0bxxx0..Accesses from an untrusted master are allowed.
|
|
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bxx0x..This peripheral allows write accesses.
|
|
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
|
|
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
|
|
*/
|
|
#define AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK)
|
|
#define AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U)
|
|
#define AIPSTZ_OPACR2_OPAC17_SHIFT (24U)
|
|
/*! OPAC17
|
|
* 0bxxx0..Accesses from an untrusted master are allowed.
|
|
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bxx0x..This peripheral allows write accesses.
|
|
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
|
|
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
|
|
*/
|
|
#define AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK)
|
|
#define AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U)
|
|
#define AIPSTZ_OPACR2_OPAC16_SHIFT (28U)
|
|
/*! OPAC16
|
|
* 0bxxx0..Accesses from an untrusted master are allowed.
|
|
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bxx0x..This peripheral allows write accesses.
|
|
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
|
|
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
|
|
*/
|
|
#define AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name OPACR3 - Off-Platform Peripheral Access Control Registers */
|
|
/*! @{ */
|
|
#define AIPSTZ_OPACR3_OPAC31_MASK (0xFU)
|
|
#define AIPSTZ_OPACR3_OPAC31_SHIFT (0U)
|
|
/*! OPAC31
|
|
* 0bxxx0..Accesses from an untrusted master are allowed.
|
|
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bxx0x..This peripheral allows write accesses.
|
|
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
|
|
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
|
|
*/
|
|
#define AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK)
|
|
#define AIPSTZ_OPACR3_OPAC30_MASK (0xF0U)
|
|
#define AIPSTZ_OPACR3_OPAC30_SHIFT (4U)
|
|
/*! OPAC30
|
|
* 0bxxx0..Accesses from an untrusted master are allowed.
|
|
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bxx0x..This peripheral allows write accesses.
|
|
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
|
|
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
|
|
*/
|
|
#define AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK)
|
|
#define AIPSTZ_OPACR3_OPAC29_MASK (0xF00U)
|
|
#define AIPSTZ_OPACR3_OPAC29_SHIFT (8U)
|
|
/*! OPAC29
|
|
* 0bxxx0..Accesses from an untrusted master are allowed.
|
|
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bxx0x..This peripheral allows write accesses.
|
|
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
|
|
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
|
|
*/
|
|
#define AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK)
|
|
#define AIPSTZ_OPACR3_OPAC28_MASK (0xF000U)
|
|
#define AIPSTZ_OPACR3_OPAC28_SHIFT (12U)
|
|
/*! OPAC28
|
|
* 0bxxx0..Accesses from an untrusted master are allowed.
|
|
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bxx0x..This peripheral allows write accesses.
|
|
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
|
|
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
|
|
*/
|
|
#define AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK)
|
|
#define AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U)
|
|
#define AIPSTZ_OPACR3_OPAC27_SHIFT (16U)
|
|
/*! OPAC27
|
|
* 0bxxx0..Accesses from an untrusted master are allowed.
|
|
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bxx0x..This peripheral allows write accesses.
|
|
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
|
|
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
|
|
*/
|
|
#define AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK)
|
|
#define AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U)
|
|
#define AIPSTZ_OPACR3_OPAC26_SHIFT (20U)
|
|
/*! OPAC26
|
|
* 0bxxx0..Accesses from an untrusted master are allowed.
|
|
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bxx0x..This peripheral allows write accesses.
|
|
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
|
|
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
|
|
*/
|
|
#define AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK)
|
|
#define AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U)
|
|
#define AIPSTZ_OPACR3_OPAC25_SHIFT (24U)
|
|
/*! OPAC25
|
|
* 0bxxx0..Accesses from an untrusted master are allowed.
|
|
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bxx0x..This peripheral allows write accesses.
|
|
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
|
|
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
|
|
*/
|
|
#define AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK)
|
|
#define AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U)
|
|
#define AIPSTZ_OPACR3_OPAC24_SHIFT (28U)
|
|
/*! OPAC24
|
|
* 0bxxx0..Accesses from an untrusted master are allowed.
|
|
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bxx0x..This peripheral allows write accesses.
|
|
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
|
|
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
|
|
*/
|
|
#define AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name OPACR4 - Off-Platform Peripheral Access Control Registers */
|
|
/*! @{ */
|
|
#define AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U)
|
|
#define AIPSTZ_OPACR4_OPAC33_SHIFT (24U)
|
|
/*! OPAC33
|
|
* 0bxxx0..Accesses from an untrusted master are allowed.
|
|
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bxx0x..This peripheral allows write accesses.
|
|
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
|
|
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
|
|
*/
|
|
#define AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK)
|
|
#define AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U)
|
|
#define AIPSTZ_OPACR4_OPAC32_SHIFT (28U)
|
|
/*! OPAC32
|
|
* 0bxxx0..Accesses from an untrusted master are allowed.
|
|
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bxx0x..This peripheral allows write accesses.
|
|
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
|
|
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
|
|
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
|
|
*/
|
|
#define AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group AIPSTZ_Register_Masks */
|
|
|
|
|
|
/* AIPSTZ - Peripheral instance base addresses */
|
|
/** Peripheral AIPSTZ1 base address */
|
|
#define AIPSTZ1_BASE (0x4007C000u)
|
|
/** Peripheral AIPSTZ1 base pointer */
|
|
#define AIPSTZ1 ((AIPSTZ_Type *)AIPSTZ1_BASE)
|
|
/** Peripheral AIPSTZ2 base address */
|
|
#define AIPSTZ2_BASE (0x4017C000u)
|
|
/** Peripheral AIPSTZ2 base pointer */
|
|
#define AIPSTZ2 ((AIPSTZ_Type *)AIPSTZ2_BASE)
|
|
/** Peripheral AIPSTZ3 base address */
|
|
#define AIPSTZ3_BASE (0x4027C000u)
|
|
/** Peripheral AIPSTZ3 base pointer */
|
|
#define AIPSTZ3 ((AIPSTZ_Type *)AIPSTZ3_BASE)
|
|
/** Peripheral AIPSTZ4 base address */
|
|
#define AIPSTZ4_BASE (0x4037C000u)
|
|
/** Peripheral AIPSTZ4 base pointer */
|
|
#define AIPSTZ4 ((AIPSTZ_Type *)AIPSTZ4_BASE)
|
|
/** Array initializer of AIPSTZ peripheral base addresses */
|
|
#define AIPSTZ_BASE_ADDRS { 0u, AIPSTZ1_BASE, AIPSTZ2_BASE, AIPSTZ3_BASE, AIPSTZ4_BASE }
|
|
/** Array initializer of AIPSTZ peripheral base pointers */
|
|
#define AIPSTZ_BASE_PTRS { (AIPSTZ_Type *)0u, AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4 }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group AIPSTZ_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- AOI Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup AOI_Peripheral_Access_Layer AOI Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** AOI - Register Layout Typedef */
|
|
typedef struct {
|
|
struct { /* offset: 0x0, array step: 0x4 */
|
|
__IO uint16_t BFCRT01; /**< Boolean Function Term 0 and 1 Configuration Register for EVENTn, array offset: 0x0, array step: 0x4 */
|
|
__IO uint16_t BFCRT23; /**< Boolean Function Term 2 and 3 Configuration Register for EVENTn, array offset: 0x2, array step: 0x4 */
|
|
} BFCRT[4];
|
|
} AOI_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- AOI Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup AOI_Register_Masks AOI Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name BFCRT01 - Boolean Function Term 0 and 1 Configuration Register for EVENTn */
|
|
/*! @{ */
|
|
#define AOI_BFCRT01_PT1_DC_MASK (0x3U)
|
|
#define AOI_BFCRT01_PT1_DC_SHIFT (0U)
|
|
/*! PT1_DC - Product term 1, D input configuration
|
|
* 0b00..Force the D input in this product term to a logical zero
|
|
* 0b01..Pass the D input in this product term
|
|
* 0b10..Complement the D input in this product term
|
|
* 0b11..Force the D input in this product term to a logical one
|
|
*/
|
|
#define AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK)
|
|
#define AOI_BFCRT01_PT1_CC_MASK (0xCU)
|
|
#define AOI_BFCRT01_PT1_CC_SHIFT (2U)
|
|
/*! PT1_CC - Product term 1, C input configuration
|
|
* 0b00..Force the C input in this product term to a logical zero
|
|
* 0b01..Pass the C input in this product term
|
|
* 0b10..Complement the C input in this product term
|
|
* 0b11..Force the C input in this product term to a logical one
|
|
*/
|
|
#define AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK)
|
|
#define AOI_BFCRT01_PT1_BC_MASK (0x30U)
|
|
#define AOI_BFCRT01_PT1_BC_SHIFT (4U)
|
|
/*! PT1_BC - Product term 1, B input configuration
|
|
* 0b00..Force the B input in this product term to a logical zero
|
|
* 0b01..Pass the B input in this product term
|
|
* 0b10..Complement the B input in this product term
|
|
* 0b11..Force the B input in this product term to a logical one
|
|
*/
|
|
#define AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK)
|
|
#define AOI_BFCRT01_PT1_AC_MASK (0xC0U)
|
|
#define AOI_BFCRT01_PT1_AC_SHIFT (6U)
|
|
/*! PT1_AC - Product term 1, A input configuration
|
|
* 0b00..Force the A input in this product term to a logical zero
|
|
* 0b01..Pass the A input in this product term
|
|
* 0b10..Complement the A input in this product term
|
|
* 0b11..Force the A input in this product term to a logical one
|
|
*/
|
|
#define AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK)
|
|
#define AOI_BFCRT01_PT0_DC_MASK (0x300U)
|
|
#define AOI_BFCRT01_PT0_DC_SHIFT (8U)
|
|
/*! PT0_DC - Product term 0, D input configuration
|
|
* 0b00..Force the D input in this product term to a logical zero
|
|
* 0b01..Pass the D input in this product term
|
|
* 0b10..Complement the D input in this product term
|
|
* 0b11..Force the D input in this product term to a logical one
|
|
*/
|
|
#define AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK)
|
|
#define AOI_BFCRT01_PT0_CC_MASK (0xC00U)
|
|
#define AOI_BFCRT01_PT0_CC_SHIFT (10U)
|
|
/*! PT0_CC - Product term 0, C input configuration
|
|
* 0b00..Force the C input in this product term to a logical zero
|
|
* 0b01..Pass the C input in this product term
|
|
* 0b10..Complement the C input in this product term
|
|
* 0b11..Force the C input in this product term to a logical one
|
|
*/
|
|
#define AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK)
|
|
#define AOI_BFCRT01_PT0_BC_MASK (0x3000U)
|
|
#define AOI_BFCRT01_PT0_BC_SHIFT (12U)
|
|
/*! PT0_BC - Product term 0, B input configuration
|
|
* 0b00..Force the B input in this product term to a logical zero
|
|
* 0b01..Pass the B input in this product term
|
|
* 0b10..Complement the B input in this product term
|
|
* 0b11..Force the B input in this product term to a logical one
|
|
*/
|
|
#define AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK)
|
|
#define AOI_BFCRT01_PT0_AC_MASK (0xC000U)
|
|
#define AOI_BFCRT01_PT0_AC_SHIFT (14U)
|
|
/*! PT0_AC - Product term 0, A input configuration
|
|
* 0b00..Force the A input in this product term to a logical zero
|
|
* 0b01..Pass the A input in this product term
|
|
* 0b10..Complement the A input in this product term
|
|
* 0b11..Force the A input in this product term to a logical one
|
|
*/
|
|
#define AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of AOI_BFCRT01 */
|
|
#define AOI_BFCRT01_COUNT (4U)
|
|
|
|
/*! @name BFCRT23 - Boolean Function Term 2 and 3 Configuration Register for EVENTn */
|
|
/*! @{ */
|
|
#define AOI_BFCRT23_PT3_DC_MASK (0x3U)
|
|
#define AOI_BFCRT23_PT3_DC_SHIFT (0U)
|
|
/*! PT3_DC - Product term 3, D input configuration
|
|
* 0b00..Force the D input in this product term to a logical zero
|
|
* 0b01..Pass the D input in this product term
|
|
* 0b10..Complement the D input in this product term
|
|
* 0b11..Force the D input in this product term to a logical one
|
|
*/
|
|
#define AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK)
|
|
#define AOI_BFCRT23_PT3_CC_MASK (0xCU)
|
|
#define AOI_BFCRT23_PT3_CC_SHIFT (2U)
|
|
/*! PT3_CC - Product term 3, C input configuration
|
|
* 0b00..Force the C input in this product term to a logical zero
|
|
* 0b01..Pass the C input in this product term
|
|
* 0b10..Complement the C input in this product term
|
|
* 0b11..Force the C input in this product term to a logical one
|
|
*/
|
|
#define AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK)
|
|
#define AOI_BFCRT23_PT3_BC_MASK (0x30U)
|
|
#define AOI_BFCRT23_PT3_BC_SHIFT (4U)
|
|
/*! PT3_BC - Product term 3, B input configuration
|
|
* 0b00..Force the B input in this product term to a logical zero
|
|
* 0b01..Pass the B input in this product term
|
|
* 0b10..Complement the B input in this product term
|
|
* 0b11..Force the B input in this product term to a logical one
|
|
*/
|
|
#define AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK)
|
|
#define AOI_BFCRT23_PT3_AC_MASK (0xC0U)
|
|
#define AOI_BFCRT23_PT3_AC_SHIFT (6U)
|
|
/*! PT3_AC - Product term 3, A input configuration
|
|
* 0b00..Force the A input in this product term to a logical zero
|
|
* 0b01..Pass the A input in this product term
|
|
* 0b10..Complement the A input in this product term
|
|
* 0b11..Force the A input in this product term to a logical one
|
|
*/
|
|
#define AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK)
|
|
#define AOI_BFCRT23_PT2_DC_MASK (0x300U)
|
|
#define AOI_BFCRT23_PT2_DC_SHIFT (8U)
|
|
/*! PT2_DC - Product term 2, D input configuration
|
|
* 0b00..Force the D input in this product term to a logical zero
|
|
* 0b01..Pass the D input in this product term
|
|
* 0b10..Complement the D input in this product term
|
|
* 0b11..Force the D input in this product term to a logical one
|
|
*/
|
|
#define AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK)
|
|
#define AOI_BFCRT23_PT2_CC_MASK (0xC00U)
|
|
#define AOI_BFCRT23_PT2_CC_SHIFT (10U)
|
|
/*! PT2_CC - Product term 2, C input configuration
|
|
* 0b00..Force the C input in this product term to a logical zero
|
|
* 0b01..Pass the C input in this product term
|
|
* 0b10..Complement the C input in this product term
|
|
* 0b11..Force the C input in this product term to a logical one
|
|
*/
|
|
#define AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK)
|
|
#define AOI_BFCRT23_PT2_BC_MASK (0x3000U)
|
|
#define AOI_BFCRT23_PT2_BC_SHIFT (12U)
|
|
/*! PT2_BC - Product term 2, B input configuration
|
|
* 0b00..Force the B input in this product term to a logical zero
|
|
* 0b01..Pass the B input in this product term
|
|
* 0b10..Complement the B input in this product term
|
|
* 0b11..Force the B input in this product term to a logical one
|
|
*/
|
|
#define AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK)
|
|
#define AOI_BFCRT23_PT2_AC_MASK (0xC000U)
|
|
#define AOI_BFCRT23_PT2_AC_SHIFT (14U)
|
|
/*! PT2_AC - Product term 2, A input configuration
|
|
* 0b00..Force the A input in this product term to a logical zero
|
|
* 0b01..Pass the A input in this product term
|
|
* 0b10..Complement the A input in this product term
|
|
* 0b11..Force the A input in this product term to a logical one
|
|
*/
|
|
#define AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of AOI_BFCRT23 */
|
|
#define AOI_BFCRT23_COUNT (4U)
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group AOI_Register_Masks */
|
|
|
|
|
|
/* AOI - Peripheral instance base addresses */
|
|
/** Peripheral AOI1 base address */
|
|
#define AOI1_BASE (0x403B4000u)
|
|
/** Peripheral AOI1 base pointer */
|
|
#define AOI1 ((AOI_Type *)AOI1_BASE)
|
|
/** Peripheral AOI2 base address */
|
|
#define AOI2_BASE (0x403B8000u)
|
|
/** Peripheral AOI2 base pointer */
|
|
#define AOI2 ((AOI_Type *)AOI2_BASE)
|
|
/** Array initializer of AOI peripheral base addresses */
|
|
#define AOI_BASE_ADDRS { 0u, AOI1_BASE, AOI2_BASE }
|
|
/** Array initializer of AOI peripheral base pointers */
|
|
#define AOI_BASE_PTRS { (AOI_Type *)0u, AOI1, AOI2 }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group AOI_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- BEE Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup BEE_Peripheral_Access_Layer BEE Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** BEE - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t CTRL; /**< BEE Control Register, offset: 0x0 */
|
|
__IO uint32_t ADDR_OFFSET0; /**< , offset: 0x4 */
|
|
__IO uint32_t ADDR_OFFSET1; /**< , offset: 0x8 */
|
|
__IO uint32_t AES_KEY0_W0; /**< , offset: 0xC */
|
|
__IO uint32_t AES_KEY0_W1; /**< , offset: 0x10 */
|
|
__IO uint32_t AES_KEY0_W2; /**< , offset: 0x14 */
|
|
__IO uint32_t AES_KEY0_W3; /**< , offset: 0x18 */
|
|
__IO uint32_t STATUS; /**< , offset: 0x1C */
|
|
__O uint32_t CTR_NONCE0_W0; /**< , offset: 0x20 */
|
|
__O uint32_t CTR_NONCE0_W1; /**< , offset: 0x24 */
|
|
__O uint32_t CTR_NONCE0_W2; /**< , offset: 0x28 */
|
|
__O uint32_t CTR_NONCE0_W3; /**< , offset: 0x2C */
|
|
__O uint32_t CTR_NONCE1_W0; /**< , offset: 0x30 */
|
|
__O uint32_t CTR_NONCE1_W1; /**< , offset: 0x34 */
|
|
__O uint32_t CTR_NONCE1_W2; /**< , offset: 0x38 */
|
|
__O uint32_t CTR_NONCE1_W3; /**< , offset: 0x3C */
|
|
__IO uint32_t REGION1_TOP; /**< , offset: 0x40 */
|
|
__IO uint32_t REGION1_BOT; /**< , offset: 0x44 */
|
|
} BEE_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- BEE Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup BEE_Register_Masks BEE Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name CTRL - BEE Control Register */
|
|
/*! @{ */
|
|
#define BEE_CTRL_BEE_ENABLE_MASK (0x1U)
|
|
#define BEE_CTRL_BEE_ENABLE_SHIFT (0U)
|
|
/*! BEE_ENABLE
|
|
* 0b0..Disable BEE
|
|
* 0b1..Enable BEE
|
|
*/
|
|
#define BEE_CTRL_BEE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_SHIFT)) & BEE_CTRL_BEE_ENABLE_MASK)
|
|
#define BEE_CTRL_CTRL_CLK_EN_MASK (0x2U)
|
|
#define BEE_CTRL_CTRL_CLK_EN_SHIFT (1U)
|
|
#define BEE_CTRL_CTRL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_MASK)
|
|
#define BEE_CTRL_CTRL_SFTRST_N_MASK (0x4U)
|
|
#define BEE_CTRL_CTRL_SFTRST_N_SHIFT (2U)
|
|
#define BEE_CTRL_CTRL_SFTRST_N(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_MASK)
|
|
#define BEE_CTRL_KEY_VALID_MASK (0x10U)
|
|
#define BEE_CTRL_KEY_VALID_SHIFT (4U)
|
|
#define BEE_CTRL_KEY_VALID(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_SHIFT)) & BEE_CTRL_KEY_VALID_MASK)
|
|
#define BEE_CTRL_KEY_REGION_SEL_MASK (0x20U)
|
|
#define BEE_CTRL_KEY_REGION_SEL_SHIFT (5U)
|
|
/*! KEY_REGION_SEL
|
|
* 0b0..Load AES key for region0
|
|
* 0b1..Load AES key for region1
|
|
*/
|
|
#define BEE_CTRL_KEY_REGION_SEL(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_MASK)
|
|
#define BEE_CTRL_AC_PROT_EN_MASK (0x40U)
|
|
#define BEE_CTRL_AC_PROT_EN_SHIFT (6U)
|
|
#define BEE_CTRL_AC_PROT_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_SHIFT)) & BEE_CTRL_AC_PROT_EN_MASK)
|
|
#define BEE_CTRL_LITTLE_ENDIAN_MASK (0x80U)
|
|
#define BEE_CTRL_LITTLE_ENDIAN_SHIFT (7U)
|
|
/*! LITTLE_ENDIAN
|
|
* 0b0..The input and output data of the AES core is swapped as below: {B15,B14,B13,B12,B11,B10,B9,B8, B7,B6,B5,B4,B3,B2,B1,B0} swap to {B0,B1,B2,B3,B4,B5,B6,B7, B8,B9,B10,B11,B12,B13,B14,B15}, where B0~B15 refers to Byte0 to Byte15.
|
|
* 0b1..The input and output data of AES core is not swapped.
|
|
*/
|
|
#define BEE_CTRL_LITTLE_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_MASK)
|
|
#define BEE_CTRL_SECURITY_LEVEL_R0_MASK (0x300U)
|
|
#define BEE_CTRL_SECURITY_LEVEL_R0_SHIFT (8U)
|
|
#define BEE_CTRL_SECURITY_LEVEL_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_MASK)
|
|
#define BEE_CTRL_CTRL_AES_MODE_R0_MASK (0x400U)
|
|
#define BEE_CTRL_CTRL_AES_MODE_R0_SHIFT (10U)
|
|
/*! CTRL_AES_MODE_R0
|
|
* 0b0..ECB
|
|
* 0b1..CTR
|
|
*/
|
|
#define BEE_CTRL_CTRL_AES_MODE_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_MASK)
|
|
#define BEE_CTRL_SECURITY_LEVEL_R1_MASK (0x3000U)
|
|
#define BEE_CTRL_SECURITY_LEVEL_R1_SHIFT (12U)
|
|
#define BEE_CTRL_SECURITY_LEVEL_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_MASK)
|
|
#define BEE_CTRL_CTRL_AES_MODE_R1_MASK (0x4000U)
|
|
#define BEE_CTRL_CTRL_AES_MODE_R1_SHIFT (14U)
|
|
/*! CTRL_AES_MODE_R1
|
|
* 0b0..ECB
|
|
* 0b1..CTR
|
|
*/
|
|
#define BEE_CTRL_CTRL_AES_MODE_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_MASK)
|
|
#define BEE_CTRL_BEE_ENABLE_LOCK_MASK (0x10000U)
|
|
#define BEE_CTRL_BEE_ENABLE_LOCK_SHIFT (16U)
|
|
#define BEE_CTRL_BEE_ENABLE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_LOCK_SHIFT)) & BEE_CTRL_BEE_ENABLE_LOCK_MASK)
|
|
#define BEE_CTRL_CTRL_CLK_EN_LOCK_MASK (0x20000U)
|
|
#define BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT (17U)
|
|
#define BEE_CTRL_CTRL_CLK_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_LOCK_MASK)
|
|
#define BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK (0x40000U)
|
|
#define BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT (18U)
|
|
#define BEE_CTRL_CTRL_SFTRST_N_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK)
|
|
#define BEE_CTRL_REGION1_ADDR_LOCK_MASK (0x80000U)
|
|
#define BEE_CTRL_REGION1_ADDR_LOCK_SHIFT (19U)
|
|
#define BEE_CTRL_REGION1_ADDR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_ADDR_LOCK_SHIFT)) & BEE_CTRL_REGION1_ADDR_LOCK_MASK)
|
|
#define BEE_CTRL_KEY_VALID_LOCK_MASK (0x100000U)
|
|
#define BEE_CTRL_KEY_VALID_LOCK_SHIFT (20U)
|
|
#define BEE_CTRL_KEY_VALID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_LOCK_SHIFT)) & BEE_CTRL_KEY_VALID_LOCK_MASK)
|
|
#define BEE_CTRL_KEY_REGION_SEL_LOCK_MASK (0x200000U)
|
|
#define BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT (21U)
|
|
#define BEE_CTRL_KEY_REGION_SEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_LOCK_MASK)
|
|
#define BEE_CTRL_AC_PROT_EN_LOCK_MASK (0x400000U)
|
|
#define BEE_CTRL_AC_PROT_EN_LOCK_SHIFT (22U)
|
|
#define BEE_CTRL_AC_PROT_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_LOCK_SHIFT)) & BEE_CTRL_AC_PROT_EN_LOCK_MASK)
|
|
#define BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK (0x800000U)
|
|
#define BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT (23U)
|
|
#define BEE_CTRL_LITTLE_ENDIAN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK)
|
|
#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK (0x3000000U)
|
|
#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT (24U)
|
|
#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK)
|
|
#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK (0x4000000U)
|
|
#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT (26U)
|
|
#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK)
|
|
#define BEE_CTRL_REGION0_KEY_LOCK_MASK (0x8000000U)
|
|
#define BEE_CTRL_REGION0_KEY_LOCK_SHIFT (27U)
|
|
#define BEE_CTRL_REGION0_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION0_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION0_KEY_LOCK_MASK)
|
|
#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK (0x30000000U)
|
|
#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT (28U)
|
|
#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK)
|
|
#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK (0x40000000U)
|
|
#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT (30U)
|
|
#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK)
|
|
#define BEE_CTRL_REGION1_KEY_LOCK_MASK (0x80000000U)
|
|
#define BEE_CTRL_REGION1_KEY_LOCK_SHIFT (31U)
|
|
#define BEE_CTRL_REGION1_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION1_KEY_LOCK_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ADDR_OFFSET0 - */
|
|
/*! @{ */
|
|
#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK (0xFFFFU)
|
|
#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT (0U)
|
|
#define BEE_ADDR_OFFSET0_ADDR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK)
|
|
#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK (0xFFFF0000U)
|
|
#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT (16U)
|
|
#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ADDR_OFFSET1 - */
|
|
/*! @{ */
|
|
#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK (0xFFFFU)
|
|
#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT (0U)
|
|
#define BEE_ADDR_OFFSET1_ADDR_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK)
|
|
#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK (0xFFFF0000U)
|
|
#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT (16U)
|
|
#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name AES_KEY0_W0 - */
|
|
/*! @{ */
|
|
#define BEE_AES_KEY0_W0_KEY0_MASK (0xFFFFFFFFU)
|
|
#define BEE_AES_KEY0_W0_KEY0_SHIFT (0U)
|
|
#define BEE_AES_KEY0_W0_KEY0(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W0_KEY0_SHIFT)) & BEE_AES_KEY0_W0_KEY0_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name AES_KEY0_W1 - */
|
|
/*! @{ */
|
|
#define BEE_AES_KEY0_W1_KEY1_MASK (0xFFFFFFFFU)
|
|
#define BEE_AES_KEY0_W1_KEY1_SHIFT (0U)
|
|
#define BEE_AES_KEY0_W1_KEY1(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W1_KEY1_SHIFT)) & BEE_AES_KEY0_W1_KEY1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name AES_KEY0_W2 - */
|
|
/*! @{ */
|
|
#define BEE_AES_KEY0_W2_KEY2_MASK (0xFFFFFFFFU)
|
|
#define BEE_AES_KEY0_W2_KEY2_SHIFT (0U)
|
|
#define BEE_AES_KEY0_W2_KEY2(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W2_KEY2_SHIFT)) & BEE_AES_KEY0_W2_KEY2_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name AES_KEY0_W3 - */
|
|
/*! @{ */
|
|
#define BEE_AES_KEY0_W3_KEY3_MASK (0xFFFFFFFFU)
|
|
#define BEE_AES_KEY0_W3_KEY3_SHIFT (0U)
|
|
#define BEE_AES_KEY0_W3_KEY3(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W3_KEY3_SHIFT)) & BEE_AES_KEY0_W3_KEY3_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name STATUS - */
|
|
/*! @{ */
|
|
#define BEE_STATUS_IRQ_VEC_MASK (0xFFU)
|
|
#define BEE_STATUS_IRQ_VEC_SHIFT (0U)
|
|
#define BEE_STATUS_IRQ_VEC(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_IRQ_VEC_SHIFT)) & BEE_STATUS_IRQ_VEC_MASK)
|
|
#define BEE_STATUS_BEE_IDLE_MASK (0x100U)
|
|
#define BEE_STATUS_BEE_IDLE_SHIFT (8U)
|
|
#define BEE_STATUS_BEE_IDLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_BEE_IDLE_SHIFT)) & BEE_STATUS_BEE_IDLE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CTR_NONCE0_W0 - */
|
|
/*! @{ */
|
|
#define BEE_CTR_NONCE0_W0_NONCE00_MASK (0xFFFFFFFFU)
|
|
#define BEE_CTR_NONCE0_W0_NONCE00_SHIFT (0U)
|
|
#define BEE_CTR_NONCE0_W0_NONCE00(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W0_NONCE00_SHIFT)) & BEE_CTR_NONCE0_W0_NONCE00_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CTR_NONCE0_W1 - */
|
|
/*! @{ */
|
|
#define BEE_CTR_NONCE0_W1_NONCE01_MASK (0xFFFFFFFFU)
|
|
#define BEE_CTR_NONCE0_W1_NONCE01_SHIFT (0U)
|
|
#define BEE_CTR_NONCE0_W1_NONCE01(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W1_NONCE01_SHIFT)) & BEE_CTR_NONCE0_W1_NONCE01_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CTR_NONCE0_W2 - */
|
|
/*! @{ */
|
|
#define BEE_CTR_NONCE0_W2_NONCE02_MASK (0xFFFFFFFFU)
|
|
#define BEE_CTR_NONCE0_W2_NONCE02_SHIFT (0U)
|
|
#define BEE_CTR_NONCE0_W2_NONCE02(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W2_NONCE02_SHIFT)) & BEE_CTR_NONCE0_W2_NONCE02_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CTR_NONCE0_W3 - */
|
|
/*! @{ */
|
|
#define BEE_CTR_NONCE0_W3_NONCE03_MASK (0xFFFFFFFFU)
|
|
#define BEE_CTR_NONCE0_W3_NONCE03_SHIFT (0U)
|
|
#define BEE_CTR_NONCE0_W3_NONCE03(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W3_NONCE03_SHIFT)) & BEE_CTR_NONCE0_W3_NONCE03_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CTR_NONCE1_W0 - */
|
|
/*! @{ */
|
|
#define BEE_CTR_NONCE1_W0_NONCE10_MASK (0xFFFFFFFFU)
|
|
#define BEE_CTR_NONCE1_W0_NONCE10_SHIFT (0U)
|
|
#define BEE_CTR_NONCE1_W0_NONCE10(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W0_NONCE10_SHIFT)) & BEE_CTR_NONCE1_W0_NONCE10_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CTR_NONCE1_W1 - */
|
|
/*! @{ */
|
|
#define BEE_CTR_NONCE1_W1_NONCE11_MASK (0xFFFFFFFFU)
|
|
#define BEE_CTR_NONCE1_W1_NONCE11_SHIFT (0U)
|
|
#define BEE_CTR_NONCE1_W1_NONCE11(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W1_NONCE11_SHIFT)) & BEE_CTR_NONCE1_W1_NONCE11_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CTR_NONCE1_W2 - */
|
|
/*! @{ */
|
|
#define BEE_CTR_NONCE1_W2_NONCE12_MASK (0xFFFFFFFFU)
|
|
#define BEE_CTR_NONCE1_W2_NONCE12_SHIFT (0U)
|
|
#define BEE_CTR_NONCE1_W2_NONCE12(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W2_NONCE12_SHIFT)) & BEE_CTR_NONCE1_W2_NONCE12_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CTR_NONCE1_W3 - */
|
|
/*! @{ */
|
|
#define BEE_CTR_NONCE1_W3_NONCE13_MASK (0xFFFFFFFFU)
|
|
#define BEE_CTR_NONCE1_W3_NONCE13_SHIFT (0U)
|
|
#define BEE_CTR_NONCE1_W3_NONCE13(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W3_NONCE13_SHIFT)) & BEE_CTR_NONCE1_W3_NONCE13_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name REGION1_TOP - */
|
|
/*! @{ */
|
|
#define BEE_REGION1_TOP_REGION1_TOP_MASK (0xFFFFFFFFU)
|
|
#define BEE_REGION1_TOP_REGION1_TOP_SHIFT (0U)
|
|
#define BEE_REGION1_TOP_REGION1_TOP(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_TOP_REGION1_TOP_SHIFT)) & BEE_REGION1_TOP_REGION1_TOP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name REGION1_BOT - */
|
|
/*! @{ */
|
|
#define BEE_REGION1_BOT_REGION1_BOT_MASK (0xFFFFFFFFU)
|
|
#define BEE_REGION1_BOT_REGION1_BOT_SHIFT (0U)
|
|
#define BEE_REGION1_BOT_REGION1_BOT(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_BOT_REGION1_BOT_SHIFT)) & BEE_REGION1_BOT_REGION1_BOT_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group BEE_Register_Masks */
|
|
|
|
|
|
/* BEE - Peripheral instance base addresses */
|
|
/** Peripheral BEE base address */
|
|
#define BEE_BASE (0x403EC000u)
|
|
/** Peripheral BEE base pointer */
|
|
#define BEE ((BEE_Type *)BEE_BASE)
|
|
/** Array initializer of BEE peripheral base addresses */
|
|
#define BEE_BASE_ADDRS { BEE_BASE }
|
|
/** Array initializer of BEE peripheral base pointers */
|
|
#define BEE_BASE_PTRS { BEE }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group BEE_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- CAN Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** CAN - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
|
|
__IO uint32_t CTRL1; /**< Control 1 Register, offset: 0x4 */
|
|
__IO uint32_t TIMER; /**< Free Running Timer Register, offset: 0x8 */
|
|
uint8_t RESERVED_0[4];
|
|
__IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
|
|
__IO uint32_t RX14MASK; /**< Rx Buffer 14 Mask Register, offset: 0x14 */
|
|
__IO uint32_t RX15MASK; /**< Rx Buffer 15 Mask Register, offset: 0x18 */
|
|
__IO uint32_t ECR; /**< Error Counter Register, offset: 0x1C */
|
|
__IO uint32_t ESR1; /**< Error and Status 1 Register, offset: 0x20 */
|
|
__IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */
|
|
__IO uint32_t IMASK1; /**< Interrupt Masks 1 Register, offset: 0x28 */
|
|
__IO uint32_t IFLAG2; /**< Interrupt Flags 2 Register, offset: 0x2C */
|
|
__IO uint32_t IFLAG1; /**< Interrupt Flags 1 Register, offset: 0x30 */
|
|
__IO uint32_t CTRL2; /**< Control 2 Register, offset: 0x34 */
|
|
__I uint32_t ESR2; /**< Error and Status 2 Register, offset: 0x38 */
|
|
uint8_t RESERVED_1[8];
|
|
__I uint32_t CRCR; /**< CRC Register, offset: 0x44 */
|
|
__IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask Register, offset: 0x48 */
|
|
__I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */
|
|
uint8_t RESERVED_2[8];
|
|
__I uint32_t DBG1; /**< Debug 1 register, offset: 0x58 */
|
|
__I uint32_t DBG2; /**< Debug 2 register, offset: 0x5C */
|
|
uint8_t RESERVED_3[32];
|
|
struct { /* offset: 0x80, array step: 0x10 */
|
|
__IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */
|
|
__IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */
|
|
__IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */
|
|
__IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */
|
|
} MB[64];
|
|
uint8_t RESERVED_4[1024];
|
|
__IO uint32_t RXIMR[64]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
|
|
uint8_t RESERVED_5[96];
|
|
__IO uint32_t GFWR; /**< Glitch Filter Width Registers, offset: 0x9E0 */
|
|
} CAN_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- CAN Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup CAN_Register_Masks CAN Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name MCR - Module Configuration Register */
|
|
/*! @{ */
|
|
#define CAN_MCR_MAXMB_MASK (0x7FU)
|
|
#define CAN_MCR_MAXMB_SHIFT (0U)
|
|
#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
|
|
#define CAN_MCR_IDAM_MASK (0x300U)
|
|
#define CAN_MCR_IDAM_SHIFT (8U)
|
|
/*! IDAM
|
|
* 0b00..Format A One full ID (standard or extended) per ID filter Table element.
|
|
* 0b01..Format B Two full standard IDs or two partial 14-bit extended IDs per ID filter Table element.
|
|
* 0b10..Format C Four partial 8-bit IDs (standard or extended) per ID filter Table element.
|
|
* 0b11..Format D All frames rejected.
|
|
*/
|
|
#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
|
|
#define CAN_MCR_AEN_MASK (0x1000U)
|
|
#define CAN_MCR_AEN_SHIFT (12U)
|
|
/*! AEN
|
|
* 0b1..Abort enabled
|
|
* 0b0..Abort disabled
|
|
*/
|
|
#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
|
|
#define CAN_MCR_LPRIOEN_MASK (0x2000U)
|
|
#define CAN_MCR_LPRIOEN_SHIFT (13U)
|
|
/*! LPRIOEN
|
|
* 0b1..Local Priority enabled
|
|
* 0b0..Local Priority disabled
|
|
*/
|
|
#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
|
|
#define CAN_MCR_IRMQ_MASK (0x10000U)
|
|
#define CAN_MCR_IRMQ_SHIFT (16U)
|
|
/*! IRMQ
|
|
* 0b1..Individual Rx masking and queue feature are enabled.
|
|
* 0b0..Individual Rx masking and queue feature are disabled.For backward compatibility, the reading of C/S word locks the MB even if it is EMPTY.
|
|
*/
|
|
#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
|
|
#define CAN_MCR_SRXDIS_MASK (0x20000U)
|
|
#define CAN_MCR_SRXDIS_SHIFT (17U)
|
|
/*! SRXDIS
|
|
* 0b1..Self reception disabled
|
|
* 0b0..Self reception enabled
|
|
*/
|
|
#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
|
|
#define CAN_MCR_WAKSRC_MASK (0x80000U)
|
|
#define CAN_MCR_WAKSRC_SHIFT (19U)
|
|
/*! WAKSRC
|
|
* 0b1..FLEXCAN uses the filtered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus
|
|
* 0b0..FLEXCAN uses the unfiltered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus.
|
|
*/
|
|
#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
|
|
#define CAN_MCR_LPMACK_MASK (0x100000U)
|
|
#define CAN_MCR_LPMACK_SHIFT (20U)
|
|
/*! LPMACK
|
|
* 0b1..FLEXCAN is either in Disable Mode, or Stop mode
|
|
* 0b0..FLEXCAN not in any of the low power modes
|
|
*/
|
|
#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
|
|
#define CAN_MCR_WRNEN_MASK (0x200000U)
|
|
#define CAN_MCR_WRNEN_SHIFT (21U)
|
|
/*! WRNEN
|
|
* 0b1..TWRN_INT and RWRN_INT bits are set when the respective error counter transition from <96 to >= 96.
|
|
* 0b0..TWRN_INT and RWRN_INT bits are zero, independent of the values in the error counters.
|
|
*/
|
|
#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
|
|
#define CAN_MCR_SLFWAK_MASK (0x400000U)
|
|
#define CAN_MCR_SLFWAK_SHIFT (22U)
|
|
/*! SLFWAK
|
|
* 0b1..FLEXCAN Self Wake Up feature is enabled
|
|
* 0b0..FLEXCAN Self Wake Up feature is disabled
|
|
*/
|
|
#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
|
|
#define CAN_MCR_SUPV_MASK (0x800000U)
|
|
#define CAN_MCR_SUPV_SHIFT (23U)
|
|
/*! SUPV
|
|
* 0b1..FlexCAN is in Supervisor Mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location
|
|
* 0b0..FlexCAN is in User Mode. Affected registers allow both Supervisor and Unrestricted accesses
|
|
*/
|
|
#define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
|
|
#define CAN_MCR_FRZACK_MASK (0x1000000U)
|
|
#define CAN_MCR_FRZACK_SHIFT (24U)
|
|
/*! FRZACK
|
|
* 0b1..FLEXCAN in Freeze Mode, prescaler stopped
|
|
* 0b0..FLEXCAN not in Freeze Mode, prescaler running
|
|
*/
|
|
#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
|
|
#define CAN_MCR_SOFTRST_MASK (0x2000000U)
|
|
#define CAN_MCR_SOFTRST_SHIFT (25U)
|
|
/*! SOFTRST
|
|
* 0b1..Reset the registers
|
|
* 0b0..No reset request
|
|
*/
|
|
#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
|
|
#define CAN_MCR_WAKMSK_MASK (0x4000000U)
|
|
#define CAN_MCR_WAKMSK_SHIFT (26U)
|
|
/*! WAKMSK
|
|
* 0b1..Wake Up Interrupt is enabled
|
|
* 0b0..Wake Up Interrupt is disabled
|
|
*/
|
|
#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
|
|
#define CAN_MCR_NOTRDY_MASK (0x8000000U)
|
|
#define CAN_MCR_NOTRDY_SHIFT (27U)
|
|
/*! NOTRDY
|
|
* 0b1..FLEXCAN module is either in Disable Mode, Stop Mode or Freeze Mode
|
|
* 0b0..FLEXCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode
|
|
*/
|
|
#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
|
|
#define CAN_MCR_HALT_MASK (0x10000000U)
|
|
#define CAN_MCR_HALT_SHIFT (28U)
|
|
/*! HALT
|
|
* 0b1..Enters Freeze Mode if the FRZ bit is asserted.
|
|
* 0b0..No Freeze Mode request.
|
|
*/
|
|
#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
|
|
#define CAN_MCR_RFEN_MASK (0x20000000U)
|
|
#define CAN_MCR_RFEN_SHIFT (29U)
|
|
/*! RFEN
|
|
* 0b1..FIFO enabled
|
|
* 0b0..FIFO not enabled
|
|
*/
|
|
#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
|
|
#define CAN_MCR_FRZ_MASK (0x40000000U)
|
|
#define CAN_MCR_FRZ_SHIFT (30U)
|
|
/*! FRZ
|
|
* 0b1..Enabled to enter Freeze Mode
|
|
* 0b0..Not enabled to enter Freeze Mode
|
|
*/
|
|
#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
|
|
#define CAN_MCR_MDIS_MASK (0x80000000U)
|
|
#define CAN_MCR_MDIS_SHIFT (31U)
|
|
/*! MDIS
|
|
* 0b1..Disable the FLEXCAN module
|
|
* 0b0..Enable the FLEXCAN module
|
|
*/
|
|
#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CTRL1 - Control 1 Register */
|
|
/*! @{ */
|
|
#define CAN_CTRL1_PROPSEG_MASK (0x7U)
|
|
#define CAN_CTRL1_PROPSEG_SHIFT (0U)
|
|
#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
|
|
#define CAN_CTRL1_LOM_MASK (0x8U)
|
|
#define CAN_CTRL1_LOM_SHIFT (3U)
|
|
/*! LOM
|
|
* 0b1..FLEXCAN module operates in Listen Only Mode
|
|
* 0b0..Listen Only Mode is deactivated
|
|
*/
|
|
#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
|
|
#define CAN_CTRL1_LBUF_MASK (0x10U)
|
|
#define CAN_CTRL1_LBUF_SHIFT (4U)
|
|
/*! LBUF
|
|
* 0b1..Lowest number buffer is transmitted first
|
|
* 0b0..Buffer with highest priority is transmitted first
|
|
*/
|
|
#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
|
|
#define CAN_CTRL1_TSYN_MASK (0x20U)
|
|
#define CAN_CTRL1_TSYN_SHIFT (5U)
|
|
/*! TSYN
|
|
* 0b1..Timer Sync feature enabled
|
|
* 0b0..Timer Sync feature disabled
|
|
*/
|
|
#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
|
|
#define CAN_CTRL1_BOFFREC_MASK (0x40U)
|
|
#define CAN_CTRL1_BOFFREC_SHIFT (6U)
|
|
/*! BOFFREC
|
|
* 0b1..Automatic recovering from Bus Off state disabled
|
|
* 0b0..Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B
|
|
*/
|
|
#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
|
|
#define CAN_CTRL1_SMP_MASK (0x80U)
|
|
#define CAN_CTRL1_SMP_SHIFT (7U)
|
|
/*! SMP
|
|
* 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples, a majority rule is used
|
|
* 0b0..Just one sample is used to determine the bit value
|
|
*/
|
|
#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
|
|
#define CAN_CTRL1_RWRNMSK_MASK (0x400U)
|
|
#define CAN_CTRL1_RWRNMSK_SHIFT (10U)
|
|
/*! RWRNMSK
|
|
* 0b1..Rx Warning Interrupt enabled
|
|
* 0b0..Rx Warning Interrupt disabled
|
|
*/
|
|
#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
|
|
#define CAN_CTRL1_TWRNMSK_MASK (0x800U)
|
|
#define CAN_CTRL1_TWRNMSK_SHIFT (11U)
|
|
/*! TWRNMSK
|
|
* 0b1..Tx Warning Interrupt enabled
|
|
* 0b0..Tx Warning Interrupt disabled
|
|
*/
|
|
#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
|
|
#define CAN_CTRL1_LPB_MASK (0x1000U)
|
|
#define CAN_CTRL1_LPB_SHIFT (12U)
|
|
/*! LPB
|
|
* 0b1..Loop Back enabled
|
|
* 0b0..Loop Back disabled
|
|
*/
|
|
#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
|
|
#define CAN_CTRL1_ERRMSK_MASK (0x4000U)
|
|
#define CAN_CTRL1_ERRMSK_SHIFT (14U)
|
|
/*! ERRMSK
|
|
* 0b1..Error interrupt enabled
|
|
* 0b0..Error interrupt disabled
|
|
*/
|
|
#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
|
|
#define CAN_CTRL1_BOFFMSK_MASK (0x8000U)
|
|
#define CAN_CTRL1_BOFFMSK_SHIFT (15U)
|
|
/*! BOFFMSK
|
|
* 0b1..Bus Off interrupt enabled
|
|
* 0b0..Bus Off interrupt disabled
|
|
*/
|
|
#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
|
|
#define CAN_CTRL1_PSEG2_MASK (0x70000U)
|
|
#define CAN_CTRL1_PSEG2_SHIFT (16U)
|
|
#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
|
|
#define CAN_CTRL1_PSEG1_MASK (0x380000U)
|
|
#define CAN_CTRL1_PSEG1_SHIFT (19U)
|
|
#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
|
|
#define CAN_CTRL1_RJW_MASK (0xC00000U)
|
|
#define CAN_CTRL1_RJW_SHIFT (22U)
|
|
#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
|
|
#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U)
|
|
#define CAN_CTRL1_PRESDIV_SHIFT (24U)
|
|
#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TIMER - Free Running Timer Register */
|
|
/*! @{ */
|
|
#define CAN_TIMER_TIMER_MASK (0xFFFFU)
|
|
#define CAN_TIMER_TIMER_SHIFT (0U)
|
|
#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RXMGMASK - Rx Mailboxes Global Mask Register */
|
|
/*! @{ */
|
|
#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU)
|
|
#define CAN_RXMGMASK_MG_SHIFT (0U)
|
|
/*! MG
|
|
* 0b00000000000000000000000000000001..The corresponding bit in the filter is checked against the one received
|
|
* 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care"
|
|
*/
|
|
#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RX14MASK - Rx Buffer 14 Mask Register */
|
|
/*! @{ */
|
|
#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU)
|
|
#define CAN_RX14MASK_RX14M_SHIFT (0U)
|
|
/*! RX14M
|
|
* 0b00000000000000000000000000000001..The corresponding bit in the filter is checked
|
|
* 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care"
|
|
*/
|
|
#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RX15MASK - Rx Buffer 15 Mask Register */
|
|
/*! @{ */
|
|
#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU)
|
|
#define CAN_RX15MASK_RX15M_SHIFT (0U)
|
|
/*! RX15M
|
|
* 0b00000000000000000000000000000001..The corresponding bit in the filter is checked
|
|
* 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care"
|
|
*/
|
|
#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ECR - Error Counter Register */
|
|
/*! @{ */
|
|
#define CAN_ECR_TX_ERR_COUNTER_MASK (0xFFU)
|
|
#define CAN_ECR_TX_ERR_COUNTER_SHIFT (0U)
|
|
#define CAN_ECR_TX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TX_ERR_COUNTER_SHIFT)) & CAN_ECR_TX_ERR_COUNTER_MASK)
|
|
#define CAN_ECR_RX_ERR_COUNTER_MASK (0xFF00U)
|
|
#define CAN_ECR_RX_ERR_COUNTER_SHIFT (8U)
|
|
#define CAN_ECR_RX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RX_ERR_COUNTER_SHIFT)) & CAN_ECR_RX_ERR_COUNTER_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ESR1 - Error and Status 1 Register */
|
|
/*! @{ */
|
|
#define CAN_ESR1_WAKINT_MASK (0x1U)
|
|
#define CAN_ESR1_WAKINT_SHIFT (0U)
|
|
/*! WAKINT
|
|
* 0b1..Indicates a recessive to dominant transition received on the CAN bus when the FLEXCAN module is in Stop Mode
|
|
* 0b0..No such occurrence
|
|
*/
|
|
#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
|
|
#define CAN_ESR1_ERRINT_MASK (0x2U)
|
|
#define CAN_ESR1_ERRINT_SHIFT (1U)
|
|
/*! ERRINT
|
|
* 0b1..Indicates setting of any Error Bit in the Error and Status Register
|
|
* 0b0..No such occurrence
|
|
*/
|
|
#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
|
|
#define CAN_ESR1_BOFFINT_MASK (0x4U)
|
|
#define CAN_ESR1_BOFFINT_SHIFT (2U)
|
|
/*! BOFFINT
|
|
* 0b1..FLEXCAN module entered 'Bus Off' state
|
|
* 0b0..No such occurrence
|
|
*/
|
|
#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
|
|
#define CAN_ESR1_RX_MASK (0x8U)
|
|
#define CAN_ESR1_RX_SHIFT (3U)
|
|
/*! RX
|
|
* 0b1..FLEXCAN is transmitting a message
|
|
* 0b0..FLEXCAN is receiving a message
|
|
*/
|
|
#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
|
|
#define CAN_ESR1_FLTCONF_MASK (0x30U)
|
|
#define CAN_ESR1_FLTCONF_SHIFT (4U)
|
|
/*! FLTCONF
|
|
* 0b00..Error Active
|
|
* 0b01..Error Passive
|
|
* 0b1x..Bus off
|
|
*/
|
|
#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
|
|
#define CAN_ESR1_TX_MASK (0x40U)
|
|
#define CAN_ESR1_TX_SHIFT (6U)
|
|
/*! TX
|
|
* 0b1..FLEXCAN is transmitting a message
|
|
* 0b0..FLEXCAN is receiving a message
|
|
*/
|
|
#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
|
|
#define CAN_ESR1_IDLE_MASK (0x80U)
|
|
#define CAN_ESR1_IDLE_SHIFT (7U)
|
|
/*! IDLE
|
|
* 0b1..CAN bus is now IDLE
|
|
* 0b0..No such occurrence
|
|
*/
|
|
#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
|
|
#define CAN_ESR1_RXWRN_MASK (0x100U)
|
|
#define CAN_ESR1_RXWRN_SHIFT (8U)
|
|
/*! RXWRN
|
|
* 0b1..Rx_Err_Counter >= 96
|
|
* 0b0..No such occurrence
|
|
*/
|
|
#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
|
|
#define CAN_ESR1_TXWRN_MASK (0x200U)
|
|
#define CAN_ESR1_TXWRN_SHIFT (9U)
|
|
/*! TXWRN
|
|
* 0b1..TX_Err_Counter >= 96
|
|
* 0b0..No such occurrence
|
|
*/
|
|
#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
|
|
#define CAN_ESR1_STFERR_MASK (0x400U)
|
|
#define CAN_ESR1_STFERR_SHIFT (10U)
|
|
/*! STFERR
|
|
* 0b1..A Stuffing Error occurred since last read of this register.
|
|
* 0b0..No such occurrence.
|
|
*/
|
|
#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
|
|
#define CAN_ESR1_FRMERR_MASK (0x800U)
|
|
#define CAN_ESR1_FRMERR_SHIFT (11U)
|
|
/*! FRMERR
|
|
* 0b1..A Form Error occurred since last read of this register
|
|
* 0b0..No such occurrence
|
|
*/
|
|
#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
|
|
#define CAN_ESR1_CRCERR_MASK (0x1000U)
|
|
#define CAN_ESR1_CRCERR_SHIFT (12U)
|
|
/*! CRCERR
|
|
* 0b1..A CRC error occurred since last read of this register.
|
|
* 0b0..No such occurrence
|
|
*/
|
|
#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
|
|
#define CAN_ESR1_ACKERR_MASK (0x2000U)
|
|
#define CAN_ESR1_ACKERR_SHIFT (13U)
|
|
/*! ACKERR
|
|
* 0b1..An ACK error occurred since last read of this register
|
|
* 0b0..No such occurrence
|
|
*/
|
|
#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
|
|
#define CAN_ESR1_BIT0ERR_MASK (0x4000U)
|
|
#define CAN_ESR1_BIT0ERR_SHIFT (14U)
|
|
/*! BIT0ERR
|
|
* 0b1..At least one bit sent as dominant is received as recessive
|
|
* 0b0..No such occurrence
|
|
*/
|
|
#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
|
|
#define CAN_ESR1_BIT1ERR_MASK (0x8000U)
|
|
#define CAN_ESR1_BIT1ERR_SHIFT (15U)
|
|
/*! BIT1ERR
|
|
* 0b1..At least one bit sent as recessive is received as dominant
|
|
* 0b0..No such occurrence
|
|
*/
|
|
#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
|
|
#define CAN_ESR1_RWRNINT_MASK (0x10000U)
|
|
#define CAN_ESR1_RWRNINT_SHIFT (16U)
|
|
/*! RWRNINT
|
|
* 0b1..The Rx error counter transition from < 96 to >= 96
|
|
* 0b0..No such occurrence
|
|
*/
|
|
#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
|
|
#define CAN_ESR1_TWRNINT_MASK (0x20000U)
|
|
#define CAN_ESR1_TWRNINT_SHIFT (17U)
|
|
/*! TWRNINT
|
|
* 0b1..The Tx error counter transition from < 96 to >= 96
|
|
* 0b0..No such occurrence
|
|
*/
|
|
#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
|
|
#define CAN_ESR1_SYNCH_MASK (0x40000U)
|
|
#define CAN_ESR1_SYNCH_SHIFT (18U)
|
|
/*! SYNCH
|
|
* 0b1..FlexCAN is synchronized to the CAN bus
|
|
* 0b0..FlexCAN is not synchronized to the CAN bus
|
|
*/
|
|
#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name IMASK2 - Interrupt Masks 2 Register */
|
|
/*! @{ */
|
|
#define CAN_IMASK2_BUFHM_MASK (0xFFFFFFFFU)
|
|
#define CAN_IMASK2_BUFHM_SHIFT (0U)
|
|
/*! BUFHM
|
|
* 0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled
|
|
* 0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled
|
|
*/
|
|
#define CAN_IMASK2_BUFHM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUFHM_SHIFT)) & CAN_IMASK2_BUFHM_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name IMASK1 - Interrupt Masks 1 Register */
|
|
/*! @{ */
|
|
#define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU)
|
|
#define CAN_IMASK1_BUFLM_SHIFT (0U)
|
|
/*! BUFLM
|
|
* 0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled
|
|
* 0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled
|
|
*/
|
|
#define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name IFLAG2 - Interrupt Flags 2 Register */
|
|
/*! @{ */
|
|
#define CAN_IFLAG2_BUFHI_MASK (0xFFFFFFFFU)
|
|
#define CAN_IFLAG2_BUFHI_SHIFT (0U)
|
|
/*! BUFHI
|
|
* 0b00000000000000000000000000000001..The corresponding buffer has successfully completed transmission or reception
|
|
* 0b00000000000000000000000000000000..No such occurrence
|
|
*/
|
|
#define CAN_IFLAG2_BUFHI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUFHI_SHIFT)) & CAN_IFLAG2_BUFHI_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name IFLAG1 - Interrupt Flags 1 Register */
|
|
/*! @{ */
|
|
#define CAN_IFLAG1_BUF4TO0I_MASK (0x1FU)
|
|
#define CAN_IFLAG1_BUF4TO0I_SHIFT (0U)
|
|
/*! BUF4TO0I
|
|
* 0b00001..Corresponding MB completed transmission/reception
|
|
* 0b00000..No such occurrence
|
|
*/
|
|
#define CAN_IFLAG1_BUF4TO0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO0I_SHIFT)) & CAN_IFLAG1_BUF4TO0I_MASK)
|
|
#define CAN_IFLAG1_BUF5I_MASK (0x20U)
|
|
#define CAN_IFLAG1_BUF5I_SHIFT (5U)
|
|
/*! BUF5I
|
|
* 0b1..MB5 completed transmission/reception or frames available in the FIFO
|
|
* 0b0..No such occurrence
|
|
*/
|
|
#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
|
|
#define CAN_IFLAG1_BUF6I_MASK (0x40U)
|
|
#define CAN_IFLAG1_BUF6I_SHIFT (6U)
|
|
/*! BUF6I
|
|
* 0b1..MB6 completed transmission/reception or FIFO almost full
|
|
* 0b0..No such occurrence
|
|
*/
|
|
#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
|
|
#define CAN_IFLAG1_BUF7I_MASK (0x80U)
|
|
#define CAN_IFLAG1_BUF7I_SHIFT (7U)
|
|
/*! BUF7I
|
|
* 0b1..MB7 completed transmission/reception or FIFO overflow
|
|
* 0b0..No such occurrence
|
|
*/
|
|
#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
|
|
#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U)
|
|
#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U)
|
|
/*! BUF31TO8I
|
|
* 0b000000000000000000000001..The corresponding MB has successfully completed transmission or reception
|
|
* 0b000000000000000000000000..No such occurrence
|
|
*/
|
|
#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CTRL2 - Control 2 Register */
|
|
/*! @{ */
|
|
#define CAN_CTRL2_EACEN_MASK (0x10000U)
|
|
#define CAN_CTRL2_EACEN_SHIFT (16U)
|
|
/*! EACEN
|
|
* 0b1..Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply.
|
|
* 0b0..Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits.
|
|
*/
|
|
#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
|
|
#define CAN_CTRL2_RRS_MASK (0x20000U)
|
|
#define CAN_CTRL2_RRS_SHIFT (17U)
|
|
/*! RRS
|
|
* 0b1..Remote Request Frame is stored
|
|
* 0b0..Remote Response Frame is generated
|
|
*/
|
|
#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
|
|
#define CAN_CTRL2_MRP_MASK (0x40000U)
|
|
#define CAN_CTRL2_MRP_SHIFT (18U)
|
|
/*! MRP
|
|
* 0b1..Matching starts from Mailboxes and continues on Rx FIFO
|
|
* 0b0..Matching starts from Rx FIFO and continues on Mailboxes
|
|
*/
|
|
#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
|
|
#define CAN_CTRL2_TASD_MASK (0xF80000U)
|
|
#define CAN_CTRL2_TASD_SHIFT (19U)
|
|
#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
|
|
#define CAN_CTRL2_RFFN_MASK (0xF000000U)
|
|
#define CAN_CTRL2_RFFN_SHIFT (24U)
|
|
#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
|
|
#define CAN_CTRL2_WRMFRZ_MASK (0x10000000U)
|
|
#define CAN_CTRL2_WRMFRZ_SHIFT (28U)
|
|
/*! WRMFRZ
|
|
* 0b1..Enable unrestricted write access to FlexCAN memory
|
|
* 0b0..Keep the write access restricted in some regions of FlexCAN memory
|
|
*/
|
|
#define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ESR2 - Error and Status 2 Register */
|
|
/*! @{ */
|
|
#define CAN_ESR2_IMB_MASK (0x2000U)
|
|
#define CAN_ESR2_IMB_SHIFT (13U)
|
|
/*! IMB
|
|
* 0b1..If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one.
|
|
* 0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox.
|
|
*/
|
|
#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
|
|
#define CAN_ESR2_VPS_MASK (0x4000U)
|
|
#define CAN_ESR2_VPS_SHIFT (14U)
|
|
/*! VPS
|
|
* 0b1..Contents of IMB and LPTM are valid
|
|
* 0b0..Contents of IMB and LPTM are invalid
|
|
*/
|
|
#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
|
|
#define CAN_ESR2_LPTM_MASK (0x7F0000U)
|
|
#define CAN_ESR2_LPTM_SHIFT (16U)
|
|
#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CRCR - CRC Register */
|
|
/*! @{ */
|
|
#define CAN_CRCR_TXCRC_MASK (0x7FFFU)
|
|
#define CAN_CRCR_TXCRC_SHIFT (0U)
|
|
#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
|
|
#define CAN_CRCR_MBCRC_MASK (0x7F0000U)
|
|
#define CAN_CRCR_MBCRC_SHIFT (16U)
|
|
#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RXFGMASK - Rx FIFO Global Mask Register */
|
|
/*! @{ */
|
|
#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU)
|
|
#define CAN_RXFGMASK_FGM_SHIFT (0U)
|
|
/*! FGM
|
|
* 0b00000000000000000000000000000001..The corresponding bit in the filter is checked
|
|
* 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care"
|
|
*/
|
|
#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RXFIR - Rx FIFO Information Register */
|
|
/*! @{ */
|
|
#define CAN_RXFIR_IDHIT_MASK (0x1FFU)
|
|
#define CAN_RXFIR_IDHIT_SHIFT (0U)
|
|
#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DBG1 - Debug 1 register */
|
|
/*! @{ */
|
|
#define CAN_DBG1_CFSM_MASK (0x3FU)
|
|
#define CAN_DBG1_CFSM_SHIFT (0U)
|
|
#define CAN_DBG1_CFSM(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CFSM_SHIFT)) & CAN_DBG1_CFSM_MASK)
|
|
#define CAN_DBG1_CBN_MASK (0x1F000000U)
|
|
#define CAN_DBG1_CBN_SHIFT (24U)
|
|
#define CAN_DBG1_CBN(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CBN_SHIFT)) & CAN_DBG1_CBN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DBG2 - Debug 2 register */
|
|
/*! @{ */
|
|
#define CAN_DBG2_RMP_MASK (0x7FU)
|
|
#define CAN_DBG2_RMP_SHIFT (0U)
|
|
#define CAN_DBG2_RMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_RMP_SHIFT)) & CAN_DBG2_RMP_MASK)
|
|
#define CAN_DBG2_MPP_MASK (0x80U)
|
|
#define CAN_DBG2_MPP_SHIFT (7U)
|
|
/*! MPP - Matching Process in Progress
|
|
* 0b0..No matching process ongoing.
|
|
* 0b1..Matching process is in progress.
|
|
*/
|
|
#define CAN_DBG2_MPP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_MPP_SHIFT)) & CAN_DBG2_MPP_MASK)
|
|
#define CAN_DBG2_TAP_MASK (0x7F00U)
|
|
#define CAN_DBG2_TAP_SHIFT (8U)
|
|
#define CAN_DBG2_TAP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_TAP_SHIFT)) & CAN_DBG2_TAP_MASK)
|
|
#define CAN_DBG2_APP_MASK (0x8000U)
|
|
#define CAN_DBG2_APP_SHIFT (15U)
|
|
/*! APP - Arbitration Process in Progress
|
|
* 0b0..No matching process ongoing.
|
|
* 0b1..Matching process is in progress.
|
|
*/
|
|
#define CAN_DBG2_APP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_APP_SHIFT)) & CAN_DBG2_APP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CS - Message Buffer 0 CS Register..Message Buffer 63 CS Register */
|
|
/*! @{ */
|
|
#define CAN_CS_TIME_STAMP_MASK (0xFFFFU)
|
|
#define CAN_CS_TIME_STAMP_SHIFT (0U)
|
|
#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
|
|
#define CAN_CS_DLC_MASK (0xF0000U)
|
|
#define CAN_CS_DLC_SHIFT (16U)
|
|
#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
|
|
#define CAN_CS_RTR_MASK (0x100000U)
|
|
#define CAN_CS_RTR_SHIFT (20U)
|
|
#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
|
|
#define CAN_CS_IDE_MASK (0x200000U)
|
|
#define CAN_CS_IDE_SHIFT (21U)
|
|
#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
|
|
#define CAN_CS_SRR_MASK (0x400000U)
|
|
#define CAN_CS_SRR_SHIFT (22U)
|
|
#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
|
|
#define CAN_CS_CODE_MASK (0xF000000U)
|
|
#define CAN_CS_CODE_SHIFT (24U)
|
|
#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of CAN_CS */
|
|
#define CAN_CS_COUNT (64U)
|
|
|
|
/*! @name ID - Message Buffer 0 ID Register..Message Buffer 63 ID Register */
|
|
/*! @{ */
|
|
#define CAN_ID_EXT_MASK (0x3FFFFU)
|
|
#define CAN_ID_EXT_SHIFT (0U)
|
|
#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
|
|
#define CAN_ID_STD_MASK (0x1FFC0000U)
|
|
#define CAN_ID_STD_SHIFT (18U)
|
|
#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
|
|
#define CAN_ID_PRIO_MASK (0xE0000000U)
|
|
#define CAN_ID_PRIO_SHIFT (29U)
|
|
#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of CAN_ID */
|
|
#define CAN_ID_COUNT (64U)
|
|
|
|
/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register */
|
|
/*! @{ */
|
|
#define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU)
|
|
#define CAN_WORD0_DATA_BYTE_3_SHIFT (0U)
|
|
#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
|
|
#define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U)
|
|
#define CAN_WORD0_DATA_BYTE_2_SHIFT (8U)
|
|
#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
|
|
#define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U)
|
|
#define CAN_WORD0_DATA_BYTE_1_SHIFT (16U)
|
|
#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
|
|
#define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U)
|
|
#define CAN_WORD0_DATA_BYTE_0_SHIFT (24U)
|
|
#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of CAN_WORD0 */
|
|
#define CAN_WORD0_COUNT (64U)
|
|
|
|
/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register */
|
|
/*! @{ */
|
|
#define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU)
|
|
#define CAN_WORD1_DATA_BYTE_7_SHIFT (0U)
|
|
#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
|
|
#define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U)
|
|
#define CAN_WORD1_DATA_BYTE_6_SHIFT (8U)
|
|
#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
|
|
#define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U)
|
|
#define CAN_WORD1_DATA_BYTE_5_SHIFT (16U)
|
|
#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
|
|
#define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U)
|
|
#define CAN_WORD1_DATA_BYTE_4_SHIFT (24U)
|
|
#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of CAN_WORD1 */
|
|
#define CAN_WORD1_COUNT (64U)
|
|
|
|
/*! @name RXIMR - Rx Individual Mask Registers */
|
|
/*! @{ */
|
|
#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU)
|
|
#define CAN_RXIMR_MI_SHIFT (0U)
|
|
/*! MI
|
|
* 0b00000000000000000000000000000001..The corresponding bit in the filter is checked
|
|
* 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care"
|
|
*/
|
|
#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of CAN_RXIMR */
|
|
#define CAN_RXIMR_COUNT (64U)
|
|
|
|
/*! @name GFWR - Glitch Filter Width Registers */
|
|
/*! @{ */
|
|
#define CAN_GFWR_GFWR_MASK (0xFFU)
|
|
#define CAN_GFWR_GFWR_SHIFT (0U)
|
|
#define CAN_GFWR_GFWR(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFWR_GFWR_SHIFT)) & CAN_GFWR_GFWR_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group CAN_Register_Masks */
|
|
|
|
|
|
/* CAN - Peripheral instance base addresses */
|
|
/** Peripheral CAN1 base address */
|
|
#define CAN1_BASE (0x401D0000u)
|
|
/** Peripheral CAN1 base pointer */
|
|
#define CAN1 ((CAN_Type *)CAN1_BASE)
|
|
/** Peripheral CAN2 base address */
|
|
#define CAN2_BASE (0x401D4000u)
|
|
/** Peripheral CAN2 base pointer */
|
|
#define CAN2 ((CAN_Type *)CAN2_BASE)
|
|
/** Array initializer of CAN peripheral base addresses */
|
|
#define CAN_BASE_ADDRS { 0u, CAN1_BASE, CAN2_BASE }
|
|
/** Array initializer of CAN peripheral base pointers */
|
|
#define CAN_BASE_PTRS { (CAN_Type *)0u, CAN1, CAN2 }
|
|
/** Interrupt vectors for the CAN peripheral type */
|
|
#define CAN_Rx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
|
|
#define CAN_Tx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
|
|
#define CAN_Wake_Up_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
|
|
#define CAN_Error_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
|
|
#define CAN_Bus_Off_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
|
|
#define CAN_ORed_Message_buffer_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
|
|
/* Backward compatibility */
|
|
#define CAN_ECR_TXERRCNT_MASK CAN_ECR_TX_ERR_COUNTER_MASK
|
|
#define CAN_ECR_TXERRCNT_SHIFT CAN_ECR_TX_ERR_COUNTER_SHIFT
|
|
#define CAN_ECR_TXERRCNT(x) CAN_ECR_TX_ERR_COUNTER(x)
|
|
#define CAN_ECR_RXERRCNT_MASK CAN_ECR_RX_ERR_COUNTER_MASK
|
|
#define CAN_ECR_RXERRCNT_SHIFT CAN_ECR_RX_ERR_COUNTER_SHIFT
|
|
#define CAN_ECR_RXERRCNT(x) CAN_ECR_RX_ERR_COUNTER(x)
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group CAN_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- CCM Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** CCM - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t CCR; /**< CCM Control Register, offset: 0x0 */
|
|
uint8_t RESERVED_0[4];
|
|
__I uint32_t CSR; /**< CCM Status Register, offset: 0x8 */
|
|
__IO uint32_t CCSR; /**< CCM Clock Switcher Register, offset: 0xC */
|
|
__IO uint32_t CACRR; /**< CCM Arm Clock Root Register, offset: 0x10 */
|
|
__IO uint32_t CBCDR; /**< CCM Bus Clock Divider Register, offset: 0x14 */
|
|
__IO uint32_t CBCMR; /**< CCM Bus Clock Multiplexer Register, offset: 0x18 */
|
|
__IO uint32_t CSCMR1; /**< CCM Serial Clock Multiplexer Register 1, offset: 0x1C */
|
|
__IO uint32_t CSCMR2; /**< CCM Serial Clock Multiplexer Register 2, offset: 0x20 */
|
|
__IO uint32_t CSCDR1; /**< CCM Serial Clock Divider Register 1, offset: 0x24 */
|
|
__IO uint32_t CS1CDR; /**< CCM Clock Divider Register, offset: 0x28 */
|
|
__IO uint32_t CS2CDR; /**< CCM Clock Divider Register, offset: 0x2C */
|
|
__IO uint32_t CDCDR; /**< CCM D1 Clock Divider Register, offset: 0x30 */
|
|
uint8_t RESERVED_1[4];
|
|
__IO uint32_t CSCDR2; /**< CCM Serial Clock Divider Register 2, offset: 0x38 */
|
|
__IO uint32_t CSCDR3; /**< CCM Serial Clock Divider Register 3, offset: 0x3C */
|
|
uint8_t RESERVED_2[8];
|
|
__I uint32_t CDHIPR; /**< CCM Divider Handshake In-Process Register, offset: 0x48 */
|
|
uint8_t RESERVED_3[8];
|
|
__IO uint32_t CLPCR; /**< CCM Low Power Control Register, offset: 0x54 */
|
|
__IO uint32_t CISR; /**< CCM Interrupt Status Register, offset: 0x58 */
|
|
__IO uint32_t CIMR; /**< CCM Interrupt Mask Register, offset: 0x5C */
|
|
__IO uint32_t CCOSR; /**< CCM Clock Output Source Register, offset: 0x60 */
|
|
__IO uint32_t CGPR; /**< CCM General Purpose Register, offset: 0x64 */
|
|
__IO uint32_t CCGR0; /**< CCM Clock Gating Register 0, offset: 0x68 */
|
|
__IO uint32_t CCGR1; /**< CCM Clock Gating Register 1, offset: 0x6C */
|
|
__IO uint32_t CCGR2; /**< CCM Clock Gating Register 2, offset: 0x70 */
|
|
__IO uint32_t CCGR3; /**< CCM Clock Gating Register 3, offset: 0x74 */
|
|
__IO uint32_t CCGR4; /**< CCM Clock Gating Register 4, offset: 0x78 */
|
|
__IO uint32_t CCGR5; /**< CCM Clock Gating Register 5, offset: 0x7C */
|
|
__IO uint32_t CCGR6; /**< CCM Clock Gating Register 6, offset: 0x80 */
|
|
uint8_t RESERVED_4[4];
|
|
__IO uint32_t CMEOR; /**< CCM Module Enable Overide Register, offset: 0x88 */
|
|
} CCM_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- CCM Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup CCM_Register_Masks CCM Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name CCR - CCM Control Register */
|
|
/*! @{ */
|
|
#define CCM_CCR_OSCNT_MASK (0xFFU)
|
|
#define CCM_CCR_OSCNT_SHIFT (0U)
|
|
/*! OSCNT
|
|
* 0b00000000..count 1 ckil
|
|
* 0b11111111..count 256 ckil's
|
|
*/
|
|
#define CCM_CCR_OSCNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_OSCNT_SHIFT)) & CCM_CCR_OSCNT_MASK)
|
|
#define CCM_CCR_COSC_EN_MASK (0x1000U)
|
|
#define CCM_CCR_COSC_EN_SHIFT (12U)
|
|
/*! COSC_EN
|
|
* 0b0..disable on chip oscillator
|
|
* 0b1..enable on chip oscillator
|
|
*/
|
|
#define CCM_CCR_COSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_COSC_EN_SHIFT)) & CCM_CCR_COSC_EN_MASK)
|
|
#define CCM_CCR_REG_BYPASS_COUNT_MASK (0x7E00000U)
|
|
#define CCM_CCR_REG_BYPASS_COUNT_SHIFT (21U)
|
|
/*! REG_BYPASS_COUNT
|
|
* 0b000000..no delay
|
|
* 0b000001..1 CKIL clock period delay
|
|
* 0b111111..63 CKIL clock periods delay
|
|
*/
|
|
#define CCM_CCR_REG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)) & CCM_CCR_REG_BYPASS_COUNT_MASK)
|
|
#define CCM_CCR_RBC_EN_MASK (0x8000000U)
|
|
#define CCM_CCR_RBC_EN_SHIFT (27U)
|
|
/*! RBC_EN
|
|
* 0b1..REG_BYPASS_COUNTER enabled.
|
|
* 0b0..REG_BYPASS_COUNTER disabled
|
|
*/
|
|
#define CCM_CCR_RBC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_RBC_EN_SHIFT)) & CCM_CCR_RBC_EN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CSR - CCM Status Register */
|
|
/*! @{ */
|
|
#define CCM_CSR_REF_EN_B_MASK (0x1U)
|
|
#define CCM_CSR_REF_EN_B_SHIFT (0U)
|
|
/*! REF_EN_B
|
|
* 0b0..value of CCM_REF_EN_B is '0'
|
|
* 0b1..value of CCM_REF_EN_B is '1'
|
|
*/
|
|
#define CCM_CSR_REF_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_REF_EN_B_SHIFT)) & CCM_CSR_REF_EN_B_MASK)
|
|
#define CCM_CSR_CAMP2_READY_MASK (0x8U)
|
|
#define CCM_CSR_CAMP2_READY_SHIFT (3U)
|
|
/*! CAMP2_READY
|
|
* 0b0..CAMP2 is not ready.
|
|
* 0b1..CAMP2 is ready.
|
|
*/
|
|
#define CCM_CSR_CAMP2_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_CAMP2_READY_SHIFT)) & CCM_CSR_CAMP2_READY_MASK)
|
|
#define CCM_CSR_COSC_READY_MASK (0x20U)
|
|
#define CCM_CSR_COSC_READY_SHIFT (5U)
|
|
/*! COSC_READY
|
|
* 0b0..on board oscillator is not ready.
|
|
* 0b1..on board oscillator is ready.
|
|
*/
|
|
#define CCM_CSR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_COSC_READY_SHIFT)) & CCM_CSR_COSC_READY_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CCSR - CCM Clock Switcher Register */
|
|
/*! @{ */
|
|
#define CCM_CCSR_PLL3_SW_CLK_SEL_MASK (0x1U)
|
|
#define CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT (0U)
|
|
/*! PLL3_SW_CLK_SEL
|
|
* 0b0..pll3_main_clk
|
|
* 0b1..pll3 bypass clock
|
|
*/
|
|
#define CCM_CCSR_PLL3_SW_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL3_SW_CLK_SEL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CACRR - CCM Arm Clock Root Register */
|
|
/*! @{ */
|
|
#define CCM_CACRR_ARM_PODF_MASK (0x7U)
|
|
#define CCM_CACRR_ARM_PODF_SHIFT (0U)
|
|
/*! ARM_PODF
|
|
* 0b000..divide by 1
|
|
* 0b001..divide by 2
|
|
* 0b010..divide by 3
|
|
* 0b011..divide by 4
|
|
* 0b100..divide by 5
|
|
* 0b101..divide by 6
|
|
* 0b110..divide by 7
|
|
* 0b111..divide by 8
|
|
*/
|
|
#define CCM_CACRR_ARM_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CACRR_ARM_PODF_SHIFT)) & CCM_CACRR_ARM_PODF_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CBCDR - CCM Bus Clock Divider Register */
|
|
/*! @{ */
|
|
#define CCM_CBCDR_SEMC_CLK_SEL_MASK (0x40U)
|
|
#define CCM_CBCDR_SEMC_CLK_SEL_SHIFT (6U)
|
|
/*! SEMC_CLK_SEL
|
|
* 0b0..Periph_clk output will be used as SEMC clock root
|
|
* 0b1..SEMC alternative clock will be used as SEMC clock root
|
|
*/
|
|
#define CCM_CBCDR_SEMC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_CLK_SEL_MASK)
|
|
#define CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK (0x80U)
|
|
#define CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT (7U)
|
|
/*! SEMC_ALT_CLK_SEL
|
|
* 0b0..PLL2 PFD2 will be selected as alternative clock for SEMC root clock
|
|
* 0b1..PLL3 PFD1 will be selected as alternative clock for SEMC root clock
|
|
*/
|
|
#define CCM_CBCDR_SEMC_ALT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK)
|
|
#define CCM_CBCDR_IPG_PODF_MASK (0x300U)
|
|
#define CCM_CBCDR_IPG_PODF_SHIFT (8U)
|
|
/*! IPG_PODF
|
|
* 0b00..divide by 1
|
|
* 0b01..divide by 2
|
|
* 0b10..divide by 3
|
|
* 0b11..divide by 4
|
|
*/
|
|
#define CCM_CBCDR_IPG_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_IPG_PODF_SHIFT)) & CCM_CBCDR_IPG_PODF_MASK)
|
|
#define CCM_CBCDR_AHB_PODF_MASK (0x1C00U)
|
|
#define CCM_CBCDR_AHB_PODF_SHIFT (10U)
|
|
/*! AHB_PODF
|
|
* 0b000..divide by 1
|
|
* 0b001..divide by 2
|
|
* 0b010..divide by 3
|
|
* 0b011..divide by 4
|
|
* 0b100..divide by 5
|
|
* 0b101..divide by 6
|
|
* 0b110..divide by 7
|
|
* 0b111..divide by 8
|
|
*/
|
|
#define CCM_CBCDR_AHB_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AHB_PODF_SHIFT)) & CCM_CBCDR_AHB_PODF_MASK)
|
|
#define CCM_CBCDR_SEMC_PODF_MASK (0x70000U)
|
|
#define CCM_CBCDR_SEMC_PODF_SHIFT (16U)
|
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/*! SEMC_PODF
|
|
* 0b000..divide by 1
|
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* 0b001..divide by 2
|
|
* 0b010..divide by 3
|
|
* 0b011..divide by 4
|
|
* 0b100..divide by 5
|
|
* 0b101..divide by 6
|
|
* 0b110..divide by 7
|
|
* 0b111..divide by 8
|
|
*/
|
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#define CCM_CBCDR_SEMC_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_PODF_SHIFT)) & CCM_CBCDR_SEMC_PODF_MASK)
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#define CCM_CBCDR_PERIPH_CLK_SEL_MASK (0x2000000U)
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#define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25U)
|
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/*! PERIPH_CLK_SEL
|
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* 0b0..derive clock from pre_periph_clk_sel
|
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* 0b1..derive clock from periph_clk2_clk_divided
|
|
*/
|
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#define CCM_CBCDR_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH_CLK_SEL_MASK)
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#define CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x38000000U)
|
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#define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27U)
|
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/*! PERIPH_CLK2_PODF
|
|
* 0b000..divide by 1
|
|
* 0b001..divide by 2
|
|
* 0b010..divide by 3
|
|
* 0b011..divide by 4
|
|
* 0b100..divide by 5
|
|
* 0b101..divide by 6
|
|
* 0b110..divide by 7
|
|
* 0b111..divide by 8
|
|
*/
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#define CCM_CBCDR_PERIPH_CLK2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH_CLK2_PODF_MASK)
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/*! @} */
|
|
|
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/*! @name CBCMR - CCM Bus Clock Multiplexer Register */
|
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/*! @{ */
|
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#define CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x30U)
|
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#define CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4U)
|
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/*! LPSPI_CLK_SEL
|
|
* 0b00..derive clock from PLL3 PFD1 clk
|
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* 0b01..derive clock from PLL3 PFD0
|
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* 0b10..derive clock from PLL2
|
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* 0b11..derive clock from PLL2 PFD2
|
|
*/
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#define CCM_CBCMR_LPSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)) & CCM_CBCMR_LPSPI_CLK_SEL_MASK)
|
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#define CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3000U)
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#define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12U)
|
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/*! PERIPH_CLK2_SEL
|
|
* 0b00..derive clock from pll3_sw_clk
|
|
* 0b01..derive clock from osc_clk (pll1_ref_clk)
|
|
* 0b10..derive clock from pll2_bypass_clk
|
|
* 0b11..reserved
|
|
*/
|
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#define CCM_CBCMR_PERIPH_CLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)
|
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#define CCM_CBCMR_TRACE_CLK_SEL_MASK (0xC000U)
|
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#define CCM_CBCMR_TRACE_CLK_SEL_SHIFT (14U)
|
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/*! TRACE_CLK_SEL
|
|
* 0b00..derive clock from PLL2
|
|
* 0b01..derive clock from PLL2 PFD2
|
|
* 0b10..derive clock from PLL2 PFD0
|
|
* 0b11..derive clock from PLL2 PFD1
|
|
*/
|
|
#define CCM_CBCMR_TRACE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)) & CCM_CBCMR_TRACE_CLK_SEL_MASK)
|
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#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0xC0000U)
|
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#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18U)
|
|
/*! PRE_PERIPH_CLK_SEL
|
|
* 0b00..derive clock from PLL2
|
|
* 0b01..derive clock from PLL2 PFD2
|
|
* 0b10..derive clock from PLL2 PFD0
|
|
* 0b11..derive clock from divided PLL1
|
|
*/
|
|
#define CCM_CBCMR_PRE_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
|
|
#define CCM_CBCMR_LCDIF_PODF_MASK (0x3800000U)
|
|
#define CCM_CBCMR_LCDIF_PODF_SHIFT (23U)
|
|
/*! LCDIF_PODF
|
|
* 0b000..divide by 1
|
|
* 0b001..divide by 2
|
|
* 0b010..divide by 3
|
|
* 0b011..divide by 4
|
|
* 0b100..divide by 5
|
|
* 0b101..divide by 6
|
|
* 0b110..divide by 7
|
|
* 0b111..divide by 8
|
|
*/
|
|
#define CCM_CBCMR_LCDIF_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LCDIF_PODF_SHIFT)) & CCM_CBCMR_LCDIF_PODF_MASK)
|
|
#define CCM_CBCMR_LPSPI_PODF_MASK (0x1C000000U)
|
|
#define CCM_CBCMR_LPSPI_PODF_SHIFT (26U)
|
|
/*! LPSPI_PODF
|
|
* 0b000..divide by 1
|
|
* 0b001..divide by 2
|
|
* 0b010..divide by 3
|
|
* 0b011..divide by 4
|
|
* 0b100..divide by 5
|
|
* 0b101..divide by 6
|
|
* 0b110..divide by 7
|
|
* 0b111..divide by 8
|
|
*/
|
|
#define CCM_CBCMR_LPSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_PODF_SHIFT)) & CCM_CBCMR_LPSPI_PODF_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CSCMR1 - CCM Serial Clock Multiplexer Register 1 */
|
|
/*! @{ */
|
|
#define CCM_CSCMR1_PERCLK_PODF_MASK (0x3FU)
|
|
#define CCM_CSCMR1_PERCLK_PODF_SHIFT (0U)
|
|
/*! PERCLK_PODF
|
|
* 0b000000..divide by 1
|
|
* 0b000001..divide by 2
|
|
* 0b000010..divide by 3
|
|
* 0b000011..divide by 4
|
|
* 0b000100..divide by 5
|
|
* 0b000101..divide by 6
|
|
* 0b000110..divide by 7
|
|
* 0b111111..divide by 64
|
|
*/
|
|
#define CCM_CSCMR1_PERCLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_PODF_SHIFT)) & CCM_CSCMR1_PERCLK_PODF_MASK)
|
|
#define CCM_CSCMR1_PERCLK_CLK_SEL_MASK (0x40U)
|
|
#define CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6U)
|
|
/*! PERCLK_CLK_SEL
|
|
* 0b0..derive clock from ipg clk root
|
|
* 0b1..derive clock from osc_clk
|
|
*/
|
|
#define CCM_CSCMR1_PERCLK_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)) & CCM_CSCMR1_PERCLK_CLK_SEL_MASK)
|
|
#define CCM_CSCMR1_SAI1_CLK_SEL_MASK (0xC00U)
|
|
#define CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10U)
|
|
/*! SAI1_CLK_SEL
|
|
* 0b00..derive clock from PLL3 PFD2
|
|
* 0b01..derive clock from PLL5
|
|
* 0b10..derive clock from PLL4
|
|
* 0b11..Reserved
|
|
*/
|
|
#define CCM_CSCMR1_SAI1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI1_CLK_SEL_MASK)
|
|
#define CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3000U)
|
|
#define CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12U)
|
|
/*! SAI2_CLK_SEL
|
|
* 0b00..derive clock from PLL3 PFD2
|
|
* 0b01..derive clock from PLL5
|
|
* 0b10..derive clock from PLL4
|
|
* 0b11..Reserved
|
|
*/
|
|
#define CCM_CSCMR1_SAI2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI2_CLK_SEL_MASK)
|
|
#define CCM_CSCMR1_SAI3_CLK_SEL_MASK (0xC000U)
|
|
#define CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14U)
|
|
/*! SAI3_CLK_SEL
|
|
* 0b00..derive clock from PLL3 PFD2
|
|
* 0b01..derive clock from PLL5
|
|
* 0b10..derive clock from PLL4
|
|
* 0b11..Reserved
|
|
*/
|
|
#define CCM_CSCMR1_SAI3_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI3_CLK_SEL_MASK)
|
|
#define CCM_CSCMR1_USDHC1_CLK_SEL_MASK (0x10000U)
|
|
#define CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT (16U)
|
|
/*! USDHC1_CLK_SEL
|
|
* 0b0..derive clock from PLL2 PFD2
|
|
* 0b1..derive clock from PLL2 PFD0
|
|
*/
|
|
#define CCM_CSCMR1_USDHC1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC1_CLK_SEL_MASK)
|
|
#define CCM_CSCMR1_USDHC2_CLK_SEL_MASK (0x20000U)
|
|
#define CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT (17U)
|
|
/*! USDHC2_CLK_SEL
|
|
* 0b0..derive clock from PLL2 PFD2
|
|
* 0b1..derive clock from PLL2 PFD0
|
|
*/
|
|
#define CCM_CSCMR1_USDHC2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC2_CLK_SEL_MASK)
|
|
#define CCM_CSCMR1_FLEXSPI_PODF_MASK (0x3800000U)
|
|
#define CCM_CSCMR1_FLEXSPI_PODF_SHIFT (23U)
|
|
/*! FLEXSPI_PODF
|
|
* 0b000..divide by 1
|
|
* 0b001..divide by 2
|
|
* 0b010..divide by 3
|
|
* 0b011..divide by 4
|
|
* 0b100..divide by 5
|
|
* 0b101..divide by 6
|
|
* 0b110..divide by 7
|
|
* 0b111..divide by 8
|
|
*/
|
|
#define CCM_CSCMR1_FLEXSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT)) & CCM_CSCMR1_FLEXSPI_PODF_MASK)
|
|
#define CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK (0x60000000U)
|
|
#define CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT (29U)
|
|
/*! FLEXSPI_CLK_SEL
|
|
* 0b00..derive clock from semc_clk_root_pre
|
|
* 0b01..derive clock from pll3_sw_clk
|
|
* 0b10..derive clock from PLL2 PFD2
|
|
* 0b11..derive clock from PLL3 PFD0
|
|
*/
|
|
#define CCM_CSCMR1_FLEXSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)) & CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CSCMR2 - CCM Serial Clock Multiplexer Register 2 */
|
|
/*! @{ */
|
|
#define CCM_CSCMR2_CAN_CLK_PODF_MASK (0xFCU)
|
|
#define CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2U)
|
|
/*! CAN_CLK_PODF
|
|
* 0b000000..divide by 1
|
|
* 0b000111..divide by 8
|
|
* 0b111111..divide by 2^6
|
|
*/
|
|
#define CCM_CSCMR2_CAN_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT)) & CCM_CSCMR2_CAN_CLK_PODF_MASK)
|
|
#define CCM_CSCMR2_CAN_CLK_SEL_MASK (0x300U)
|
|
#define CCM_CSCMR2_CAN_CLK_SEL_SHIFT (8U)
|
|
/*! CAN_CLK_SEL
|
|
* 0b00..derive clock from pll3_sw_clk divided clock (60M)
|
|
* 0b01..derive clock from osc_clk (24M)
|
|
* 0b10..derive clock from pll3_sw_clk divided clock (80M)
|
|
* 0b11..Disable FlexCAN clock
|
|
*/
|
|
#define CCM_CSCMR2_CAN_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)) & CCM_CSCMR2_CAN_CLK_SEL_MASK)
|
|
#define CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK (0x180000U)
|
|
#define CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT (19U)
|
|
/*! FLEXIO2_CLK_SEL
|
|
* 0b00..derive clock from PLL4 divided clock
|
|
* 0b01..derive clock from PLL3 PFD2 clock
|
|
* 0b10..derive clock from PLL5 clock
|
|
* 0b11..derive clock from pll3_sw_clk
|
|
*/
|
|
#define CCM_CSCMR2_FLEXIO2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT)) & CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CSCDR1 - CCM Serial Clock Divider Register 1 */
|
|
/*! @{ */
|
|
#define CCM_CSCDR1_UART_CLK_PODF_MASK (0x3FU)
|
|
#define CCM_CSCDR1_UART_CLK_PODF_SHIFT (0U)
|
|
/*! UART_CLK_PODF
|
|
* 0b000000..divide by 1
|
|
* 0b111111..divide by 2^6
|
|
*/
|
|
#define CCM_CSCDR1_UART_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)) & CCM_CSCDR1_UART_CLK_PODF_MASK)
|
|
#define CCM_CSCDR1_UART_CLK_SEL_MASK (0x40U)
|
|
#define CCM_CSCDR1_UART_CLK_SEL_SHIFT (6U)
|
|
/*! UART_CLK_SEL
|
|
* 0b0..derive clock from pll3_80m
|
|
* 0b1..derive clock from osc_clk
|
|
*/
|
|
#define CCM_CSCDR1_UART_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_SEL_SHIFT)) & CCM_CSCDR1_UART_CLK_SEL_MASK)
|
|
#define CCM_CSCDR1_USDHC1_PODF_MASK (0x3800U)
|
|
#define CCM_CSCDR1_USDHC1_PODF_SHIFT (11U)
|
|
/*! USDHC1_PODF
|
|
* 0b000..divide by 1
|
|
* 0b001..divide by 2
|
|
* 0b010..divide by 3
|
|
* 0b011..divide by 4
|
|
* 0b100..divide by 5
|
|
* 0b101..divide by 6
|
|
* 0b110..divide by 7
|
|
* 0b111..divide by 8
|
|
*/
|
|
#define CCM_CSCDR1_USDHC1_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC1_PODF_SHIFT)) & CCM_CSCDR1_USDHC1_PODF_MASK)
|
|
#define CCM_CSCDR1_USDHC2_PODF_MASK (0x70000U)
|
|
#define CCM_CSCDR1_USDHC2_PODF_SHIFT (16U)
|
|
/*! USDHC2_PODF
|
|
* 0b000..divide by 1
|
|
* 0b001..divide by 2
|
|
* 0b010..divide by 3
|
|
* 0b011..divide by 4
|
|
* 0b100..divide by 5
|
|
* 0b101..divide by 6
|
|
* 0b110..divide by 7
|
|
* 0b111..divide by 8
|
|
*/
|
|
#define CCM_CSCDR1_USDHC2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC2_PODF_SHIFT)) & CCM_CSCDR1_USDHC2_PODF_MASK)
|
|
#define CCM_CSCDR1_TRACE_PODF_MASK (0x6000000U)
|
|
#define CCM_CSCDR1_TRACE_PODF_SHIFT (25U)
|
|
/*! TRACE_PODF
|
|
* 0b00..divide by 1
|
|
* 0b01..divide by 2
|
|
* 0b10..divide by 3
|
|
* 0b11..divide by 4
|
|
*/
|
|
#define CCM_CSCDR1_TRACE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_TRACE_PODF_SHIFT)) & CCM_CSCDR1_TRACE_PODF_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CS1CDR - CCM Clock Divider Register */
|
|
/*! @{ */
|
|
#define CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3FU)
|
|
#define CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0U)
|
|
/*! SAI1_CLK_PODF
|
|
* 0b000000..divide by 1
|
|
* 0b111111..divide by 2^6
|
|
*/
|
|
#define CCM_CS1CDR_SAI1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PODF_MASK)
|
|
#define CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x1C0U)
|
|
#define CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6U)
|
|
/*! SAI1_CLK_PRED
|
|
* 0b000..divide by 1
|
|
* 0b001..divide by 2
|
|
* 0b010..divide by 3
|
|
* 0b011..divide by 4
|
|
* 0b100..divide by 5
|
|
* 0b101..divide by 6
|
|
* 0b110..divide by 7
|
|
* 0b111..divide by 8
|
|
*/
|
|
#define CCM_CS1CDR_SAI1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PRED_MASK)
|
|
#define CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK (0xE00U)
|
|
#define CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT (9U)
|
|
/*! FLEXIO2_CLK_PRED
|
|
* 0b000..divide by 1
|
|
* 0b001..divide by 2
|
|
* 0b010..divide by 3
|
|
* 0b011..divide by 4
|
|
* 0b100..divide by 5
|
|
* 0b101..divide by 6
|
|
* 0b110..divide by 7
|
|
* 0b111..divide by 8
|
|
*/
|
|
#define CCM_CS1CDR_FLEXIO2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK)
|
|
#define CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F0000U)
|
|
#define CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16U)
|
|
/*! SAI3_CLK_PODF
|
|
* 0b000000..divide by 1
|
|
* 0b111111..divide by 2^6
|
|
*/
|
|
#define CCM_CS1CDR_SAI3_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PODF_MASK)
|
|
#define CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x1C00000U)
|
|
#define CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22U)
|
|
/*! SAI3_CLK_PRED
|
|
* 0b000..divide by 1
|
|
* 0b001..divide by 2
|
|
* 0b010..divide by 3
|
|
* 0b011..divide by 4
|
|
* 0b100..divide by 5
|
|
* 0b101..divide by 6
|
|
* 0b110..divide by 7
|
|
* 0b111..divide by 8
|
|
*/
|
|
#define CCM_CS1CDR_SAI3_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PRED_MASK)
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#define CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK (0xE000000U)
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#define CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT (25U)
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/*! FLEXIO2_CLK_PODF
|
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* 0b000..divide by 1
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* 0b001..divide by 2
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* 0b010..divide by 3
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* 0b011..divide by 4
|
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* 0b100..divide by 5
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* 0b101..divide by 6
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* 0b110..divide by 7
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* 0b111..divide by 8
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*/
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#define CCM_CS1CDR_FLEXIO2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK)
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/*! @} */
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/*! @name CS2CDR - CCM Clock Divider Register */
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/*! @{ */
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#define CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3FU)
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#define CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0U)
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/*! SAI2_CLK_PODF
|
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* 0b000000..divide by 1
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* 0b111111..divide by 2^6
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*/
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#define CCM_CS2CDR_SAI2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PODF_MASK)
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#define CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x1C0U)
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#define CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6U)
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/*! SAI2_CLK_PRED
|
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* 0b000..divide by 1
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* 0b001..divide by 2
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* 0b010..divide by 3
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* 0b011..divide by 4
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* 0b100..divide by 5
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* 0b101..divide by 6
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* 0b110..divide by 7
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* 0b111..divide by 8
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*/
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#define CCM_CS2CDR_SAI2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PRED_MASK)
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/*! @} */
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/*! @name CDCDR - CCM D1 Clock Divider Register */
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/*! @{ */
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#define CCM_CDCDR_FLEXIO1_CLK_SEL_MASK (0x180U)
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#define CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT (7U)
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/*! FLEXIO1_CLK_SEL
|
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* 0b00..derive clock from PLL4
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* 0b01..derive clock from PLL3 PFD2
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* 0b10..derive clock from PLL5
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* 0b11..derive clock from pll3_sw_clk
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*/
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#define CCM_CDCDR_FLEXIO1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_SEL_MASK)
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#define CCM_CDCDR_FLEXIO1_CLK_PODF_MASK (0xE00U)
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#define CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT (9U)
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/*! FLEXIO1_CLK_PODF
|
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* 0b000..divide by 1
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* 0b111..divide by 8
|
|
*/
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#define CCM_CDCDR_FLEXIO1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PODF_MASK)
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#define CCM_CDCDR_FLEXIO1_CLK_PRED_MASK (0x7000U)
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#define CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT (12U)
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/*! FLEXIO1_CLK_PRED
|
|
* 0b000..divide by 1 (do not use with high input frequencies)
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* 0b001..divide by 2
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* 0b010..divide by 3
|
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* 0b111..divide by 8
|
|
*/
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#define CCM_CDCDR_FLEXIO1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PRED_MASK)
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#define CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x300000U)
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#define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20U)
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/*! SPDIF0_CLK_SEL
|
|
* 0b00..derive clock from PLL4
|
|
* 0b01..derive clock from PLL3 PFD2
|
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* 0b10..derive clock from PLL5
|
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* 0b11..derive clock from pll3_sw_clk
|
|
*/
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#define CCM_CDCDR_SPDIF0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_SEL_MASK)
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#define CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x1C00000U)
|
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#define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22U)
|
|
/*! SPDIF0_CLK_PODF
|
|
* 0b000..divide by 1
|
|
* 0b111..divide by 8
|
|
*/
|
|
#define CCM_CDCDR_SPDIF0_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PODF_MASK)
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|
#define CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0xE000000U)
|
|
#define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25U)
|
|
/*! SPDIF0_CLK_PRED
|
|
* 0b000..divide by 1 (do not use with high input frequencies)
|
|
* 0b001..divide by 2
|
|
* 0b010..divide by 3
|
|
* 0b111..divide by 8
|
|
*/
|
|
#define CCM_CDCDR_SPDIF0_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PRED_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CSCDR2 - CCM Serial Clock Divider Register 2 */
|
|
/*! @{ */
|
|
#define CCM_CSCDR2_LCDIF_PRED_MASK (0x7000U)
|
|
#define CCM_CSCDR2_LCDIF_PRED_SHIFT (12U)
|
|
/*! LCDIF_PRED
|
|
* 0b000..divide by 1
|
|
* 0b001..divide by 2
|
|
* 0b010..divide by 3
|
|
* 0b011..divide by 4
|
|
* 0b100..divide by 5
|
|
* 0b101..divide by 6
|
|
* 0b110..divide by 7
|
|
* 0b111..divide by 8
|
|
*/
|
|
#define CCM_CSCDR2_LCDIF_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRED_SHIFT)) & CCM_CSCDR2_LCDIF_PRED_MASK)
|
|
#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK (0x38000U)
|
|
#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT (15U)
|
|
/*! LCDIF_PRE_CLK_SEL
|
|
* 0b000..derive clock from PLL2
|
|
* 0b001..derive clock from PLL3 PFD3
|
|
* 0b010..derive clock from PLL5
|
|
* 0b011..derive clock from PLL2 PFD0
|
|
* 0b100..derive clock from PLL2 PFD1
|
|
* 0b101..derive clock from PLL3 PFD1
|
|
*/
|
|
#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT)) & CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK)
|
|
#define CCM_CSCDR2_LPI2C_CLK_SEL_MASK (0x40000U)
|
|
#define CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT (18U)
|
|
/*! LPI2C_CLK_SEL
|
|
* 0b0..derive clock from pll3_60m
|
|
* 0b1..derive clock from osc_clk
|
|
*/
|
|
#define CCM_CSCDR2_LPI2C_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_SEL_MASK)
|
|
#define CCM_CSCDR2_LPI2C_CLK_PODF_MASK (0x1F80000U)
|
|
#define CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT (19U)
|
|
/*! LPI2C_CLK_PODF
|
|
* 0b000000..divide by 1
|
|
* 0b111111..divide by 2^6
|
|
*/
|
|
#define CCM_CSCDR2_LPI2C_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_PODF_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CSCDR3 - CCM Serial Clock Divider Register 3 */
|
|
/*! @{ */
|
|
#define CCM_CSCDR3_CSI_CLK_SEL_MASK (0x600U)
|
|
#define CCM_CSCDR3_CSI_CLK_SEL_SHIFT (9U)
|
|
/*! CSI_CLK_SEL
|
|
* 0b00..derive clock from osc_clk (24M)
|
|
* 0b01..derive clock from PLL2 PFD2
|
|
* 0b10..derive clock from pll3_120M
|
|
* 0b11..derive clock from PLL3 PFD1
|
|
*/
|
|
#define CCM_CSCDR3_CSI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT)) & CCM_CSCDR3_CSI_CLK_SEL_MASK)
|
|
#define CCM_CSCDR3_CSI_PODF_MASK (0x3800U)
|
|
#define CCM_CSCDR3_CSI_PODF_SHIFT (11U)
|
|
/*! CSI_PODF
|
|
* 0b000..divide by 1
|
|
* 0b001..divide by 2
|
|
* 0b010..divide by 3
|
|
* 0b011..divide by 4
|
|
* 0b100..divide by 5
|
|
* 0b101..divide by 6
|
|
* 0b110..divide by 7
|
|
* 0b111..divide by 8
|
|
*/
|
|
#define CCM_CSCDR3_CSI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_PODF_SHIFT)) & CCM_CSCDR3_CSI_PODF_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CDHIPR - CCM Divider Handshake In-Process Register */
|
|
/*! @{ */
|
|
#define CCM_CDHIPR_SEMC_PODF_BUSY_MASK (0x1U)
|
|
#define CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT (0U)
|
|
/*! SEMC_PODF_BUSY
|
|
* 0b0..divider is not busy and its value represents the actual division.
|
|
* 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the semc_podf will be applied.
|
|
*/
|
|
#define CCM_CDHIPR_SEMC_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT)) & CCM_CDHIPR_SEMC_PODF_BUSY_MASK)
|
|
#define CCM_CDHIPR_AHB_PODF_BUSY_MASK (0x2U)
|
|
#define CCM_CDHIPR_AHB_PODF_BUSY_SHIFT (1U)
|
|
/*! AHB_PODF_BUSY
|
|
* 0b0..divider is not busy and its value represents the actual division.
|
|
* 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the ahb_podf will be applied.
|
|
*/
|
|
#define CCM_CDHIPR_AHB_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AHB_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AHB_PODF_BUSY_MASK)
|
|
#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK (0x8U)
|
|
#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT (3U)
|
|
/*! PERIPH2_CLK_SEL_BUSY
|
|
* 0b0..mux is not busy and its value represents the actual division.
|
|
* 0b1..mux is busy with handshake process with module. The value read in the periph2_clk_sel represents the previous value of select, and after the handshake periph2_clk_sel value will be applied.
|
|
*/
|
|
#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK)
|
|
#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK (0x20U)
|
|
#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT (5U)
|
|
/*! PERIPH_CLK_SEL_BUSY
|
|
* 0b0..mux is not busy and its value represents the actual division.
|
|
* 0b1..mux is busy with handshake process with module. The value read in the periph_clk_sel represents the previous value of select, and after the handshake periph_clk_sel value will be applied.
|
|
*/
|
|
#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK)
|
|
#define CCM_CDHIPR_ARM_PODF_BUSY_MASK (0x10000U)
|
|
#define CCM_CDHIPR_ARM_PODF_BUSY_SHIFT (16U)
|
|
/*! ARM_PODF_BUSY
|
|
* 0b0..divider is not busy and its value represents the actual division.
|
|
* 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the arm_podf will be applied.
|
|
*/
|
|
#define CCM_CDHIPR_ARM_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_ARM_PODF_BUSY_SHIFT)) & CCM_CDHIPR_ARM_PODF_BUSY_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CLPCR - CCM Low Power Control Register */
|
|
/*! @{ */
|
|
#define CCM_CLPCR_LPM_MASK (0x3U)
|
|
#define CCM_CLPCR_LPM_SHIFT (0U)
|
|
/*! LPM
|
|
* 0b00..Remain in run mode
|
|
* 0b01..Transfer to wait mode
|
|
* 0b10..Transfer to stop mode
|
|
* 0b11..Reserved
|
|
*/
|
|
#define CCM_CLPCR_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_LPM_SHIFT)) & CCM_CLPCR_LPM_MASK)
|
|
#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK (0x20U)
|
|
#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT (5U)
|
|
/*! ARM_CLK_DIS_ON_LPM
|
|
* 0b0..ARM clock enabled on wait mode.
|
|
* 0b1..ARM clock disabled on wait mode. .
|
|
*/
|
|
#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT)) & CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK)
|
|
#define CCM_CLPCR_SBYOS_MASK (0x40U)
|
|
#define CCM_CLPCR_SBYOS_SHIFT (6U)
|
|
/*! SBYOS
|
|
* 0b0..On-chip oscillator will not be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will remain asserted - '0' and cosc_pwrdown will remain de asserted - '0')
|
|
* 0b1..On-chip oscillator will be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will be deasserted - '1' and cosc_pwrdown will be asserted - '1'). When returning from STOP mode, external oscillator will be enabled again, on-chip oscillator will return to oscillator mode, and after oscnt count, CCM will continue with the exit from the STOP mode process.
|
|
*/
|
|
#define CCM_CLPCR_SBYOS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_SBYOS_SHIFT)) & CCM_CLPCR_SBYOS_MASK)
|
|
#define CCM_CLPCR_DIS_REF_OSC_MASK (0x80U)
|
|
#define CCM_CLPCR_DIS_REF_OSC_SHIFT (7U)
|
|
/*! DIS_REF_OSC
|
|
* 0b0..external high frequency oscillator will be enabled, i.e. CCM_REF_EN_B = '0'.
|
|
* 0b1..external high frequency oscillator will be disabled, i.e. CCM_REF_EN_B = '1'
|
|
*/
|
|
#define CCM_CLPCR_DIS_REF_OSC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_DIS_REF_OSC_SHIFT)) & CCM_CLPCR_DIS_REF_OSC_MASK)
|
|
#define CCM_CLPCR_VSTBY_MASK (0x100U)
|
|
#define CCM_CLPCR_VSTBY_SHIFT (8U)
|
|
/*! VSTBY
|
|
* 0b0..Voltage will not be changed to standby voltage after next entrance to STOP mode. ( PMIC_STBY_REQ will remain negated - '0')
|
|
* 0b1..Voltage will be requested to change to standby voltage after next entrance to stop mode. ( PMIC_STBY_REQ will be asserted - '1').
|
|
*/
|
|
#define CCM_CLPCR_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_VSTBY_SHIFT)) & CCM_CLPCR_VSTBY_MASK)
|
|
#define CCM_CLPCR_STBY_COUNT_MASK (0x600U)
|
|
#define CCM_CLPCR_STBY_COUNT_SHIFT (9U)
|
|
/*! STBY_COUNT
|
|
* 0b00..CCM will wait (1*pmic_delay_scaler)+1 ckil clock cycles
|
|
* 0b01..CCM will wait (3*pmic_delay_scaler)+1 ckil clock cycles
|
|
* 0b10..CCM will wait (7*pmic_delay_scaler)+1 ckil clock cycles
|
|
* 0b11..CCM will wait (15*pmic_delay_scaler)+1 ckil clock cycles
|
|
*/
|
|
#define CCM_CLPCR_STBY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_STBY_COUNT_SHIFT)) & CCM_CLPCR_STBY_COUNT_MASK)
|
|
#define CCM_CLPCR_COSC_PWRDOWN_MASK (0x800U)
|
|
#define CCM_CLPCR_COSC_PWRDOWN_SHIFT (11U)
|
|
/*! COSC_PWRDOWN
|
|
* 0b0..On chip oscillator will not be powered down, i.e. cosc_pwrdown = '0'.
|
|
* 0b1..On chip oscillator will be powered down, i.e. cosc_pwrdown = '1'.
|
|
*/
|
|
#define CCM_CLPCR_COSC_PWRDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_COSC_PWRDOWN_SHIFT)) & CCM_CLPCR_COSC_PWRDOWN_MASK)
|
|
#define CCM_CLPCR_BYPASS_LPM_HS1_MASK (0x80000U)
|
|
#define CCM_CLPCR_BYPASS_LPM_HS1_SHIFT (19U)
|
|
#define CCM_CLPCR_BYPASS_LPM_HS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS1_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS1_MASK)
|
|
#define CCM_CLPCR_BYPASS_LPM_HS0_MASK (0x200000U)
|
|
#define CCM_CLPCR_BYPASS_LPM_HS0_SHIFT (21U)
|
|
#define CCM_CLPCR_BYPASS_LPM_HS0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS0_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS0_MASK)
|
|
#define CCM_CLPCR_MASK_CORE0_WFI_MASK (0x400000U)
|
|
#define CCM_CLPCR_MASK_CORE0_WFI_SHIFT (22U)
|
|
/*! MASK_CORE0_WFI
|
|
* 0b0..WFI of core0 is not masked
|
|
* 0b1..WFI of core0 is masked
|
|
*/
|
|
#define CCM_CLPCR_MASK_CORE0_WFI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_CORE0_WFI_SHIFT)) & CCM_CLPCR_MASK_CORE0_WFI_MASK)
|
|
#define CCM_CLPCR_MASK_SCU_IDLE_MASK (0x4000000U)
|
|
#define CCM_CLPCR_MASK_SCU_IDLE_SHIFT (26U)
|
|
/*! MASK_SCU_IDLE
|
|
* 0b1..SCU IDLE is masked
|
|
* 0b0..SCU IDLE is not masked
|
|
*/
|
|
#define CCM_CLPCR_MASK_SCU_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_SCU_IDLE_SHIFT)) & CCM_CLPCR_MASK_SCU_IDLE_MASK)
|
|
#define CCM_CLPCR_MASK_L2CC_IDLE_MASK (0x8000000U)
|
|
#define CCM_CLPCR_MASK_L2CC_IDLE_SHIFT (27U)
|
|
/*! MASK_L2CC_IDLE
|
|
* 0b1..L2CC IDLE is masked
|
|
* 0b0..L2CC IDLE is not masked
|
|
*/
|
|
#define CCM_CLPCR_MASK_L2CC_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_L2CC_IDLE_SHIFT)) & CCM_CLPCR_MASK_L2CC_IDLE_MASK)
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/*! @} */
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|
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/*! @name CISR - CCM Interrupt Status Register */
|
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/*! @{ */
|
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#define CCM_CISR_LRF_PLL_MASK (0x1U)
|
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#define CCM_CISR_LRF_PLL_SHIFT (0U)
|
|
/*! LRF_PLL
|
|
* 0b0..interrupt is not generated due to lock ready of all enabled and not bypaseed PLLs
|
|
* 0b1..interrupt generated due to lock ready of all enabled and not bypaseed PLLs
|
|
*/
|
|
#define CCM_CISR_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_LRF_PLL_SHIFT)) & CCM_CISR_LRF_PLL_MASK)
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#define CCM_CISR_COSC_READY_MASK (0x40U)
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#define CCM_CISR_COSC_READY_SHIFT (6U)
|
|
/*! COSC_READY
|
|
* 0b0..interrupt is not generated due to on board oscillator ready
|
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* 0b1..interrupt generated due to on board oscillator ready
|
|
*/
|
|
#define CCM_CISR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_COSC_READY_SHIFT)) & CCM_CISR_COSC_READY_MASK)
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#define CCM_CISR_SEMC_PODF_LOADED_MASK (0x20000U)
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#define CCM_CISR_SEMC_PODF_LOADED_SHIFT (17U)
|
|
/*! SEMC_PODF_LOADED
|
|
* 0b0..interrupt is not generated due to frequency change of semc_podf
|
|
* 0b1..interrupt generated due to frequency change of semc_podf
|
|
*/
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|
#define CCM_CISR_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_SEMC_PODF_LOADED_SHIFT)) & CCM_CISR_SEMC_PODF_LOADED_MASK)
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#define CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)
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#define CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)
|
|
/*! PERIPH2_CLK_SEL_LOADED
|
|
* 0b0..interrupt is not generated due to frequency change of periph2_clk_sel
|
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* 0b1..interrupt generated due to frequency change of periph2_clk_sel
|
|
*/
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#define CCM_CISR_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK)
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#define CCM_CISR_AHB_PODF_LOADED_MASK (0x100000U)
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#define CCM_CISR_AHB_PODF_LOADED_SHIFT (20U)
|
|
/*! AHB_PODF_LOADED
|
|
* 0b0..interrupt is not generated due to frequency change of ahb_podf
|
|
* 0b1..interrupt generated due to frequency change of ahb_podf
|
|
*/
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#define CCM_CISR_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AHB_PODF_LOADED_SHIFT)) & CCM_CISR_AHB_PODF_LOADED_MASK)
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#define CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)
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#define CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT (22U)
|
|
/*! PERIPH_CLK_SEL_LOADED
|
|
* 0b0..interrupt is not generated due to update of periph_clk_sel.
|
|
* 0b1..interrupt generated due to update of periph_clk_sel.
|
|
*/
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|
#define CCM_CISR_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK)
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#define CCM_CISR_ARM_PODF_LOADED_MASK (0x4000000U)
|
|
#define CCM_CISR_ARM_PODF_LOADED_SHIFT (26U)
|
|
/*! ARM_PODF_LOADED
|
|
* 0b0..interrupt is not generated due to frequency change of arm_podf
|
|
* 0b1..interrupt generated due to frequency change of arm_podf
|
|
*/
|
|
#define CCM_CISR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_ARM_PODF_LOADED_SHIFT)) & CCM_CISR_ARM_PODF_LOADED_MASK)
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/*! @} */
|
|
|
|
/*! @name CIMR - CCM Interrupt Mask Register */
|
|
/*! @{ */
|
|
#define CCM_CIMR_MASK_LRF_PLL_MASK (0x1U)
|
|
#define CCM_CIMR_MASK_LRF_PLL_SHIFT (0U)
|
|
/*! MASK_LRF_PLL
|
|
* 0b0..don't mask interrupt due to lrf of PLLs - interrupt will be created
|
|
* 0b1..mask interrupt due to lrf of PLLs
|
|
*/
|
|
#define CCM_CIMR_MASK_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_LRF_PLL_SHIFT)) & CCM_CIMR_MASK_LRF_PLL_MASK)
|
|
#define CCM_CIMR_MASK_COSC_READY_MASK (0x40U)
|
|
#define CCM_CIMR_MASK_COSC_READY_SHIFT (6U)
|
|
/*! MASK_COSC_READY
|
|
* 0b0..don't mask interrupt due to on board oscillator ready - interrupt will be created
|
|
* 0b1..mask interrupt due to on board oscillator ready
|
|
*/
|
|
#define CCM_CIMR_MASK_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_COSC_READY_SHIFT)) & CCM_CIMR_MASK_COSC_READY_MASK)
|
|
#define CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK (0x20000U)
|
|
#define CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT (17U)
|
|
/*! MASK_SEMC_PODF_LOADED
|
|
* 0b0..don't mask interrupt due to frequency change of semc_podf - interrupt will be created
|
|
* 0b1..mask interrupt due to frequency change of semc_podf
|
|
*/
|
|
#define CCM_CIMR_MASK_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK)
|
|
#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)
|
|
#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)
|
|
/*! MASK_PERIPH2_CLK_SEL_LOADED
|
|
* 0b0..don't mask interrupt due to update of periph2_clk_sel - interrupt will be created
|
|
* 0b1..mask interrupt due to update of periph2_clk_sel
|
|
*/
|
|
#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK)
|
|
#define CCM_CIMR_MASK_AHB_PODF_LOADED_MASK (0x100000U)
|
|
#define CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT (20U)
|
|
/*! MASK_AHB_PODF_LOADED
|
|
* 0b0..don't mask interrupt due to frequency change of ahb_podf - interrupt will be created
|
|
* 0b1..mask interrupt due to frequency change of ahb_podf
|
|
*/
|
|
#define CCM_CIMR_MASK_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AHB_PODF_LOADED_MASK)
|
|
#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)
|
|
#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT (22U)
|
|
/*! MASK_PERIPH_CLK_SEL_LOADED
|
|
* 0b0..don't mask interrupt due to update of periph_clk_sel - interrupt will be created
|
|
* 0b1..mask interrupt due to update of periph_clk_sel
|
|
*/
|
|
#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK)
|
|
#define CCM_CIMR_ARM_PODF_LOADED_MASK (0x4000000U)
|
|
#define CCM_CIMR_ARM_PODF_LOADED_SHIFT (26U)
|
|
/*! ARM_PODF_LOADED
|
|
* 0b0..don't mask interrupt due to frequency change of arm_podf - interrupt will be created
|
|
* 0b1..mask interrupt due to frequency change of arm_podf
|
|
*/
|
|
#define CCM_CIMR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_ARM_PODF_LOADED_SHIFT)) & CCM_CIMR_ARM_PODF_LOADED_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CCOSR - CCM Clock Output Source Register */
|
|
/*! @{ */
|
|
#define CCM_CCOSR_CLKO1_SEL_MASK (0xFU)
|
|
#define CCM_CCOSR_CLKO1_SEL_SHIFT (0U)
|
|
/*! CLKO1_SEL
|
|
* 0b0000..USB1 PLL clock (divided by 2)
|
|
* 0b0001..SYS PLL clock (divided by 2)
|
|
* 0b0011..VIDEO PLL clock (divided by 2)
|
|
* 0b0101..semc_clk_root
|
|
* 0b0110..Reserved
|
|
* 0b1010..lcdif_pix_clk_root
|
|
* 0b1011..ahb_clk_root
|
|
* 0b1100..ipg_clk_root
|
|
* 0b1101..perclk_root
|
|
* 0b1110..ckil_sync_clk_root
|
|
* 0b1111..pll4_main_clk
|
|
*/
|
|
#define CCM_CCOSR_CLKO1_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_SEL_SHIFT)) & CCM_CCOSR_CLKO1_SEL_MASK)
|
|
#define CCM_CCOSR_CLKO1_DIV_MASK (0x70U)
|
|
#define CCM_CCOSR_CLKO1_DIV_SHIFT (4U)
|
|
/*! CLKO1_DIV
|
|
* 0b000..divide by 1
|
|
* 0b001..divide by 2
|
|
* 0b010..divide by 3
|
|
* 0b011..divide by 4
|
|
* 0b100..divide by 5
|
|
* 0b101..divide by 6
|
|
* 0b110..divide by 7
|
|
* 0b111..divide by 8
|
|
*/
|
|
#define CCM_CCOSR_CLKO1_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_DIV_SHIFT)) & CCM_CCOSR_CLKO1_DIV_MASK)
|
|
#define CCM_CCOSR_CLKO1_EN_MASK (0x80U)
|
|
#define CCM_CCOSR_CLKO1_EN_SHIFT (7U)
|
|
/*! CLKO1_EN
|
|
* 0b0..CCM_CLKO1 disabled.
|
|
* 0b1..CCM_CLKO1 enabled.
|
|
*/
|
|
#define CCM_CCOSR_CLKO1_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_EN_SHIFT)) & CCM_CCOSR_CLKO1_EN_MASK)
|
|
#define CCM_CCOSR_CLK_OUT_SEL_MASK (0x100U)
|
|
#define CCM_CCOSR_CLK_OUT_SEL_SHIFT (8U)
|
|
/*! CLK_OUT_SEL
|
|
* 0b0..CCM_CLKO1 output drives CCM_CLKO1 clock
|
|
* 0b1..CCM_CLKO1 output drives CCM_CLKO2 clock
|
|
*/
|
|
#define CCM_CCOSR_CLK_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLK_OUT_SEL_SHIFT)) & CCM_CCOSR_CLK_OUT_SEL_MASK)
|
|
#define CCM_CCOSR_CLKO2_SEL_MASK (0x1F0000U)
|
|
#define CCM_CCOSR_CLKO2_SEL_SHIFT (16U)
|
|
/*! CLKO2_SEL
|
|
* 0b00011..usdhc1_clk_root
|
|
* 0b00101..wrck_clk_root
|
|
* 0b00110..lpi2c_clk_root
|
|
* 0b01011..csi_clk_root
|
|
* 0b01110..osc_clk
|
|
* 0b10001..usdhc2_clk_root
|
|
* 0b10010..sai1_clk_root
|
|
* 0b10011..sai2_clk_root
|
|
* 0b10100..sai3_clk_root
|
|
* 0b10111..can_clk_root
|
|
* 0b11011..flexspi_clk_root
|
|
* 0b11100..uart_clk_root
|
|
* 0b11101..spdif0_clk_root
|
|
* 0b11111..Reserved
|
|
*/
|
|
#define CCM_CCOSR_CLKO2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_SEL_SHIFT)) & CCM_CCOSR_CLKO2_SEL_MASK)
|
|
#define CCM_CCOSR_CLKO2_DIV_MASK (0xE00000U)
|
|
#define CCM_CCOSR_CLKO2_DIV_SHIFT (21U)
|
|
/*! CLKO2_DIV
|
|
* 0b000..divide by 1
|
|
* 0b001..divide by 2
|
|
* 0b010..divide by 3
|
|
* 0b011..divide by 4
|
|
* 0b100..divide by 5
|
|
* 0b101..divide by 6
|
|
* 0b110..divide by 7
|
|
* 0b111..divide by 8
|
|
*/
|
|
#define CCM_CCOSR_CLKO2_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_DIV_SHIFT)) & CCM_CCOSR_CLKO2_DIV_MASK)
|
|
#define CCM_CCOSR_CLKO2_EN_MASK (0x1000000U)
|
|
#define CCM_CCOSR_CLKO2_EN_SHIFT (24U)
|
|
/*! CLKO2_EN
|
|
* 0b0..CCM_CLKO2 disabled.
|
|
* 0b1..CCM_CLKO2 enabled.
|
|
*/
|
|
#define CCM_CCOSR_CLKO2_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_EN_SHIFT)) & CCM_CCOSR_CLKO2_EN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CGPR - CCM General Purpose Register */
|
|
/*! @{ */
|
|
#define CCM_CGPR_PMIC_DELAY_SCALER_MASK (0x1U)
|
|
#define CCM_CGPR_PMIC_DELAY_SCALER_SHIFT (0U)
|
|
/*! PMIC_DELAY_SCALER
|
|
* 0b0..clock is not divided
|
|
* 0b1..clock is divided /8
|
|
*/
|
|
#define CCM_CGPR_PMIC_DELAY_SCALER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_PMIC_DELAY_SCALER_SHIFT)) & CCM_CGPR_PMIC_DELAY_SCALER_MASK)
|
|
#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK (0x10U)
|
|
#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT (4U)
|
|
/*! EFUSE_PROG_SUPPLY_GATE
|
|
* 0b0..fuse programing supply voltage is gated off to the efuse module
|
|
* 0b1..allow fuse programing.
|
|
*/
|
|
#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT)) & CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK)
|
|
#define CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0xC000U)
|
|
#define CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14U)
|
|
/*! SYS_MEM_DS_CTRL
|
|
* 0b00..Disable memory DS mode always
|
|
* 0b01..Enable memory (outside ARM platform) DS mode when system STOP and PLL are disabled
|
|
* 0b1x..enable memory (outside ARM platform) DS mode when system is in STOP mode
|
|
*/
|
|
#define CCM_CGPR_SYS_MEM_DS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)) & CCM_CGPR_SYS_MEM_DS_CTRL_MASK)
|
|
#define CCM_CGPR_FPL_MASK (0x10000U)
|
|
#define CCM_CGPR_FPL_SHIFT (16U)
|
|
/*! FPL - Fast PLL enable.
|
|
* 0b0..Engage PLL enable default way.
|
|
* 0b1..Engage PLL enable 3 CKIL clocks earlier at exiting low power mode (STOP). Should be used only if 24MHz OSC was active in low power mode.
|
|
*/
|
|
#define CCM_CGPR_FPL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_FPL_SHIFT)) & CCM_CGPR_FPL_MASK)
|
|
#define CCM_CGPR_INT_MEM_CLK_LPM_MASK (0x20000U)
|
|
#define CCM_CGPR_INT_MEM_CLK_LPM_SHIFT (17U)
|
|
/*! INT_MEM_CLK_LPM
|
|
* 0b0..Disable the clock to the ARM platform memories when entering Low Power Mode
|
|
* 0b1..Keep the clocks to the ARM platform memories enabled only if an interrupt is pending when entering Low Power Modes (WAIT and STOP without power gating)
|
|
*/
|
|
#define CCM_CGPR_INT_MEM_CLK_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_INT_MEM_CLK_LPM_SHIFT)) & CCM_CGPR_INT_MEM_CLK_LPM_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CCGR0 - CCM Clock Gating Register 0 */
|
|
/*! @{ */
|
|
#define CCM_CCGR0_CG0_MASK (0x3U)
|
|
#define CCM_CCGR0_CG0_SHIFT (0U)
|
|
#define CCM_CCGR0_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG0_SHIFT)) & CCM_CCGR0_CG0_MASK)
|
|
#define CCM_CCGR0_CG1_MASK (0xCU)
|
|
#define CCM_CCGR0_CG1_SHIFT (2U)
|
|
#define CCM_CCGR0_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG1_SHIFT)) & CCM_CCGR0_CG1_MASK)
|
|
#define CCM_CCGR0_CG2_MASK (0x30U)
|
|
#define CCM_CCGR0_CG2_SHIFT (4U)
|
|
#define CCM_CCGR0_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG2_SHIFT)) & CCM_CCGR0_CG2_MASK)
|
|
#define CCM_CCGR0_CG3_MASK (0xC0U)
|
|
#define CCM_CCGR0_CG3_SHIFT (6U)
|
|
#define CCM_CCGR0_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG3_SHIFT)) & CCM_CCGR0_CG3_MASK)
|
|
#define CCM_CCGR0_CG4_MASK (0x300U)
|
|
#define CCM_CCGR0_CG4_SHIFT (8U)
|
|
#define CCM_CCGR0_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG4_SHIFT)) & CCM_CCGR0_CG4_MASK)
|
|
#define CCM_CCGR0_CG5_MASK (0xC00U)
|
|
#define CCM_CCGR0_CG5_SHIFT (10U)
|
|
#define CCM_CCGR0_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG5_SHIFT)) & CCM_CCGR0_CG5_MASK)
|
|
#define CCM_CCGR0_CG6_MASK (0x3000U)
|
|
#define CCM_CCGR0_CG6_SHIFT (12U)
|
|
#define CCM_CCGR0_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG6_SHIFT)) & CCM_CCGR0_CG6_MASK)
|
|
#define CCM_CCGR0_CG7_MASK (0xC000U)
|
|
#define CCM_CCGR0_CG7_SHIFT (14U)
|
|
#define CCM_CCGR0_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG7_SHIFT)) & CCM_CCGR0_CG7_MASK)
|
|
#define CCM_CCGR0_CG8_MASK (0x30000U)
|
|
#define CCM_CCGR0_CG8_SHIFT (16U)
|
|
#define CCM_CCGR0_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG8_SHIFT)) & CCM_CCGR0_CG8_MASK)
|
|
#define CCM_CCGR0_CG9_MASK (0xC0000U)
|
|
#define CCM_CCGR0_CG9_SHIFT (18U)
|
|
#define CCM_CCGR0_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG9_SHIFT)) & CCM_CCGR0_CG9_MASK)
|
|
#define CCM_CCGR0_CG10_MASK (0x300000U)
|
|
#define CCM_CCGR0_CG10_SHIFT (20U)
|
|
#define CCM_CCGR0_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG10_SHIFT)) & CCM_CCGR0_CG10_MASK)
|
|
#define CCM_CCGR0_CG11_MASK (0xC00000U)
|
|
#define CCM_CCGR0_CG11_SHIFT (22U)
|
|
#define CCM_CCGR0_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG11_SHIFT)) & CCM_CCGR0_CG11_MASK)
|
|
#define CCM_CCGR0_CG12_MASK (0x3000000U)
|
|
#define CCM_CCGR0_CG12_SHIFT (24U)
|
|
#define CCM_CCGR0_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG12_SHIFT)) & CCM_CCGR0_CG12_MASK)
|
|
#define CCM_CCGR0_CG13_MASK (0xC000000U)
|
|
#define CCM_CCGR0_CG13_SHIFT (26U)
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#define CCM_CCGR0_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG13_SHIFT)) & CCM_CCGR0_CG13_MASK)
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#define CCM_CCGR0_CG14_MASK (0x30000000U)
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#define CCM_CCGR0_CG14_SHIFT (28U)
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#define CCM_CCGR0_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG14_SHIFT)) & CCM_CCGR0_CG14_MASK)
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#define CCM_CCGR0_CG15_MASK (0xC0000000U)
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#define CCM_CCGR0_CG15_SHIFT (30U)
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#define CCM_CCGR0_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG15_SHIFT)) & CCM_CCGR0_CG15_MASK)
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/*! @} */
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/*! @name CCGR1 - CCM Clock Gating Register 1 */
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/*! @{ */
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#define CCM_CCGR1_CG0_MASK (0x3U)
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#define CCM_CCGR1_CG0_SHIFT (0U)
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#define CCM_CCGR1_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG0_SHIFT)) & CCM_CCGR1_CG0_MASK)
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#define CCM_CCGR1_CG1_MASK (0xCU)
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#define CCM_CCGR1_CG1_SHIFT (2U)
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#define CCM_CCGR1_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG1_SHIFT)) & CCM_CCGR1_CG1_MASK)
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#define CCM_CCGR1_CG2_MASK (0x30U)
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#define CCM_CCGR1_CG2_SHIFT (4U)
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#define CCM_CCGR1_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG2_SHIFT)) & CCM_CCGR1_CG2_MASK)
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#define CCM_CCGR1_CG3_MASK (0xC0U)
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#define CCM_CCGR1_CG3_SHIFT (6U)
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#define CCM_CCGR1_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG3_SHIFT)) & CCM_CCGR1_CG3_MASK)
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#define CCM_CCGR1_CG4_MASK (0x300U)
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#define CCM_CCGR1_CG4_SHIFT (8U)
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#define CCM_CCGR1_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG4_SHIFT)) & CCM_CCGR1_CG4_MASK)
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#define CCM_CCGR1_CG5_MASK (0xC00U)
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#define CCM_CCGR1_CG5_SHIFT (10U)
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#define CCM_CCGR1_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG5_SHIFT)) & CCM_CCGR1_CG5_MASK)
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#define CCM_CCGR1_CG6_MASK (0x3000U)
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#define CCM_CCGR1_CG6_SHIFT (12U)
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#define CCM_CCGR1_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG6_SHIFT)) & CCM_CCGR1_CG6_MASK)
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#define CCM_CCGR1_CG7_MASK (0xC000U)
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#define CCM_CCGR1_CG7_SHIFT (14U)
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#define CCM_CCGR1_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG7_SHIFT)) & CCM_CCGR1_CG7_MASK)
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#define CCM_CCGR1_CG8_MASK (0x30000U)
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#define CCM_CCGR1_CG8_SHIFT (16U)
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#define CCM_CCGR1_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG8_SHIFT)) & CCM_CCGR1_CG8_MASK)
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#define CCM_CCGR1_CG9_MASK (0xC0000U)
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#define CCM_CCGR1_CG9_SHIFT (18U)
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#define CCM_CCGR1_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG9_SHIFT)) & CCM_CCGR1_CG9_MASK)
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#define CCM_CCGR1_CG10_MASK (0x300000U)
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#define CCM_CCGR1_CG10_SHIFT (20U)
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#define CCM_CCGR1_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG10_SHIFT)) & CCM_CCGR1_CG10_MASK)
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#define CCM_CCGR1_CG11_MASK (0xC00000U)
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#define CCM_CCGR1_CG11_SHIFT (22U)
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#define CCM_CCGR1_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG11_SHIFT)) & CCM_CCGR1_CG11_MASK)
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#define CCM_CCGR1_CG12_MASK (0x3000000U)
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#define CCM_CCGR1_CG12_SHIFT (24U)
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#define CCM_CCGR1_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG12_SHIFT)) & CCM_CCGR1_CG12_MASK)
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#define CCM_CCGR1_CG13_MASK (0xC000000U)
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#define CCM_CCGR1_CG13_SHIFT (26U)
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#define CCM_CCGR1_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG13_SHIFT)) & CCM_CCGR1_CG13_MASK)
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#define CCM_CCGR1_CG14_MASK (0x30000000U)
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#define CCM_CCGR1_CG14_SHIFT (28U)
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#define CCM_CCGR1_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG14_SHIFT)) & CCM_CCGR1_CG14_MASK)
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#define CCM_CCGR1_CG15_MASK (0xC0000000U)
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#define CCM_CCGR1_CG15_SHIFT (30U)
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#define CCM_CCGR1_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG15_SHIFT)) & CCM_CCGR1_CG15_MASK)
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/*! @} */
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/*! @name CCGR2 - CCM Clock Gating Register 2 */
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/*! @{ */
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#define CCM_CCGR2_CG0_MASK (0x3U)
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#define CCM_CCGR2_CG0_SHIFT (0U)
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#define CCM_CCGR2_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG0_SHIFT)) & CCM_CCGR2_CG0_MASK)
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#define CCM_CCGR2_CG1_MASK (0xCU)
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#define CCM_CCGR2_CG1_SHIFT (2U)
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#define CCM_CCGR2_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG1_SHIFT)) & CCM_CCGR2_CG1_MASK)
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#define CCM_CCGR2_CG2_MASK (0x30U)
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#define CCM_CCGR2_CG2_SHIFT (4U)
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#define CCM_CCGR2_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG2_SHIFT)) & CCM_CCGR2_CG2_MASK)
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#define CCM_CCGR2_CG3_MASK (0xC0U)
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#define CCM_CCGR2_CG3_SHIFT (6U)
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#define CCM_CCGR2_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG3_SHIFT)) & CCM_CCGR2_CG3_MASK)
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#define CCM_CCGR2_CG4_MASK (0x300U)
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#define CCM_CCGR2_CG4_SHIFT (8U)
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#define CCM_CCGR2_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG4_SHIFT)) & CCM_CCGR2_CG4_MASK)
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#define CCM_CCGR2_CG5_MASK (0xC00U)
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#define CCM_CCGR2_CG5_SHIFT (10U)
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#define CCM_CCGR2_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG5_SHIFT)) & CCM_CCGR2_CG5_MASK)
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#define CCM_CCGR2_CG6_MASK (0x3000U)
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#define CCM_CCGR2_CG6_SHIFT (12U)
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#define CCM_CCGR2_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG6_SHIFT)) & CCM_CCGR2_CG6_MASK)
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#define CCM_CCGR2_CG7_MASK (0xC000U)
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#define CCM_CCGR2_CG7_SHIFT (14U)
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#define CCM_CCGR2_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG7_SHIFT)) & CCM_CCGR2_CG7_MASK)
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#define CCM_CCGR2_CG8_MASK (0x30000U)
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#define CCM_CCGR2_CG8_SHIFT (16U)
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#define CCM_CCGR2_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG8_SHIFT)) & CCM_CCGR2_CG8_MASK)
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#define CCM_CCGR2_CG9_MASK (0xC0000U)
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#define CCM_CCGR2_CG9_SHIFT (18U)
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#define CCM_CCGR2_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG9_SHIFT)) & CCM_CCGR2_CG9_MASK)
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#define CCM_CCGR2_CG10_MASK (0x300000U)
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#define CCM_CCGR2_CG10_SHIFT (20U)
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#define CCM_CCGR2_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG10_SHIFT)) & CCM_CCGR2_CG10_MASK)
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#define CCM_CCGR2_CG11_MASK (0xC00000U)
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#define CCM_CCGR2_CG11_SHIFT (22U)
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#define CCM_CCGR2_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG11_SHIFT)) & CCM_CCGR2_CG11_MASK)
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#define CCM_CCGR2_CG12_MASK (0x3000000U)
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#define CCM_CCGR2_CG12_SHIFT (24U)
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#define CCM_CCGR2_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG12_SHIFT)) & CCM_CCGR2_CG12_MASK)
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#define CCM_CCGR2_CG13_MASK (0xC000000U)
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#define CCM_CCGR2_CG13_SHIFT (26U)
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#define CCM_CCGR2_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG13_SHIFT)) & CCM_CCGR2_CG13_MASK)
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#define CCM_CCGR2_CG14_MASK (0x30000000U)
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#define CCM_CCGR2_CG14_SHIFT (28U)
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#define CCM_CCGR2_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG14_SHIFT)) & CCM_CCGR2_CG14_MASK)
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#define CCM_CCGR2_CG15_MASK (0xC0000000U)
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#define CCM_CCGR2_CG15_SHIFT (30U)
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#define CCM_CCGR2_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG15_SHIFT)) & CCM_CCGR2_CG15_MASK)
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/*! @} */
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/*! @name CCGR3 - CCM Clock Gating Register 3 */
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/*! @{ */
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#define CCM_CCGR3_CG0_MASK (0x3U)
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#define CCM_CCGR3_CG0_SHIFT (0U)
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#define CCM_CCGR3_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG0_SHIFT)) & CCM_CCGR3_CG0_MASK)
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#define CCM_CCGR3_CG1_MASK (0xCU)
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#define CCM_CCGR3_CG1_SHIFT (2U)
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#define CCM_CCGR3_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG1_SHIFT)) & CCM_CCGR3_CG1_MASK)
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#define CCM_CCGR3_CG2_MASK (0x30U)
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#define CCM_CCGR3_CG2_SHIFT (4U)
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#define CCM_CCGR3_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG2_SHIFT)) & CCM_CCGR3_CG2_MASK)
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#define CCM_CCGR3_CG3_MASK (0xC0U)
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#define CCM_CCGR3_CG3_SHIFT (6U)
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#define CCM_CCGR3_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG3_SHIFT)) & CCM_CCGR3_CG3_MASK)
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#define CCM_CCGR3_CG4_MASK (0x300U)
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#define CCM_CCGR3_CG4_SHIFT (8U)
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#define CCM_CCGR3_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG4_SHIFT)) & CCM_CCGR3_CG4_MASK)
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#define CCM_CCGR3_CG5_MASK (0xC00U)
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#define CCM_CCGR3_CG5_SHIFT (10U)
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#define CCM_CCGR3_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG5_SHIFT)) & CCM_CCGR3_CG5_MASK)
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#define CCM_CCGR3_CG6_MASK (0x3000U)
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#define CCM_CCGR3_CG6_SHIFT (12U)
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#define CCM_CCGR3_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG6_SHIFT)) & CCM_CCGR3_CG6_MASK)
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#define CCM_CCGR3_CG7_MASK (0xC000U)
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#define CCM_CCGR3_CG7_SHIFT (14U)
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#define CCM_CCGR3_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG7_SHIFT)) & CCM_CCGR3_CG7_MASK)
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#define CCM_CCGR3_CG8_MASK (0x30000U)
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#define CCM_CCGR3_CG8_SHIFT (16U)
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#define CCM_CCGR3_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG8_SHIFT)) & CCM_CCGR3_CG8_MASK)
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#define CCM_CCGR3_CG9_MASK (0xC0000U)
|
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#define CCM_CCGR3_CG9_SHIFT (18U)
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#define CCM_CCGR3_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG9_SHIFT)) & CCM_CCGR3_CG9_MASK)
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#define CCM_CCGR3_CG10_MASK (0x300000U)
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#define CCM_CCGR3_CG10_SHIFT (20U)
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#define CCM_CCGR3_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG10_SHIFT)) & CCM_CCGR3_CG10_MASK)
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#define CCM_CCGR3_CG11_MASK (0xC00000U)
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#define CCM_CCGR3_CG11_SHIFT (22U)
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#define CCM_CCGR3_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG11_SHIFT)) & CCM_CCGR3_CG11_MASK)
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#define CCM_CCGR3_CG12_MASK (0x3000000U)
|
|
#define CCM_CCGR3_CG12_SHIFT (24U)
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#define CCM_CCGR3_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG12_SHIFT)) & CCM_CCGR3_CG12_MASK)
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#define CCM_CCGR3_CG13_MASK (0xC000000U)
|
|
#define CCM_CCGR3_CG13_SHIFT (26U)
|
|
#define CCM_CCGR3_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG13_SHIFT)) & CCM_CCGR3_CG13_MASK)
|
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#define CCM_CCGR3_CG14_MASK (0x30000000U)
|
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#define CCM_CCGR3_CG14_SHIFT (28U)
|
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#define CCM_CCGR3_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG14_SHIFT)) & CCM_CCGR3_CG14_MASK)
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#define CCM_CCGR3_CG15_MASK (0xC0000000U)
|
|
#define CCM_CCGR3_CG15_SHIFT (30U)
|
|
#define CCM_CCGR3_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG15_SHIFT)) & CCM_CCGR3_CG15_MASK)
|
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/*! @} */
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|
|
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/*! @name CCGR4 - CCM Clock Gating Register 4 */
|
|
/*! @{ */
|
|
#define CCM_CCGR4_CG0_MASK (0x3U)
|
|
#define CCM_CCGR4_CG0_SHIFT (0U)
|
|
#define CCM_CCGR4_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG0_SHIFT)) & CCM_CCGR4_CG0_MASK)
|
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#define CCM_CCGR4_CG1_MASK (0xCU)
|
|
#define CCM_CCGR4_CG1_SHIFT (2U)
|
|
#define CCM_CCGR4_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG1_SHIFT)) & CCM_CCGR4_CG1_MASK)
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#define CCM_CCGR4_CG2_MASK (0x30U)
|
|
#define CCM_CCGR4_CG2_SHIFT (4U)
|
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#define CCM_CCGR4_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG2_SHIFT)) & CCM_CCGR4_CG2_MASK)
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#define CCM_CCGR4_CG3_MASK (0xC0U)
|
|
#define CCM_CCGR4_CG3_SHIFT (6U)
|
|
#define CCM_CCGR4_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG3_SHIFT)) & CCM_CCGR4_CG3_MASK)
|
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#define CCM_CCGR4_CG4_MASK (0x300U)
|
|
#define CCM_CCGR4_CG4_SHIFT (8U)
|
|
#define CCM_CCGR4_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG4_SHIFT)) & CCM_CCGR4_CG4_MASK)
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#define CCM_CCGR4_CG5_MASK (0xC00U)
|
|
#define CCM_CCGR4_CG5_SHIFT (10U)
|
|
#define CCM_CCGR4_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG5_SHIFT)) & CCM_CCGR4_CG5_MASK)
|
|
#define CCM_CCGR4_CG6_MASK (0x3000U)
|
|
#define CCM_CCGR4_CG6_SHIFT (12U)
|
|
#define CCM_CCGR4_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG6_SHIFT)) & CCM_CCGR4_CG6_MASK)
|
|
#define CCM_CCGR4_CG7_MASK (0xC000U)
|
|
#define CCM_CCGR4_CG7_SHIFT (14U)
|
|
#define CCM_CCGR4_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG7_SHIFT)) & CCM_CCGR4_CG7_MASK)
|
|
#define CCM_CCGR4_CG8_MASK (0x30000U)
|
|
#define CCM_CCGR4_CG8_SHIFT (16U)
|
|
#define CCM_CCGR4_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG8_SHIFT)) & CCM_CCGR4_CG8_MASK)
|
|
#define CCM_CCGR4_CG9_MASK (0xC0000U)
|
|
#define CCM_CCGR4_CG9_SHIFT (18U)
|
|
#define CCM_CCGR4_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG9_SHIFT)) & CCM_CCGR4_CG9_MASK)
|
|
#define CCM_CCGR4_CG10_MASK (0x300000U)
|
|
#define CCM_CCGR4_CG10_SHIFT (20U)
|
|
#define CCM_CCGR4_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG10_SHIFT)) & CCM_CCGR4_CG10_MASK)
|
|
#define CCM_CCGR4_CG11_MASK (0xC00000U)
|
|
#define CCM_CCGR4_CG11_SHIFT (22U)
|
|
#define CCM_CCGR4_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG11_SHIFT)) & CCM_CCGR4_CG11_MASK)
|
|
#define CCM_CCGR4_CG12_MASK (0x3000000U)
|
|
#define CCM_CCGR4_CG12_SHIFT (24U)
|
|
#define CCM_CCGR4_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG12_SHIFT)) & CCM_CCGR4_CG12_MASK)
|
|
#define CCM_CCGR4_CG13_MASK (0xC000000U)
|
|
#define CCM_CCGR4_CG13_SHIFT (26U)
|
|
#define CCM_CCGR4_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG13_SHIFT)) & CCM_CCGR4_CG13_MASK)
|
|
#define CCM_CCGR4_CG14_MASK (0x30000000U)
|
|
#define CCM_CCGR4_CG14_SHIFT (28U)
|
|
#define CCM_CCGR4_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG14_SHIFT)) & CCM_CCGR4_CG14_MASK)
|
|
#define CCM_CCGR4_CG15_MASK (0xC0000000U)
|
|
#define CCM_CCGR4_CG15_SHIFT (30U)
|
|
#define CCM_CCGR4_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG15_SHIFT)) & CCM_CCGR4_CG15_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CCGR5 - CCM Clock Gating Register 5 */
|
|
/*! @{ */
|
|
#define CCM_CCGR5_CG0_MASK (0x3U)
|
|
#define CCM_CCGR5_CG0_SHIFT (0U)
|
|
#define CCM_CCGR5_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG0_SHIFT)) & CCM_CCGR5_CG0_MASK)
|
|
#define CCM_CCGR5_CG1_MASK (0xCU)
|
|
#define CCM_CCGR5_CG1_SHIFT (2U)
|
|
#define CCM_CCGR5_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG1_SHIFT)) & CCM_CCGR5_CG1_MASK)
|
|
#define CCM_CCGR5_CG2_MASK (0x30U)
|
|
#define CCM_CCGR5_CG2_SHIFT (4U)
|
|
#define CCM_CCGR5_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG2_SHIFT)) & CCM_CCGR5_CG2_MASK)
|
|
#define CCM_CCGR5_CG3_MASK (0xC0U)
|
|
#define CCM_CCGR5_CG3_SHIFT (6U)
|
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#define CCM_CCGR5_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG3_SHIFT)) & CCM_CCGR5_CG3_MASK)
|
|
#define CCM_CCGR5_CG4_MASK (0x300U)
|
|
#define CCM_CCGR5_CG4_SHIFT (8U)
|
|
#define CCM_CCGR5_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG4_SHIFT)) & CCM_CCGR5_CG4_MASK)
|
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#define CCM_CCGR5_CG5_MASK (0xC00U)
|
|
#define CCM_CCGR5_CG5_SHIFT (10U)
|
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#define CCM_CCGR5_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG5_SHIFT)) & CCM_CCGR5_CG5_MASK)
|
|
#define CCM_CCGR5_CG6_MASK (0x3000U)
|
|
#define CCM_CCGR5_CG6_SHIFT (12U)
|
|
#define CCM_CCGR5_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG6_SHIFT)) & CCM_CCGR5_CG6_MASK)
|
|
#define CCM_CCGR5_CG7_MASK (0xC000U)
|
|
#define CCM_CCGR5_CG7_SHIFT (14U)
|
|
#define CCM_CCGR5_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG7_SHIFT)) & CCM_CCGR5_CG7_MASK)
|
|
#define CCM_CCGR5_CG8_MASK (0x30000U)
|
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#define CCM_CCGR5_CG8_SHIFT (16U)
|
|
#define CCM_CCGR5_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG8_SHIFT)) & CCM_CCGR5_CG8_MASK)
|
|
#define CCM_CCGR5_CG9_MASK (0xC0000U)
|
|
#define CCM_CCGR5_CG9_SHIFT (18U)
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#define CCM_CCGR5_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG9_SHIFT)) & CCM_CCGR5_CG9_MASK)
|
|
#define CCM_CCGR5_CG10_MASK (0x300000U)
|
|
#define CCM_CCGR5_CG10_SHIFT (20U)
|
|
#define CCM_CCGR5_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG10_SHIFT)) & CCM_CCGR5_CG10_MASK)
|
|
#define CCM_CCGR5_CG11_MASK (0xC00000U)
|
|
#define CCM_CCGR5_CG11_SHIFT (22U)
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|
#define CCM_CCGR5_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG11_SHIFT)) & CCM_CCGR5_CG11_MASK)
|
|
#define CCM_CCGR5_CG12_MASK (0x3000000U)
|
|
#define CCM_CCGR5_CG12_SHIFT (24U)
|
|
#define CCM_CCGR5_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG12_SHIFT)) & CCM_CCGR5_CG12_MASK)
|
|
#define CCM_CCGR5_CG13_MASK (0xC000000U)
|
|
#define CCM_CCGR5_CG13_SHIFT (26U)
|
|
#define CCM_CCGR5_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG13_SHIFT)) & CCM_CCGR5_CG13_MASK)
|
|
#define CCM_CCGR5_CG14_MASK (0x30000000U)
|
|
#define CCM_CCGR5_CG14_SHIFT (28U)
|
|
#define CCM_CCGR5_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG14_SHIFT)) & CCM_CCGR5_CG14_MASK)
|
|
#define CCM_CCGR5_CG15_MASK (0xC0000000U)
|
|
#define CCM_CCGR5_CG15_SHIFT (30U)
|
|
#define CCM_CCGR5_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG15_SHIFT)) & CCM_CCGR5_CG15_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CCGR6 - CCM Clock Gating Register 6 */
|
|
/*! @{ */
|
|
#define CCM_CCGR6_CG0_MASK (0x3U)
|
|
#define CCM_CCGR6_CG0_SHIFT (0U)
|
|
#define CCM_CCGR6_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG0_SHIFT)) & CCM_CCGR6_CG0_MASK)
|
|
#define CCM_CCGR6_CG1_MASK (0xCU)
|
|
#define CCM_CCGR6_CG1_SHIFT (2U)
|
|
#define CCM_CCGR6_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG1_SHIFT)) & CCM_CCGR6_CG1_MASK)
|
|
#define CCM_CCGR6_CG2_MASK (0x30U)
|
|
#define CCM_CCGR6_CG2_SHIFT (4U)
|
|
#define CCM_CCGR6_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG2_SHIFT)) & CCM_CCGR6_CG2_MASK)
|
|
#define CCM_CCGR6_CG3_MASK (0xC0U)
|
|
#define CCM_CCGR6_CG3_SHIFT (6U)
|
|
#define CCM_CCGR6_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG3_SHIFT)) & CCM_CCGR6_CG3_MASK)
|
|
#define CCM_CCGR6_CG4_MASK (0x300U)
|
|
#define CCM_CCGR6_CG4_SHIFT (8U)
|
|
#define CCM_CCGR6_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG4_SHIFT)) & CCM_CCGR6_CG4_MASK)
|
|
#define CCM_CCGR6_CG5_MASK (0xC00U)
|
|
#define CCM_CCGR6_CG5_SHIFT (10U)
|
|
#define CCM_CCGR6_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG5_SHIFT)) & CCM_CCGR6_CG5_MASK)
|
|
#define CCM_CCGR6_CG6_MASK (0x3000U)
|
|
#define CCM_CCGR6_CG6_SHIFT (12U)
|
|
#define CCM_CCGR6_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG6_SHIFT)) & CCM_CCGR6_CG6_MASK)
|
|
#define CCM_CCGR6_CG7_MASK (0xC000U)
|
|
#define CCM_CCGR6_CG7_SHIFT (14U)
|
|
#define CCM_CCGR6_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG7_SHIFT)) & CCM_CCGR6_CG7_MASK)
|
|
#define CCM_CCGR6_CG8_MASK (0x30000U)
|
|
#define CCM_CCGR6_CG8_SHIFT (16U)
|
|
#define CCM_CCGR6_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG8_SHIFT)) & CCM_CCGR6_CG8_MASK)
|
|
#define CCM_CCGR6_CG9_MASK (0xC0000U)
|
|
#define CCM_CCGR6_CG9_SHIFT (18U)
|
|
#define CCM_CCGR6_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG9_SHIFT)) & CCM_CCGR6_CG9_MASK)
|
|
#define CCM_CCGR6_CG10_MASK (0x300000U)
|
|
#define CCM_CCGR6_CG10_SHIFT (20U)
|
|
#define CCM_CCGR6_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG10_SHIFT)) & CCM_CCGR6_CG10_MASK)
|
|
#define CCM_CCGR6_CG11_MASK (0xC00000U)
|
|
#define CCM_CCGR6_CG11_SHIFT (22U)
|
|
#define CCM_CCGR6_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG11_SHIFT)) & CCM_CCGR6_CG11_MASK)
|
|
#define CCM_CCGR6_CG12_MASK (0x3000000U)
|
|
#define CCM_CCGR6_CG12_SHIFT (24U)
|
|
#define CCM_CCGR6_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG12_SHIFT)) & CCM_CCGR6_CG12_MASK)
|
|
#define CCM_CCGR6_CG13_MASK (0xC000000U)
|
|
#define CCM_CCGR6_CG13_SHIFT (26U)
|
|
#define CCM_CCGR6_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG13_SHIFT)) & CCM_CCGR6_CG13_MASK)
|
|
#define CCM_CCGR6_CG14_MASK (0x30000000U)
|
|
#define CCM_CCGR6_CG14_SHIFT (28U)
|
|
#define CCM_CCGR6_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG14_SHIFT)) & CCM_CCGR6_CG14_MASK)
|
|
#define CCM_CCGR6_CG15_MASK (0xC0000000U)
|
|
#define CCM_CCGR6_CG15_SHIFT (30U)
|
|
#define CCM_CCGR6_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG15_SHIFT)) & CCM_CCGR6_CG15_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CMEOR - CCM Module Enable Overide Register */
|
|
/*! @{ */
|
|
#define CCM_CMEOR_MOD_EN_OV_GPT_MASK (0x20U)
|
|
#define CCM_CMEOR_MOD_EN_OV_GPT_SHIFT (5U)
|
|
/*! MOD_EN_OV_GPT
|
|
* 0b0..don't override module enable signal
|
|
* 0b1..override module enable signal
|
|
*/
|
|
#define CCM_CMEOR_MOD_EN_OV_GPT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_GPT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_GPT_MASK)
|
|
#define CCM_CMEOR_MOD_EN_OV_PIT_MASK (0x40U)
|
|
#define CCM_CMEOR_MOD_EN_OV_PIT_SHIFT (6U)
|
|
/*! MOD_EN_OV_PIT
|
|
* 0b0..don't override module enable signal
|
|
* 0b1..override module enable signal
|
|
*/
|
|
#define CCM_CMEOR_MOD_EN_OV_PIT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_PIT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_PIT_MASK)
|
|
#define CCM_CMEOR_MOD_EN_USDHC_MASK (0x80U)
|
|
#define CCM_CMEOR_MOD_EN_USDHC_SHIFT (7U)
|
|
/*! MOD_EN_USDHC
|
|
* 0b0..don't override module enable signal
|
|
* 0b1..override module enable signal
|
|
*/
|
|
#define CCM_CMEOR_MOD_EN_USDHC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_USDHC_SHIFT)) & CCM_CMEOR_MOD_EN_USDHC_MASK)
|
|
#define CCM_CMEOR_MOD_EN_OV_TRNG_MASK (0x200U)
|
|
#define CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT (9U)
|
|
/*! MOD_EN_OV_TRNG
|
|
* 0b0..don't override module enable signal
|
|
* 0b1..override module enable signal
|
|
*/
|
|
#define CCM_CMEOR_MOD_EN_OV_TRNG(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT)) & CCM_CMEOR_MOD_EN_OV_TRNG_MASK)
|
|
#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK (0x10000000U)
|
|
#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT (28U)
|
|
/*! MOD_EN_OV_CAN2_CPI
|
|
* 0b0..don't override module enable signal
|
|
* 0b1..override module enable signal
|
|
*/
|
|
#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK)
|
|
#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK (0x40000000U)
|
|
#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT (30U)
|
|
/*! MOD_EN_OV_CAN1_CPI
|
|
* 0b0..don't overide module enable signal
|
|
* 0b1..overide module enable signal
|
|
*/
|
|
#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group CCM_Register_Masks */
|
|
|
|
|
|
/* CCM - Peripheral instance base addresses */
|
|
/** Peripheral CCM base address */
|
|
#define CCM_BASE (0x400FC000u)
|
|
/** Peripheral CCM base pointer */
|
|
#define CCM ((CCM_Type *)CCM_BASE)
|
|
/** Array initializer of CCM peripheral base addresses */
|
|
#define CCM_BASE_ADDRS { CCM_BASE }
|
|
/** Array initializer of CCM peripheral base pointers */
|
|
#define CCM_BASE_PTRS { CCM }
|
|
/** Interrupt vectors for the CCM peripheral type */
|
|
#define CCM_IRQS { CCM_1_IRQn, CCM_2_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group CCM_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- CCM_ANALOG Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup CCM_ANALOG_Peripheral_Access_Layer CCM_ANALOG Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** CCM_ANALOG - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t PLL_ARM; /**< Analog ARM PLL control Register, offset: 0x0 */
|
|
__IO uint32_t PLL_ARM_SET; /**< Analog ARM PLL control Register, offset: 0x4 */
|
|
__IO uint32_t PLL_ARM_CLR; /**< Analog ARM PLL control Register, offset: 0x8 */
|
|
__IO uint32_t PLL_ARM_TOG; /**< Analog ARM PLL control Register, offset: 0xC */
|
|
__IO uint32_t PLL_USB1; /**< Analog USB1 480MHz PLL Control Register, offset: 0x10 */
|
|
__IO uint32_t PLL_USB1_SET; /**< Analog USB1 480MHz PLL Control Register, offset: 0x14 */
|
|
__IO uint32_t PLL_USB1_CLR; /**< Analog USB1 480MHz PLL Control Register, offset: 0x18 */
|
|
__IO uint32_t PLL_USB1_TOG; /**< Analog USB1 480MHz PLL Control Register, offset: 0x1C */
|
|
__IO uint32_t PLL_USB2; /**< Analog USB2 480MHz PLL Control Register, offset: 0x20 */
|
|
__IO uint32_t PLL_USB2_SET; /**< Analog USB2 480MHz PLL Control Register, offset: 0x24 */
|
|
__IO uint32_t PLL_USB2_CLR; /**< Analog USB2 480MHz PLL Control Register, offset: 0x28 */
|
|
__IO uint32_t PLL_USB2_TOG; /**< Analog USB2 480MHz PLL Control Register, offset: 0x2C */
|
|
__IO uint32_t PLL_SYS; /**< Analog System PLL Control Register, offset: 0x30 */
|
|
__IO uint32_t PLL_SYS_SET; /**< Analog System PLL Control Register, offset: 0x34 */
|
|
__IO uint32_t PLL_SYS_CLR; /**< Analog System PLL Control Register, offset: 0x38 */
|
|
__IO uint32_t PLL_SYS_TOG; /**< Analog System PLL Control Register, offset: 0x3C */
|
|
__IO uint32_t PLL_SYS_SS; /**< 528MHz System PLL Spread Spectrum Register, offset: 0x40 */
|
|
uint8_t RESERVED_0[12];
|
|
__IO uint32_t PLL_SYS_NUM; /**< Numerator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x50 */
|
|
uint8_t RESERVED_1[12];
|
|
__IO uint32_t PLL_SYS_DENOM; /**< Denominator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x60 */
|
|
uint8_t RESERVED_2[12];
|
|
__IO uint32_t PLL_AUDIO; /**< Analog Audio PLL control Register, offset: 0x70 */
|
|
__IO uint32_t PLL_AUDIO_SET; /**< Analog Audio PLL control Register, offset: 0x74 */
|
|
__IO uint32_t PLL_AUDIO_CLR; /**< Analog Audio PLL control Register, offset: 0x78 */
|
|
__IO uint32_t PLL_AUDIO_TOG; /**< Analog Audio PLL control Register, offset: 0x7C */
|
|
__IO uint32_t PLL_AUDIO_NUM; /**< Numerator of Audio PLL Fractional Loop Divider Register, offset: 0x80 */
|
|
uint8_t RESERVED_3[12];
|
|
__IO uint32_t PLL_AUDIO_DENOM; /**< Denominator of Audio PLL Fractional Loop Divider Register, offset: 0x90 */
|
|
uint8_t RESERVED_4[12];
|
|
__IO uint32_t PLL_VIDEO; /**< Analog Video PLL control Register, offset: 0xA0 */
|
|
__IO uint32_t PLL_VIDEO_SET; /**< Analog Video PLL control Register, offset: 0xA4 */
|
|
__IO uint32_t PLL_VIDEO_CLR; /**< Analog Video PLL control Register, offset: 0xA8 */
|
|
__IO uint32_t PLL_VIDEO_TOG; /**< Analog Video PLL control Register, offset: 0xAC */
|
|
__IO uint32_t PLL_VIDEO_NUM; /**< Numerator of Video PLL Fractional Loop Divider Register, offset: 0xB0 */
|
|
uint8_t RESERVED_5[12];
|
|
__IO uint32_t PLL_VIDEO_DENOM; /**< Denominator of Video PLL Fractional Loop Divider Register, offset: 0xC0 */
|
|
uint8_t RESERVED_6[28];
|
|
__IO uint32_t PLL_ENET; /**< Analog ENET PLL Control Register, offset: 0xE0 */
|
|
__IO uint32_t PLL_ENET_SET; /**< Analog ENET PLL Control Register, offset: 0xE4 */
|
|
__IO uint32_t PLL_ENET_CLR; /**< Analog ENET PLL Control Register, offset: 0xE8 */
|
|
__IO uint32_t PLL_ENET_TOG; /**< Analog ENET PLL Control Register, offset: 0xEC */
|
|
__IO uint32_t PFD_480; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF0 */
|
|
__IO uint32_t PFD_480_SET; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF4 */
|
|
__IO uint32_t PFD_480_CLR; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF8 */
|
|
__IO uint32_t PFD_480_TOG; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xFC */
|
|
__IO uint32_t PFD_528; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x100 */
|
|
__IO uint32_t PFD_528_SET; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x104 */
|
|
__IO uint32_t PFD_528_CLR; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x108 */
|
|
__IO uint32_t PFD_528_TOG; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x10C */
|
|
uint8_t RESERVED_7[64];
|
|
__IO uint32_t MISC0; /**< Miscellaneous Register 0, offset: 0x150 */
|
|
__IO uint32_t MISC0_SET; /**< Miscellaneous Register 0, offset: 0x154 */
|
|
__IO uint32_t MISC0_CLR; /**< Miscellaneous Register 0, offset: 0x158 */
|
|
__IO uint32_t MISC0_TOG; /**< Miscellaneous Register 0, offset: 0x15C */
|
|
__IO uint32_t MISC1; /**< Miscellaneous Register 1, offset: 0x160 */
|
|
__IO uint32_t MISC1_SET; /**< Miscellaneous Register 1, offset: 0x164 */
|
|
__IO uint32_t MISC1_CLR; /**< Miscellaneous Register 1, offset: 0x168 */
|
|
__IO uint32_t MISC1_TOG; /**< Miscellaneous Register 1, offset: 0x16C */
|
|
__IO uint32_t MISC2; /**< Miscellaneous Register 2, offset: 0x170 */
|
|
__IO uint32_t MISC2_SET; /**< Miscellaneous Register 2, offset: 0x174 */
|
|
__IO uint32_t MISC2_CLR; /**< Miscellaneous Register 2, offset: 0x178 */
|
|
__IO uint32_t MISC2_TOG; /**< Miscellaneous Register 2, offset: 0x17C */
|
|
} CCM_ANALOG_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- CCM_ANALOG Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup CCM_ANALOG_Register_Masks CCM_ANALOG Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name PLL_ARM - Analog ARM PLL control Register */
|
|
/*! @{ */
|
|
#define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK (0x7FU)
|
|
#define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT (0U)
|
|
#define CCM_ANALOG_PLL_ARM_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK)
|
|
#define CCM_ANALOG_PLL_ARM_POWERDOWN_MASK (0x1000U)
|
|
#define CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT (12U)
|
|
#define CCM_ANALOG_PLL_ARM_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_POWERDOWN_MASK)
|
|
#define CCM_ANALOG_PLL_ARM_ENABLE_MASK (0x2000U)
|
|
#define CCM_ANALOG_PLL_ARM_ENABLE_SHIFT (13U)
|
|
#define CCM_ANALOG_PLL_ARM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_ENABLE_MASK)
|
|
#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK (0xC000U)
|
|
#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT (14U)
|
|
/*! BYPASS_CLK_SRC
|
|
* 0b00..Select the 24MHz oscillator as source.
|
|
* 0b01..Select the CLK1_N / CLK1_P as source.
|
|
* 0b10..Reserved1
|
|
* 0b11..Reserved2
|
|
*/
|
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#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK)
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#define CCM_ANALOG_PLL_ARM_BYPASS_MASK (0x10000U)
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#define CCM_ANALOG_PLL_ARM_BYPASS_SHIFT (16U)
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#define CCM_ANALOG_PLL_ARM_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_MASK)
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#define CCM_ANALOG_PLL_ARM_PLL_SEL_MASK (0x80000U)
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#define CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT (19U)
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#define CCM_ANALOG_PLL_ARM_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_PLL_SEL_MASK)
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#define CCM_ANALOG_PLL_ARM_LOCK_MASK (0x80000000U)
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#define CCM_ANALOG_PLL_ARM_LOCK_SHIFT (31U)
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#define CCM_ANALOG_PLL_ARM_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_LOCK_MASK)
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/*! @} */
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/*! @name PLL_ARM_SET - Analog ARM PLL control Register */
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/*! @{ */
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#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK (0x7FU)
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#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT (0U)
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#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK (0x1000U)
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#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT (12U)
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#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK)
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#define CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK (0x2000U)
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#define CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT (13U)
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#define CCM_ANALOG_PLL_ARM_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK)
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#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK (0xC000U)
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#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT (14U)
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/*! BYPASS_CLK_SRC
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* 0b00..Select the 24MHz oscillator as source.
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* 0b01..Select the CLK1_N / CLK1_P as source.
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* 0b10..Reserved1
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* 0b11..Reserved2
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*/
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#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK)
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#define CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK (0x10000U)
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#define CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT (16U)
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#define CCM_ANALOG_PLL_ARM_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK)
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#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK (0x80000U)
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#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT (19U)
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#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK)
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#define CCM_ANALOG_PLL_ARM_SET_LOCK_MASK (0x80000000U)
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#define CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT (31U)
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#define CCM_ANALOG_PLL_ARM_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_LOCK_MASK)
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/*! @} */
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/*! @name PLL_ARM_CLR - Analog ARM PLL control Register */
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/*! @{ */
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#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK (0x7FU)
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#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT (0U)
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#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK (0x1000U)
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#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT (12U)
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#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK)
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#define CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK (0x2000U)
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#define CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT (13U)
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#define CCM_ANALOG_PLL_ARM_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK)
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#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
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#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT (14U)
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/*! BYPASS_CLK_SRC
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* 0b00..Select the 24MHz oscillator as source.
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* 0b01..Select the CLK1_N / CLK1_P as source.
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* 0b10..Reserved1
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* 0b11..Reserved2
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*/
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#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK)
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#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK (0x10000U)
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#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT (16U)
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#define CCM_ANALOG_PLL_ARM_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK)
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#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK (0x80000U)
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#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT (19U)
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#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK)
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#define CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK (0x80000000U)
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#define CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT (31U)
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#define CCM_ANALOG_PLL_ARM_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK)
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/*! @} */
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/*! @name PLL_ARM_TOG - Analog ARM PLL control Register */
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/*! @{ */
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#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK (0x7FU)
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#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT (0U)
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#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK (0x1000U)
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#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT (12U)
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#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK)
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#define CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK (0x2000U)
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#define CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT (13U)
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#define CCM_ANALOG_PLL_ARM_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK)
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#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
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#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT (14U)
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/*! BYPASS_CLK_SRC
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* 0b00..Select the 24MHz oscillator as source.
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* 0b01..Select the CLK1_N / CLK1_P as source.
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* 0b10..Reserved1
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* 0b11..Reserved2
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*/
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#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK)
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#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK (0x10000U)
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#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT (16U)
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#define CCM_ANALOG_PLL_ARM_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK)
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#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK (0x80000U)
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#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT (19U)
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#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK)
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#define CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK (0x80000000U)
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#define CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT (31U)
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#define CCM_ANALOG_PLL_ARM_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK)
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/*! @} */
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/*! @name PLL_USB1 - Analog USB1 480MHz PLL Control Register */
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/*! @{ */
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#define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x2U)
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#define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (1U)
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#define CCM_ANALOG_PLL_USB1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK (0x40U)
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#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT (6U)
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/*! EN_USB_CLKS
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* 0b0..PLL outputs for USBPHYn off.
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* 0b1..PLL outputs for USBPHYn on.
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*/
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#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK)
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#define CCM_ANALOG_PLL_USB1_POWER_MASK (0x1000U)
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#define CCM_ANALOG_PLL_USB1_POWER_SHIFT (12U)
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#define CCM_ANALOG_PLL_USB1_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_POWER_MASK)
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#define CCM_ANALOG_PLL_USB1_ENABLE_MASK (0x2000U)
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#define CCM_ANALOG_PLL_USB1_ENABLE_SHIFT (13U)
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#define CCM_ANALOG_PLL_USB1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_ENABLE_MASK)
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#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0xC000U)
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#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14U)
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/*! BYPASS_CLK_SRC
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* 0b00..Select the 24MHz oscillator as source.
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* 0b01..Select the CLK1_N / CLK1_P as source.
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*/
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#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK)
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#define CCM_ANALOG_PLL_USB1_BYPASS_MASK (0x10000U)
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#define CCM_ANALOG_PLL_USB1_BYPASS_SHIFT (16U)
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#define CCM_ANALOG_PLL_USB1_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_MASK)
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#define CCM_ANALOG_PLL_USB1_LOCK_MASK (0x80000000U)
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#define CCM_ANALOG_PLL_USB1_LOCK_SHIFT (31U)
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#define CCM_ANALOG_PLL_USB1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_LOCK_MASK)
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/*! @} */
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/*! @name PLL_USB1_SET - Analog USB1 480MHz PLL Control Register */
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/*! @{ */
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#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK (0x2U)
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#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT (1U)
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#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK (0x40U)
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#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT (6U)
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/*! EN_USB_CLKS
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* 0b0..PLL outputs for USBPHYn off.
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* 0b1..PLL outputs for USBPHYn on.
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*/
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#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK)
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#define CCM_ANALOG_PLL_USB1_SET_POWER_MASK (0x1000U)
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#define CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT (12U)
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#define CCM_ANALOG_PLL_USB1_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_POWER_MASK)
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#define CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK (0x2000U)
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#define CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT (13U)
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#define CCM_ANALOG_PLL_USB1_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK)
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#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK (0xC000U)
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#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT (14U)
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/*! BYPASS_CLK_SRC
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|
* 0b00..Select the 24MHz oscillator as source.
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* 0b01..Select the CLK1_N / CLK1_P as source.
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|
*/
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#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK)
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#define CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK (0x10000U)
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#define CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT (16U)
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#define CCM_ANALOG_PLL_USB1_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK)
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#define CCM_ANALOG_PLL_USB1_SET_LOCK_MASK (0x80000000U)
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#define CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT (31U)
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#define CCM_ANALOG_PLL_USB1_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_LOCK_MASK)
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/*! @} */
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/*! @name PLL_USB1_CLR - Analog USB1 480MHz PLL Control Register */
|
|
/*! @{ */
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|
#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK (0x2U)
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#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT (1U)
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#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK (0x40U)
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#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT (6U)
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/*! EN_USB_CLKS
|
|
* 0b0..PLL outputs for USBPHYn off.
|
|
* 0b1..PLL outputs for USBPHYn on.
|
|
*/
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|
#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK)
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|
#define CCM_ANALOG_PLL_USB1_CLR_POWER_MASK (0x1000U)
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|
#define CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT (12U)
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|
#define CCM_ANALOG_PLL_USB1_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_POWER_MASK)
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|
#define CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK (0x2000U)
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|
#define CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT (13U)
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|
#define CCM_ANALOG_PLL_USB1_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK)
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|
#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
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|
#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT (14U)
|
|
/*! BYPASS_CLK_SRC
|
|
* 0b00..Select the 24MHz oscillator as source.
|
|
* 0b01..Select the CLK1_N / CLK1_P as source.
|
|
*/
|
|
#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK)
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|
#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK (0x10000U)
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|
#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT (16U)
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|
#define CCM_ANALOG_PLL_USB1_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK)
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|
#define CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK (0x80000000U)
|
|
#define CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT (31U)
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|
#define CCM_ANALOG_PLL_USB1_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PLL_USB1_TOG - Analog USB1 480MHz PLL Control Register */
|
|
/*! @{ */
|
|
#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK (0x2U)
|
|
#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT (1U)
|
|
#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK)
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|
#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK (0x40U)
|
|
#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT (6U)
|
|
/*! EN_USB_CLKS
|
|
* 0b0..PLL outputs for USBPHYn off.
|
|
* 0b1..PLL outputs for USBPHYn on.
|
|
*/
|
|
#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK)
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#define CCM_ANALOG_PLL_USB1_TOG_POWER_MASK (0x1000U)
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#define CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT (12U)
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#define CCM_ANALOG_PLL_USB1_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_POWER_MASK)
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#define CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK (0x2000U)
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#define CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT (13U)
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#define CCM_ANALOG_PLL_USB1_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK)
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#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
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#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT (14U)
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/*! BYPASS_CLK_SRC
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* 0b00..Select the 24MHz oscillator as source.
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* 0b01..Select the CLK1_N / CLK1_P as source.
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*/
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#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK)
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#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK (0x10000U)
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#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT (16U)
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#define CCM_ANALOG_PLL_USB1_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK)
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#define CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK (0x80000000U)
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#define CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT (31U)
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#define CCM_ANALOG_PLL_USB1_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK)
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/*! @} */
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/*! @name PLL_USB2 - Analog USB2 480MHz PLL Control Register */
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/*! @{ */
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#define CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK (0x2U)
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#define CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT (1U)
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#define CCM_ANALOG_PLL_USB2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK (0x40U)
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#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT (6U)
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#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK)
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#define CCM_ANALOG_PLL_USB2_POWER_MASK (0x1000U)
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#define CCM_ANALOG_PLL_USB2_POWER_SHIFT (12U)
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#define CCM_ANALOG_PLL_USB2_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_POWER_MASK)
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#define CCM_ANALOG_PLL_USB2_ENABLE_MASK (0x2000U)
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#define CCM_ANALOG_PLL_USB2_ENABLE_SHIFT (13U)
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#define CCM_ANALOG_PLL_USB2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_ENABLE_MASK)
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#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK (0xC000U)
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#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT (14U)
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/*! BYPASS_CLK_SRC
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* 0b00..Select the 24MHz oscillator as source.
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* 0b01..Select the CLK1_N / CLK1_P as source.
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* 0b10..Reserved1
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* 0b11..Reserved2
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*/
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#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK)
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#define CCM_ANALOG_PLL_USB2_BYPASS_MASK (0x10000U)
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#define CCM_ANALOG_PLL_USB2_BYPASS_SHIFT (16U)
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#define CCM_ANALOG_PLL_USB2_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_MASK)
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#define CCM_ANALOG_PLL_USB2_LOCK_MASK (0x80000000U)
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#define CCM_ANALOG_PLL_USB2_LOCK_SHIFT (31U)
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#define CCM_ANALOG_PLL_USB2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_LOCK_MASK)
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/*! @} */
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/*! @name PLL_USB2_SET - Analog USB2 480MHz PLL Control Register */
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/*! @{ */
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#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK (0x2U)
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#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT (1U)
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#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK (0x40U)
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#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT (6U)
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#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK)
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#define CCM_ANALOG_PLL_USB2_SET_POWER_MASK (0x1000U)
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#define CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT (12U)
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#define CCM_ANALOG_PLL_USB2_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_POWER_MASK)
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#define CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK (0x2000U)
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#define CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT (13U)
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#define CCM_ANALOG_PLL_USB2_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK)
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#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK (0xC000U)
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#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT (14U)
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/*! BYPASS_CLK_SRC
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* 0b00..Select the 24MHz oscillator as source.
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* 0b01..Select the CLK1_N / CLK1_P as source.
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* 0b10..Reserved1
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* 0b11..Reserved2
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*/
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#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK)
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#define CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK (0x10000U)
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#define CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT (16U)
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#define CCM_ANALOG_PLL_USB2_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK)
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#define CCM_ANALOG_PLL_USB2_SET_LOCK_MASK (0x80000000U)
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#define CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT (31U)
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#define CCM_ANALOG_PLL_USB2_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_LOCK_MASK)
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/*! @} */
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/*! @name PLL_USB2_CLR - Analog USB2 480MHz PLL Control Register */
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/*! @{ */
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#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK (0x2U)
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#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT (1U)
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#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK (0x40U)
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#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT (6U)
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#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK)
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#define CCM_ANALOG_PLL_USB2_CLR_POWER_MASK (0x1000U)
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#define CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT (12U)
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#define CCM_ANALOG_PLL_USB2_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_POWER_MASK)
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#define CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK (0x2000U)
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#define CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT (13U)
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#define CCM_ANALOG_PLL_USB2_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK)
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#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
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#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT (14U)
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/*! BYPASS_CLK_SRC
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* 0b00..Select the 24MHz oscillator as source.
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* 0b01..Select the CLK1_N / CLK1_P as source.
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* 0b10..Reserved1
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* 0b11..Reserved2
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*/
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#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK)
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#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK (0x10000U)
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#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT (16U)
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#define CCM_ANALOG_PLL_USB2_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK)
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#define CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK (0x80000000U)
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#define CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT (31U)
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#define CCM_ANALOG_PLL_USB2_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK)
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/*! @} */
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/*! @name PLL_USB2_TOG - Analog USB2 480MHz PLL Control Register */
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/*! @{ */
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#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK (0x2U)
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#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT (1U)
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#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK (0x40U)
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#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT (6U)
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#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK)
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#define CCM_ANALOG_PLL_USB2_TOG_POWER_MASK (0x1000U)
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#define CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT (12U)
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#define CCM_ANALOG_PLL_USB2_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_POWER_MASK)
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#define CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK (0x2000U)
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#define CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT (13U)
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#define CCM_ANALOG_PLL_USB2_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK)
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#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
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#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT (14U)
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/*! BYPASS_CLK_SRC
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* 0b00..Select the 24MHz oscillator as source.
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* 0b01..Select the CLK1_N / CLK1_P as source.
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* 0b10..Reserved1
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* 0b11..Reserved2
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*/
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#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK)
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#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK (0x10000U)
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#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT (16U)
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#define CCM_ANALOG_PLL_USB2_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK)
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#define CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK (0x80000000U)
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#define CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT (31U)
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#define CCM_ANALOG_PLL_USB2_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK)
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/*! @} */
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/*! @name PLL_SYS - Analog System PLL Control Register */
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/*! @{ */
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#define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x1U)
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#define CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0U)
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#define CCM_ANALOG_PLL_SYS_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_SYS_POWERDOWN_MASK (0x1000U)
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#define CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT (12U)
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#define CCM_ANALOG_PLL_SYS_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_POWERDOWN_MASK)
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#define CCM_ANALOG_PLL_SYS_ENABLE_MASK (0x2000U)
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#define CCM_ANALOG_PLL_SYS_ENABLE_SHIFT (13U)
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#define CCM_ANALOG_PLL_SYS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_ENABLE_MASK)
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#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0xC000U)
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#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14U)
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/*! BYPASS_CLK_SRC
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* 0b00..Select the 24MHz oscillator as source.
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* 0b01..Select the CLK1_N / CLK1_P as source.
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*/
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#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK)
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#define CCM_ANALOG_PLL_SYS_BYPASS_MASK (0x10000U)
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#define CCM_ANALOG_PLL_SYS_BYPASS_SHIFT (16U)
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#define CCM_ANALOG_PLL_SYS_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_MASK)
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#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK (0x40000U)
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#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_SHIFT (18U)
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#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK)
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#define CCM_ANALOG_PLL_SYS_LOCK_MASK (0x80000000U)
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#define CCM_ANALOG_PLL_SYS_LOCK_SHIFT (31U)
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#define CCM_ANALOG_PLL_SYS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_LOCK_MASK)
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/*! @} */
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/*! @name PLL_SYS_SET - Analog System PLL Control Register */
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/*! @{ */
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#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK (0x1U)
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#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT (0U)
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#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK (0x1000U)
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#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT (12U)
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#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK)
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#define CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK (0x2000U)
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#define CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT (13U)
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#define CCM_ANALOG_PLL_SYS_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK)
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#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK (0xC000U)
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#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT (14U)
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/*! BYPASS_CLK_SRC
|
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* 0b00..Select the 24MHz oscillator as source.
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* 0b01..Select the CLK1_N / CLK1_P as source.
|
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*/
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#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK)
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#define CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK (0x10000U)
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#define CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT (16U)
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#define CCM_ANALOG_PLL_SYS_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK)
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#define CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_MASK (0x40000U)
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#define CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_SHIFT (18U)
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#define CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_MASK)
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#define CCM_ANALOG_PLL_SYS_SET_LOCK_MASK (0x80000000U)
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#define CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT (31U)
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#define CCM_ANALOG_PLL_SYS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_LOCK_MASK)
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/*! @} */
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/*! @name PLL_SYS_CLR - Analog System PLL Control Register */
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/*! @{ */
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#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK (0x1U)
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#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT (0U)
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#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK (0x1000U)
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#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT (12U)
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#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK)
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#define CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK (0x2000U)
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#define CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT (13U)
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#define CCM_ANALOG_PLL_SYS_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK)
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#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
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#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT (14U)
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/*! BYPASS_CLK_SRC
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* 0b00..Select the 24MHz oscillator as source.
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* 0b01..Select the CLK1_N / CLK1_P as source.
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*/
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#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK)
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#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK (0x10000U)
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#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT (16U)
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#define CCM_ANALOG_PLL_SYS_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK)
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#define CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_MASK (0x40000U)
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#define CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_SHIFT (18U)
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#define CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_MASK)
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#define CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK (0x80000000U)
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#define CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT (31U)
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#define CCM_ANALOG_PLL_SYS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK)
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/*! @} */
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/*! @name PLL_SYS_TOG - Analog System PLL Control Register */
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/*! @{ */
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#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK (0x1U)
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#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT (0U)
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#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK (0x1000U)
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#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT (12U)
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#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK)
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#define CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK (0x2000U)
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#define CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT (13U)
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#define CCM_ANALOG_PLL_SYS_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK)
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#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
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#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT (14U)
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/*! BYPASS_CLK_SRC
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* 0b00..Select the 24MHz oscillator as source.
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* 0b01..Select the CLK1_N / CLK1_P as source.
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*/
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#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK)
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#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK (0x10000U)
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#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT (16U)
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#define CCM_ANALOG_PLL_SYS_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK)
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#define CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_MASK (0x40000U)
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#define CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_SHIFT (18U)
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#define CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_MASK)
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#define CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK (0x80000000U)
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#define CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT (31U)
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#define CCM_ANALOG_PLL_SYS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK)
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/*! @} */
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/*! @name PLL_SYS_SS - 528MHz System PLL Spread Spectrum Register */
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/*! @{ */
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#define CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x7FFFU)
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#define CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0U)
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#define CCM_ANALOG_PLL_SYS_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STEP_MASK)
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#define CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK (0x8000U)
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#define CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT (15U)
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/*! ENABLE - Enable bit
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* 0b0..Spread spectrum modulation disabled
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* 0b1..Soread spectrum modulation enabled
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*/
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#define CCM_ANALOG_PLL_SYS_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK)
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#define CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF0000U)
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#define CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (16U)
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#define CCM_ANALOG_PLL_SYS_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STOP_MASK)
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/*! @} */
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/*! @name PLL_SYS_NUM - Numerator of 528MHz System PLL Fractional Loop Divider Register */
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/*! @{ */
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#define CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFFU)
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#define CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0U)
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#define CCM_ANALOG_PLL_SYS_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT)) & CCM_ANALOG_PLL_SYS_NUM_A_MASK)
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/*! @} */
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/*! @name PLL_SYS_DENOM - Denominator of 528MHz System PLL Fractional Loop Divider Register */
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/*! @{ */
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#define CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFFU)
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#define CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0U)
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#define CCM_ANALOG_PLL_SYS_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_SYS_DENOM_B_MASK)
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/*! @} */
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/*! @name PLL_AUDIO - Analog Audio PLL control Register */
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/*! @{ */
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#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7FU)
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#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0U)
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#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK (0x1000U)
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#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT (12U)
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#define CCM_ANALOG_PLL_AUDIO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK)
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#define CCM_ANALOG_PLL_AUDIO_ENABLE_MASK (0x2000U)
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#define CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT (13U)
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#define CCM_ANALOG_PLL_AUDIO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_ENABLE_MASK)
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#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0xC000U)
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#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14U)
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/*! BYPASS_CLK_SRC
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* 0b00..Select the 24MHz oscillator as source.
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* 0b01..Select the CLK1_N / CLK1_P as source.
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* 0b10..Reserved1
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* 0b11..Reserved2
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*/
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#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)
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#define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK (0x10000U)
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#define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT (16U)
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#define CCM_ANALOG_PLL_AUDIO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_MASK)
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#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK (0x40000U)
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#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT (18U)
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#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK)
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#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x180000U)
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#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19U)
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/*! POST_DIV_SELECT
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* 0b00..Divide by 4.
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* 0b01..Divide by 2.
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* 0b10..Divide by 1.
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* 0b11..Reserved
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*/
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#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_AUDIO_LOCK_MASK (0x80000000U)
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#define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT (31U)
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#define CCM_ANALOG_PLL_AUDIO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_LOCK_MASK)
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/*! @} */
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/*! @name PLL_AUDIO_SET - Analog Audio PLL control Register */
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/*! @{ */
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#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK (0x7FU)
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#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT (0U)
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#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK (0x1000U)
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#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT (12U)
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#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK)
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#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK (0x2000U)
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#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT (13U)
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#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK)
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#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK (0xC000U)
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#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT (14U)
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/*! BYPASS_CLK_SRC
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|
* 0b00..Select the 24MHz oscillator as source.
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* 0b01..Select the CLK1_N / CLK1_P as source.
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|
* 0b10..Reserved1
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* 0b11..Reserved2
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*/
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#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK)
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#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK (0x10000U)
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#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT (16U)
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#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK)
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#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK (0x40000U)
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#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT (18U)
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#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK)
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#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK (0x180000U)
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#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT (19U)
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/*! POST_DIV_SELECT
|
|
* 0b00..Divide by 4.
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* 0b01..Divide by 2.
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|
* 0b10..Divide by 1.
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|
* 0b11..Reserved
|
|
*/
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#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK (0x80000000U)
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#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT (31U)
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#define CCM_ANALOG_PLL_AUDIO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK)
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/*! @} */
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/*! @name PLL_AUDIO_CLR - Analog Audio PLL control Register */
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/*! @{ */
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#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK (0x7FU)
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#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT (0U)
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#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK (0x1000U)
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#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT (12U)
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#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK)
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#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK (0x2000U)
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#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT (13U)
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#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK)
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#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
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#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT (14U)
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/*! BYPASS_CLK_SRC
|
|
* 0b00..Select the 24MHz oscillator as source.
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|
* 0b01..Select the CLK1_N / CLK1_P as source.
|
|
* 0b10..Reserved1
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|
* 0b11..Reserved2
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*/
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#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK)
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#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK (0x10000U)
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#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT (16U)
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|
#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK)
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#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK (0x40000U)
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|
#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT (18U)
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|
#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK)
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#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK (0x180000U)
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|
#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT (19U)
|
|
/*! POST_DIV_SELECT
|
|
* 0b00..Divide by 4.
|
|
* 0b01..Divide by 2.
|
|
* 0b10..Divide by 1.
|
|
* 0b11..Reserved
|
|
*/
|
|
#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK)
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|
#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK (0x80000000U)
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|
#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT (31U)
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|
#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK)
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|
/*! @} */
|
|
|
|
/*! @name PLL_AUDIO_TOG - Analog Audio PLL control Register */
|
|
/*! @{ */
|
|
#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK (0x7FU)
|
|
#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT (0U)
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|
#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK)
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|
#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK (0x1000U)
|
|
#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT (12U)
|
|
#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK)
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|
#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK (0x2000U)
|
|
#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT (13U)
|
|
#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK)
|
|
#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
|
|
#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT (14U)
|
|
/*! BYPASS_CLK_SRC
|
|
* 0b00..Select the 24MHz oscillator as source.
|
|
* 0b01..Select the CLK1_N / CLK1_P as source.
|
|
* 0b10..Reserved1
|
|
* 0b11..Reserved2
|
|
*/
|
|
#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK)
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|
#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK (0x10000U)
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#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT (16U)
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#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK)
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#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK (0x40000U)
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#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT (18U)
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#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK)
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#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK (0x180000U)
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#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT (19U)
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/*! POST_DIV_SELECT
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* 0b00..Divide by 4.
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* 0b01..Divide by 2.
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* 0b10..Divide by 1.
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* 0b11..Reserved
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*/
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#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK (0x80000000U)
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#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT (31U)
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#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK)
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/*! @} */
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/*! @name PLL_AUDIO_NUM - Numerator of Audio PLL Fractional Loop Divider Register */
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/*! @{ */
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#define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK (0x3FFFFFFFU)
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#define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT (0U)
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#define CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_AUDIO_NUM_A_MASK)
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/*! @} */
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/*! @name PLL_AUDIO_DENOM - Denominator of Audio PLL Fractional Loop Divider Register */
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/*! @{ */
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#define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFFU)
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#define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT (0U)
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#define CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK)
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/*! @} */
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/*! @name PLL_VIDEO - Analog Video PLL control Register */
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/*! @{ */
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#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK (0x7FU)
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#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT (0U)
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#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK (0x1000U)
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#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT (12U)
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#define CCM_ANALOG_PLL_VIDEO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK)
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#define CCM_ANALOG_PLL_VIDEO_ENABLE_MASK (0x2000U)
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#define CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT (13U)
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#define CCM_ANALOG_PLL_VIDEO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_ENABLE_MASK)
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#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK (0xC000U)
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#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT (14U)
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/*! BYPASS_CLK_SRC
|
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* 0b00..Select the 24MHz oscillator as source.
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* 0b01..Select the CLK1_N / CLK1_P as source.
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* 0b10..Reserved1
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* 0b11..Reserved2
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*/
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#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)
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#define CCM_ANALOG_PLL_VIDEO_BYPASS_MASK (0x10000U)
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#define CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT (16U)
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#define CCM_ANALOG_PLL_VIDEO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_MASK)
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#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK (0x40000U)
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#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT (18U)
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#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK)
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#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK (0x180000U)
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#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT (19U)
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/*! POST_DIV_SELECT
|
|
* 0b00..Divide by 4.
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* 0b01..Divide by 2.
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* 0b10..Divide by 1.
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* 0b11..Reserved
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*/
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#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_VIDEO_LOCK_MASK (0x80000000U)
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#define CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT (31U)
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#define CCM_ANALOG_PLL_VIDEO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_LOCK_MASK)
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/*! @} */
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/*! @name PLL_VIDEO_SET - Analog Video PLL control Register */
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/*! @{ */
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#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK (0x7FU)
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#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT (0U)
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#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK (0x1000U)
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#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT (12U)
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#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK)
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#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK (0x2000U)
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#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT (13U)
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#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK)
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#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK (0xC000U)
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#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT (14U)
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/*! BYPASS_CLK_SRC
|
|
* 0b00..Select the 24MHz oscillator as source.
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* 0b01..Select the CLK1_N / CLK1_P as source.
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|
* 0b10..Reserved1
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|
* 0b11..Reserved2
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|
*/
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#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK)
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#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK (0x10000U)
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#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT (16U)
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#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK)
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#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK (0x40000U)
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#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT (18U)
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#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK)
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#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK (0x180000U)
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#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT (19U)
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/*! POST_DIV_SELECT
|
|
* 0b00..Divide by 4.
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* 0b01..Divide by 2.
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* 0b10..Divide by 1.
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|
* 0b11..Reserved
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*/
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#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK (0x80000000U)
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#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT (31U)
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#define CCM_ANALOG_PLL_VIDEO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK)
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/*! @} */
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/*! @name PLL_VIDEO_CLR - Analog Video PLL control Register */
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/*! @{ */
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#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK (0x7FU)
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#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT (0U)
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#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK (0x1000U)
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#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT (12U)
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#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK)
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#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK (0x2000U)
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#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT (13U)
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#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK)
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#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
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#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT (14U)
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/*! BYPASS_CLK_SRC
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|
* 0b00..Select the 24MHz oscillator as source.
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* 0b01..Select the CLK1_N / CLK1_P as source.
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|
* 0b10..Reserved1
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* 0b11..Reserved2
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*/
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#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK)
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#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK (0x10000U)
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#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT (16U)
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#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK)
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#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK (0x40000U)
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#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT (18U)
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#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK)
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#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK (0x180000U)
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#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT (19U)
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/*! POST_DIV_SELECT
|
|
* 0b00..Divide by 4.
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|
* 0b01..Divide by 2.
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|
* 0b10..Divide by 1.
|
|
* 0b11..Reserved
|
|
*/
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#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK (0x80000000U)
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#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT (31U)
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#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK)
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/*! @} */
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/*! @name PLL_VIDEO_TOG - Analog Video PLL control Register */
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/*! @{ */
|
|
#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK (0x7FU)
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#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT (0U)
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#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK (0x1000U)
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#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT (12U)
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#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK)
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#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK (0x2000U)
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#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT (13U)
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#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK)
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#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
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#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT (14U)
|
|
/*! BYPASS_CLK_SRC
|
|
* 0b00..Select the 24MHz oscillator as source.
|
|
* 0b01..Select the CLK1_N / CLK1_P as source.
|
|
* 0b10..Reserved1
|
|
* 0b11..Reserved2
|
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*/
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#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK)
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#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK (0x10000U)
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#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT (16U)
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|
#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK)
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#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK (0x40000U)
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#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT (18U)
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#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK)
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#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK (0x180000U)
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|
#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT (19U)
|
|
/*! POST_DIV_SELECT
|
|
* 0b00..Divide by 4.
|
|
* 0b01..Divide by 2.
|
|
* 0b10..Divide by 1.
|
|
* 0b11..Reserved
|
|
*/
|
|
#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK)
|
|
#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK (0x80000000U)
|
|
#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT (31U)
|
|
#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PLL_VIDEO_NUM - Numerator of Video PLL Fractional Loop Divider Register */
|
|
/*! @{ */
|
|
#define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK (0x3FFFFFFFU)
|
|
#define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT (0U)
|
|
#define CCM_ANALOG_PLL_VIDEO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_VIDEO_NUM_A_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PLL_VIDEO_DENOM - Denominator of Video PLL Fractional Loop Divider Register */
|
|
/*! @{ */
|
|
#define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK (0x3FFFFFFFU)
|
|
#define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT (0U)
|
|
#define CCM_ANALOG_PLL_VIDEO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PLL_ENET - Analog ENET PLL Control Register */
|
|
/*! @{ */
|
|
#define CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK (0x3U)
|
|
#define CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT (0U)
|
|
#define CCM_ANALOG_PLL_ENET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)
|
|
#define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK (0x1000U)
|
|
#define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT (12U)
|
|
#define CCM_ANALOG_PLL_ENET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK)
|
|
#define CCM_ANALOG_PLL_ENET_ENABLE_MASK (0x2000U)
|
|
#define CCM_ANALOG_PLL_ENET_ENABLE_SHIFT (13U)
|
|
#define CCM_ANALOG_PLL_ENET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_ENABLE_MASK)
|
|
#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0xC000U)
|
|
#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14U)
|
|
/*! BYPASS_CLK_SRC
|
|
* 0b00..Select the 24MHz oscillator as source.
|
|
* 0b01..Select the CLK1_N / CLK1_P as source.
|
|
* 0b10..Reserved1
|
|
* 0b11..Reserved2
|
|
*/
|
|
#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK)
|
|
#define CCM_ANALOG_PLL_ENET_BYPASS_MASK (0x10000U)
|
|
#define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT (16U)
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#define CCM_ANALOG_PLL_ENET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_MASK)
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#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK (0x40000U)
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#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT (18U)
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#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK)
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#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK (0x200000U)
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#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT (21U)
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#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK)
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#define CCM_ANALOG_PLL_ENET_LOCK_MASK (0x80000000U)
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#define CCM_ANALOG_PLL_ENET_LOCK_SHIFT (31U)
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#define CCM_ANALOG_PLL_ENET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_LOCK_MASK)
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/*! @} */
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/*! @name PLL_ENET_SET - Analog ENET PLL Control Register */
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/*! @{ */
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#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK (0x3U)
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#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT (0U)
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#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK (0x1000U)
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#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT (12U)
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#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK)
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#define CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK (0x2000U)
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#define CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT (13U)
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#define CCM_ANALOG_PLL_ENET_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK)
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#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK (0xC000U)
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#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT (14U)
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/*! BYPASS_CLK_SRC
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* 0b00..Select the 24MHz oscillator as source.
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* 0b01..Select the CLK1_N / CLK1_P as source.
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* 0b10..Reserved1
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* 0b11..Reserved2
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*/
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#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK)
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#define CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK (0x10000U)
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#define CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT (16U)
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#define CCM_ANALOG_PLL_ENET_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK)
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#define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK (0x40000U)
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#define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT (18U)
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#define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK)
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#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK (0x200000U)
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#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT (21U)
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#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK)
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#define CCM_ANALOG_PLL_ENET_SET_LOCK_MASK (0x80000000U)
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#define CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT (31U)
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#define CCM_ANALOG_PLL_ENET_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_LOCK_MASK)
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/*! @} */
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/*! @name PLL_ENET_CLR - Analog ENET PLL Control Register */
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/*! @{ */
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#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK (0x3U)
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#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT (0U)
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#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK (0x1000U)
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#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT (12U)
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#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK)
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#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK (0x2000U)
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#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT (13U)
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#define CCM_ANALOG_PLL_ENET_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK)
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#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
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#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT (14U)
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/*! BYPASS_CLK_SRC
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* 0b00..Select the 24MHz oscillator as source.
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* 0b01..Select the CLK1_N / CLK1_P as source.
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* 0b10..Reserved1
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* 0b11..Reserved2
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*/
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#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK)
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#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK (0x10000U)
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#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT (16U)
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#define CCM_ANALOG_PLL_ENET_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK)
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#define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK (0x40000U)
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#define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT (18U)
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#define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK)
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#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK (0x200000U)
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#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT (21U)
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#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK)
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#define CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK (0x80000000U)
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#define CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT (31U)
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#define CCM_ANALOG_PLL_ENET_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK)
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/*! @} */
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/*! @name PLL_ENET_TOG - Analog ENET PLL Control Register */
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/*! @{ */
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#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK (0x3U)
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#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT (0U)
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#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK)
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#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK (0x1000U)
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#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT (12U)
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#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK)
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#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK (0x2000U)
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#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT (13U)
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#define CCM_ANALOG_PLL_ENET_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK)
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#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
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#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT (14U)
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/*! BYPASS_CLK_SRC
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* 0b00..Select the 24MHz oscillator as source.
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* 0b01..Select the CLK1_N / CLK1_P as source.
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* 0b10..Reserved1
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* 0b11..Reserved2
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*/
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#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK)
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#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK (0x10000U)
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#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT (16U)
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#define CCM_ANALOG_PLL_ENET_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK)
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#define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK (0x40000U)
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#define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT (18U)
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#define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK)
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#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK (0x200000U)
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#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT (21U)
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#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK)
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#define CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK (0x80000000U)
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#define CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT (31U)
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#define CCM_ANALOG_PLL_ENET_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK)
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/*! @} */
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/*! @name PFD_480 - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */
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/*! @{ */
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#define CCM_ANALOG_PFD_480_PFD0_FRAC_MASK (0x3FU)
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#define CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT (0U)
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#define CCM_ANALOG_PFD_480_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK)
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#define CCM_ANALOG_PFD_480_PFD0_STABLE_MASK (0x40U)
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#define CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT (6U)
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#define CCM_ANALOG_PFD_480_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_STABLE_MASK)
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#define CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK (0x80U)
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#define CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT (7U)
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#define CCM_ANALOG_PFD_480_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK)
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#define CCM_ANALOG_PFD_480_PFD1_FRAC_MASK (0x3F00U)
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#define CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT (8U)
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#define CCM_ANALOG_PFD_480_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK)
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#define CCM_ANALOG_PFD_480_PFD1_STABLE_MASK (0x4000U)
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#define CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT (14U)
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#define CCM_ANALOG_PFD_480_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_STABLE_MASK)
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#define CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK (0x8000U)
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#define CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT (15U)
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#define CCM_ANALOG_PFD_480_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK)
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#define CCM_ANALOG_PFD_480_PFD2_FRAC_MASK (0x3F0000U)
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#define CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT (16U)
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#define CCM_ANALOG_PFD_480_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK)
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#define CCM_ANALOG_PFD_480_PFD2_STABLE_MASK (0x400000U)
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#define CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT (22U)
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#define CCM_ANALOG_PFD_480_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_STABLE_MASK)
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#define CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK (0x800000U)
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#define CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT (23U)
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#define CCM_ANALOG_PFD_480_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK)
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#define CCM_ANALOG_PFD_480_PFD3_FRAC_MASK (0x3F000000U)
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#define CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT (24U)
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#define CCM_ANALOG_PFD_480_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK)
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#define CCM_ANALOG_PFD_480_PFD3_STABLE_MASK (0x40000000U)
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#define CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT (30U)
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#define CCM_ANALOG_PFD_480_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_STABLE_MASK)
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#define CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK (0x80000000U)
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#define CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT (31U)
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#define CCM_ANALOG_PFD_480_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK)
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/*! @} */
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/*! @name PFD_480_SET - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */
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/*! @{ */
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#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK (0x3FU)
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#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT (0U)
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#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK)
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#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK (0x40U)
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#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT (6U)
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#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK)
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#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK (0x80U)
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#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT (7U)
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#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK)
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#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK (0x3F00U)
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#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT (8U)
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#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK)
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#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK (0x4000U)
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#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT (14U)
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#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK)
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#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK (0x8000U)
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#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT (15U)
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#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK)
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#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK (0x3F0000U)
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#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT (16U)
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#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK)
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#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK (0x400000U)
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#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT (22U)
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#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK)
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#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK (0x800000U)
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#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT (23U)
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#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK)
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#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK (0x3F000000U)
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#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT (24U)
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#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK)
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#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK (0x40000000U)
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#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT (30U)
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#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK)
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#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK (0x80000000U)
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#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT (31U)
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#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK)
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/*! @} */
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/*! @name PFD_480_CLR - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */
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/*! @{ */
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#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK (0x3FU)
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#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT (0U)
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#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK)
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#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK (0x40U)
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#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT (6U)
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#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK)
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#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK (0x80U)
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#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT (7U)
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#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK)
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#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK (0x3F00U)
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#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT (8U)
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#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK)
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#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK (0x4000U)
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#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT (14U)
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#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK)
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#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK (0x8000U)
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#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT (15U)
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#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK)
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#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK (0x3F0000U)
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#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT (16U)
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#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK)
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#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK (0x400000U)
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#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT (22U)
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#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK)
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#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK (0x800000U)
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#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT (23U)
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#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK)
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#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK (0x3F000000U)
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#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT (24U)
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#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK)
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#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK (0x40000000U)
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#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT (30U)
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#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK)
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#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK (0x80000000U)
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#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT (31U)
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#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK)
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/*! @} */
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/*! @name PFD_480_TOG - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */
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/*! @{ */
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#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK (0x3FU)
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#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT (0U)
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#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK)
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#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK (0x40U)
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#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT (6U)
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#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK)
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#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK (0x80U)
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#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT (7U)
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#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK)
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#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK (0x3F00U)
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#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT (8U)
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#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK)
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#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK (0x4000U)
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#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT (14U)
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#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK)
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#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK (0x8000U)
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#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT (15U)
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#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK)
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#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK (0x3F0000U)
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#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT (16U)
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#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK)
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#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK (0x400000U)
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#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT (22U)
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#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK)
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#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK (0x800000U)
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#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT (23U)
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#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK)
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#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK (0x3F000000U)
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#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT (24U)
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#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK)
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#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK (0x40000000U)
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#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT (30U)
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#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK)
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#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK (0x80000000U)
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#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT (31U)
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#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK)
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/*! @} */
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/*! @name PFD_528 - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */
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/*! @{ */
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#define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK (0x3FU)
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#define CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0U)
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#define CCM_ANALOG_PFD_528_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK)
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#define CCM_ANALOG_PFD_528_PFD0_STABLE_MASK (0x40U)
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#define CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT (6U)
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#define CCM_ANALOG_PFD_528_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_STABLE_MASK)
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#define CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK (0x80U)
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#define CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT (7U)
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#define CCM_ANALOG_PFD_528_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK)
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#define CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3F00U)
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#define CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT (8U)
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#define CCM_ANALOG_PFD_528_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK)
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#define CCM_ANALOG_PFD_528_PFD1_STABLE_MASK (0x4000U)
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#define CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT (14U)
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#define CCM_ANALOG_PFD_528_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_STABLE_MASK)
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#define CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK (0x8000U)
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#define CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT (15U)
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#define CCM_ANALOG_PFD_528_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK)
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#define CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3F0000U)
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#define CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16U)
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#define CCM_ANALOG_PFD_528_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK)
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#define CCM_ANALOG_PFD_528_PFD2_STABLE_MASK (0x400000U)
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#define CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT (22U)
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#define CCM_ANALOG_PFD_528_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_STABLE_MASK)
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#define CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK (0x800000U)
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#define CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT (23U)
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#define CCM_ANALOG_PFD_528_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK)
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#define CCM_ANALOG_PFD_528_PFD3_FRAC_MASK (0x3F000000U)
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#define CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT (24U)
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#define CCM_ANALOG_PFD_528_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK)
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#define CCM_ANALOG_PFD_528_PFD3_STABLE_MASK (0x40000000U)
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#define CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT (30U)
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#define CCM_ANALOG_PFD_528_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_STABLE_MASK)
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#define CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK (0x80000000U)
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#define CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT (31U)
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#define CCM_ANALOG_PFD_528_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK)
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/*! @} */
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/*! @name PFD_528_SET - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */
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/*! @{ */
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#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK (0x3FU)
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#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT (0U)
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#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK)
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#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK (0x40U)
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#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT (6U)
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#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK)
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#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK (0x80U)
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#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT (7U)
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#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK)
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#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK (0x3F00U)
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#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT (8U)
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#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK)
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#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK (0x4000U)
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#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT (14U)
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#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK)
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#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK (0x8000U)
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#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT (15U)
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#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK)
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#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK (0x3F0000U)
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#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT (16U)
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#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK)
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#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK (0x400000U)
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#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT (22U)
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#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK)
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#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK (0x800000U)
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#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT (23U)
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#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK)
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#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK (0x3F000000U)
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#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT (24U)
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#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK)
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#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK (0x40000000U)
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#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT (30U)
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#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK)
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#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK (0x80000000U)
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#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT (31U)
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#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK)
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/*! @} */
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/*! @name PFD_528_CLR - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */
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/*! @{ */
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#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK (0x3FU)
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#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT (0U)
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#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK)
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#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK (0x40U)
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#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT (6U)
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#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK)
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#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK (0x80U)
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#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT (7U)
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#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK)
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#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK (0x3F00U)
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#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT (8U)
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#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK)
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#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK (0x4000U)
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#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT (14U)
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#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK)
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#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK (0x8000U)
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#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT (15U)
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#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK)
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#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK (0x3F0000U)
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#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT (16U)
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#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK)
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#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK (0x400000U)
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#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT (22U)
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#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK)
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#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK (0x800000U)
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#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT (23U)
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#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK)
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#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK (0x3F000000U)
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#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT (24U)
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#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK)
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#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK (0x40000000U)
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#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT (30U)
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#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK)
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#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK (0x80000000U)
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#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT (31U)
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#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK)
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/*! @} */
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/*! @name PFD_528_TOG - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */
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/*! @{ */
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#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK (0x3FU)
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#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT (0U)
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#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK)
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#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK (0x40U)
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#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT (6U)
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#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK)
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#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK (0x80U)
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#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT (7U)
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#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK)
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#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK (0x3F00U)
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#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT (8U)
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#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK)
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#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK (0x4000U)
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#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT (14U)
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#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK)
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#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK (0x8000U)
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#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT (15U)
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#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK)
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#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK (0x3F0000U)
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#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT (16U)
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#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK)
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#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK (0x400000U)
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#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT (22U)
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#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK)
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#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK (0x800000U)
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#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT (23U)
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#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK)
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#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK (0x3F000000U)
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#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT (24U)
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#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK)
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#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK (0x40000000U)
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#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT (30U)
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#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK)
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#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK (0x80000000U)
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#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT (31U)
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#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK)
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/*! @} */
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/*! @name MISC0 - Miscellaneous Register 0 */
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/*! @{ */
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#define CCM_ANALOG_MISC0_REFTOP_PWD_MASK (0x1U)
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#define CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT (0U)
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#define CCM_ANALOG_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_PWD_MASK)
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#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)
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#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)
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/*! REFTOP_SELFBIASOFF
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* 0b0..Uses coarse bias currents for startup
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* 0b1..Uses bandgap-based bias currents for best performance.
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*/
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#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK)
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#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK (0x70U)
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#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT (4U)
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/*! REFTOP_VBGADJ
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* 0b000..Nominal VBG
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* 0b001..VBG+0.78%
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* 0b010..VBG+1.56%
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* 0b011..VBG+2.34%
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* 0b100..VBG-0.78%
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* 0b101..VBG-1.56%
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* 0b110..VBG-2.34%
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* 0b111..VBG-3.12%
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*/
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#define CCM_ANALOG_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK)
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#define CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK (0x80U)
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#define CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT (7U)
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#define CCM_ANALOG_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK)
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#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)
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#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT (10U)
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/*! STOP_MODE_CONFIG
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* 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off;
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* 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off;
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* 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off.
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* 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.
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*/
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#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK)
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#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)
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#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)
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/*! DISCON_HIGH_SNVS
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* 0b0..Turn on the switch
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* 0b1..Turn off the switch
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*/
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#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK)
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#define CCM_ANALOG_MISC0_OSC_I_MASK (0x6000U)
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#define CCM_ANALOG_MISC0_OSC_I_SHIFT (13U)
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/*! OSC_I
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* 0b00..Nominal
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* 0b01..Decrease current by 12.5%
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* 0b10..Decrease current by 25.0%
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* 0b11..Decrease current by 37.5%
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*/
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#define CCM_ANALOG_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_OSC_I_MASK)
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#define CCM_ANALOG_MISC0_OSC_XTALOK_MASK (0x8000U)
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#define CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT (15U)
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#define CCM_ANALOG_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_MASK)
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#define CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK (0x10000U)
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#define CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT (16U)
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#define CCM_ANALOG_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK)
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#define CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK (0x2000000U)
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#define CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT (25U)
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/*! CLKGATE_CTRL
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* 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
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* 0b1..Prevent the logic from ever gating off the clock.
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*/
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#define CCM_ANALOG_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK)
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#define CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)
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#define CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT (26U)
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/*! CLKGATE_DELAY
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* 0b000..0.5ms
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* 0b001..1.0ms
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* 0b010..2.0ms
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* 0b011..3.0ms
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* 0b100..4.0ms
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* 0b101..5.0ms
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* 0b110..6.0ms
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* 0b111..7.0ms
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*/
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#define CCM_ANALOG_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK)
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#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)
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#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)
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/*! RTC_XTAL_SOURCE
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* 0b0..Internal ring oscillator
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* 0b1..RTC_XTAL
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*/
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#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK)
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#define CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK (0x40000000U)
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#define CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT (30U)
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#define CCM_ANALOG_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK)
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/*! @} */
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/*! @name MISC0_SET - Miscellaneous Register 0 */
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/*! @{ */
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#define CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK (0x1U)
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#define CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT (0U)
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#define CCM_ANALOG_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK)
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#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)
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#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)
|
|
/*! REFTOP_SELFBIASOFF
|
|
* 0b0..Uses coarse bias currents for startup
|
|
* 0b1..Uses bandgap-based bias currents for best performance.
|
|
*/
|
|
#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK)
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#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)
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#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)
|
|
/*! REFTOP_VBGADJ
|
|
* 0b000..Nominal VBG
|
|
* 0b001..VBG+0.78%
|
|
* 0b010..VBG+1.56%
|
|
* 0b011..VBG+2.34%
|
|
* 0b100..VBG-0.78%
|
|
* 0b101..VBG-1.56%
|
|
* 0b110..VBG-2.34%
|
|
* 0b111..VBG-3.12%
|
|
*/
|
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#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK)
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#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)
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#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)
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#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK)
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#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)
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#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)
|
|
/*! STOP_MODE_CONFIG
|
|
* 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off;
|
|
* 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off;
|
|
* 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off.
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* 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.
|
|
*/
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#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK)
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#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)
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#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)
|
|
/*! DISCON_HIGH_SNVS
|
|
* 0b0..Turn on the switch
|
|
* 0b1..Turn off the switch
|
|
*/
|
|
#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK)
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#define CCM_ANALOG_MISC0_SET_OSC_I_MASK (0x6000U)
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#define CCM_ANALOG_MISC0_SET_OSC_I_SHIFT (13U)
|
|
/*! OSC_I
|
|
* 0b00..Nominal
|
|
* 0b01..Decrease current by 12.5%
|
|
* 0b10..Decrease current by 25.0%
|
|
* 0b11..Decrease current by 37.5%
|
|
*/
|
|
#define CCM_ANALOG_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_I_MASK)
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#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK (0x8000U)
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#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT (15U)
|
|
#define CCM_ANALOG_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK)
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#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)
|
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#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)
|
|
#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK)
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|
#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)
|
|
#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)
|
|
/*! CLKGATE_CTRL
|
|
* 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
|
|
* 0b1..Prevent the logic from ever gating off the clock.
|
|
*/
|
|
#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK)
|
|
#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)
|
|
#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)
|
|
/*! CLKGATE_DELAY
|
|
* 0b000..0.5ms
|
|
* 0b001..1.0ms
|
|
* 0b010..2.0ms
|
|
* 0b011..3.0ms
|
|
* 0b100..4.0ms
|
|
* 0b101..5.0ms
|
|
* 0b110..6.0ms
|
|
* 0b111..7.0ms
|
|
*/
|
|
#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK)
|
|
#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)
|
|
#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)
|
|
/*! RTC_XTAL_SOURCE
|
|
* 0b0..Internal ring oscillator
|
|
* 0b1..RTC_XTAL
|
|
*/
|
|
#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK)
|
|
#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)
|
|
#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)
|
|
#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MISC0_CLR - Miscellaneous Register 0 */
|
|
/*! @{ */
|
|
#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK (0x1U)
|
|
#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT (0U)
|
|
#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK)
|
|
#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)
|
|
#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)
|
|
/*! REFTOP_SELFBIASOFF
|
|
* 0b0..Uses coarse bias currents for startup
|
|
* 0b1..Uses bandgap-based bias currents for best performance.
|
|
*/
|
|
#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)
|
|
#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)
|
|
#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)
|
|
/*! REFTOP_VBGADJ
|
|
* 0b000..Nominal VBG
|
|
* 0b001..VBG+0.78%
|
|
* 0b010..VBG+1.56%
|
|
* 0b011..VBG+2.34%
|
|
* 0b100..VBG-0.78%
|
|
* 0b101..VBG-1.56%
|
|
* 0b110..VBG-2.34%
|
|
* 0b111..VBG-3.12%
|
|
*/
|
|
#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK)
|
|
#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)
|
|
#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)
|
|
#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK)
|
|
#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)
|
|
#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)
|
|
/*! STOP_MODE_CONFIG
|
|
* 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off;
|
|
* 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off;
|
|
* 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off.
|
|
* 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.
|
|
*/
|
|
#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK)
|
|
#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)
|
|
#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)
|
|
/*! DISCON_HIGH_SNVS
|
|
* 0b0..Turn on the switch
|
|
* 0b1..Turn off the switch
|
|
*/
|
|
#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK)
|
|
#define CCM_ANALOG_MISC0_CLR_OSC_I_MASK (0x6000U)
|
|
#define CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT (13U)
|
|
/*! OSC_I
|
|
* 0b00..Nominal
|
|
* 0b01..Decrease current by 12.5%
|
|
* 0b10..Decrease current by 25.0%
|
|
* 0b11..Decrease current by 37.5%
|
|
*/
|
|
#define CCM_ANALOG_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_I_MASK)
|
|
#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)
|
|
#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT (15U)
|
|
#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK)
|
|
#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)
|
|
#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)
|
|
#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK)
|
|
#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)
|
|
#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)
|
|
/*! CLKGATE_CTRL
|
|
* 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
|
|
* 0b1..Prevent the logic from ever gating off the clock.
|
|
*/
|
|
#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK)
|
|
#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)
|
|
#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)
|
|
/*! CLKGATE_DELAY
|
|
* 0b000..0.5ms
|
|
* 0b001..1.0ms
|
|
* 0b010..2.0ms
|
|
* 0b011..3.0ms
|
|
* 0b100..4.0ms
|
|
* 0b101..5.0ms
|
|
* 0b110..6.0ms
|
|
* 0b111..7.0ms
|
|
*/
|
|
#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK)
|
|
#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)
|
|
#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)
|
|
/*! RTC_XTAL_SOURCE
|
|
* 0b0..Internal ring oscillator
|
|
* 0b1..RTC_XTAL
|
|
*/
|
|
#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK)
|
|
#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)
|
|
#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)
|
|
#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MISC0_TOG - Miscellaneous Register 0 */
|
|
/*! @{ */
|
|
#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK (0x1U)
|
|
#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT (0U)
|
|
#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK)
|
|
#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)
|
|
#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)
|
|
/*! REFTOP_SELFBIASOFF
|
|
* 0b0..Uses coarse bias currents for startup
|
|
* 0b1..Uses bandgap-based bias currents for best performance.
|
|
*/
|
|
#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)
|
|
#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)
|
|
#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)
|
|
/*! REFTOP_VBGADJ
|
|
* 0b000..Nominal VBG
|
|
* 0b001..VBG+0.78%
|
|
* 0b010..VBG+1.56%
|
|
* 0b011..VBG+2.34%
|
|
* 0b100..VBG-0.78%
|
|
* 0b101..VBG-1.56%
|
|
* 0b110..VBG-2.34%
|
|
* 0b111..VBG-3.12%
|
|
*/
|
|
#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK)
|
|
#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)
|
|
#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)
|
|
#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK)
|
|
#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)
|
|
#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)
|
|
/*! STOP_MODE_CONFIG
|
|
* 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off;
|
|
* 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off;
|
|
* 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off.
|
|
* 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.
|
|
*/
|
|
#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK)
|
|
#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)
|
|
#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)
|
|
/*! DISCON_HIGH_SNVS
|
|
* 0b0..Turn on the switch
|
|
* 0b1..Turn off the switch
|
|
*/
|
|
#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK)
|
|
#define CCM_ANALOG_MISC0_TOG_OSC_I_MASK (0x6000U)
|
|
#define CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT (13U)
|
|
/*! OSC_I
|
|
* 0b00..Nominal
|
|
* 0b01..Decrease current by 12.5%
|
|
* 0b10..Decrease current by 25.0%
|
|
* 0b11..Decrease current by 37.5%
|
|
*/
|
|
#define CCM_ANALOG_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_I_MASK)
|
|
#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)
|
|
#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT (15U)
|
|
#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK)
|
|
#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)
|
|
#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)
|
|
#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK)
|
|
#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)
|
|
#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)
|
|
/*! CLKGATE_CTRL
|
|
* 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
|
|
* 0b1..Prevent the logic from ever gating off the clock.
|
|
*/
|
|
#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK)
|
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#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)
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#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)
|
|
/*! CLKGATE_DELAY
|
|
* 0b000..0.5ms
|
|
* 0b001..1.0ms
|
|
* 0b010..2.0ms
|
|
* 0b011..3.0ms
|
|
* 0b100..4.0ms
|
|
* 0b101..5.0ms
|
|
* 0b110..6.0ms
|
|
* 0b111..7.0ms
|
|
*/
|
|
#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK)
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#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)
|
|
#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)
|
|
/*! RTC_XTAL_SOURCE
|
|
* 0b0..Internal ring oscillator
|
|
* 0b1..RTC_XTAL
|
|
*/
|
|
#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK)
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#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)
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#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)
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#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK)
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/*! @} */
|
|
|
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/*! @name MISC1 - Miscellaneous Register 1 */
|
|
/*! @{ */
|
|
#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK (0x1FU)
|
|
#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT (0U)
|
|
/*! LVDS1_CLK_SEL
|
|
* 0b00000..Arm PLL
|
|
* 0b00001..System PLL
|
|
* 0b00010..ref_pfd4_clk == pll2_pfd0_clk
|
|
* 0b00011..ref_pfd5_clk == pll2_pfd1_clk
|
|
* 0b00100..ref_pfd6_clk == pll2_pfd2_clk
|
|
* 0b00101..ref_pfd7_clk == pll2_pfd3_clk
|
|
* 0b00110..Audio PLL
|
|
* 0b00111..Video PLL
|
|
* 0b01001..ethernet ref clock (ENET_PLL)
|
|
* 0b01100..USB1 PLL clock
|
|
* 0b01101..USB2 PLL clock
|
|
* 0b01110..ref_pfd0_clk == pll3_pfd0_clk
|
|
* 0b01111..ref_pfd1_clk == pll3_pfd1_clk
|
|
* 0b10000..ref_pfd2_clk == pll3_pfd2_clk
|
|
* 0b10001..ref_pfd3_clk == pll3_pfd3_clk
|
|
* 0b10010..xtal (24M)
|
|
*/
|
|
#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)
|
|
#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK (0x400U)
|
|
#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT (10U)
|
|
#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK)
|
|
#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK (0x1000U)
|
|
#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT (12U)
|
|
#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK)
|
|
#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U)
|
|
#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U)
|
|
#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK)
|
|
#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U)
|
|
#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U)
|
|
#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK)
|
|
#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U)
|
|
#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT (27U)
|
|
#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK)
|
|
#define CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK (0x10000000U)
|
|
#define CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT (28U)
|
|
#define CCM_ANALOG_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK)
|
|
#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U)
|
|
#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT (29U)
|
|
#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK)
|
|
#define CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK (0x40000000U)
|
|
#define CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT (30U)
|
|
#define CCM_ANALOG_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK)
|
|
#define CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK (0x80000000U)
|
|
#define CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT (31U)
|
|
#define CCM_ANALOG_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MISC1_SET - Miscellaneous Register 1 */
|
|
/*! @{ */
|
|
#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU)
|
|
#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U)
|
|
/*! LVDS1_CLK_SEL
|
|
* 0b00000..Arm PLL
|
|
* 0b00001..System PLL
|
|
* 0b00010..ref_pfd4_clk == pll2_pfd0_clk
|
|
* 0b00011..ref_pfd5_clk == pll2_pfd1_clk
|
|
* 0b00100..ref_pfd6_clk == pll2_pfd2_clk
|
|
* 0b00101..ref_pfd7_clk == pll2_pfd3_clk
|
|
* 0b00110..Audio PLL
|
|
* 0b00111..Video PLL
|
|
* 0b01001..ethernet ref clock (ENET_PLL)
|
|
* 0b01100..USB1 PLL clock
|
|
* 0b01101..USB2 PLL clock
|
|
* 0b01110..ref_pfd0_clk == pll3_pfd0_clk
|
|
* 0b01111..ref_pfd1_clk == pll3_pfd1_clk
|
|
* 0b10000..ref_pfd2_clk == pll3_pfd2_clk
|
|
* 0b10001..ref_pfd3_clk == pll3_pfd3_clk
|
|
* 0b10010..xtal (24M)
|
|
*/
|
|
#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK)
|
|
#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U)
|
|
#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U)
|
|
#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK)
|
|
#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U)
|
|
#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U)
|
|
#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK)
|
|
#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U)
|
|
#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U)
|
|
#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK)
|
|
#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U)
|
|
#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U)
|
|
#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK)
|
|
#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U)
|
|
#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U)
|
|
#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK)
|
|
#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U)
|
|
#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U)
|
|
#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK)
|
|
#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U)
|
|
#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U)
|
|
#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK)
|
|
#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U)
|
|
#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT (30U)
|
|
#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK)
|
|
#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U)
|
|
#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT (31U)
|
|
#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MISC1_CLR - Miscellaneous Register 1 */
|
|
/*! @{ */
|
|
#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU)
|
|
#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U)
|
|
/*! LVDS1_CLK_SEL
|
|
* 0b00000..Arm PLL
|
|
* 0b00001..System PLL
|
|
* 0b00010..ref_pfd4_clk == pll2_pfd0_clk
|
|
* 0b00011..ref_pfd5_clk == pll2_pfd1_clk
|
|
* 0b00100..ref_pfd6_clk == pll2_pfd2_clk
|
|
* 0b00101..ref_pfd7_clk == pll2_pfd3_clk
|
|
* 0b00110..Audio PLL
|
|
* 0b00111..Video PLL
|
|
* 0b01001..ethernet ref clock (ENET_PLL)
|
|
* 0b01100..USB1 PLL clock
|
|
* 0b01101..USB2 PLL clock
|
|
* 0b01110..ref_pfd0_clk == pll3_pfd0_clk
|
|
* 0b01111..ref_pfd1_clk == pll3_pfd1_clk
|
|
* 0b10000..ref_pfd2_clk == pll3_pfd2_clk
|
|
* 0b10001..ref_pfd3_clk == pll3_pfd3_clk
|
|
* 0b10010..xtal (24M)
|
|
*/
|
|
#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK)
|
|
#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U)
|
|
#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U)
|
|
#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK)
|
|
#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U)
|
|
#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U)
|
|
#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK)
|
|
#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U)
|
|
#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U)
|
|
#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK)
|
|
#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U)
|
|
#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U)
|
|
#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK)
|
|
#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U)
|
|
#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U)
|
|
#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK)
|
|
#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U)
|
|
#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U)
|
|
#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK)
|
|
#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U)
|
|
#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U)
|
|
#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK)
|
|
#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U)
|
|
#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U)
|
|
#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK)
|
|
#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U)
|
|
#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U)
|
|
#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MISC1_TOG - Miscellaneous Register 1 */
|
|
/*! @{ */
|
|
#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU)
|
|
#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U)
|
|
/*! LVDS1_CLK_SEL
|
|
* 0b00000..Arm PLL
|
|
* 0b00001..System PLL
|
|
* 0b00010..ref_pfd4_clk == pll2_pfd0_clk
|
|
* 0b00011..ref_pfd5_clk == pll2_pfd1_clk
|
|
* 0b00100..ref_pfd6_clk == pll2_pfd2_clk
|
|
* 0b00101..ref_pfd7_clk == pll2_pfd3_clk
|
|
* 0b00110..Audio PLL
|
|
* 0b00111..Video PLL
|
|
* 0b01001..ethernet ref clock (ENET_PLL)
|
|
* 0b01100..USB1 PLL clock
|
|
* 0b01101..USB2 PLL clock
|
|
* 0b01110..ref_pfd0_clk == pll3_pfd0_clk
|
|
* 0b01111..ref_pfd1_clk == pll3_pfd1_clk
|
|
* 0b10000..ref_pfd2_clk == pll3_pfd2_clk
|
|
* 0b10001..ref_pfd3_clk == pll3_pfd3_clk
|
|
* 0b10010..xtal (24M)
|
|
*/
|
|
#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK)
|
|
#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U)
|
|
#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U)
|
|
#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK)
|
|
#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U)
|
|
#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U)
|
|
#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK)
|
|
#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U)
|
|
#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U)
|
|
#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK)
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#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U)
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#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U)
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#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK)
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#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U)
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#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U)
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#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK)
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#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U)
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#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U)
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#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK)
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#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U)
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#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U)
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#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK)
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#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U)
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#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U)
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#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK)
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#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U)
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#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U)
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#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK)
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/*! @} */
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/*! @name MISC2 - Miscellaneous Register 2 */
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/*! @{ */
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#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK (0x7U)
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#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT (0U)
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/*! REG0_BO_OFFSET
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* 0b100..Brownout offset = 0.100V
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* 0b111..Brownout offset = 0.175V
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*/
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#define CCM_ANALOG_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK)
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#define CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK (0x8U)
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#define CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT (3U)
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/*! REG0_BO_STATUS
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* 0b1..Brownout, supply is below target minus brownout offset.
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*/
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#define CCM_ANALOG_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK)
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#define CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK (0x20U)
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#define CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT (5U)
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#define CCM_ANALOG_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK)
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#define CCM_ANALOG_MISC2_REG0_OK_MASK (0x40U)
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#define CCM_ANALOG_MISC2_REG0_OK_SHIFT (6U)
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#define CCM_ANALOG_MISC2_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_REG0_OK_MASK)
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#define CCM_ANALOG_MISC2_PLL3_disable_MASK (0x80U)
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#define CCM_ANALOG_MISC2_PLL3_disable_SHIFT (7U)
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/*! PLL3_disable
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* 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode
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* 0b1..PLL3 can be disabled when the SoC is not in any low power mode
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*/
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#define CCM_ANALOG_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_PLL3_disable_MASK)
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#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK (0x700U)
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#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT (8U)
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/*! REG1_BO_OFFSET
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* 0b100..Brownout offset = 0.100V
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* 0b111..Brownout offset = 0.175V
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*/
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#define CCM_ANALOG_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK)
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#define CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK (0x800U)
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#define CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT (11U)
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/*! REG1_BO_STATUS
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* 0b1..Brownout, supply is below target minus brownout offset.
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*/
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#define CCM_ANALOG_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK)
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#define CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK (0x2000U)
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#define CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT (13U)
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#define CCM_ANALOG_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK)
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#define CCM_ANALOG_MISC2_REG1_OK_MASK (0x4000U)
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#define CCM_ANALOG_MISC2_REG1_OK_SHIFT (14U)
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#define CCM_ANALOG_MISC2_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_REG1_OK_MASK)
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#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK (0x8000U)
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#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT (15U)
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/*! AUDIO_DIV_LSB
|
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* 0b0..divide by 1 (Default)
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* 0b1..divide by 2
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|
*/
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#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK)
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#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK (0x70000U)
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#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT (16U)
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/*! REG2_BO_OFFSET
|
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* 0b100..Brownout offset = 0.100V
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* 0b111..Brownout offset = 0.175V
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*/
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#define CCM_ANALOG_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK)
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#define CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK (0x80000U)
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#define CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT (19U)
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#define CCM_ANALOG_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK)
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#define CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK (0x200000U)
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#define CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT (21U)
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#define CCM_ANALOG_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK)
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#define CCM_ANALOG_MISC2_REG2_OK_MASK (0x400000U)
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#define CCM_ANALOG_MISC2_REG2_OK_SHIFT (22U)
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#define CCM_ANALOG_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_REG2_OK_MASK)
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#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK (0x800000U)
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#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT (23U)
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/*! AUDIO_DIV_MSB
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* 0b0..divide by 1 (Default)
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* 0b1..divide by 2
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*/
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#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK)
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#define CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK (0x3000000U)
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#define CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT (24U)
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/*! REG0_STEP_TIME
|
|
* 0b00..64
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* 0b01..128
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* 0b10..256
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* 0b11..512
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*/
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#define CCM_ANALOG_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK)
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#define CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK (0xC000000U)
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#define CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT (26U)
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/*! REG1_STEP_TIME
|
|
* 0b00..64
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* 0b01..128
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* 0b10..256
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* 0b11..512
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*/
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#define CCM_ANALOG_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK)
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|
#define CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK (0x30000000U)
|
|
#define CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT (28U)
|
|
/*! REG2_STEP_TIME
|
|
* 0b00..64
|
|
* 0b01..128
|
|
* 0b10..256
|
|
* 0b11..512
|
|
*/
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|
#define CCM_ANALOG_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK)
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|
#define CCM_ANALOG_MISC2_VIDEO_DIV_MASK (0xC0000000U)
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|
#define CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT (30U)
|
|
/*! VIDEO_DIV
|
|
* 0b00..divide by 1 (Default)
|
|
* 0b01..divide by 2
|
|
* 0b10..divide by 1
|
|
* 0b11..divide by 4
|
|
*/
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|
#define CCM_ANALOG_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_VIDEO_DIV_MASK)
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/*! @} */
|
|
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|
/*! @name MISC2_SET - Miscellaneous Register 2 */
|
|
/*! @{ */
|
|
#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U)
|
|
#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U)
|
|
/*! REG0_BO_OFFSET
|
|
* 0b100..Brownout offset = 0.100V
|
|
* 0b111..Brownout offset = 0.175V
|
|
*/
|
|
#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK)
|
|
#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK (0x8U)
|
|
#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT (3U)
|
|
/*! REG0_BO_STATUS
|
|
* 0b1..Brownout, supply is below target minus brownout offset.
|
|
*/
|
|
#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK)
|
|
#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U)
|
|
#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U)
|
|
#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK)
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|
#define CCM_ANALOG_MISC2_SET_REG0_OK_MASK (0x40U)
|
|
#define CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT (6U)
|
|
#define CCM_ANALOG_MISC2_SET_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_OK_MASK)
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|
#define CCM_ANALOG_MISC2_SET_PLL3_disable_MASK (0x80U)
|
|
#define CCM_ANALOG_MISC2_SET_PLL3_disable_SHIFT (7U)
|
|
/*! PLL3_disable
|
|
* 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode
|
|
* 0b1..PLL3 can be disabled when the SoC is not in any low power mode
|
|
*/
|
|
#define CCM_ANALOG_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_SET_PLL3_disable_MASK)
|
|
#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U)
|
|
#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U)
|
|
/*! REG1_BO_OFFSET
|
|
* 0b100..Brownout offset = 0.100V
|
|
* 0b111..Brownout offset = 0.175V
|
|
*/
|
|
#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK)
|
|
#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK (0x800U)
|
|
#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT (11U)
|
|
/*! REG1_BO_STATUS
|
|
* 0b1..Brownout, supply is below target minus brownout offset.
|
|
*/
|
|
#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK)
|
|
#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U)
|
|
#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U)
|
|
#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK)
|
|
#define CCM_ANALOG_MISC2_SET_REG1_OK_MASK (0x4000U)
|
|
#define CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT (14U)
|
|
#define CCM_ANALOG_MISC2_SET_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_OK_MASK)
|
|
#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U)
|
|
#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U)
|
|
/*! AUDIO_DIV_LSB
|
|
* 0b0..divide by 1 (Default)
|
|
* 0b1..divide by 2
|
|
*/
|
|
#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK)
|
|
#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U)
|
|
#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U)
|
|
/*! REG2_BO_OFFSET
|
|
* 0b100..Brownout offset = 0.100V
|
|
* 0b111..Brownout offset = 0.175V
|
|
*/
|
|
#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK)
|
|
#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U)
|
|
#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT (19U)
|
|
#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK)
|
|
#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U)
|
|
#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U)
|
|
#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK)
|
|
#define CCM_ANALOG_MISC2_SET_REG2_OK_MASK (0x400000U)
|
|
#define CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT (22U)
|
|
#define CCM_ANALOG_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_OK_MASK)
|
|
#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U)
|
|
#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U)
|
|
/*! AUDIO_DIV_MSB
|
|
* 0b0..divide by 1 (Default)
|
|
* 0b1..divide by 2
|
|
*/
|
|
#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK)
|
|
#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U)
|
|
#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT (24U)
|
|
/*! REG0_STEP_TIME
|
|
* 0b00..64
|
|
* 0b01..128
|
|
* 0b10..256
|
|
* 0b11..512
|
|
*/
|
|
#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK)
|
|
#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U)
|
|
#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT (26U)
|
|
/*! REG1_STEP_TIME
|
|
* 0b00..64
|
|
* 0b01..128
|
|
* 0b10..256
|
|
* 0b11..512
|
|
*/
|
|
#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK)
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#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U)
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#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT (28U)
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/*! REG2_STEP_TIME
|
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* 0b00..64
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* 0b01..128
|
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* 0b10..256
|
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* 0b11..512
|
|
*/
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#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK)
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#define CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U)
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#define CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT (30U)
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/*! VIDEO_DIV
|
|
* 0b00..divide by 1 (Default)
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* 0b01..divide by 2
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* 0b10..divide by 1
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* 0b11..divide by 4
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*/
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#define CCM_ANALOG_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK)
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/*! @} */
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/*! @name MISC2_CLR - Miscellaneous Register 2 */
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/*! @{ */
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#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U)
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#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U)
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/*! REG0_BO_OFFSET
|
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* 0b100..Brownout offset = 0.100V
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* 0b111..Brownout offset = 0.175V
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|
*/
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#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK)
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#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U)
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#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U)
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/*! REG0_BO_STATUS
|
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* 0b1..Brownout, supply is below target minus brownout offset.
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*/
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#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK)
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#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U)
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#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U)
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#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK)
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#define CCM_ANALOG_MISC2_CLR_REG0_OK_MASK (0x40U)
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#define CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT (6U)
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#define CCM_ANALOG_MISC2_CLR_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_OK_MASK)
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#define CCM_ANALOG_MISC2_CLR_PLL3_disable_MASK (0x80U)
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#define CCM_ANALOG_MISC2_CLR_PLL3_disable_SHIFT (7U)
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/*! PLL3_disable
|
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* 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode
|
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* 0b1..PLL3 can be disabled when the SoC is not in any low power mode
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*/
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#define CCM_ANALOG_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_CLR_PLL3_disable_MASK)
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#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U)
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#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U)
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/*! REG1_BO_OFFSET
|
|
* 0b100..Brownout offset = 0.100V
|
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* 0b111..Brownout offset = 0.175V
|
|
*/
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|
#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK)
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#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U)
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#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U)
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/*! REG1_BO_STATUS
|
|
* 0b1..Brownout, supply is below target minus brownout offset.
|
|
*/
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#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK)
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#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U)
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#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U)
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#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK)
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#define CCM_ANALOG_MISC2_CLR_REG1_OK_MASK (0x4000U)
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#define CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT (14U)
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|
#define CCM_ANALOG_MISC2_CLR_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_OK_MASK)
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#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U)
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|
#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U)
|
|
/*! AUDIO_DIV_LSB
|
|
* 0b0..divide by 1 (Default)
|
|
* 0b1..divide by 2
|
|
*/
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|
#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK)
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|
#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U)
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|
#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U)
|
|
/*! REG2_BO_OFFSET
|
|
* 0b100..Brownout offset = 0.100V
|
|
* 0b111..Brownout offset = 0.175V
|
|
*/
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|
#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK)
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|
#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U)
|
|
#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U)
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|
#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK)
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|
#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U)
|
|
#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U)
|
|
#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK)
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|
#define CCM_ANALOG_MISC2_CLR_REG2_OK_MASK (0x400000U)
|
|
#define CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT (22U)
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|
#define CCM_ANALOG_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_OK_MASK)
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|
#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U)
|
|
#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U)
|
|
/*! AUDIO_DIV_MSB
|
|
* 0b0..divide by 1 (Default)
|
|
* 0b1..divide by 2
|
|
*/
|
|
#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK)
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|
#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U)
|
|
#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U)
|
|
/*! REG0_STEP_TIME
|
|
* 0b00..64
|
|
* 0b01..128
|
|
* 0b10..256
|
|
* 0b11..512
|
|
*/
|
|
#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK)
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|
#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U)
|
|
#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U)
|
|
/*! REG1_STEP_TIME
|
|
* 0b00..64
|
|
* 0b01..128
|
|
* 0b10..256
|
|
* 0b11..512
|
|
*/
|
|
#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK)
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|
#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U)
|
|
#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U)
|
|
/*! REG2_STEP_TIME
|
|
* 0b00..64
|
|
* 0b01..128
|
|
* 0b10..256
|
|
* 0b11..512
|
|
*/
|
|
#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK)
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|
#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U)
|
|
#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT (30U)
|
|
/*! VIDEO_DIV
|
|
* 0b00..divide by 1 (Default)
|
|
* 0b01..divide by 2
|
|
* 0b10..divide by 1
|
|
* 0b11..divide by 4
|
|
*/
|
|
#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK)
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|
/*! @} */
|
|
|
|
/*! @name MISC2_TOG - Miscellaneous Register 2 */
|
|
/*! @{ */
|
|
#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U)
|
|
#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U)
|
|
/*! REG0_BO_OFFSET
|
|
* 0b100..Brownout offset = 0.100V
|
|
* 0b111..Brownout offset = 0.175V
|
|
*/
|
|
#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK)
|
|
#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U)
|
|
#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U)
|
|
/*! REG0_BO_STATUS
|
|
* 0b1..Brownout, supply is below target minus brownout offset.
|
|
*/
|
|
#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK)
|
|
#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U)
|
|
#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U)
|
|
#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK)
|
|
#define CCM_ANALOG_MISC2_TOG_REG0_OK_MASK (0x40U)
|
|
#define CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT (6U)
|
|
#define CCM_ANALOG_MISC2_TOG_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_OK_MASK)
|
|
#define CCM_ANALOG_MISC2_TOG_PLL3_disable_MASK (0x80U)
|
|
#define CCM_ANALOG_MISC2_TOG_PLL3_disable_SHIFT (7U)
|
|
/*! PLL3_disable
|
|
* 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode
|
|
* 0b1..PLL3 can be disabled when the SoC is not in any low power mode
|
|
*/
|
|
#define CCM_ANALOG_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_TOG_PLL3_disable_MASK)
|
|
#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U)
|
|
#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U)
|
|
/*! REG1_BO_OFFSET
|
|
* 0b100..Brownout offset = 0.100V
|
|
* 0b111..Brownout offset = 0.175V
|
|
*/
|
|
#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK)
|
|
#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U)
|
|
#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U)
|
|
/*! REG1_BO_STATUS
|
|
* 0b1..Brownout, supply is below target minus brownout offset.
|
|
*/
|
|
#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK)
|
|
#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U)
|
|
#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U)
|
|
#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK)
|
|
#define CCM_ANALOG_MISC2_TOG_REG1_OK_MASK (0x4000U)
|
|
#define CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT (14U)
|
|
#define CCM_ANALOG_MISC2_TOG_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_OK_MASK)
|
|
#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U)
|
|
#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U)
|
|
/*! AUDIO_DIV_LSB
|
|
* 0b0..divide by 1 (Default)
|
|
* 0b1..divide by 2
|
|
*/
|
|
#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK)
|
|
#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U)
|
|
#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U)
|
|
/*! REG2_BO_OFFSET
|
|
* 0b100..Brownout offset = 0.100V
|
|
* 0b111..Brownout offset = 0.175V
|
|
*/
|
|
#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK)
|
|
#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U)
|
|
#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U)
|
|
#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK)
|
|
#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U)
|
|
#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U)
|
|
#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK)
|
|
#define CCM_ANALOG_MISC2_TOG_REG2_OK_MASK (0x400000U)
|
|
#define CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT (22U)
|
|
#define CCM_ANALOG_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_OK_MASK)
|
|
#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U)
|
|
#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U)
|
|
/*! AUDIO_DIV_MSB
|
|
* 0b0..divide by 1 (Default)
|
|
* 0b1..divide by 2
|
|
*/
|
|
#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK)
|
|
#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U)
|
|
#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U)
|
|
/*! REG0_STEP_TIME
|
|
* 0b00..64
|
|
* 0b01..128
|
|
* 0b10..256
|
|
* 0b11..512
|
|
*/
|
|
#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK)
|
|
#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U)
|
|
#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U)
|
|
/*! REG1_STEP_TIME
|
|
* 0b00..64
|
|
* 0b01..128
|
|
* 0b10..256
|
|
* 0b11..512
|
|
*/
|
|
#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK)
|
|
#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U)
|
|
#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U)
|
|
/*! REG2_STEP_TIME
|
|
* 0b00..64
|
|
* 0b01..128
|
|
* 0b10..256
|
|
* 0b11..512
|
|
*/
|
|
#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK)
|
|
#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U)
|
|
#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT (30U)
|
|
/*! VIDEO_DIV
|
|
* 0b00..divide by 1 (Default)
|
|
* 0b01..divide by 2
|
|
* 0b10..divide by 1
|
|
* 0b11..divide by 4
|
|
*/
|
|
#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group CCM_ANALOG_Register_Masks */
|
|
|
|
|
|
/* CCM_ANALOG - Peripheral instance base addresses */
|
|
/** Peripheral CCM_ANALOG base address */
|
|
#define CCM_ANALOG_BASE (0x400D8000u)
|
|
/** Peripheral CCM_ANALOG base pointer */
|
|
#define CCM_ANALOG ((CCM_ANALOG_Type *)CCM_ANALOG_BASE)
|
|
/** Array initializer of CCM_ANALOG peripheral base addresses */
|
|
#define CCM_ANALOG_BASE_ADDRS { CCM_ANALOG_BASE }
|
|
/** Array initializer of CCM_ANALOG peripheral base pointers */
|
|
#define CCM_ANALOG_BASE_PTRS { CCM_ANALOG }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group CCM_ANALOG_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- CMP Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** CMP - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
|
|
__IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
|
|
__IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
|
|
__IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
|
|
__IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
|
|
__IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
|
|
} CMP_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- CMP Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup CMP_Register_Masks CMP Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name CR0 - CMP Control Register 0 */
|
|
/*! @{ */
|
|
#define CMP_CR0_HYSTCTR_MASK (0x3U)
|
|
#define CMP_CR0_HYSTCTR_SHIFT (0U)
|
|
/*! HYSTCTR - Comparator hard block hysteresis control
|
|
* 0b00..Level 0
|
|
* 0b01..Level 1
|
|
* 0b10..Level 2
|
|
* 0b11..Level 3
|
|
*/
|
|
#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
|
|
#define CMP_CR0_FILTER_CNT_MASK (0x70U)
|
|
#define CMP_CR0_FILTER_CNT_SHIFT (4U)
|
|
/*! FILTER_CNT - Filter Sample Count
|
|
* 0b000..Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA.
|
|
* 0b001..One sample must agree. The comparator output is simply sampled.
|
|
* 0b010..2 consecutive samples must agree.
|
|
* 0b011..3 consecutive samples must agree.
|
|
* 0b100..4 consecutive samples must agree.
|
|
* 0b101..5 consecutive samples must agree.
|
|
* 0b110..6 consecutive samples must agree.
|
|
* 0b111..7 consecutive samples must agree.
|
|
*/
|
|
#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CR1 - CMP Control Register 1 */
|
|
/*! @{ */
|
|
#define CMP_CR1_EN_MASK (0x1U)
|
|
#define CMP_CR1_EN_SHIFT (0U)
|
|
/*! EN - Comparator Module Enable
|
|
* 0b0..Analog Comparator is disabled.
|
|
* 0b1..Analog Comparator is enabled.
|
|
*/
|
|
#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
|
|
#define CMP_CR1_OPE_MASK (0x2U)
|
|
#define CMP_CR1_OPE_SHIFT (1U)
|
|
/*! OPE - Comparator Output Pin Enable
|
|
* 0b0..CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect.
|
|
* 0b1..CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect.
|
|
*/
|
|
#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
|
|
#define CMP_CR1_COS_MASK (0x4U)
|
|
#define CMP_CR1_COS_SHIFT (2U)
|
|
/*! COS - Comparator Output Select
|
|
* 0b0..Set the filtered comparator output (CMPO) to equal COUT.
|
|
* 0b1..Set the unfiltered comparator output (CMPO) to equal COUTA.
|
|
*/
|
|
#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
|
|
#define CMP_CR1_INV_MASK (0x8U)
|
|
#define CMP_CR1_INV_SHIFT (3U)
|
|
/*! INV - Comparator INVERT
|
|
* 0b0..Does not invert the comparator output.
|
|
* 0b1..Inverts the comparator output.
|
|
*/
|
|
#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
|
|
#define CMP_CR1_PMODE_MASK (0x10U)
|
|
#define CMP_CR1_PMODE_SHIFT (4U)
|
|
/*! PMODE - Power Mode Select
|
|
* 0b0..Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption.
|
|
* 0b1..High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.
|
|
*/
|
|
#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
|
|
#define CMP_CR1_WE_MASK (0x40U)
|
|
#define CMP_CR1_WE_SHIFT (6U)
|
|
/*! WE - Windowing Enable
|
|
* 0b0..Windowing mode is not selected.
|
|
* 0b1..Windowing mode is selected.
|
|
*/
|
|
#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
|
|
#define CMP_CR1_SE_MASK (0x80U)
|
|
#define CMP_CR1_SE_SHIFT (7U)
|
|
/*! SE - Sample Enable
|
|
* 0b0..Sampling mode is not selected.
|
|
* 0b1..Sampling mode is selected.
|
|
*/
|
|
#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FPR - CMP Filter Period Register */
|
|
/*! @{ */
|
|
#define CMP_FPR_FILT_PER_MASK (0xFFU)
|
|
#define CMP_FPR_FILT_PER_SHIFT (0U)
|
|
#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SCR - CMP Status and Control Register */
|
|
/*! @{ */
|
|
#define CMP_SCR_COUT_MASK (0x1U)
|
|
#define CMP_SCR_COUT_SHIFT (0U)
|
|
#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
|
|
#define CMP_SCR_CFF_MASK (0x2U)
|
|
#define CMP_SCR_CFF_SHIFT (1U)
|
|
/*! CFF - Analog Comparator Flag Falling
|
|
* 0b0..Falling-edge on COUT has not been detected.
|
|
* 0b1..Falling-edge on COUT has occurred.
|
|
*/
|
|
#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
|
|
#define CMP_SCR_CFR_MASK (0x4U)
|
|
#define CMP_SCR_CFR_SHIFT (2U)
|
|
/*! CFR - Analog Comparator Flag Rising
|
|
* 0b0..Rising-edge on COUT has not been detected.
|
|
* 0b1..Rising-edge on COUT has occurred.
|
|
*/
|
|
#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
|
|
#define CMP_SCR_IEF_MASK (0x8U)
|
|
#define CMP_SCR_IEF_SHIFT (3U)
|
|
/*! IEF - Comparator Interrupt Enable Falling
|
|
* 0b0..Interrupt is disabled.
|
|
* 0b1..Interrupt is enabled.
|
|
*/
|
|
#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
|
|
#define CMP_SCR_IER_MASK (0x10U)
|
|
#define CMP_SCR_IER_SHIFT (4U)
|
|
/*! IER - Comparator Interrupt Enable Rising
|
|
* 0b0..Interrupt is disabled.
|
|
* 0b1..Interrupt is enabled.
|
|
*/
|
|
#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
|
|
#define CMP_SCR_DMAEN_MASK (0x40U)
|
|
#define CMP_SCR_DMAEN_SHIFT (6U)
|
|
/*! DMAEN - DMA Enable Control
|
|
* 0b0..DMA is disabled.
|
|
* 0b1..DMA is enabled.
|
|
*/
|
|
#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DACCR - DAC Control Register */
|
|
/*! @{ */
|
|
#define CMP_DACCR_VOSEL_MASK (0x3FU)
|
|
#define CMP_DACCR_VOSEL_SHIFT (0U)
|
|
#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
|
|
#define CMP_DACCR_VRSEL_MASK (0x40U)
|
|
#define CMP_DACCR_VRSEL_SHIFT (6U)
|
|
/*! VRSEL - Supply Voltage Reference Source Select
|
|
* 0b0..Vin1 is selected as resistor ladder network supply reference.
|
|
* 0b1..Vin2 is selected as resistor ladder network supply reference.
|
|
*/
|
|
#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
|
|
#define CMP_DACCR_DACEN_MASK (0x80U)
|
|
#define CMP_DACCR_DACEN_SHIFT (7U)
|
|
/*! DACEN - DAC Enable
|
|
* 0b0..DAC is disabled.
|
|
* 0b1..DAC is enabled.
|
|
*/
|
|
#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MUXCR - MUX Control Register */
|
|
/*! @{ */
|
|
#define CMP_MUXCR_MSEL_MASK (0x7U)
|
|
#define CMP_MUXCR_MSEL_SHIFT (0U)
|
|
/*! MSEL - Minus Input Mux Control
|
|
* 0b000..IN0
|
|
* 0b001..IN1
|
|
* 0b010..IN2
|
|
* 0b011..IN3
|
|
* 0b100..IN4
|
|
* 0b101..IN5
|
|
* 0b110..IN6
|
|
* 0b111..IN7
|
|
*/
|
|
#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
|
|
#define CMP_MUXCR_PSEL_MASK (0x38U)
|
|
#define CMP_MUXCR_PSEL_SHIFT (3U)
|
|
/*! PSEL - Plus Input Mux Control
|
|
* 0b000..IN0
|
|
* 0b001..IN1
|
|
* 0b010..IN2
|
|
* 0b011..IN3
|
|
* 0b100..IN4
|
|
* 0b101..IN5
|
|
* 0b110..IN6
|
|
* 0b111..IN7
|
|
*/
|
|
#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group CMP_Register_Masks */
|
|
|
|
|
|
/* CMP - Peripheral instance base addresses */
|
|
/** Peripheral CMP1 base address */
|
|
#define CMP1_BASE (0x40094000u)
|
|
/** Peripheral CMP1 base pointer */
|
|
#define CMP1 ((CMP_Type *)CMP1_BASE)
|
|
/** Peripheral CMP2 base address */
|
|
#define CMP2_BASE (0x40094008u)
|
|
/** Peripheral CMP2 base pointer */
|
|
#define CMP2 ((CMP_Type *)CMP2_BASE)
|
|
/** Peripheral CMP3 base address */
|
|
#define CMP3_BASE (0x40094010u)
|
|
/** Peripheral CMP3 base pointer */
|
|
#define CMP3 ((CMP_Type *)CMP3_BASE)
|
|
/** Peripheral CMP4 base address */
|
|
#define CMP4_BASE (0x40094018u)
|
|
/** Peripheral CMP4 base pointer */
|
|
#define CMP4 ((CMP_Type *)CMP4_BASE)
|
|
/** Array initializer of CMP peripheral base addresses */
|
|
#define CMP_BASE_ADDRS { 0u, CMP1_BASE, CMP2_BASE, CMP3_BASE, CMP4_BASE }
|
|
/** Array initializer of CMP peripheral base pointers */
|
|
#define CMP_BASE_PTRS { (CMP_Type *)0u, CMP1, CMP2, CMP3, CMP4 }
|
|
/** Interrupt vectors for the CMP peripheral type */
|
|
#define CMP_IRQS { NotAvail_IRQn, ACMP1_IRQn, ACMP2_IRQn, ACMP3_IRQn, ACMP4_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group CMP_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- CSI Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup CSI_Peripheral_Access_Layer CSI Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** CSI - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t CSICR1; /**< CSI Control Register 1, offset: 0x0 */
|
|
__IO uint32_t CSICR2; /**< CSI Control Register 2, offset: 0x4 */
|
|
__IO uint32_t CSICR3; /**< CSI Control Register 3, offset: 0x8 */
|
|
__I uint32_t CSISTATFIFO; /**< CSI Statistic FIFO Register, offset: 0xC */
|
|
__I uint32_t CSIRFIFO; /**< CSI RX FIFO Register, offset: 0x10 */
|
|
__IO uint32_t CSIRXCNT; /**< CSI RX Count Register, offset: 0x14 */
|
|
__IO uint32_t CSISR; /**< CSI Status Register, offset: 0x18 */
|
|
uint8_t RESERVED_0[4];
|
|
__IO uint32_t CSIDMASA_STATFIFO; /**< CSI DMA Start Address Register - for STATFIFO, offset: 0x20 */
|
|
__IO uint32_t CSIDMATS_STATFIFO; /**< CSI DMA Transfer Size Register - for STATFIFO, offset: 0x24 */
|
|
__IO uint32_t CSIDMASA_FB1; /**< CSI DMA Start Address Register - for Frame Buffer1, offset: 0x28 */
|
|
__IO uint32_t CSIDMASA_FB2; /**< CSI DMA Transfer Size Register - for Frame Buffer2, offset: 0x2C */
|
|
__IO uint32_t CSIFBUF_PARA; /**< CSI Frame Buffer Parameter Register, offset: 0x30 */
|
|
__IO uint32_t CSIIMAG_PARA; /**< CSI Image Parameter Register, offset: 0x34 */
|
|
uint8_t RESERVED_1[16];
|
|
__IO uint32_t CSICR18; /**< CSI Control Register 18, offset: 0x48 */
|
|
__IO uint32_t CSICR19; /**< CSI Control Register 19, offset: 0x4C */
|
|
} CSI_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- CSI Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup CSI_Register_Masks CSI Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name CSICR1 - CSI Control Register 1 */
|
|
/*! @{ */
|
|
#define CSI_CSICR1_PIXEL_BIT_MASK (0x1U)
|
|
#define CSI_CSICR1_PIXEL_BIT_SHIFT (0U)
|
|
/*! PIXEL_BIT
|
|
* 0b0..8-bit data for each pixel
|
|
* 0b1..10-bit data for each pixel
|
|
*/
|
|
#define CSI_CSICR1_PIXEL_BIT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PIXEL_BIT_SHIFT)) & CSI_CSICR1_PIXEL_BIT_MASK)
|
|
#define CSI_CSICR1_REDGE_MASK (0x2U)
|
|
#define CSI_CSICR1_REDGE_SHIFT (1U)
|
|
/*! REDGE
|
|
* 0b0..Pixel data is latched at the falling edge of CSI_PIXCLK
|
|
* 0b1..Pixel data is latched at the rising edge of CSI_PIXCLK
|
|
*/
|
|
#define CSI_CSICR1_REDGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_REDGE_SHIFT)) & CSI_CSICR1_REDGE_MASK)
|
|
#define CSI_CSICR1_INV_PCLK_MASK (0x4U)
|
|
#define CSI_CSICR1_INV_PCLK_SHIFT (2U)
|
|
/*! INV_PCLK
|
|
* 0b0..CSI_PIXCLK is directly applied to internal circuitry
|
|
* 0b1..CSI_PIXCLK is inverted before applied to internal circuitry
|
|
*/
|
|
#define CSI_CSICR1_INV_PCLK(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_PCLK_SHIFT)) & CSI_CSICR1_INV_PCLK_MASK)
|
|
#define CSI_CSICR1_INV_DATA_MASK (0x8U)
|
|
#define CSI_CSICR1_INV_DATA_SHIFT (3U)
|
|
/*! INV_DATA
|
|
* 0b0..CSI_D[7:0] data lines are directly applied to internal circuitry
|
|
* 0b1..CSI_D[7:0] data lines are inverted before applied to internal circuitry
|
|
*/
|
|
#define CSI_CSICR1_INV_DATA(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_DATA_SHIFT)) & CSI_CSICR1_INV_DATA_MASK)
|
|
#define CSI_CSICR1_GCLK_MODE_MASK (0x10U)
|
|
#define CSI_CSICR1_GCLK_MODE_SHIFT (4U)
|
|
/*! GCLK_MODE
|
|
* 0b0..Non-gated clock mode. All incoming pixel clocks are valid. HSYNC is ignored.
|
|
* 0b1..Gated clock mode. Pixel clock signal is valid only when HSYNC is active.
|
|
*/
|
|
#define CSI_CSICR1_GCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_GCLK_MODE_SHIFT)) & CSI_CSICR1_GCLK_MODE_MASK)
|
|
#define CSI_CSICR1_CLR_RXFIFO_MASK (0x20U)
|
|
#define CSI_CSICR1_CLR_RXFIFO_SHIFT (5U)
|
|
#define CSI_CSICR1_CLR_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_RXFIFO_SHIFT)) & CSI_CSICR1_CLR_RXFIFO_MASK)
|
|
#define CSI_CSICR1_CLR_STATFIFO_MASK (0x40U)
|
|
#define CSI_CSICR1_CLR_STATFIFO_SHIFT (6U)
|
|
#define CSI_CSICR1_CLR_STATFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_STATFIFO_SHIFT)) & CSI_CSICR1_CLR_STATFIFO_MASK)
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#define CSI_CSICR1_PACK_DIR_MASK (0x80U)
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#define CSI_CSICR1_PACK_DIR_SHIFT (7U)
|
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/*! PACK_DIR
|
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* 0b0..Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. For stat data, 0xAAAA, 0xBBBB, it will appear as 0xBBBBAAAA in STAT FIFO.
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* 0b1..Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. For stat data, 0xAAAA, 0xBBBB, it will appear as 0xAAAABBBB in STAT FIFO.
|
|
*/
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#define CSI_CSICR1_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PACK_DIR_SHIFT)) & CSI_CSICR1_PACK_DIR_MASK)
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#define CSI_CSICR1_FCC_MASK (0x100U)
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#define CSI_CSICR1_FCC_SHIFT (8U)
|
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/*! FCC
|
|
* 0b0..Asynchronous FIFO clear is selected.
|
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* 0b1..Synchronous FIFO clear is selected.
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|
*/
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#define CSI_CSICR1_FCC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FCC_SHIFT)) & CSI_CSICR1_FCC_MASK)
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#define CSI_CSICR1_CCIR_EN_MASK (0x400U)
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#define CSI_CSICR1_CCIR_EN_SHIFT (10U)
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/*! CCIR_EN
|
|
* 0b0..Traditional interface is selected. Timing interface logic is used to latch data.
|
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* 0b1..CCIR656 interface is selected.
|
|
*/
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#define CSI_CSICR1_CCIR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_EN_SHIFT)) & CSI_CSICR1_CCIR_EN_MASK)
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#define CSI_CSICR1_HSYNC_POL_MASK (0x800U)
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#define CSI_CSICR1_HSYNC_POL_SHIFT (11U)
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/*! HSYNC_POL
|
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* 0b0..HSYNC is active low
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* 0b1..HSYNC is active high
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|
*/
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#define CSI_CSICR1_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_HSYNC_POL_SHIFT)) & CSI_CSICR1_HSYNC_POL_MASK)
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#define CSI_CSICR1_SOF_INTEN_MASK (0x10000U)
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#define CSI_CSICR1_SOF_INTEN_SHIFT (16U)
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/*! SOF_INTEN
|
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* 0b0..SOF interrupt disable
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* 0b1..SOF interrupt enable
|
|
*/
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#define CSI_CSICR1_SOF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_INTEN_SHIFT)) & CSI_CSICR1_SOF_INTEN_MASK)
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#define CSI_CSICR1_SOF_POL_MASK (0x20000U)
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#define CSI_CSICR1_SOF_POL_SHIFT (17U)
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/*! SOF_POL
|
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* 0b0..SOF interrupt is generated on SOF falling edge
|
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* 0b1..SOF interrupt is generated on SOF rising edge
|
|
*/
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#define CSI_CSICR1_SOF_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_POL_SHIFT)) & CSI_CSICR1_SOF_POL_MASK)
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#define CSI_CSICR1_RXFF_INTEN_MASK (0x40000U)
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#define CSI_CSICR1_RXFF_INTEN_SHIFT (18U)
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/*! RXFF_INTEN
|
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* 0b0..RxFIFO full interrupt disable
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* 0b1..RxFIFO full interrupt enable
|
|
*/
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#define CSI_CSICR1_RXFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RXFF_INTEN_SHIFT)) & CSI_CSICR1_RXFF_INTEN_MASK)
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#define CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK (0x80000U)
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#define CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT (19U)
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/*! FB1_DMA_DONE_INTEN
|
|
* 0b0..Frame Buffer1 DMA Transfer Done interrupt disable
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* 0b1..Frame Buffer1 DMA Transfer Done interrupt enable
|
|
*/
|
|
#define CSI_CSICR1_FB1_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK)
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#define CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK (0x100000U)
|
|
#define CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT (20U)
|
|
/*! FB2_DMA_DONE_INTEN
|
|
* 0b0..Frame Buffer2 DMA Transfer Done interrupt disable
|
|
* 0b1..Frame Buffer2 DMA Transfer Done interrupt enable
|
|
*/
|
|
#define CSI_CSICR1_FB2_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK)
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#define CSI_CSICR1_STATFF_INTEN_MASK (0x200000U)
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|
#define CSI_CSICR1_STATFF_INTEN_SHIFT (21U)
|
|
/*! STATFF_INTEN
|
|
* 0b0..STATFIFO full interrupt disable
|
|
* 0b1..STATFIFO full interrupt enable
|
|
*/
|
|
#define CSI_CSICR1_STATFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_STATFF_INTEN_SHIFT)) & CSI_CSICR1_STATFF_INTEN_MASK)
|
|
#define CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK (0x400000U)
|
|
#define CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT (22U)
|
|
/*! SFF_DMA_DONE_INTEN
|
|
* 0b0..STATFIFO DMA Transfer Done interrupt disable
|
|
* 0b1..STATFIFO DMA Transfer Done interrupt enable
|
|
*/
|
|
#define CSI_CSICR1_SFF_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK)
|
|
#define CSI_CSICR1_RF_OR_INTEN_MASK (0x1000000U)
|
|
#define CSI_CSICR1_RF_OR_INTEN_SHIFT (24U)
|
|
/*! RF_OR_INTEN
|
|
* 0b0..RxFIFO overrun interrupt is disabled
|
|
* 0b1..RxFIFO overrun interrupt is enabled
|
|
*/
|
|
#define CSI_CSICR1_RF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RF_OR_INTEN_SHIFT)) & CSI_CSICR1_RF_OR_INTEN_MASK)
|
|
#define CSI_CSICR1_SF_OR_INTEN_MASK (0x2000000U)
|
|
#define CSI_CSICR1_SF_OR_INTEN_SHIFT (25U)
|
|
/*! SF_OR_INTEN
|
|
* 0b0..STATFIFO overrun interrupt is disabled
|
|
* 0b1..STATFIFO overrun interrupt is enabled
|
|
*/
|
|
#define CSI_CSICR1_SF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SF_OR_INTEN_SHIFT)) & CSI_CSICR1_SF_OR_INTEN_MASK)
|
|
#define CSI_CSICR1_COF_INT_EN_MASK (0x4000000U)
|
|
#define CSI_CSICR1_COF_INT_EN_SHIFT (26U)
|
|
/*! COF_INT_EN
|
|
* 0b0..COF interrupt is disabled
|
|
* 0b1..COF interrupt is enabled
|
|
*/
|
|
#define CSI_CSICR1_COF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_COF_INT_EN_SHIFT)) & CSI_CSICR1_COF_INT_EN_MASK)
|
|
#define CSI_CSICR1_CCIR_MODE_MASK (0x8000000U)
|
|
#define CSI_CSICR1_CCIR_MODE_SHIFT (27U)
|
|
/*! CCIR_MODE
|
|
* 0b0..Progressive mode is selected
|
|
* 0b1..Interlace mode is selected
|
|
*/
|
|
#define CSI_CSICR1_CCIR_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_MODE_SHIFT)) & CSI_CSICR1_CCIR_MODE_MASK)
|
|
#define CSI_CSICR1_PrP_IF_EN_MASK (0x10000000U)
|
|
#define CSI_CSICR1_PrP_IF_EN_SHIFT (28U)
|
|
/*! PrP_IF_EN
|
|
* 0b0..CSI to PrP bus is disabled
|
|
* 0b1..CSI to PrP bus is enabled
|
|
*/
|
|
#define CSI_CSICR1_PrP_IF_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PrP_IF_EN_SHIFT)) & CSI_CSICR1_PrP_IF_EN_MASK)
|
|
#define CSI_CSICR1_EOF_INT_EN_MASK (0x20000000U)
|
|
#define CSI_CSICR1_EOF_INT_EN_SHIFT (29U)
|
|
/*! EOF_INT_EN
|
|
* 0b0..EOF interrupt is disabled.
|
|
* 0b1..EOF interrupt is generated when RX count value is reached.
|
|
*/
|
|
#define CSI_CSICR1_EOF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EOF_INT_EN_SHIFT)) & CSI_CSICR1_EOF_INT_EN_MASK)
|
|
#define CSI_CSICR1_EXT_VSYNC_MASK (0x40000000U)
|
|
#define CSI_CSICR1_EXT_VSYNC_SHIFT (30U)
|
|
/*! EXT_VSYNC
|
|
* 0b0..Internal VSYNC mode
|
|
* 0b1..External VSYNC mode
|
|
*/
|
|
#define CSI_CSICR1_EXT_VSYNC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EXT_VSYNC_SHIFT)) & CSI_CSICR1_EXT_VSYNC_MASK)
|
|
#define CSI_CSICR1_SWAP16_EN_MASK (0x80000000U)
|
|
#define CSI_CSICR1_SWAP16_EN_SHIFT (31U)
|
|
/*! SWAP16_EN
|
|
* 0b0..Disable swapping
|
|
* 0b1..Enable swapping
|
|
*/
|
|
#define CSI_CSICR1_SWAP16_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SWAP16_EN_SHIFT)) & CSI_CSICR1_SWAP16_EN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CSICR2 - CSI Control Register 2 */
|
|
/*! @{ */
|
|
#define CSI_CSICR2_HSC_MASK (0xFFU)
|
|
#define CSI_CSICR2_HSC_SHIFT (0U)
|
|
#define CSI_CSICR2_HSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_HSC_SHIFT)) & CSI_CSICR2_HSC_MASK)
|
|
#define CSI_CSICR2_VSC_MASK (0xFF00U)
|
|
#define CSI_CSICR2_VSC_SHIFT (8U)
|
|
#define CSI_CSICR2_VSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_VSC_SHIFT)) & CSI_CSICR2_VSC_MASK)
|
|
#define CSI_CSICR2_LVRM_MASK (0x70000U)
|
|
#define CSI_CSICR2_LVRM_SHIFT (16U)
|
|
/*! LVRM
|
|
* 0b000..512 x 384
|
|
* 0b001..448 x 336
|
|
* 0b010..384 x 288
|
|
* 0b011..384 x 256
|
|
* 0b100..320 x 240
|
|
* 0b101..288 x 216
|
|
* 0b110..400 x 300
|
|
*/
|
|
#define CSI_CSICR2_LVRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_LVRM_SHIFT)) & CSI_CSICR2_LVRM_MASK)
|
|
#define CSI_CSICR2_BTS_MASK (0x180000U)
|
|
#define CSI_CSICR2_BTS_SHIFT (19U)
|
|
/*! BTS
|
|
* 0b00..GR
|
|
* 0b01..RG
|
|
* 0b10..BG
|
|
* 0b11..GB
|
|
*/
|
|
#define CSI_CSICR2_BTS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_BTS_SHIFT)) & CSI_CSICR2_BTS_MASK)
|
|
#define CSI_CSICR2_SCE_MASK (0x800000U)
|
|
#define CSI_CSICR2_SCE_SHIFT (23U)
|
|
/*! SCE
|
|
* 0b0..Skip count disable
|
|
* 0b1..Skip count enable
|
|
*/
|
|
#define CSI_CSICR2_SCE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_SCE_SHIFT)) & CSI_CSICR2_SCE_MASK)
|
|
#define CSI_CSICR2_AFS_MASK (0x3000000U)
|
|
#define CSI_CSICR2_AFS_SHIFT (24U)
|
|
/*! AFS
|
|
* 0b00..Abs Diff on consecutive green pixels
|
|
* 0b01..Abs Diff on every third green pixels
|
|
* 0b1x..Abs Diff on every four green pixels
|
|
*/
|
|
#define CSI_CSICR2_AFS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_AFS_SHIFT)) & CSI_CSICR2_AFS_MASK)
|
|
#define CSI_CSICR2_DRM_MASK (0x4000000U)
|
|
#define CSI_CSICR2_DRM_SHIFT (26U)
|
|
/*! DRM
|
|
* 0b0..Stats grid of 8 x 6
|
|
* 0b1..Stats grid of 8 x 12
|
|
*/
|
|
#define CSI_CSICR2_DRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DRM_SHIFT)) & CSI_CSICR2_DRM_MASK)
|
|
#define CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK (0x30000000U)
|
|
#define CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT (28U)
|
|
/*! DMA_BURST_TYPE_SFF
|
|
* 0bx0..INCR8
|
|
* 0b01..INCR4
|
|
* 0b11..INCR16
|
|
*/
|
|
#define CSI_CSICR2_DMA_BURST_TYPE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK)
|
|
#define CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK (0xC0000000U)
|
|
#define CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT (30U)
|
|
/*! DMA_BURST_TYPE_RFF
|
|
* 0bx0..INCR8
|
|
* 0b01..INCR4
|
|
* 0b11..INCR16
|
|
*/
|
|
#define CSI_CSICR2_DMA_BURST_TYPE_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CSICR3 - CSI Control Register 3 */
|
|
/*! @{ */
|
|
#define CSI_CSICR3_ECC_AUTO_EN_MASK (0x1U)
|
|
#define CSI_CSICR3_ECC_AUTO_EN_SHIFT (0U)
|
|
/*! ECC_AUTO_EN
|
|
* 0b0..Auto Error correction is disabled.
|
|
* 0b1..Auto Error correction is enabled.
|
|
*/
|
|
#define CSI_CSICR3_ECC_AUTO_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_AUTO_EN_SHIFT)) & CSI_CSICR3_ECC_AUTO_EN_MASK)
|
|
#define CSI_CSICR3_ECC_INT_EN_MASK (0x2U)
|
|
#define CSI_CSICR3_ECC_INT_EN_SHIFT (1U)
|
|
/*! ECC_INT_EN
|
|
* 0b0..No interrupt is generated when error is detected. Only the status bit ECC_INT is set.
|
|
* 0b1..Interrupt is generated when error is detected.
|
|
*/
|
|
#define CSI_CSICR3_ECC_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_INT_EN_SHIFT)) & CSI_CSICR3_ECC_INT_EN_MASK)
|
|
#define CSI_CSICR3_ZERO_PACK_EN_MASK (0x4U)
|
|
#define CSI_CSICR3_ZERO_PACK_EN_SHIFT (2U)
|
|
/*! ZERO_PACK_EN
|
|
* 0b0..Zero packing disabled
|
|
* 0b1..Zero packing enabled
|
|
*/
|
|
#define CSI_CSICR3_ZERO_PACK_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ZERO_PACK_EN_SHIFT)) & CSI_CSICR3_ZERO_PACK_EN_MASK)
|
|
#define CSI_CSICR3_TWO_8BIT_SENSOR_MASK (0x8U)
|
|
#define CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT (3U)
|
|
/*! TWO_8BIT_SENSOR
|
|
* 0b0..Only one sensor is connected.
|
|
* 0b1..Two 8-bit sensors are connected or one 16-bit sensor is connected.
|
|
*/
|
|
#define CSI_CSICR3_TWO_8BIT_SENSOR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT)) & CSI_CSICR3_TWO_8BIT_SENSOR_MASK)
|
|
#define CSI_CSICR3_RxFF_LEVEL_MASK (0x70U)
|
|
#define CSI_CSICR3_RxFF_LEVEL_SHIFT (4U)
|
|
/*! RxFF_LEVEL
|
|
* 0b000..4 Double words
|
|
* 0b001..8 Double words
|
|
* 0b010..16 Double words
|
|
* 0b011..24 Double words
|
|
* 0b100..32 Double words
|
|
* 0b101..48 Double words
|
|
* 0b110..64 Double words
|
|
* 0b111..96 Double words
|
|
*/
|
|
#define CSI_CSICR3_RxFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_RxFF_LEVEL_SHIFT)) & CSI_CSICR3_RxFF_LEVEL_MASK)
|
|
#define CSI_CSICR3_HRESP_ERR_EN_MASK (0x80U)
|
|
#define CSI_CSICR3_HRESP_ERR_EN_SHIFT (7U)
|
|
/*! HRESP_ERR_EN
|
|
* 0b0..Disable hresponse error interrupt
|
|
* 0b1..Enable hresponse error interrupt
|
|
*/
|
|
#define CSI_CSICR3_HRESP_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_HRESP_ERR_EN_SHIFT)) & CSI_CSICR3_HRESP_ERR_EN_MASK)
|
|
#define CSI_CSICR3_STATFF_LEVEL_MASK (0x700U)
|
|
#define CSI_CSICR3_STATFF_LEVEL_SHIFT (8U)
|
|
/*! STATFF_LEVEL
|
|
* 0b000..4 Double words
|
|
* 0b001..8 Double words
|
|
* 0b010..12 Double words
|
|
* 0b011..16 Double words
|
|
* 0b100..24 Double words
|
|
* 0b101..32 Double words
|
|
* 0b110..48 Double words
|
|
* 0b111..64 Double words
|
|
*/
|
|
#define CSI_CSICR3_STATFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_STATFF_LEVEL_SHIFT)) & CSI_CSICR3_STATFF_LEVEL_MASK)
|
|
#define CSI_CSICR3_DMA_REQ_EN_SFF_MASK (0x800U)
|
|
#define CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT (11U)
|
|
/*! DMA_REQ_EN_SFF
|
|
* 0b0..Disable the dma request
|
|
* 0b1..Enable the dma request
|
|
*/
|
|
#define CSI_CSICR3_DMA_REQ_EN_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_SFF_MASK)
|
|
#define CSI_CSICR3_DMA_REQ_EN_RFF_MASK (0x1000U)
|
|
#define CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT (12U)
|
|
/*! DMA_REQ_EN_RFF
|
|
* 0b0..Disable the dma request
|
|
* 0b1..Enable the dma request
|
|
*/
|
|
#define CSI_CSICR3_DMA_REQ_EN_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_RFF_MASK)
|
|
#define CSI_CSICR3_DMA_REFLASH_SFF_MASK (0x2000U)
|
|
#define CSI_CSICR3_DMA_REFLASH_SFF_SHIFT (13U)
|
|
/*! DMA_REFLASH_SFF
|
|
* 0b0..No reflashing
|
|
* 0b1..Reflash the embedded DMA controller
|
|
*/
|
|
#define CSI_CSICR3_DMA_REFLASH_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_SFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_SFF_MASK)
|
|
#define CSI_CSICR3_DMA_REFLASH_RFF_MASK (0x4000U)
|
|
#define CSI_CSICR3_DMA_REFLASH_RFF_SHIFT (14U)
|
|
/*! DMA_REFLASH_RFF
|
|
* 0b0..No reflashing
|
|
* 0b1..Reflash the embedded DMA controller
|
|
*/
|
|
#define CSI_CSICR3_DMA_REFLASH_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_RFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_RFF_MASK)
|
|
#define CSI_CSICR3_FRMCNT_RST_MASK (0x8000U)
|
|
#define CSI_CSICR3_FRMCNT_RST_SHIFT (15U)
|
|
/*! FRMCNT_RST
|
|
* 0b0..Do not reset
|
|
* 0b1..Reset frame counter immediately
|
|
*/
|
|
#define CSI_CSICR3_FRMCNT_RST(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_RST_SHIFT)) & CSI_CSICR3_FRMCNT_RST_MASK)
|
|
#define CSI_CSICR3_FRMCNT_MASK (0xFFFF0000U)
|
|
#define CSI_CSICR3_FRMCNT_SHIFT (16U)
|
|
#define CSI_CSICR3_FRMCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_SHIFT)) & CSI_CSICR3_FRMCNT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CSISTATFIFO - CSI Statistic FIFO Register */
|
|
/*! @{ */
|
|
#define CSI_CSISTATFIFO_STAT_MASK (0xFFFFFFFFU)
|
|
#define CSI_CSISTATFIFO_STAT_SHIFT (0U)
|
|
#define CSI_CSISTATFIFO_STAT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISTATFIFO_STAT_SHIFT)) & CSI_CSISTATFIFO_STAT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CSIRFIFO - CSI RX FIFO Register */
|
|
/*! @{ */
|
|
#define CSI_CSIRFIFO_IMAGE_MASK (0xFFFFFFFFU)
|
|
#define CSI_CSIRFIFO_IMAGE_SHIFT (0U)
|
|
#define CSI_CSIRFIFO_IMAGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRFIFO_IMAGE_SHIFT)) & CSI_CSIRFIFO_IMAGE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CSIRXCNT - CSI RX Count Register */
|
|
/*! @{ */
|
|
#define CSI_CSIRXCNT_RXCNT_MASK (0x3FFFFFU)
|
|
#define CSI_CSIRXCNT_RXCNT_SHIFT (0U)
|
|
#define CSI_CSIRXCNT_RXCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRXCNT_RXCNT_SHIFT)) & CSI_CSIRXCNT_RXCNT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CSISR - CSI Status Register */
|
|
/*! @{ */
|
|
#define CSI_CSISR_DRDY_MASK (0x1U)
|
|
#define CSI_CSISR_DRDY_SHIFT (0U)
|
|
/*! DRDY
|
|
* 0b0..No data (word) is ready
|
|
* 0b1..At least 1 datum (word) is ready in RXFIFO.
|
|
*/
|
|
#define CSI_CSISR_DRDY(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DRDY_SHIFT)) & CSI_CSISR_DRDY_MASK)
|
|
#define CSI_CSISR_ECC_INT_MASK (0x2U)
|
|
#define CSI_CSISR_ECC_INT_SHIFT (1U)
|
|
/*! ECC_INT
|
|
* 0b0..No error detected
|
|
* 0b1..Error is detected in CCIR coding
|
|
*/
|
|
#define CSI_CSISR_ECC_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_ECC_INT_SHIFT)) & CSI_CSISR_ECC_INT_MASK)
|
|
#define CSI_CSISR_HRESP_ERR_INT_MASK (0x80U)
|
|
#define CSI_CSISR_HRESP_ERR_INT_SHIFT (7U)
|
|
/*! HRESP_ERR_INT
|
|
* 0b0..No hresponse error.
|
|
* 0b1..Hresponse error is detected.
|
|
*/
|
|
#define CSI_CSISR_HRESP_ERR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_HRESP_ERR_INT_SHIFT)) & CSI_CSISR_HRESP_ERR_INT_MASK)
|
|
#define CSI_CSISR_COF_INT_MASK (0x2000U)
|
|
#define CSI_CSISR_COF_INT_SHIFT (13U)
|
|
/*! COF_INT
|
|
* 0b0..Video field has no change.
|
|
* 0b1..Change of video field is detected.
|
|
*/
|
|
#define CSI_CSISR_COF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_COF_INT_SHIFT)) & CSI_CSISR_COF_INT_MASK)
|
|
#define CSI_CSISR_F1_INT_MASK (0x4000U)
|
|
#define CSI_CSISR_F1_INT_SHIFT (14U)
|
|
/*! F1_INT
|
|
* 0b0..Field 1 of video is not detected.
|
|
* 0b1..Field 1 of video is about to start.
|
|
*/
|
|
#define CSI_CSISR_F1_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F1_INT_SHIFT)) & CSI_CSISR_F1_INT_MASK)
|
|
#define CSI_CSISR_F2_INT_MASK (0x8000U)
|
|
#define CSI_CSISR_F2_INT_SHIFT (15U)
|
|
/*! F2_INT
|
|
* 0b0..Field 2 of video is not detected
|
|
* 0b1..Field 2 of video is about to start
|
|
*/
|
|
#define CSI_CSISR_F2_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F2_INT_SHIFT)) & CSI_CSISR_F2_INT_MASK)
|
|
#define CSI_CSISR_SOF_INT_MASK (0x10000U)
|
|
#define CSI_CSISR_SOF_INT_SHIFT (16U)
|
|
/*! SOF_INT
|
|
* 0b0..SOF is not detected.
|
|
* 0b1..SOF is detected.
|
|
*/
|
|
#define CSI_CSISR_SOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SOF_INT_SHIFT)) & CSI_CSISR_SOF_INT_MASK)
|
|
#define CSI_CSISR_EOF_INT_MASK (0x20000U)
|
|
#define CSI_CSISR_EOF_INT_SHIFT (17U)
|
|
/*! EOF_INT
|
|
* 0b0..EOF is not detected.
|
|
* 0b1..EOF is detected.
|
|
*/
|
|
#define CSI_CSISR_EOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_EOF_INT_SHIFT)) & CSI_CSISR_EOF_INT_MASK)
|
|
#define CSI_CSISR_RxFF_INT_MASK (0x40000U)
|
|
#define CSI_CSISR_RxFF_INT_SHIFT (18U)
|
|
/*! RxFF_INT
|
|
* 0b0..RxFIFO is not full.
|
|
* 0b1..RxFIFO is full.
|
|
*/
|
|
#define CSI_CSISR_RxFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RxFF_INT_SHIFT)) & CSI_CSISR_RxFF_INT_MASK)
|
|
#define CSI_CSISR_DMA_TSF_DONE_FB1_MASK (0x80000U)
|
|
#define CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT (19U)
|
|
/*! DMA_TSF_DONE_FB1
|
|
* 0b0..DMA transfer is not completed.
|
|
* 0b1..DMA transfer is completed.
|
|
*/
|
|
#define CSI_CSISR_DMA_TSF_DONE_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB1_MASK)
|
|
#define CSI_CSISR_DMA_TSF_DONE_FB2_MASK (0x100000U)
|
|
#define CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT (20U)
|
|
/*! DMA_TSF_DONE_FB2
|
|
* 0b0..DMA transfer is not completed.
|
|
* 0b1..DMA transfer is completed.
|
|
*/
|
|
#define CSI_CSISR_DMA_TSF_DONE_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB2_MASK)
|
|
#define CSI_CSISR_STATFF_INT_MASK (0x200000U)
|
|
#define CSI_CSISR_STATFF_INT_SHIFT (21U)
|
|
/*! STATFF_INT
|
|
* 0b0..STATFIFO is not full.
|
|
* 0b1..STATFIFO is full.
|
|
*/
|
|
#define CSI_CSISR_STATFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_STATFF_INT_SHIFT)) & CSI_CSISR_STATFF_INT_MASK)
|
|
#define CSI_CSISR_DMA_TSF_DONE_SFF_MASK (0x400000U)
|
|
#define CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT (22U)
|
|
/*! DMA_TSF_DONE_SFF
|
|
* 0b0..DMA transfer is not completed.
|
|
* 0b1..DMA transfer is completed.
|
|
*/
|
|
#define CSI_CSISR_DMA_TSF_DONE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_SFF_MASK)
|
|
#define CSI_CSISR_RF_OR_INT_MASK (0x1000000U)
|
|
#define CSI_CSISR_RF_OR_INT_SHIFT (24U)
|
|
/*! RF_OR_INT
|
|
* 0b0..RXFIFO has not overflowed.
|
|
* 0b1..RXFIFO has overflowed.
|
|
*/
|
|
#define CSI_CSISR_RF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RF_OR_INT_SHIFT)) & CSI_CSISR_RF_OR_INT_MASK)
|
|
#define CSI_CSISR_SF_OR_INT_MASK (0x2000000U)
|
|
#define CSI_CSISR_SF_OR_INT_SHIFT (25U)
|
|
/*! SF_OR_INT
|
|
* 0b0..STATFIFO has not overflowed.
|
|
* 0b1..STATFIFO has overflowed.
|
|
*/
|
|
#define CSI_CSISR_SF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SF_OR_INT_SHIFT)) & CSI_CSISR_SF_OR_INT_MASK)
|
|
#define CSI_CSISR_DMA_FIELD1_DONE_MASK (0x4000000U)
|
|
#define CSI_CSISR_DMA_FIELD1_DONE_SHIFT (26U)
|
|
#define CSI_CSISR_DMA_FIELD1_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD1_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD1_DONE_MASK)
|
|
#define CSI_CSISR_DMA_FIELD0_DONE_MASK (0x8000000U)
|
|
#define CSI_CSISR_DMA_FIELD0_DONE_SHIFT (27U)
|
|
#define CSI_CSISR_DMA_FIELD0_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD0_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD0_DONE_MASK)
|
|
#define CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK (0x10000000U)
|
|
#define CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT (28U)
|
|
#define CSI_CSISR_BASEADDR_CHHANGE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT)) & CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CSIDMASA_STATFIFO - CSI DMA Start Address Register - for STATFIFO */
|
|
/*! @{ */
|
|
#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK (0xFFFFFFFCU)
|
|
#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT (2U)
|
|
#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT)) & CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CSIDMATS_STATFIFO - CSI DMA Transfer Size Register - for STATFIFO */
|
|
/*! @{ */
|
|
#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK (0xFFFFFFFFU)
|
|
#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT (0U)
|
|
#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT)) & CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CSIDMASA_FB1 - CSI DMA Start Address Register - for Frame Buffer1 */
|
|
/*! @{ */
|
|
#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK (0xFFFFFFFCU)
|
|
#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT (2U)
|
|
#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT)) & CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CSIDMASA_FB2 - CSI DMA Transfer Size Register - for Frame Buffer2 */
|
|
/*! @{ */
|
|
#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK (0xFFFFFFFCU)
|
|
#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT (2U)
|
|
#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT)) & CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CSIFBUF_PARA - CSI Frame Buffer Parameter Register */
|
|
/*! @{ */
|
|
#define CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK (0xFFFFU)
|
|
#define CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT (0U)
|
|
#define CSI_CSIFBUF_PARA_FBUF_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK)
|
|
#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK (0xFFFF0000U)
|
|
#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT (16U)
|
|
#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CSIIMAG_PARA - CSI Image Parameter Register */
|
|
/*! @{ */
|
|
#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK (0xFFFFU)
|
|
#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT (0U)
|
|
#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK)
|
|
#define CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK (0xFFFF0000U)
|
|
#define CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT (16U)
|
|
#define CSI_CSIIMAG_PARA_IMAGE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CSICR18 - CSI Control Register 18 */
|
|
/*! @{ */
|
|
#define CSI_CSICR18_DEINTERLACE_EN_MASK (0x4U)
|
|
#define CSI_CSICR18_DEINTERLACE_EN_SHIFT (2U)
|
|
/*! DEINTERLACE_EN
|
|
* 0b0..Deinterlace disabled
|
|
* 0b1..Deinterlace enabled
|
|
*/
|
|
#define CSI_CSICR18_DEINTERLACE_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DEINTERLACE_EN_SHIFT)) & CSI_CSICR18_DEINTERLACE_EN_MASK)
|
|
#define CSI_CSICR18_PARALLEL24_EN_MASK (0x8U)
|
|
#define CSI_CSICR18_PARALLEL24_EN_SHIFT (3U)
|
|
#define CSI_CSICR18_PARALLEL24_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_PARALLEL24_EN_SHIFT)) & CSI_CSICR18_PARALLEL24_EN_MASK)
|
|
#define CSI_CSICR18_BASEADDR_SWITCH_EN_MASK (0x10U)
|
|
#define CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT (4U)
|
|
#define CSI_CSICR18_BASEADDR_SWITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_EN_MASK)
|
|
#define CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK (0x20U)
|
|
#define CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT (5U)
|
|
/*! BASEADDR_SWITCH_SEL
|
|
* 0b0..Switching base address at the edge of the vsync
|
|
* 0b1..Switching base address at the edge of the first data of each frame
|
|
*/
|
|
#define CSI_CSICR18_BASEADDR_SWITCH_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK)
|
|
#define CSI_CSICR18_FIELD0_DONE_IE_MASK (0x40U)
|
|
#define CSI_CSICR18_FIELD0_DONE_IE_SHIFT (6U)
|
|
/*! FIELD0_DONE_IE
|
|
* 0b0..Interrupt disabled
|
|
* 0b1..Interrupt enabled
|
|
*/
|
|
#define CSI_CSICR18_FIELD0_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_FIELD0_DONE_IE_SHIFT)) & CSI_CSICR18_FIELD0_DONE_IE_MASK)
|
|
#define CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK (0x80U)
|
|
#define CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT (7U)
|
|
/*! DMA_FIELD1_DONE_IE
|
|
* 0b0..Interrupt disabled
|
|
* 0b1..Interrupt enabled
|
|
*/
|
|
#define CSI_CSICR18_DMA_FIELD1_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT)) & CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK)
|
|
#define CSI_CSICR18_LAST_DMA_REQ_SEL_MASK (0x100U)
|
|
#define CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT (8U)
|
|
/*! LAST_DMA_REQ_SEL
|
|
* 0b0..fifo_full_level
|
|
* 0b1..hburst_length
|
|
*/
|
|
#define CSI_CSICR18_LAST_DMA_REQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT)) & CSI_CSICR18_LAST_DMA_REQ_SEL_MASK)
|
|
#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK (0x200U)
|
|
#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT (9U)
|
|
#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT)) & CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK)
|
|
#define CSI_CSICR18_RGB888A_FORMAT_SEL_MASK (0x400U)
|
|
#define CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT (10U)
|
|
/*! RGB888A_FORMAT_SEL
|
|
* 0b0..{8'h0, data[23:0]}
|
|
* 0b1..{data[23:0], 8'h0}
|
|
*/
|
|
#define CSI_CSICR18_RGB888A_FORMAT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT)) & CSI_CSICR18_RGB888A_FORMAT_SEL_MASK)
|
|
#define CSI_CSICR18_AHB_HPROT_MASK (0xF000U)
|
|
#define CSI_CSICR18_AHB_HPROT_SHIFT (12U)
|
|
#define CSI_CSICR18_AHB_HPROT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_AHB_HPROT_SHIFT)) & CSI_CSICR18_AHB_HPROT_MASK)
|
|
#define CSI_CSICR18_MASK_OPTION_MASK (0xC0000U)
|
|
#define CSI_CSICR18_MASK_OPTION_SHIFT (18U)
|
|
/*! MASK_OPTION
|
|
* 0b00..Writing to memory from first completely frame, when using this option, the CSI_ENABLE should be 1.
|
|
* 0b01..Writing to memory when CSI_ENABLE is 1.
|
|
* 0b10..Writing to memory from second completely frame, when using this option, the CSI_ENABLE should be 1.
|
|
* 0b11..Writing to memory when data comes in, not matter the CSI_ENABLE is 1 or 0.
|
|
*/
|
|
#define CSI_CSICR18_MASK_OPTION(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_MASK_OPTION_SHIFT)) & CSI_CSICR18_MASK_OPTION_MASK)
|
|
#define CSI_CSICR18_CSI_ENABLE_MASK (0x80000000U)
|
|
#define CSI_CSICR18_CSI_ENABLE_SHIFT (31U)
|
|
#define CSI_CSICR18_CSI_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_CSI_ENABLE_SHIFT)) & CSI_CSICR18_CSI_ENABLE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CSICR19 - CSI Control Register 19 */
|
|
/*! @{ */
|
|
#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK (0xFFU)
|
|
#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT (0U)
|
|
#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT)) & CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group CSI_Register_Masks */
|
|
|
|
|
|
/* CSI - Peripheral instance base addresses */
|
|
/** Peripheral CSI base address */
|
|
#define CSI_BASE (0x402BC000u)
|
|
/** Peripheral CSI base pointer */
|
|
#define CSI ((CSI_Type *)CSI_BASE)
|
|
/** Array initializer of CSI peripheral base addresses */
|
|
#define CSI_BASE_ADDRS { CSI_BASE }
|
|
/** Array initializer of CSI peripheral base pointers */
|
|
#define CSI_BASE_PTRS { CSI }
|
|
/** Interrupt vectors for the CSI peripheral type */
|
|
#define CSI_IRQS { CSI_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group CSI_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- CSU Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup CSU_Peripheral_Access_Layer CSU Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** CSU - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t CSL[32]; /**< Config security level register, array offset: 0x0, array step: 0x4 */
|
|
uint8_t RESERVED_0[384];
|
|
__IO uint32_t HP0; /**< HP0 register, offset: 0x200 */
|
|
uint8_t RESERVED_1[20];
|
|
__IO uint32_t SA; /**< Secure access register, offset: 0x218 */
|
|
uint8_t RESERVED_2[316];
|
|
__IO uint32_t HPCONTROL0; /**< HPCONTROL0 register, offset: 0x358 */
|
|
} CSU_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- CSU Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup CSU_Register_Masks CSU Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name CSL - Config security level register */
|
|
/*! @{ */
|
|
#define CSU_CSL_SUR_S2_MASK (0x1U)
|
|
#define CSU_CSL_SUR_S2_SHIFT (0U)
|
|
/*! SUR_S2
|
|
* 0b0..The secure user read access is disabled for the second slave.
|
|
* 0b1..The secure user read access is enabled for the second slave.
|
|
*/
|
|
#define CSU_CSL_SUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S2_SHIFT)) & CSU_CSL_SUR_S2_MASK)
|
|
#define CSU_CSL_SSR_S2_MASK (0x2U)
|
|
#define CSU_CSL_SSR_S2_SHIFT (1U)
|
|
/*! SSR_S2
|
|
* 0b0..The secure supervisor read access is disabled for the second slave.
|
|
* 0b1..The secure supervisor read access is enabled for the second slave.
|
|
*/
|
|
#define CSU_CSL_SSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S2_SHIFT)) & CSU_CSL_SSR_S2_MASK)
|
|
#define CSU_CSL_NUR_S2_MASK (0x4U)
|
|
#define CSU_CSL_NUR_S2_SHIFT (2U)
|
|
/*! NUR_S2
|
|
* 0b0..The non-secure user read access is disabled for the second slave.
|
|
* 0b1..The non-secure user read access is enabled for the second slave.
|
|
*/
|
|
#define CSU_CSL_NUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S2_SHIFT)) & CSU_CSL_NUR_S2_MASK)
|
|
#define CSU_CSL_NSR_S2_MASK (0x8U)
|
|
#define CSU_CSL_NSR_S2_SHIFT (3U)
|
|
/*! NSR_S2
|
|
* 0b0..The non-secure supervisor read access is disabled for the second slave.
|
|
* 0b1..The non-secure supervisor read access is enabled for the second slave.
|
|
*/
|
|
#define CSU_CSL_NSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S2_SHIFT)) & CSU_CSL_NSR_S2_MASK)
|
|
#define CSU_CSL_SUW_S2_MASK (0x10U)
|
|
#define CSU_CSL_SUW_S2_SHIFT (4U)
|
|
/*! SUW_S2
|
|
* 0b0..The secure user write access is disabled for the second slave.
|
|
* 0b1..The secure user write access is enabled for the second slave.
|
|
*/
|
|
#define CSU_CSL_SUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S2_SHIFT)) & CSU_CSL_SUW_S2_MASK)
|
|
#define CSU_CSL_SSW_S2_MASK (0x20U)
|
|
#define CSU_CSL_SSW_S2_SHIFT (5U)
|
|
/*! SSW_S2
|
|
* 0b0..The secure supervisor write access is disabled for the second slave.
|
|
* 0b1..The secure supervisor write access is enabled for the second slave.
|
|
*/
|
|
#define CSU_CSL_SSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S2_SHIFT)) & CSU_CSL_SSW_S2_MASK)
|
|
#define CSU_CSL_NUW_S2_MASK (0x40U)
|
|
#define CSU_CSL_NUW_S2_SHIFT (6U)
|
|
/*! NUW_S2
|
|
* 0b0..The non-secure user write access is disabled for the second slave.
|
|
* 0b1..The non-secure user write access is enabled for the second slave.
|
|
*/
|
|
#define CSU_CSL_NUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S2_SHIFT)) & CSU_CSL_NUW_S2_MASK)
|
|
#define CSU_CSL_NSW_S2_MASK (0x80U)
|
|
#define CSU_CSL_NSW_S2_SHIFT (7U)
|
|
/*! NSW_S2
|
|
* 0b0..The non-secure supervisor write access is disabled for the second slave.
|
|
* 0b1..The non-secure supervisor write access is enabled for the second slave.
|
|
*/
|
|
#define CSU_CSL_NSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S2_SHIFT)) & CSU_CSL_NSW_S2_MASK)
|
|
#define CSU_CSL_LOCK_S2_MASK (0x100U)
|
|
#define CSU_CSL_LOCK_S2_SHIFT (8U)
|
|
/*! LOCK_S2
|
|
* 0b0..Not locked. Bits 7-0 can be written by the software.
|
|
* 0b1..Bits 7-0 are locked and cannot be written by the software
|
|
*/
|
|
#define CSU_CSL_LOCK_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S2_SHIFT)) & CSU_CSL_LOCK_S2_MASK)
|
|
#define CSU_CSL_SUR_S1_MASK (0x10000U)
|
|
#define CSU_CSL_SUR_S1_SHIFT (16U)
|
|
/*! SUR_S1
|
|
* 0b0..The secure user read access is disabled for the first slave.
|
|
* 0b1..The secure user read access is enabled for the first slave.
|
|
*/
|
|
#define CSU_CSL_SUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S1_SHIFT)) & CSU_CSL_SUR_S1_MASK)
|
|
#define CSU_CSL_SSR_S1_MASK (0x20000U)
|
|
#define CSU_CSL_SSR_S1_SHIFT (17U)
|
|
/*! SSR_S1
|
|
* 0b0..The secure supervisor read access is disabled for the first slave.
|
|
* 0b1..The secure supervisor read access is enabled for the first slave.
|
|
*/
|
|
#define CSU_CSL_SSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S1_SHIFT)) & CSU_CSL_SSR_S1_MASK)
|
|
#define CSU_CSL_NUR_S1_MASK (0x40000U)
|
|
#define CSU_CSL_NUR_S1_SHIFT (18U)
|
|
/*! NUR_S1
|
|
* 0b0..The non-secure user read access is disabled for the first slave.
|
|
* 0b1..The non-secure user read access is enabled for the first slave.
|
|
*/
|
|
#define CSU_CSL_NUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S1_SHIFT)) & CSU_CSL_NUR_S1_MASK)
|
|
#define CSU_CSL_NSR_S1_MASK (0x80000U)
|
|
#define CSU_CSL_NSR_S1_SHIFT (19U)
|
|
/*! NSR_S1
|
|
* 0b0..The non-secure supervisor read access is disabled for the first slave.
|
|
* 0b1..The non-secure supervisor read access is enabled for the first slave.
|
|
*/
|
|
#define CSU_CSL_NSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S1_SHIFT)) & CSU_CSL_NSR_S1_MASK)
|
|
#define CSU_CSL_SUW_S1_MASK (0x100000U)
|
|
#define CSU_CSL_SUW_S1_SHIFT (20U)
|
|
/*! SUW_S1
|
|
* 0b0..The secure user write access is disabled for the first slave.
|
|
* 0b1..The secure user write access is enabled for the first slave.
|
|
*/
|
|
#define CSU_CSL_SUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S1_SHIFT)) & CSU_CSL_SUW_S1_MASK)
|
|
#define CSU_CSL_SSW_S1_MASK (0x200000U)
|
|
#define CSU_CSL_SSW_S1_SHIFT (21U)
|
|
/*! SSW_S1
|
|
* 0b0..The secure supervisor write access is disabled for the first slave.
|
|
* 0b1..The secure supervisor write access is enabled for the first slave.
|
|
*/
|
|
#define CSU_CSL_SSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S1_SHIFT)) & CSU_CSL_SSW_S1_MASK)
|
|
#define CSU_CSL_NUW_S1_MASK (0x400000U)
|
|
#define CSU_CSL_NUW_S1_SHIFT (22U)
|
|
/*! NUW_S1
|
|
* 0b0..The non-secure user write access is disabled for the first slave.
|
|
* 0b1..The non-secure user write access is enabled for the first slave.
|
|
*/
|
|
#define CSU_CSL_NUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S1_SHIFT)) & CSU_CSL_NUW_S1_MASK)
|
|
#define CSU_CSL_NSW_S1_MASK (0x800000U)
|
|
#define CSU_CSL_NSW_S1_SHIFT (23U)
|
|
/*! NSW_S1
|
|
* 0b0..The non-secure supervisor write access is disabled for the first slave.
|
|
* 0b1..The non-secure supervisor write access is enabled for the first slave
|
|
*/
|
|
#define CSU_CSL_NSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S1_SHIFT)) & CSU_CSL_NSW_S1_MASK)
|
|
#define CSU_CSL_LOCK_S1_MASK (0x1000000U)
|
|
#define CSU_CSL_LOCK_S1_SHIFT (24U)
|
|
/*! LOCK_S1
|
|
* 0b0..Not locked. The bits 16-23 can be written by the software.
|
|
* 0b1..The bits 16-23 are locked and can't be written by the software.
|
|
*/
|
|
#define CSU_CSL_LOCK_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S1_SHIFT)) & CSU_CSL_LOCK_S1_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of CSU_CSL */
|
|
#define CSU_CSL_COUNT (32U)
|
|
|
|
/*! @name HP0 - HP0 register */
|
|
/*! @{ */
|
|
#define CSU_HP0_HP_DMA_MASK (0x4U)
|
|
#define CSU_HP0_HP_DMA_SHIFT (2U)
|
|
/*! HP_DMA
|
|
* 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
|
|
* 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
|
|
*/
|
|
#define CSU_HP0_HP_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DMA_SHIFT)) & CSU_HP0_HP_DMA_MASK)
|
|
#define CSU_HP0_L_DMA_MASK (0x8U)
|
|
#define CSU_HP0_L_DMA_SHIFT (3U)
|
|
/*! L_DMA
|
|
* 0b0..No lock-the adjacent (next lower) bit can be written by the software.
|
|
* 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
|
|
*/
|
|
#define CSU_HP0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DMA_SHIFT)) & CSU_HP0_L_DMA_MASK)
|
|
#define CSU_HP0_HP_LCDIF_MASK (0x10U)
|
|
#define CSU_HP0_HP_LCDIF_SHIFT (4U)
|
|
/*! HP_LCDIF
|
|
* 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
|
|
* 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
|
|
*/
|
|
#define CSU_HP0_HP_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_LCDIF_SHIFT)) & CSU_HP0_HP_LCDIF_MASK)
|
|
#define CSU_HP0_L_LCDIF_MASK (0x20U)
|
|
#define CSU_HP0_L_LCDIF_SHIFT (5U)
|
|
/*! L_LCDIF
|
|
* 0b0..No lock-the adjacent (next lower) bit can be written by the software.
|
|
* 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
|
|
*/
|
|
#define CSU_HP0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_LCDIF_SHIFT)) & CSU_HP0_L_LCDIF_MASK)
|
|
#define CSU_HP0_HP_CSI_MASK (0x40U)
|
|
#define CSU_HP0_HP_CSI_SHIFT (6U)
|
|
/*! HP_CSI
|
|
* 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
|
|
* 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
|
|
*/
|
|
#define CSU_HP0_HP_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_CSI_SHIFT)) & CSU_HP0_HP_CSI_MASK)
|
|
#define CSU_HP0_L_CSI_MASK (0x80U)
|
|
#define CSU_HP0_L_CSI_SHIFT (7U)
|
|
/*! L_CSI
|
|
* 0b0..No lock-the adjacent (next lower) bit can be written by the software.
|
|
* 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
|
|
*/
|
|
#define CSU_HP0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_CSI_SHIFT)) & CSU_HP0_L_CSI_MASK)
|
|
#define CSU_HP0_HP_PXP_MASK (0x100U)
|
|
#define CSU_HP0_HP_PXP_SHIFT (8U)
|
|
/*! HP_PXP
|
|
* 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
|
|
* 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
|
|
*/
|
|
#define CSU_HP0_HP_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_PXP_SHIFT)) & CSU_HP0_HP_PXP_MASK)
|
|
#define CSU_HP0_L_PXP_MASK (0x200U)
|
|
#define CSU_HP0_L_PXP_SHIFT (9U)
|
|
/*! L_PXP
|
|
* 0b0..No lock-the adjacent (next lower) bit can be written by the software.
|
|
* 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
|
|
*/
|
|
#define CSU_HP0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_PXP_SHIFT)) & CSU_HP0_L_PXP_MASK)
|
|
#define CSU_HP0_HP_DCP_MASK (0x400U)
|
|
#define CSU_HP0_HP_DCP_SHIFT (10U)
|
|
/*! HP_DCP
|
|
* 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
|
|
* 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
|
|
*/
|
|
#define CSU_HP0_HP_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DCP_SHIFT)) & CSU_HP0_HP_DCP_MASK)
|
|
#define CSU_HP0_L_DCP_MASK (0x800U)
|
|
#define CSU_HP0_L_DCP_SHIFT (11U)
|
|
/*! L_DCP
|
|
* 0b0..No lock-the adjacent (next lower) bit can be written by the software.
|
|
* 0b1..Lock-the adjacent (next lower) bit cannot be written by the software.
|
|
*/
|
|
#define CSU_HP0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DCP_SHIFT)) & CSU_HP0_L_DCP_MASK)
|
|
#define CSU_HP0_HP_ENET_MASK (0x4000U)
|
|
#define CSU_HP0_HP_ENET_SHIFT (14U)
|
|
/*! HP_ENET
|
|
* 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
|
|
* 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
|
|
*/
|
|
#define CSU_HP0_HP_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_ENET_SHIFT)) & CSU_HP0_HP_ENET_MASK)
|
|
#define CSU_HP0_L_ENET_MASK (0x8000U)
|
|
#define CSU_HP0_L_ENET_SHIFT (15U)
|
|
/*! L_ENET
|
|
* 0b0..No lock-the adjacent (next lower) bit can be written by the software.
|
|
* 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
|
|
*/
|
|
#define CSU_HP0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_ENET_SHIFT)) & CSU_HP0_L_ENET_MASK)
|
|
#define CSU_HP0_HP_USDHC1_MASK (0x10000U)
|
|
#define CSU_HP0_HP_USDHC1_SHIFT (16U)
|
|
/*! HP_USDHC1
|
|
* 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
|
|
* 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
|
|
*/
|
|
#define CSU_HP0_HP_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC1_SHIFT)) & CSU_HP0_HP_USDHC1_MASK)
|
|
#define CSU_HP0_L_USDHC1_MASK (0x20000U)
|
|
#define CSU_HP0_L_USDHC1_SHIFT (17U)
|
|
/*! L_USDHC1
|
|
* 0b0..No lock-the adjacent (next lower) bit can be written by the software.
|
|
* 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
|
|
*/
|
|
#define CSU_HP0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC1_SHIFT)) & CSU_HP0_L_USDHC1_MASK)
|
|
#define CSU_HP0_HP_USDHC2_MASK (0x40000U)
|
|
#define CSU_HP0_HP_USDHC2_SHIFT (18U)
|
|
/*! HP_USDHC2
|
|
* 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
|
|
* 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
|
|
*/
|
|
#define CSU_HP0_HP_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC2_SHIFT)) & CSU_HP0_HP_USDHC2_MASK)
|
|
#define CSU_HP0_L_USDHC2_MASK (0x80000U)
|
|
#define CSU_HP0_L_USDHC2_SHIFT (19U)
|
|
/*! L_USDHC2
|
|
* 0b0..No lock-the adjacent (next lower) bit can be written by the software.
|
|
* 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
|
|
*/
|
|
#define CSU_HP0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC2_SHIFT)) & CSU_HP0_L_USDHC2_MASK)
|
|
#define CSU_HP0_HP_TPSMP_MASK (0x100000U)
|
|
#define CSU_HP0_HP_TPSMP_SHIFT (20U)
|
|
/*! HP_TPSMP
|
|
* 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
|
|
* 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
|
|
*/
|
|
#define CSU_HP0_HP_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_TPSMP_SHIFT)) & CSU_HP0_HP_TPSMP_MASK)
|
|
#define CSU_HP0_L_TPSMP_MASK (0x200000U)
|
|
#define CSU_HP0_L_TPSMP_SHIFT (21U)
|
|
/*! L_TPSMP
|
|
* 0b0..No lock-the adjacent (next lower) bit can be written by the software.
|
|
* 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
|
|
*/
|
|
#define CSU_HP0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_TPSMP_SHIFT)) & CSU_HP0_L_TPSMP_MASK)
|
|
#define CSU_HP0_HP_USB_MASK (0x400000U)
|
|
#define CSU_HP0_HP_USB_SHIFT (22U)
|
|
/*! HP_USB
|
|
* 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
|
|
* 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
|
|
*/
|
|
#define CSU_HP0_HP_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USB_SHIFT)) & CSU_HP0_HP_USB_MASK)
|
|
#define CSU_HP0_L_USB_MASK (0x800000U)
|
|
#define CSU_HP0_L_USB_SHIFT (23U)
|
|
/*! L_USB
|
|
* 0b0..No lock-the adjacent (next lower) bit can be written by the software.
|
|
* 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
|
|
*/
|
|
#define CSU_HP0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USB_SHIFT)) & CSU_HP0_L_USB_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SA - Secure access register */
|
|
/*! @{ */
|
|
#define CSU_SA_NSA_DMA_MASK (0x4U)
|
|
#define CSU_SA_NSA_DMA_SHIFT (2U)
|
|
/*! NSA_DMA - Non-secure access policy indicator bit
|
|
* 0b0..Secure access for the corresponding type-1 master
|
|
* 0b1..Non-secure access for the corresponding type-1 master
|
|
*/
|
|
#define CSU_SA_NSA_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DMA_SHIFT)) & CSU_SA_NSA_DMA_MASK)
|
|
#define CSU_SA_L_DMA_MASK (0x8U)
|
|
#define CSU_SA_L_DMA_SHIFT (3U)
|
|
/*! L_DMA
|
|
* 0b0..No lock-the adjacent (next lower) bit can be written by the software.
|
|
* 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
|
|
*/
|
|
#define CSU_SA_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DMA_SHIFT)) & CSU_SA_L_DMA_MASK)
|
|
#define CSU_SA_NSA_LCDIF_MASK (0x10U)
|
|
#define CSU_SA_NSA_LCDIF_SHIFT (4U)
|
|
/*! NSA_LCDIF - Non-secure access policy indicator bit
|
|
* 0b0..Secure access for the corresponding type-1 master
|
|
* 0b1..Non-secure access for the corresponding type-1 master
|
|
*/
|
|
#define CSU_SA_NSA_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_LCDIF_SHIFT)) & CSU_SA_NSA_LCDIF_MASK)
|
|
#define CSU_SA_L_LCDIF_MASK (0x20U)
|
|
#define CSU_SA_L_LCDIF_SHIFT (5U)
|
|
/*! L_LCDIF
|
|
* 0b0..No lock-the adjacent (next lower) bit can be written by the software.
|
|
* 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
|
|
*/
|
|
#define CSU_SA_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_LCDIF_SHIFT)) & CSU_SA_L_LCDIF_MASK)
|
|
#define CSU_SA_NSA_CSI_MASK (0x40U)
|
|
#define CSU_SA_NSA_CSI_SHIFT (6U)
|
|
/*! NSA_CSI - Non-secure access policy indicator bit
|
|
* 0b0..Secure access for the corresponding type-1 master
|
|
* 0b1..Non-secure access for the corresponding type-1 master
|
|
*/
|
|
#define CSU_SA_NSA_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_CSI_SHIFT)) & CSU_SA_NSA_CSI_MASK)
|
|
#define CSU_SA_L_CSI_MASK (0x80U)
|
|
#define CSU_SA_L_CSI_SHIFT (7U)
|
|
/*! L_CSI
|
|
* 0b0..No lock-the adjacent (next lower) bit can be written by the software.
|
|
* 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
|
|
*/
|
|
#define CSU_SA_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_CSI_SHIFT)) & CSU_SA_L_CSI_MASK)
|
|
#define CSU_SA_NSA_PXP_MASK (0x100U)
|
|
#define CSU_SA_NSA_PXP_SHIFT (8U)
|
|
/*! NSA_PXP - Non-Secure Access Policy indicator bit
|
|
* 0b0..Secure access for the corresponding type-1 master
|
|
* 0b1..Non-secure access for the corresponding type-1 master
|
|
*/
|
|
#define CSU_SA_NSA_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_PXP_SHIFT)) & CSU_SA_NSA_PXP_MASK)
|
|
#define CSU_SA_L_PXP_MASK (0x200U)
|
|
#define CSU_SA_L_PXP_SHIFT (9U)
|
|
/*! L_PXP
|
|
* 0b0..No lock-the adjacent (next lower) bit can be written by the software.
|
|
* 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
|
|
*/
|
|
#define CSU_SA_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_PXP_SHIFT)) & CSU_SA_L_PXP_MASK)
|
|
#define CSU_SA_NSA_DCP_MASK (0x400U)
|
|
#define CSU_SA_NSA_DCP_SHIFT (10U)
|
|
/*! NSA_DCP - Non-secure access policy indicator bit
|
|
* 0b0..Secure access for the corresponding type-1 master
|
|
* 0b1..Non-secure access for the corresponding type-1 master
|
|
*/
|
|
#define CSU_SA_NSA_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DCP_SHIFT)) & CSU_SA_NSA_DCP_MASK)
|
|
#define CSU_SA_L_DCP_MASK (0x800U)
|
|
#define CSU_SA_L_DCP_SHIFT (11U)
|
|
/*! L_DCP
|
|
* 0b0..No lock-the adjacent (next lower) bit can be written by the software.
|
|
* 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
|
|
*/
|
|
#define CSU_SA_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DCP_SHIFT)) & CSU_SA_L_DCP_MASK)
|
|
#define CSU_SA_NSA_ENET_MASK (0x4000U)
|
|
#define CSU_SA_NSA_ENET_SHIFT (14U)
|
|
/*! NSA_ENET - Non-secure access policy indicator bit
|
|
* 0b0..Secure access for the corresponding type-1 master
|
|
* 0b1..Non-secure access for the corresponding type-1 master
|
|
*/
|
|
#define CSU_SA_NSA_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_ENET_SHIFT)) & CSU_SA_NSA_ENET_MASK)
|
|
#define CSU_SA_L_ENET_MASK (0x8000U)
|
|
#define CSU_SA_L_ENET_SHIFT (15U)
|
|
/*! L_ENET
|
|
* 0b0..No lock-the adjacent (next lower) bit can be written by the software.
|
|
* 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
|
|
*/
|
|
#define CSU_SA_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_ENET_SHIFT)) & CSU_SA_L_ENET_MASK)
|
|
#define CSU_SA_NSA_USDHC1_MASK (0x10000U)
|
|
#define CSU_SA_NSA_USDHC1_SHIFT (16U)
|
|
/*! NSA_USDHC1 - Non-secure access policy indicator bit
|
|
* 0b0..Secure access for the corresponding type-1 master
|
|
* 0b1..Non-secure access for the corresponding type-1 master
|
|
*/
|
|
#define CSU_SA_NSA_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC1_SHIFT)) & CSU_SA_NSA_USDHC1_MASK)
|
|
#define CSU_SA_L_USDHC1_MASK (0x20000U)
|
|
#define CSU_SA_L_USDHC1_SHIFT (17U)
|
|
/*! L_USDHC1
|
|
* 0b0..No lock-the adjacent (next lower) bit can be written by the software.
|
|
* 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
|
|
*/
|
|
#define CSU_SA_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC1_SHIFT)) & CSU_SA_L_USDHC1_MASK)
|
|
#define CSU_SA_NSA_USDHC2_MASK (0x40000U)
|
|
#define CSU_SA_NSA_USDHC2_SHIFT (18U)
|
|
/*! NSA_USDHC2 - Non-secure access policy indicator bit
|
|
* 0b0..Secure access for the corresponding type-1 master
|
|
* 0b1..Non-secure access for the corresponding type-1 master
|
|
*/
|
|
#define CSU_SA_NSA_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC2_SHIFT)) & CSU_SA_NSA_USDHC2_MASK)
|
|
#define CSU_SA_L_USDHC2_MASK (0x80000U)
|
|
#define CSU_SA_L_USDHC2_SHIFT (19U)
|
|
/*! L_USDHC2
|
|
* 0b0..No lock-the adjacent (next lower) bit can be written by the software.
|
|
* 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
|
|
*/
|
|
#define CSU_SA_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC2_SHIFT)) & CSU_SA_L_USDHC2_MASK)
|
|
#define CSU_SA_NSA_TPSMP_MASK (0x100000U)
|
|
#define CSU_SA_NSA_TPSMP_SHIFT (20U)
|
|
/*! NSA_TPSMP - Non-secure access policy indicator bit
|
|
* 0b0..Secure access for the corresponding type-1 master
|
|
* 0b1..Non-secure access for the corresponding type-1 master
|
|
*/
|
|
#define CSU_SA_NSA_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_TPSMP_SHIFT)) & CSU_SA_NSA_TPSMP_MASK)
|
|
#define CSU_SA_L_TPSMP_MASK (0x200000U)
|
|
#define CSU_SA_L_TPSMP_SHIFT (21U)
|
|
/*! L_TPSMP
|
|
* 0b0..No lock-the adjacent (next lower) bit can be written by the software.
|
|
* 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
|
|
*/
|
|
#define CSU_SA_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_TPSMP_SHIFT)) & CSU_SA_L_TPSMP_MASK)
|
|
#define CSU_SA_NSA_USB_MASK (0x400000U)
|
|
#define CSU_SA_NSA_USB_SHIFT (22U)
|
|
/*! NSA_USB - Non-secure access policy indicator bit
|
|
* 0b0..Secure access for the corresponding type-1 master
|
|
* 0b1..Non-secure access for the corresponding type-1 master
|
|
*/
|
|
#define CSU_SA_NSA_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USB_SHIFT)) & CSU_SA_NSA_USB_MASK)
|
|
#define CSU_SA_L_USB_MASK (0x800000U)
|
|
#define CSU_SA_L_USB_SHIFT (23U)
|
|
/*! L_USB
|
|
* 0b0..No lock-the adjacent (next lower) bit can be written by the software.
|
|
* 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
|
|
*/
|
|
#define CSU_SA_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USB_SHIFT)) & CSU_SA_L_USB_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name HPCONTROL0 - HPCONTROL0 register */
|
|
/*! @{ */
|
|
#define CSU_HPCONTROL0_HPC_DMA_MASK (0x4U)
|
|
#define CSU_HPCONTROL0_HPC_DMA_SHIFT (2U)
|
|
/*! HPC_DMA
|
|
* 0b0..User mode for the corresponding master
|
|
* 0b1..Supervisor mode for the corresponding master
|
|
*/
|
|
#define CSU_HPCONTROL0_HPC_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DMA_SHIFT)) & CSU_HPCONTROL0_HPC_DMA_MASK)
|
|
#define CSU_HPCONTROL0_L_DMA_MASK (0x8U)
|
|
#define CSU_HPCONTROL0_L_DMA_SHIFT (3U)
|
|
/*! L_DMA
|
|
* 0b0..No lock-the adjacent (next lower) bit can be written by the software.
|
|
* 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
|
|
*/
|
|
#define CSU_HPCONTROL0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DMA_SHIFT)) & CSU_HPCONTROL0_L_DMA_MASK)
|
|
#define CSU_HPCONTROL0_HPC_LCDIF_MASK (0x10U)
|
|
#define CSU_HPCONTROL0_HPC_LCDIF_SHIFT (4U)
|
|
/*! HPC_LCDIF
|
|
* 0b0..User mode for the corresponding master
|
|
* 0b1..Supervisor mode for the corresponding master
|
|
*/
|
|
#define CSU_HPCONTROL0_HPC_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_LCDIF_SHIFT)) & CSU_HPCONTROL0_HPC_LCDIF_MASK)
|
|
#define CSU_HPCONTROL0_L_LCDIF_MASK (0x20U)
|
|
#define CSU_HPCONTROL0_L_LCDIF_SHIFT (5U)
|
|
/*! L_LCDIF
|
|
* 0b0..No lock-the adjacent (next lower) bit can be written by the software.
|
|
* 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
|
|
*/
|
|
#define CSU_HPCONTROL0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_LCDIF_SHIFT)) & CSU_HPCONTROL0_L_LCDIF_MASK)
|
|
#define CSU_HPCONTROL0_HPC_CSI_MASK (0x40U)
|
|
#define CSU_HPCONTROL0_HPC_CSI_SHIFT (6U)
|
|
/*! HPC_CSI
|
|
* 0b0..User mode for the corresponding master
|
|
* 0b1..Supervisor mode for the corresponding master
|
|
*/
|
|
#define CSU_HPCONTROL0_HPC_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_CSI_SHIFT)) & CSU_HPCONTROL0_HPC_CSI_MASK)
|
|
#define CSU_HPCONTROL0_L_CSI_MASK (0x80U)
|
|
#define CSU_HPCONTROL0_L_CSI_SHIFT (7U)
|
|
/*! L_CSI
|
|
* 0b0..No lock-the adjacent (next lower) bit can be written by the software.
|
|
* 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
|
|
*/
|
|
#define CSU_HPCONTROL0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_CSI_SHIFT)) & CSU_HPCONTROL0_L_CSI_MASK)
|
|
#define CSU_HPCONTROL0_HPC_PXP_MASK (0x100U)
|
|
#define CSU_HPCONTROL0_HPC_PXP_SHIFT (8U)
|
|
/*! HPC_PXP
|
|
* 0b0..User mode for the corresponding master
|
|
* 0b1..Supervisor mode for the corresponding master
|
|
*/
|
|
#define CSU_HPCONTROL0_HPC_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_PXP_SHIFT)) & CSU_HPCONTROL0_HPC_PXP_MASK)
|
|
#define CSU_HPCONTROL0_L_PXP_MASK (0x200U)
|
|
#define CSU_HPCONTROL0_L_PXP_SHIFT (9U)
|
|
/*! L_PXP
|
|
* 0b0..No lock-the adjacent (next lower) bit can be written by the software.
|
|
* 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
|
|
*/
|
|
#define CSU_HPCONTROL0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_PXP_SHIFT)) & CSU_HPCONTROL0_L_PXP_MASK)
|
|
#define CSU_HPCONTROL0_HPC_DCP_MASK (0x400U)
|
|
#define CSU_HPCONTROL0_HPC_DCP_SHIFT (10U)
|
|
/*! HPC_DCP
|
|
* 0b0..User mode for the corresponding master
|
|
* 0b1..Supervisor mode for the corresponding master
|
|
*/
|
|
#define CSU_HPCONTROL0_HPC_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DCP_SHIFT)) & CSU_HPCONTROL0_HPC_DCP_MASK)
|
|
#define CSU_HPCONTROL0_L_DCP_MASK (0x800U)
|
|
#define CSU_HPCONTROL0_L_DCP_SHIFT (11U)
|
|
/*! L_DCP
|
|
* 0b0..No lock-the adjacent (next lower) bit can be written by the software.
|
|
* 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
|
|
*/
|
|
#define CSU_HPCONTROL0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DCP_SHIFT)) & CSU_HPCONTROL0_L_DCP_MASK)
|
|
#define CSU_HPCONTROL0_HPC_ENET_MASK (0x4000U)
|
|
#define CSU_HPCONTROL0_HPC_ENET_SHIFT (14U)
|
|
/*! HPC_ENET
|
|
* 0b0..User mode for the corresponding master
|
|
* 0b1..Supervisor mode for the corresponding master
|
|
*/
|
|
#define CSU_HPCONTROL0_HPC_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_ENET_SHIFT)) & CSU_HPCONTROL0_HPC_ENET_MASK)
|
|
#define CSU_HPCONTROL0_L_ENET_MASK (0x8000U)
|
|
#define CSU_HPCONTROL0_L_ENET_SHIFT (15U)
|
|
/*! L_ENET
|
|
* 0b0..No lock-the adjacent (next lower) bit can be written by the software.
|
|
* 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
|
|
*/
|
|
#define CSU_HPCONTROL0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_ENET_SHIFT)) & CSU_HPCONTROL0_L_ENET_MASK)
|
|
#define CSU_HPCONTROL0_HPC_USDHC1_MASK (0x10000U)
|
|
#define CSU_HPCONTROL0_HPC_USDHC1_SHIFT (16U)
|
|
/*! HPC_USDHC1
|
|
* 0b0..User mode for the corresponding master
|
|
* 0b1..Supervisor mode for the corresponding master
|
|
*/
|
|
#define CSU_HPCONTROL0_HPC_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC1_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC1_MASK)
|
|
#define CSU_HPCONTROL0_L_USDHC1_MASK (0x20000U)
|
|
#define CSU_HPCONTROL0_L_USDHC1_SHIFT (17U)
|
|
/*! L_USDHC1
|
|
* 0b0..No lock-the adjacent (next lower) bit can be written by the software.
|
|
* 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
|
|
*/
|
|
#define CSU_HPCONTROL0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC1_SHIFT)) & CSU_HPCONTROL0_L_USDHC1_MASK)
|
|
#define CSU_HPCONTROL0_HPC_USDHC2_MASK (0x40000U)
|
|
#define CSU_HPCONTROL0_HPC_USDHC2_SHIFT (18U)
|
|
/*! HPC_USDHC2
|
|
* 0b0..User mode for the corresponding master
|
|
* 0b1..Supervisor mode for the corresponding master
|
|
*/
|
|
#define CSU_HPCONTROL0_HPC_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC2_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC2_MASK)
|
|
#define CSU_HPCONTROL0_L_USDHC2_MASK (0x80000U)
|
|
#define CSU_HPCONTROL0_L_USDHC2_SHIFT (19U)
|
|
/*! L_USDHC2
|
|
* 0b0..No lock-the adjacent (next lower) bit can be written by the software.
|
|
* 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
|
|
*/
|
|
#define CSU_HPCONTROL0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC2_SHIFT)) & CSU_HPCONTROL0_L_USDHC2_MASK)
|
|
#define CSU_HPCONTROL0_HPC_TPSMP_MASK (0x100000U)
|
|
#define CSU_HPCONTROL0_HPC_TPSMP_SHIFT (20U)
|
|
/*! HPC_TPSMP
|
|
* 0b0..User mode for the corresponding master
|
|
* 0b1..Supervisor mode for the corresponding master
|
|
*/
|
|
#define CSU_HPCONTROL0_HPC_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_TPSMP_SHIFT)) & CSU_HPCONTROL0_HPC_TPSMP_MASK)
|
|
#define CSU_HPCONTROL0_L_TPSMP_MASK (0x200000U)
|
|
#define CSU_HPCONTROL0_L_TPSMP_SHIFT (21U)
|
|
/*! L_TPSMP
|
|
* 0b0..No lock-the adjacent (next lower) bit can be written by the software.
|
|
* 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
|
|
*/
|
|
#define CSU_HPCONTROL0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_TPSMP_SHIFT)) & CSU_HPCONTROL0_L_TPSMP_MASK)
|
|
#define CSU_HPCONTROL0_HPC_USB_MASK (0x400000U)
|
|
#define CSU_HPCONTROL0_HPC_USB_SHIFT (22U)
|
|
/*! HPC_USB
|
|
* 0b0..User mode for the corresponding master
|
|
* 0b1..Supervisor mode for the corresponding master
|
|
*/
|
|
#define CSU_HPCONTROL0_HPC_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USB_SHIFT)) & CSU_HPCONTROL0_HPC_USB_MASK)
|
|
#define CSU_HPCONTROL0_L_USB_MASK (0x800000U)
|
|
#define CSU_HPCONTROL0_L_USB_SHIFT (23U)
|
|
/*! L_USB
|
|
* 0b0..No lock-the adjacent (next lower) bit can be written by the software.
|
|
* 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
|
|
*/
|
|
#define CSU_HPCONTROL0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USB_SHIFT)) & CSU_HPCONTROL0_L_USB_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group CSU_Register_Masks */
|
|
|
|
|
|
/* CSU - Peripheral instance base addresses */
|
|
/** Peripheral CSU base address */
|
|
#define CSU_BASE (0x400DC000u)
|
|
/** Peripheral CSU base pointer */
|
|
#define CSU ((CSU_Type *)CSU_BASE)
|
|
/** Array initializer of CSU peripheral base addresses */
|
|
#define CSU_BASE_ADDRS { CSU_BASE }
|
|
/** Array initializer of CSU peripheral base pointers */
|
|
#define CSU_BASE_PTRS { CSU }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group CSU_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- DCDC Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup DCDC_Peripheral_Access_Layer DCDC Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** DCDC - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t REG0; /**< DCDC Register 0, offset: 0x0 */
|
|
__IO uint32_t REG1; /**< DCDC Register 1, offset: 0x4 */
|
|
__IO uint32_t REG2; /**< DCDC Register 2, offset: 0x8 */
|
|
__IO uint32_t REG3; /**< DCDC Register 3, offset: 0xC */
|
|
} DCDC_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- DCDC Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup DCDC_Register_Masks DCDC Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name REG0 - DCDC Register 0 */
|
|
/*! @{ */
|
|
#define DCDC_REG0_PWD_ZCD_MASK (0x1U)
|
|
#define DCDC_REG0_PWD_ZCD_SHIFT (0U)
|
|
#define DCDC_REG0_PWD_ZCD(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK)
|
|
#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U)
|
|
#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT (1U)
|
|
#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)
|
|
#define DCDC_REG0_SEL_CLK_MASK (0x4U)
|
|
#define DCDC_REG0_SEL_CLK_SHIFT (2U)
|
|
#define DCDC_REG0_SEL_CLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_SEL_CLK_SHIFT)) & DCDC_REG0_SEL_CLK_MASK)
|
|
#define DCDC_REG0_PWD_OSC_INT_MASK (0x8U)
|
|
#define DCDC_REG0_PWD_OSC_INT_SHIFT (3U)
|
|
#define DCDC_REG0_PWD_OSC_INT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OSC_INT_SHIFT)) & DCDC_REG0_PWD_OSC_INT_MASK)
|
|
#define DCDC_REG0_PWD_CUR_SNS_CMP_MASK (0x10U)
|
|
#define DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT (4U)
|
|
#define DCDC_REG0_PWD_CUR_SNS_CMP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT)) & DCDC_REG0_PWD_CUR_SNS_CMP_MASK)
|
|
#define DCDC_REG0_CUR_SNS_THRSH_MASK (0xE0U)
|
|
#define DCDC_REG0_CUR_SNS_THRSH_SHIFT (5U)
|
|
#define DCDC_REG0_CUR_SNS_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)) & DCDC_REG0_CUR_SNS_THRSH_MASK)
|
|
#define DCDC_REG0_PWD_OVERCUR_DET_MASK (0x100U)
|
|
#define DCDC_REG0_PWD_OVERCUR_DET_SHIFT (8U)
|
|
#define DCDC_REG0_PWD_OVERCUR_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OVERCUR_DET_SHIFT)) & DCDC_REG0_PWD_OVERCUR_DET_MASK)
|
|
#define DCDC_REG0_OVERCUR_TRIG_ADJ_MASK (0x600U)
|
|
#define DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT (9U)
|
|
#define DCDC_REG0_OVERCUR_TRIG_ADJ(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT)) & DCDC_REG0_OVERCUR_TRIG_ADJ_MASK)
|
|
#define DCDC_REG0_PWD_CMP_BATT_DET_MASK (0x800U)
|
|
#define DCDC_REG0_PWD_CMP_BATT_DET_SHIFT (11U)
|
|
#define DCDC_REG0_PWD_CMP_BATT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_BATT_DET_SHIFT)) & DCDC_REG0_PWD_CMP_BATT_DET_MASK)
|
|
#define DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK (0xF000U)
|
|
#define DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT (12U)
|
|
#define DCDC_REG0_ADJ_POSLIMIT_BUCK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT)) & DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK)
|
|
#define DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK (0x10000U)
|
|
#define DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT (16U)
|
|
#define DCDC_REG0_EN_LP_OVERLOAD_SNS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT)) & DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK)
|
|
#define DCDC_REG0_PWD_HIGH_VOLT_DET_MASK (0x20000U)
|
|
#define DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT (17U)
|
|
#define DCDC_REG0_PWD_HIGH_VOLT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VOLT_DET_MASK)
|
|
#define DCDC_REG0_LP_OVERLOAD_THRSH_MASK (0xC0000U)
|
|
#define DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT (18U)
|
|
#define DCDC_REG0_LP_OVERLOAD_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT)) & DCDC_REG0_LP_OVERLOAD_THRSH_MASK)
|
|
#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK (0x100000U)
|
|
#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT (20U)
|
|
#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT)) & DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK)
|
|
#define DCDC_REG0_LP_HIGH_HYS_MASK (0x200000U)
|
|
#define DCDC_REG0_LP_HIGH_HYS_SHIFT (21U)
|
|
#define DCDC_REG0_LP_HIGH_HYS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_HIGH_HYS_SHIFT)) & DCDC_REG0_LP_HIGH_HYS_MASK)
|
|
#define DCDC_REG0_PWD_CMP_OFFSET_MASK (0x4000000U)
|
|
#define DCDC_REG0_PWD_CMP_OFFSET_SHIFT (26U)
|
|
#define DCDC_REG0_PWD_CMP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK)
|
|
#define DCDC_REG0_XTALOK_DISABLE_MASK (0x8000000U)
|
|
#define DCDC_REG0_XTALOK_DISABLE_SHIFT (27U)
|
|
#define DCDC_REG0_XTALOK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_XTALOK_DISABLE_MASK)
|
|
#define DCDC_REG0_CURRENT_ALERT_RESET_MASK (0x10000000U)
|
|
#define DCDC_REG0_CURRENT_ALERT_RESET_SHIFT (28U)
|
|
#define DCDC_REG0_CURRENT_ALERT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CURRENT_ALERT_RESET_SHIFT)) & DCDC_REG0_CURRENT_ALERT_RESET_MASK)
|
|
#define DCDC_REG0_XTAL_24M_OK_MASK (0x20000000U)
|
|
#define DCDC_REG0_XTAL_24M_OK_SHIFT (29U)
|
|
#define DCDC_REG0_XTAL_24M_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTAL_24M_OK_SHIFT)) & DCDC_REG0_XTAL_24M_OK_MASK)
|
|
#define DCDC_REG0_STS_DC_OK_MASK (0x80000000U)
|
|
#define DCDC_REG0_STS_DC_OK_SHIFT (31U)
|
|
#define DCDC_REG0_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name REG1 - DCDC Register 1 */
|
|
/*! @{ */
|
|
#define DCDC_REG1_REG_FBK_SEL_MASK (0x180U)
|
|
#define DCDC_REG1_REG_FBK_SEL_SHIFT (7U)
|
|
#define DCDC_REG1_REG_FBK_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_FBK_SEL_SHIFT)) & DCDC_REG1_REG_FBK_SEL_MASK)
|
|
#define DCDC_REG1_REG_RLOAD_SW_MASK (0x200U)
|
|
#define DCDC_REG1_REG_RLOAD_SW_SHIFT (9U)
|
|
#define DCDC_REG1_REG_RLOAD_SW(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_RLOAD_SW_SHIFT)) & DCDC_REG1_REG_RLOAD_SW_MASK)
|
|
#define DCDC_REG1_LP_CMP_ISRC_SEL_MASK (0x3000U)
|
|
#define DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT (12U)
|
|
#define DCDC_REG1_LP_CMP_ISRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)) & DCDC_REG1_LP_CMP_ISRC_SEL_MASK)
|
|
#define DCDC_REG1_LOOPCTRL_HST_THRESH_MASK (0x200000U)
|
|
#define DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT (21U)
|
|
#define DCDC_REG1_LOOPCTRL_HST_THRESH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_HST_THRESH_MASK)
|
|
#define DCDC_REG1_LOOPCTRL_EN_HYST_MASK (0x800000U)
|
|
#define DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT (23U)
|
|
#define DCDC_REG1_LOOPCTRL_EN_HYST(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_HYST_MASK)
|
|
#define DCDC_REG1_VBG_TRIM_MASK (0x1F000000U)
|
|
#define DCDC_REG1_VBG_TRIM_SHIFT (24U)
|
|
#define DCDC_REG1_VBG_TRIM(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name REG2 - DCDC Register 2 */
|
|
/*! @{ */
|
|
#define DCDC_REG2_LOOPCTRL_DC_C_MASK (0x3U)
|
|
#define DCDC_REG2_LOOPCTRL_DC_C_SHIFT (0U)
|
|
#define DCDC_REG2_LOOPCTRL_DC_C(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_C_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_C_MASK)
|
|
#define DCDC_REG2_LOOPCTRL_DC_R_MASK (0x3CU)
|
|
#define DCDC_REG2_LOOPCTRL_DC_R_SHIFT (2U)
|
|
#define DCDC_REG2_LOOPCTRL_DC_R(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_R_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_R_MASK)
|
|
#define DCDC_REG2_LOOPCTRL_DC_FF_MASK (0x1C0U)
|
|
#define DCDC_REG2_LOOPCTRL_DC_FF_SHIFT (6U)
|
|
#define DCDC_REG2_LOOPCTRL_DC_FF(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_FF_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_FF_MASK)
|
|
#define DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK (0xE00U)
|
|
#define DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT (9U)
|
|
#define DCDC_REG2_LOOPCTRL_EN_RCSCALE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT)) & DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK)
|
|
#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK (0x1000U)
|
|
#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT (12U)
|
|
#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT)) & DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK)
|
|
#define DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK (0x2000U)
|
|
#define DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT (13U)
|
|
#define DCDC_REG2_LOOPCTRL_HYST_SIGN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT)) & DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK)
|
|
#define DCDC_REG2_DISABLE_PULSE_SKIP_MASK (0x8000000U)
|
|
#define DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT (27U)
|
|
#define DCDC_REG2_DISABLE_PULSE_SKIP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT)) & DCDC_REG2_DISABLE_PULSE_SKIP_MASK)
|
|
#define DCDC_REG2_DCM_SET_CTRL_MASK (0x10000000U)
|
|
#define DCDC_REG2_DCM_SET_CTRL_SHIFT (28U)
|
|
#define DCDC_REG2_DCM_SET_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name REG3 - DCDC Register 3 */
|
|
/*! @{ */
|
|
#define DCDC_REG3_TRG_MASK (0x1FU)
|
|
#define DCDC_REG3_TRG_SHIFT (0U)
|
|
#define DCDC_REG3_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TRG_SHIFT)) & DCDC_REG3_TRG_MASK)
|
|
#define DCDC_REG3_TARGET_LP_MASK (0x700U)
|
|
#define DCDC_REG3_TARGET_LP_SHIFT (8U)
|
|
#define DCDC_REG3_TARGET_LP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TARGET_LP_SHIFT)) & DCDC_REG3_TARGET_LP_MASK)
|
|
#define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U)
|
|
#define DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT (24U)
|
|
#define DCDC_REG3_MINPWR_DC_HALFCLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_MINPWR_DC_HALFCLK_MASK)
|
|
#define DCDC_REG3_MISC_DELAY_TIMING_MASK (0x8000000U)
|
|
#define DCDC_REG3_MISC_DELAY_TIMING_SHIFT (27U)
|
|
#define DCDC_REG3_MISC_DELAY_TIMING(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DELAY_TIMING_SHIFT)) & DCDC_REG3_MISC_DELAY_TIMING_MASK)
|
|
#define DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK (0x10000000U)
|
|
#define DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT (28U)
|
|
#define DCDC_REG3_MISC_DISABLEFET_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT)) & DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK)
|
|
#define DCDC_REG3_DISABLE_STEP_MASK (0x40000000U)
|
|
#define DCDC_REG3_DISABLE_STEP_SHIFT (30U)
|
|
#define DCDC_REG3_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_STEP_SHIFT)) & DCDC_REG3_DISABLE_STEP_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group DCDC_Register_Masks */
|
|
|
|
|
|
/* DCDC - Peripheral instance base addresses */
|
|
/** Peripheral DCDC base address */
|
|
#define DCDC_BASE (0x40080000u)
|
|
/** Peripheral DCDC base pointer */
|
|
#define DCDC ((DCDC_Type *)DCDC_BASE)
|
|
/** Array initializer of DCDC peripheral base addresses */
|
|
#define DCDC_BASE_ADDRS { DCDC_BASE }
|
|
/** Array initializer of DCDC peripheral base pointers */
|
|
#define DCDC_BASE_PTRS { DCDC }
|
|
/** Interrupt vectors for the DCDC peripheral type */
|
|
#define DCDC_IRQS { DCDC_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group DCDC_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- DCP Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup DCP_Peripheral_Access_Layer DCP Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** DCP - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t CTRL; /**< DCP control register 0, offset: 0x0 */
|
|
uint8_t RESERVED_0[12];
|
|
__IO uint32_t STAT; /**< DCP status register, offset: 0x10 */
|
|
uint8_t RESERVED_1[12];
|
|
__IO uint32_t CHANNELCTRL; /**< DCP channel control register, offset: 0x20 */
|
|
uint8_t RESERVED_2[12];
|
|
__IO uint32_t CAPABILITY0; /**< DCP capability 0 register, offset: 0x30 */
|
|
uint8_t RESERVED_3[12];
|
|
__I uint32_t CAPABILITY1; /**< DCP capability 1 register, offset: 0x40 */
|
|
uint8_t RESERVED_4[12];
|
|
__IO uint32_t CONTEXT; /**< DCP context buffer pointer, offset: 0x50 */
|
|
uint8_t RESERVED_5[12];
|
|
__IO uint32_t KEY; /**< DCP key index, offset: 0x60 */
|
|
uint8_t RESERVED_6[12];
|
|
__IO uint32_t KEYDATA; /**< DCP key data, offset: 0x70 */
|
|
uint8_t RESERVED_7[12];
|
|
__I uint32_t PACKET0; /**< DCP work packet 0 status register, offset: 0x80 */
|
|
uint8_t RESERVED_8[12];
|
|
__I uint32_t PACKET1; /**< DCP work packet 1 status register, offset: 0x90 */
|
|
uint8_t RESERVED_9[12];
|
|
__I uint32_t PACKET2; /**< DCP work packet 2 status register, offset: 0xA0 */
|
|
uint8_t RESERVED_10[12];
|
|
__I uint32_t PACKET3; /**< DCP work packet 3 status register, offset: 0xB0 */
|
|
uint8_t RESERVED_11[12];
|
|
__I uint32_t PACKET4; /**< DCP work packet 4 status register, offset: 0xC0 */
|
|
uint8_t RESERVED_12[12];
|
|
__I uint32_t PACKET5; /**< DCP work packet 5 status register, offset: 0xD0 */
|
|
uint8_t RESERVED_13[12];
|
|
__I uint32_t PACKET6; /**< DCP work packet 6 status register, offset: 0xE0 */
|
|
uint8_t RESERVED_14[28];
|
|
__IO uint32_t CH0CMDPTR; /**< DCP channel 0 command pointer address register, offset: 0x100 */
|
|
uint8_t RESERVED_15[12];
|
|
__IO uint32_t CH0SEMA; /**< DCP channel 0 semaphore register, offset: 0x110 */
|
|
uint8_t RESERVED_16[12];
|
|
__IO uint32_t CH0STAT; /**< DCP channel 0 status register, offset: 0x120 */
|
|
uint8_t RESERVED_17[12];
|
|
__IO uint32_t CH0OPTS; /**< DCP channel 0 options register, offset: 0x130 */
|
|
uint8_t RESERVED_18[12];
|
|
__IO uint32_t CH1CMDPTR; /**< DCP channel 1 command pointer address register, offset: 0x140 */
|
|
uint8_t RESERVED_19[12];
|
|
__IO uint32_t CH1SEMA; /**< DCP channel 1 semaphore register, offset: 0x150 */
|
|
uint8_t RESERVED_20[12];
|
|
__IO uint32_t CH1STAT; /**< DCP channel 1 status register, offset: 0x160 */
|
|
uint8_t RESERVED_21[12];
|
|
__IO uint32_t CH1OPTS; /**< DCP channel 1 options register, offset: 0x170 */
|
|
uint8_t RESERVED_22[12];
|
|
__IO uint32_t CH2CMDPTR; /**< DCP channel 2 command pointer address register, offset: 0x180 */
|
|
uint8_t RESERVED_23[12];
|
|
__IO uint32_t CH2SEMA; /**< DCP channel 2 semaphore register, offset: 0x190 */
|
|
uint8_t RESERVED_24[12];
|
|
__IO uint32_t CH2STAT; /**< DCP channel 2 status register, offset: 0x1A0 */
|
|
uint8_t RESERVED_25[12];
|
|
__IO uint32_t CH2OPTS; /**< DCP channel 2 options register, offset: 0x1B0 */
|
|
uint8_t RESERVED_26[12];
|
|
__IO uint32_t CH3CMDPTR; /**< DCP channel 3 command pointer address register, offset: 0x1C0 */
|
|
uint8_t RESERVED_27[12];
|
|
__IO uint32_t CH3SEMA; /**< DCP channel 3 semaphore register, offset: 0x1D0 */
|
|
uint8_t RESERVED_28[12];
|
|
__IO uint32_t CH3STAT; /**< DCP channel 3 status register, offset: 0x1E0 */
|
|
uint8_t RESERVED_29[12];
|
|
__IO uint32_t CH3OPTS; /**< DCP channel 3 options register, offset: 0x1F0 */
|
|
uint8_t RESERVED_30[524];
|
|
__IO uint32_t DBGSELECT; /**< DCP debug select register, offset: 0x400 */
|
|
uint8_t RESERVED_31[12];
|
|
__I uint32_t DBGDATA; /**< DCP debug data register, offset: 0x410 */
|
|
uint8_t RESERVED_32[12];
|
|
__IO uint32_t PAGETABLE; /**< DCP page table register, offset: 0x420 */
|
|
uint8_t RESERVED_33[12];
|
|
__I uint32_t VERSION; /**< DCP version register, offset: 0x430 */
|
|
} DCP_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- DCP Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup DCP_Register_Masks DCP Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name CTRL - DCP control register 0 */
|
|
/*! @{ */
|
|
#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)
|
|
#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)
|
|
/*! CHANNEL_INTERRUPT_ENABLE
|
|
* 0b00000001..CH0
|
|
* 0b00000010..CH1
|
|
* 0b00000100..CH2
|
|
* 0b00001000..CH3
|
|
*/
|
|
#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK)
|
|
#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)
|
|
#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)
|
|
#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK)
|
|
#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)
|
|
#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)
|
|
#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK)
|
|
#define DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK (0x400000U)
|
|
#define DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT (22U)
|
|
#define DCP_CTRL_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK)
|
|
#define DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK (0x800000U)
|
|
#define DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT (23U)
|
|
#define DCP_CTRL_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK)
|
|
#define DCP_CTRL_PRESENT_SHA_MASK (0x10000000U)
|
|
#define DCP_CTRL_PRESENT_SHA_SHIFT (28U)
|
|
/*! PRESENT_SHA
|
|
* 0b1..Present
|
|
* 0b0..Absent
|
|
*/
|
|
#define DCP_CTRL_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_SHA_SHIFT)) & DCP_CTRL_PRESENT_SHA_MASK)
|
|
#define DCP_CTRL_PRESENT_CRYPTO_MASK (0x20000000U)
|
|
#define DCP_CTRL_PRESENT_CRYPTO_SHIFT (29U)
|
|
/*! PRESENT_CRYPTO
|
|
* 0b1..Present
|
|
* 0b0..Absent
|
|
*/
|
|
#define DCP_CTRL_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_PRESENT_CRYPTO_MASK)
|
|
#define DCP_CTRL_CLKGATE_MASK (0x40000000U)
|
|
#define DCP_CTRL_CLKGATE_SHIFT (30U)
|
|
#define DCP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLKGATE_SHIFT)) & DCP_CTRL_CLKGATE_MASK)
|
|
#define DCP_CTRL_SFTRST_MASK (0x80000000U)
|
|
#define DCP_CTRL_SFTRST_SHIFT (31U)
|
|
#define DCP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SFTRST_SHIFT)) & DCP_CTRL_SFTRST_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name STAT - DCP status register */
|
|
/*! @{ */
|
|
#define DCP_STAT_IRQ_MASK (0xFU)
|
|
#define DCP_STAT_IRQ_SHIFT (0U)
|
|
#define DCP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_IRQ_SHIFT)) & DCP_STAT_IRQ_MASK)
|
|
#define DCP_STAT_RSVD_IRQ_MASK (0x100U)
|
|
#define DCP_STAT_RSVD_IRQ_SHIFT (8U)
|
|
#define DCP_STAT_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_RSVD_IRQ_SHIFT)) & DCP_STAT_RSVD_IRQ_MASK)
|
|
#define DCP_STAT_READY_CHANNELS_MASK (0xFF0000U)
|
|
#define DCP_STAT_READY_CHANNELS_SHIFT (16U)
|
|
/*! READY_CHANNELS
|
|
* 0b00000001..CH0
|
|
* 0b00000010..CH1
|
|
* 0b00000100..CH2
|
|
* 0b00001000..CH3
|
|
*/
|
|
#define DCP_STAT_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_READY_CHANNELS_SHIFT)) & DCP_STAT_READY_CHANNELS_MASK)
|
|
#define DCP_STAT_CUR_CHANNEL_MASK (0xF000000U)
|
|
#define DCP_STAT_CUR_CHANNEL_SHIFT (24U)
|
|
/*! CUR_CHANNEL
|
|
* 0b0000..None
|
|
* 0b0001..CH0
|
|
* 0b0010..CH1
|
|
* 0b0011..CH2
|
|
* 0b0100..CH3
|
|
*/
|
|
#define DCP_STAT_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CUR_CHANNEL_SHIFT)) & DCP_STAT_CUR_CHANNEL_MASK)
|
|
#define DCP_STAT_OTP_KEY_READY_MASK (0x10000000U)
|
|
#define DCP_STAT_OTP_KEY_READY_SHIFT (28U)
|
|
#define DCP_STAT_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_OTP_KEY_READY_SHIFT)) & DCP_STAT_OTP_KEY_READY_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CHANNELCTRL - DCP channel control register */
|
|
/*! @{ */
|
|
#define DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK (0xFFU)
|
|
#define DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT (0U)
|
|
/*! ENABLE_CHANNEL
|
|
* 0b00000001..CH0
|
|
* 0b00000010..CH1
|
|
* 0b00000100..CH2
|
|
* 0b00001000..CH3
|
|
*/
|
|
#define DCP_CHANNELCTRL_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK)
|
|
#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U)
|
|
#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT (8U)
|
|
/*! HIGH_PRIORITY_CHANNEL
|
|
* 0b00000001..CH0
|
|
* 0b00000010..CH1
|
|
* 0b00000100..CH2
|
|
* 0b00001000..CH3
|
|
*/
|
|
#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK)
|
|
#define DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK (0x10000U)
|
|
#define DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT (16U)
|
|
#define DCP_CHANNELCTRL_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK)
|
|
#define DCP_CHANNELCTRL_RSVD_MASK (0xFFFE0000U)
|
|
#define DCP_CHANNELCTRL_RSVD_SHIFT (17U)
|
|
#define DCP_CHANNELCTRL_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_RSVD_SHIFT)) & DCP_CHANNELCTRL_RSVD_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CAPABILITY0 - DCP capability 0 register */
|
|
/*! @{ */
|
|
#define DCP_CAPABILITY0_NUM_KEYS_MASK (0xFFU)
|
|
#define DCP_CAPABILITY0_NUM_KEYS_SHIFT (0U)
|
|
#define DCP_CAPABILITY0_NUM_KEYS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_KEYS_SHIFT)) & DCP_CAPABILITY0_NUM_KEYS_MASK)
|
|
#define DCP_CAPABILITY0_NUM_CHANNELS_MASK (0xF00U)
|
|
#define DCP_CAPABILITY0_NUM_CHANNELS_SHIFT (8U)
|
|
#define DCP_CAPABILITY0_NUM_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_CHANNELS_SHIFT)) & DCP_CAPABILITY0_NUM_CHANNELS_MASK)
|
|
#define DCP_CAPABILITY0_RSVD_MASK (0x1FFFF000U)
|
|
#define DCP_CAPABILITY0_RSVD_SHIFT (12U)
|
|
#define DCP_CAPABILITY0_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_RSVD_SHIFT)) & DCP_CAPABILITY0_RSVD_MASK)
|
|
#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK (0x20000000U)
|
|
#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT (29U)
|
|
#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT)) & DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK)
|
|
#define DCP_CAPABILITY0_DISABLE_DECRYPT_MASK (0x80000000U)
|
|
#define DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT (31U)
|
|
#define DCP_CAPABILITY0_DISABLE_DECRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT)) & DCP_CAPABILITY0_DISABLE_DECRYPT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CAPABILITY1 - DCP capability 1 register */
|
|
/*! @{ */
|
|
#define DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK (0xFFFFU)
|
|
#define DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT (0U)
|
|
/*! CIPHER_ALGORITHMS
|
|
* 0b0000000000000001..AES128
|
|
*/
|
|
#define DCP_CAPABILITY1_CIPHER_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK)
|
|
#define DCP_CAPABILITY1_HASH_ALGORITHMS_MASK (0xFFFF0000U)
|
|
#define DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT (16U)
|
|
/*! HASH_ALGORITHMS
|
|
* 0b0000000000000001..SHA1
|
|
* 0b0000000000000010..CRC32
|
|
* 0b0000000000000100..SHA256
|
|
*/
|
|
#define DCP_CAPABILITY1_HASH_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_HASH_ALGORITHMS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CONTEXT - DCP context buffer pointer */
|
|
/*! @{ */
|
|
#define DCP_CONTEXT_ADDR_MASK (0xFFFFFFFFU)
|
|
#define DCP_CONTEXT_ADDR_SHIFT (0U)
|
|
#define DCP_CONTEXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CONTEXT_ADDR_SHIFT)) & DCP_CONTEXT_ADDR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name KEY - DCP key index */
|
|
/*! @{ */
|
|
#define DCP_KEY_SUBWORD_MASK (0x3U)
|
|
#define DCP_KEY_SUBWORD_SHIFT (0U)
|
|
#define DCP_KEY_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_SUBWORD_SHIFT)) & DCP_KEY_SUBWORD_MASK)
|
|
#define DCP_KEY_RSVD_SUBWORD_MASK (0xCU)
|
|
#define DCP_KEY_RSVD_SUBWORD_SHIFT (2U)
|
|
#define DCP_KEY_RSVD_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SUBWORD_SHIFT)) & DCP_KEY_RSVD_SUBWORD_MASK)
|
|
#define DCP_KEY_INDEX_MASK (0x30U)
|
|
#define DCP_KEY_INDEX_SHIFT (4U)
|
|
#define DCP_KEY_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_INDEX_SHIFT)) & DCP_KEY_INDEX_MASK)
|
|
#define DCP_KEY_RSVD_INDEX_MASK (0xC0U)
|
|
#define DCP_KEY_RSVD_INDEX_SHIFT (6U)
|
|
#define DCP_KEY_RSVD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_INDEX_SHIFT)) & DCP_KEY_RSVD_INDEX_MASK)
|
|
#define DCP_KEY_RSVD_MASK (0xFFFFFF00U)
|
|
#define DCP_KEY_RSVD_SHIFT (8U)
|
|
#define DCP_KEY_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SHIFT)) & DCP_KEY_RSVD_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name KEYDATA - DCP key data */
|
|
/*! @{ */
|
|
#define DCP_KEYDATA_DATA_MASK (0xFFFFFFFFU)
|
|
#define DCP_KEYDATA_DATA_SHIFT (0U)
|
|
#define DCP_KEYDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEYDATA_DATA_SHIFT)) & DCP_KEYDATA_DATA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PACKET0 - DCP work packet 0 status register */
|
|
/*! @{ */
|
|
#define DCP_PACKET0_ADDR_MASK (0xFFFFFFFFU)
|
|
#define DCP_PACKET0_ADDR_SHIFT (0U)
|
|
#define DCP_PACKET0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET0_ADDR_SHIFT)) & DCP_PACKET0_ADDR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PACKET1 - DCP work packet 1 status register */
|
|
/*! @{ */
|
|
#define DCP_PACKET1_INTERRUPT_MASK (0x1U)
|
|
#define DCP_PACKET1_INTERRUPT_SHIFT (0U)
|
|
#define DCP_PACKET1_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INTERRUPT_SHIFT)) & DCP_PACKET1_INTERRUPT_MASK)
|
|
#define DCP_PACKET1_DECR_SEMAPHORE_MASK (0x2U)
|
|
#define DCP_PACKET1_DECR_SEMAPHORE_SHIFT (1U)
|
|
#define DCP_PACKET1_DECR_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_DECR_SEMAPHORE_SHIFT)) & DCP_PACKET1_DECR_SEMAPHORE_MASK)
|
|
#define DCP_PACKET1_CHAIN_MASK (0x4U)
|
|
#define DCP_PACKET1_CHAIN_SHIFT (2U)
|
|
#define DCP_PACKET1_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_SHIFT)) & DCP_PACKET1_CHAIN_MASK)
|
|
#define DCP_PACKET1_CHAIN_CONTIGUOUS_MASK (0x8U)
|
|
#define DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT (3U)
|
|
#define DCP_PACKET1_CHAIN_CONTIGUOUS(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT)) & DCP_PACKET1_CHAIN_CONTIGUOUS_MASK)
|
|
#define DCP_PACKET1_ENABLE_MEMCOPY_MASK (0x10U)
|
|
#define DCP_PACKET1_ENABLE_MEMCOPY_SHIFT (4U)
|
|
#define DCP_PACKET1_ENABLE_MEMCOPY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_MEMCOPY_SHIFT)) & DCP_PACKET1_ENABLE_MEMCOPY_MASK)
|
|
#define DCP_PACKET1_ENABLE_CIPHER_MASK (0x20U)
|
|
#define DCP_PACKET1_ENABLE_CIPHER_SHIFT (5U)
|
|
#define DCP_PACKET1_ENABLE_CIPHER(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_CIPHER_SHIFT)) & DCP_PACKET1_ENABLE_CIPHER_MASK)
|
|
#define DCP_PACKET1_ENABLE_HASH_MASK (0x40U)
|
|
#define DCP_PACKET1_ENABLE_HASH_SHIFT (6U)
|
|
#define DCP_PACKET1_ENABLE_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_HASH_SHIFT)) & DCP_PACKET1_ENABLE_HASH_MASK)
|
|
#define DCP_PACKET1_ENABLE_BLIT_MASK (0x80U)
|
|
#define DCP_PACKET1_ENABLE_BLIT_SHIFT (7U)
|
|
#define DCP_PACKET1_ENABLE_BLIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_BLIT_SHIFT)) & DCP_PACKET1_ENABLE_BLIT_MASK)
|
|
#define DCP_PACKET1_CIPHER_ENCRYPT_MASK (0x100U)
|
|
#define DCP_PACKET1_CIPHER_ENCRYPT_SHIFT (8U)
|
|
/*! CIPHER_ENCRYPT
|
|
* 0b1..ENCRYPT
|
|
* 0b0..DECRYPT
|
|
*/
|
|
#define DCP_PACKET1_CIPHER_ENCRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_ENCRYPT_SHIFT)) & DCP_PACKET1_CIPHER_ENCRYPT_MASK)
|
|
#define DCP_PACKET1_CIPHER_INIT_MASK (0x200U)
|
|
#define DCP_PACKET1_CIPHER_INIT_SHIFT (9U)
|
|
#define DCP_PACKET1_CIPHER_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_INIT_SHIFT)) & DCP_PACKET1_CIPHER_INIT_MASK)
|
|
#define DCP_PACKET1_OTP_KEY_MASK (0x400U)
|
|
#define DCP_PACKET1_OTP_KEY_SHIFT (10U)
|
|
#define DCP_PACKET1_OTP_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OTP_KEY_SHIFT)) & DCP_PACKET1_OTP_KEY_MASK)
|
|
#define DCP_PACKET1_PAYLOAD_KEY_MASK (0x800U)
|
|
#define DCP_PACKET1_PAYLOAD_KEY_SHIFT (11U)
|
|
#define DCP_PACKET1_PAYLOAD_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_PAYLOAD_KEY_SHIFT)) & DCP_PACKET1_PAYLOAD_KEY_MASK)
|
|
#define DCP_PACKET1_HASH_INIT_MASK (0x1000U)
|
|
#define DCP_PACKET1_HASH_INIT_SHIFT (12U)
|
|
#define DCP_PACKET1_HASH_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_INIT_SHIFT)) & DCP_PACKET1_HASH_INIT_MASK)
|
|
#define DCP_PACKET1_HASH_TERM_MASK (0x2000U)
|
|
#define DCP_PACKET1_HASH_TERM_SHIFT (13U)
|
|
#define DCP_PACKET1_HASH_TERM(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_TERM_SHIFT)) & DCP_PACKET1_HASH_TERM_MASK)
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#define DCP_PACKET1_CHECK_HASH_MASK (0x4000U)
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#define DCP_PACKET1_CHECK_HASH_SHIFT (14U)
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#define DCP_PACKET1_CHECK_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHECK_HASH_SHIFT)) & DCP_PACKET1_CHECK_HASH_MASK)
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#define DCP_PACKET1_HASH_OUTPUT_MASK (0x8000U)
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#define DCP_PACKET1_HASH_OUTPUT_SHIFT (15U)
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/*! HASH_OUTPUT
|
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* 0b0..INPUT
|
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* 0b1..OUTPUT
|
|
*/
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#define DCP_PACKET1_HASH_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_OUTPUT_SHIFT)) & DCP_PACKET1_HASH_OUTPUT_MASK)
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#define DCP_PACKET1_CONSTANT_FILL_MASK (0x10000U)
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#define DCP_PACKET1_CONSTANT_FILL_SHIFT (16U)
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#define DCP_PACKET1_CONSTANT_FILL(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CONSTANT_FILL_SHIFT)) & DCP_PACKET1_CONSTANT_FILL_MASK)
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#define DCP_PACKET1_TEST_SEMA_IRQ_MASK (0x20000U)
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#define DCP_PACKET1_TEST_SEMA_IRQ_SHIFT (17U)
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#define DCP_PACKET1_TEST_SEMA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TEST_SEMA_IRQ_SHIFT)) & DCP_PACKET1_TEST_SEMA_IRQ_MASK)
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#define DCP_PACKET1_KEY_BYTESWAP_MASK (0x40000U)
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#define DCP_PACKET1_KEY_BYTESWAP_SHIFT (18U)
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#define DCP_PACKET1_KEY_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_BYTESWAP_SHIFT)) & DCP_PACKET1_KEY_BYTESWAP_MASK)
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#define DCP_PACKET1_KEY_WORDSWAP_MASK (0x80000U)
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#define DCP_PACKET1_KEY_WORDSWAP_SHIFT (19U)
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#define DCP_PACKET1_KEY_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_WORDSWAP_SHIFT)) & DCP_PACKET1_KEY_WORDSWAP_MASK)
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#define DCP_PACKET1_INPUT_BYTESWAP_MASK (0x100000U)
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#define DCP_PACKET1_INPUT_BYTESWAP_SHIFT (20U)
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#define DCP_PACKET1_INPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_INPUT_BYTESWAP_MASK)
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#define DCP_PACKET1_INPUT_WORDSWAP_MASK (0x200000U)
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#define DCP_PACKET1_INPUT_WORDSWAP_SHIFT (21U)
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#define DCP_PACKET1_INPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_INPUT_WORDSWAP_MASK)
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#define DCP_PACKET1_OUTPUT_BYTESWAP_MASK (0x400000U)
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#define DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT (22U)
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#define DCP_PACKET1_OUTPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_OUTPUT_BYTESWAP_MASK)
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#define DCP_PACKET1_OUTPUT_WORDSWAP_MASK (0x800000U)
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#define DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT (23U)
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#define DCP_PACKET1_OUTPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_OUTPUT_WORDSWAP_MASK)
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#define DCP_PACKET1_TAG_MASK (0xFF000000U)
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#define DCP_PACKET1_TAG_SHIFT (24U)
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#define DCP_PACKET1_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TAG_SHIFT)) & DCP_PACKET1_TAG_MASK)
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/*! @} */
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/*! @name PACKET2 - DCP work packet 2 status register */
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/*! @{ */
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#define DCP_PACKET2_CIPHER_SELECT_MASK (0xFU)
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#define DCP_PACKET2_CIPHER_SELECT_SHIFT (0U)
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/*! CIPHER_SELECT
|
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* 0b0000..AES128
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*/
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#define DCP_PACKET2_CIPHER_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_SELECT_SHIFT)) & DCP_PACKET2_CIPHER_SELECT_MASK)
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#define DCP_PACKET2_CIPHER_MODE_MASK (0xF0U)
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#define DCP_PACKET2_CIPHER_MODE_SHIFT (4U)
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/*! CIPHER_MODE
|
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* 0b0000..ECB
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* 0b0001..CBC
|
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*/
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#define DCP_PACKET2_CIPHER_MODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_MODE_SHIFT)) & DCP_PACKET2_CIPHER_MODE_MASK)
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#define DCP_PACKET2_KEY_SELECT_MASK (0xFF00U)
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#define DCP_PACKET2_KEY_SELECT_SHIFT (8U)
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/*! KEY_SELECT
|
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* 0b00000000..KEY0
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* 0b00000001..KEY1
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* 0b00000010..KEY2
|
|
* 0b00000011..KEY3
|
|
* 0b11111110..UNIQUE_KEY
|
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* 0b11111111..OTP_KEY
|
|
*/
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#define DCP_PACKET2_KEY_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_KEY_SELECT_SHIFT)) & DCP_PACKET2_KEY_SELECT_MASK)
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#define DCP_PACKET2_HASH_SELECT_MASK (0xF0000U)
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#define DCP_PACKET2_HASH_SELECT_SHIFT (16U)
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|
/*! HASH_SELECT
|
|
* 0b0000..SHA1
|
|
* 0b0001..CRC32
|
|
* 0b0010..SHA256
|
|
*/
|
|
#define DCP_PACKET2_HASH_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_HASH_SELECT_SHIFT)) & DCP_PACKET2_HASH_SELECT_MASK)
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#define DCP_PACKET2_RSVD_MASK (0xF00000U)
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#define DCP_PACKET2_RSVD_SHIFT (20U)
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#define DCP_PACKET2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_RSVD_SHIFT)) & DCP_PACKET2_RSVD_MASK)
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#define DCP_PACKET2_CIPHER_CFG_MASK (0xFF000000U)
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#define DCP_PACKET2_CIPHER_CFG_SHIFT (24U)
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#define DCP_PACKET2_CIPHER_CFG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_CFG_SHIFT)) & DCP_PACKET2_CIPHER_CFG_MASK)
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/*! @} */
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|
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|
/*! @name PACKET3 - DCP work packet 3 status register */
|
|
/*! @{ */
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|
#define DCP_PACKET3_ADDR_MASK (0xFFFFFFFFU)
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#define DCP_PACKET3_ADDR_SHIFT (0U)
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#define DCP_PACKET3_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET3_ADDR_SHIFT)) & DCP_PACKET3_ADDR_MASK)
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/*! @} */
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|
|
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/*! @name PACKET4 - DCP work packet 4 status register */
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|
/*! @{ */
|
|
#define DCP_PACKET4_ADDR_MASK (0xFFFFFFFFU)
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|
#define DCP_PACKET4_ADDR_SHIFT (0U)
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|
#define DCP_PACKET4_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET4_ADDR_SHIFT)) & DCP_PACKET4_ADDR_MASK)
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|
/*! @} */
|
|
|
|
/*! @name PACKET5 - DCP work packet 5 status register */
|
|
/*! @{ */
|
|
#define DCP_PACKET5_COUNT_MASK (0xFFFFFFFFU)
|
|
#define DCP_PACKET5_COUNT_SHIFT (0U)
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|
#define DCP_PACKET5_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET5_COUNT_SHIFT)) & DCP_PACKET5_COUNT_MASK)
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|
/*! @} */
|
|
|
|
/*! @name PACKET6 - DCP work packet 6 status register */
|
|
/*! @{ */
|
|
#define DCP_PACKET6_ADDR_MASK (0xFFFFFFFFU)
|
|
#define DCP_PACKET6_ADDR_SHIFT (0U)
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|
#define DCP_PACKET6_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET6_ADDR_SHIFT)) & DCP_PACKET6_ADDR_MASK)
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|
/*! @} */
|
|
|
|
/*! @name CH0CMDPTR - DCP channel 0 command pointer address register */
|
|
/*! @{ */
|
|
#define DCP_CH0CMDPTR_ADDR_MASK (0xFFFFFFFFU)
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|
#define DCP_CH0CMDPTR_ADDR_SHIFT (0U)
|
|
#define DCP_CH0CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0CMDPTR_ADDR_SHIFT)) & DCP_CH0CMDPTR_ADDR_MASK)
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|
/*! @} */
|
|
|
|
/*! @name CH0SEMA - DCP channel 0 semaphore register */
|
|
/*! @{ */
|
|
#define DCP_CH0SEMA_INCREMENT_MASK (0xFFU)
|
|
#define DCP_CH0SEMA_INCREMENT_SHIFT (0U)
|
|
#define DCP_CH0SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_INCREMENT_SHIFT)) & DCP_CH0SEMA_INCREMENT_MASK)
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|
#define DCP_CH0SEMA_VALUE_MASK (0xFF0000U)
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|
#define DCP_CH0SEMA_VALUE_SHIFT (16U)
|
|
#define DCP_CH0SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_VALUE_SHIFT)) & DCP_CH0SEMA_VALUE_MASK)
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|
/*! @} */
|
|
|
|
/*! @name CH0STAT - DCP channel 0 status register */
|
|
/*! @{ */
|
|
#define DCP_CH0STAT_RSVD_COMPLETE_MASK (0x1U)
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|
#define DCP_CH0STAT_RSVD_COMPLETE_SHIFT (0U)
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|
#define DCP_CH0STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_RSVD_COMPLETE_MASK)
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|
#define DCP_CH0STAT_HASH_MISMATCH_MASK (0x2U)
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|
#define DCP_CH0STAT_HASH_MISMATCH_SHIFT (1U)
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|
#define DCP_CH0STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_HASH_MISMATCH_MASK)
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|
#define DCP_CH0STAT_ERROR_SETUP_MASK (0x4U)
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|
#define DCP_CH0STAT_ERROR_SETUP_SHIFT (2U)
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|
#define DCP_CH0STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_ERROR_SETUP_MASK)
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|
#define DCP_CH0STAT_ERROR_PACKET_MASK (0x8U)
|
|
#define DCP_CH0STAT_ERROR_PACKET_SHIFT (3U)
|
|
#define DCP_CH0STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_ERROR_PACKET_MASK)
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|
#define DCP_CH0STAT_ERROR_SRC_MASK (0x10U)
|
|
#define DCP_CH0STAT_ERROR_SRC_SHIFT (4U)
|
|
#define DCP_CH0STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SRC_SHIFT)) & DCP_CH0STAT_ERROR_SRC_MASK)
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|
#define DCP_CH0STAT_ERROR_DST_MASK (0x20U)
|
|
#define DCP_CH0STAT_ERROR_DST_SHIFT (5U)
|
|
#define DCP_CH0STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_DST_SHIFT)) & DCP_CH0STAT_ERROR_DST_MASK)
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|
#define DCP_CH0STAT_ERROR_PAGEFAULT_MASK (0x40U)
|
|
#define DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT (6U)
|
|
#define DCP_CH0STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_ERROR_PAGEFAULT_MASK)
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|
#define DCP_CH0STAT_ERROR_CODE_MASK (0xFF0000U)
|
|
#define DCP_CH0STAT_ERROR_CODE_SHIFT (16U)
|
|
/*! ERROR_CODE
|
|
* 0b00000001..Error signalled because the next pointer is 0x00000000
|
|
* 0b00000010..Error signalled because the semaphore is non-zero and neither chain bit is set
|
|
* 0b00000011..Error signalled because an error is reported reading/writing the context buffer
|
|
* 0b00000100..Error signalled because an error is reported reading/writing the payload
|
|
* 0b00000101..Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash)
|
|
*/
|
|
#define DCP_CH0STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_CODE_SHIFT)) & DCP_CH0STAT_ERROR_CODE_MASK)
|
|
#define DCP_CH0STAT_TAG_MASK (0xFF000000U)
|
|
#define DCP_CH0STAT_TAG_SHIFT (24U)
|
|
#define DCP_CH0STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TAG_SHIFT)) & DCP_CH0STAT_TAG_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CH0OPTS - DCP channel 0 options register */
|
|
/*! @{ */
|
|
#define DCP_CH0OPTS_RECOVERY_TIMER_MASK (0xFFFFU)
|
|
#define DCP_CH0OPTS_RECOVERY_TIMER_SHIFT (0U)
|
|
#define DCP_CH0OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_RECOVERY_TIMER_MASK)
|
|
#define DCP_CH0OPTS_RSVD_MASK (0xFFFF0000U)
|
|
#define DCP_CH0OPTS_RSVD_SHIFT (16U)
|
|
#define DCP_CH0OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RSVD_SHIFT)) & DCP_CH0OPTS_RSVD_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CH1CMDPTR - DCP channel 1 command pointer address register */
|
|
/*! @{ */
|
|
#define DCP_CH1CMDPTR_ADDR_MASK (0xFFFFFFFFU)
|
|
#define DCP_CH1CMDPTR_ADDR_SHIFT (0U)
|
|
#define DCP_CH1CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1CMDPTR_ADDR_SHIFT)) & DCP_CH1CMDPTR_ADDR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CH1SEMA - DCP channel 1 semaphore register */
|
|
/*! @{ */
|
|
#define DCP_CH1SEMA_INCREMENT_MASK (0xFFU)
|
|
#define DCP_CH1SEMA_INCREMENT_SHIFT (0U)
|
|
#define DCP_CH1SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_INCREMENT_SHIFT)) & DCP_CH1SEMA_INCREMENT_MASK)
|
|
#define DCP_CH1SEMA_VALUE_MASK (0xFF0000U)
|
|
#define DCP_CH1SEMA_VALUE_SHIFT (16U)
|
|
#define DCP_CH1SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_VALUE_SHIFT)) & DCP_CH1SEMA_VALUE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CH1STAT - DCP channel 1 status register */
|
|
/*! @{ */
|
|
#define DCP_CH1STAT_RSVD_COMPLETE_MASK (0x1U)
|
|
#define DCP_CH1STAT_RSVD_COMPLETE_SHIFT (0U)
|
|
#define DCP_CH1STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_RSVD_COMPLETE_MASK)
|
|
#define DCP_CH1STAT_HASH_MISMATCH_MASK (0x2U)
|
|
#define DCP_CH1STAT_HASH_MISMATCH_SHIFT (1U)
|
|
#define DCP_CH1STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_HASH_MISMATCH_MASK)
|
|
#define DCP_CH1STAT_ERROR_SETUP_MASK (0x4U)
|
|
#define DCP_CH1STAT_ERROR_SETUP_SHIFT (2U)
|
|
#define DCP_CH1STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_ERROR_SETUP_MASK)
|
|
#define DCP_CH1STAT_ERROR_PACKET_MASK (0x8U)
|
|
#define DCP_CH1STAT_ERROR_PACKET_SHIFT (3U)
|
|
#define DCP_CH1STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_ERROR_PACKET_MASK)
|
|
#define DCP_CH1STAT_ERROR_SRC_MASK (0x10U)
|
|
#define DCP_CH1STAT_ERROR_SRC_SHIFT (4U)
|
|
#define DCP_CH1STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SRC_SHIFT)) & DCP_CH1STAT_ERROR_SRC_MASK)
|
|
#define DCP_CH1STAT_ERROR_DST_MASK (0x20U)
|
|
#define DCP_CH1STAT_ERROR_DST_SHIFT (5U)
|
|
#define DCP_CH1STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_DST_SHIFT)) & DCP_CH1STAT_ERROR_DST_MASK)
|
|
#define DCP_CH1STAT_ERROR_PAGEFAULT_MASK (0x40U)
|
|
#define DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT (6U)
|
|
#define DCP_CH1STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_ERROR_PAGEFAULT_MASK)
|
|
#define DCP_CH1STAT_ERROR_CODE_MASK (0xFF0000U)
|
|
#define DCP_CH1STAT_ERROR_CODE_SHIFT (16U)
|
|
/*! ERROR_CODE
|
|
* 0b00000001..Error is signalled because the next pointer is 0x00000000.
|
|
* 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
|
|
* 0b00000011..Error is signalled because an error was reported when reading/writing the context buffer.
|
|
* 0b00000100..Error is signalled because an error was reported when reading/writing the payload.
|
|
* 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash).
|
|
*/
|
|
#define DCP_CH1STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_CODE_SHIFT)) & DCP_CH1STAT_ERROR_CODE_MASK)
|
|
#define DCP_CH1STAT_TAG_MASK (0xFF000000U)
|
|
#define DCP_CH1STAT_TAG_SHIFT (24U)
|
|
#define DCP_CH1STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TAG_SHIFT)) & DCP_CH1STAT_TAG_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CH1OPTS - DCP channel 1 options register */
|
|
/*! @{ */
|
|
#define DCP_CH1OPTS_RECOVERY_TIMER_MASK (0xFFFFU)
|
|
#define DCP_CH1OPTS_RECOVERY_TIMER_SHIFT (0U)
|
|
#define DCP_CH1OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_RECOVERY_TIMER_MASK)
|
|
#define DCP_CH1OPTS_RSVD_MASK (0xFFFF0000U)
|
|
#define DCP_CH1OPTS_RSVD_SHIFT (16U)
|
|
#define DCP_CH1OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RSVD_SHIFT)) & DCP_CH1OPTS_RSVD_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CH2CMDPTR - DCP channel 2 command pointer address register */
|
|
/*! @{ */
|
|
#define DCP_CH2CMDPTR_ADDR_MASK (0xFFFFFFFFU)
|
|
#define DCP_CH2CMDPTR_ADDR_SHIFT (0U)
|
|
#define DCP_CH2CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2CMDPTR_ADDR_SHIFT)) & DCP_CH2CMDPTR_ADDR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CH2SEMA - DCP channel 2 semaphore register */
|
|
/*! @{ */
|
|
#define DCP_CH2SEMA_INCREMENT_MASK (0xFFU)
|
|
#define DCP_CH2SEMA_INCREMENT_SHIFT (0U)
|
|
#define DCP_CH2SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_INCREMENT_SHIFT)) & DCP_CH2SEMA_INCREMENT_MASK)
|
|
#define DCP_CH2SEMA_VALUE_MASK (0xFF0000U)
|
|
#define DCP_CH2SEMA_VALUE_SHIFT (16U)
|
|
#define DCP_CH2SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_VALUE_SHIFT)) & DCP_CH2SEMA_VALUE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CH2STAT - DCP channel 2 status register */
|
|
/*! @{ */
|
|
#define DCP_CH2STAT_RSVD_COMPLETE_MASK (0x1U)
|
|
#define DCP_CH2STAT_RSVD_COMPLETE_SHIFT (0U)
|
|
#define DCP_CH2STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_RSVD_COMPLETE_MASK)
|
|
#define DCP_CH2STAT_HASH_MISMATCH_MASK (0x2U)
|
|
#define DCP_CH2STAT_HASH_MISMATCH_SHIFT (1U)
|
|
#define DCP_CH2STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_HASH_MISMATCH_MASK)
|
|
#define DCP_CH2STAT_ERROR_SETUP_MASK (0x4U)
|
|
#define DCP_CH2STAT_ERROR_SETUP_SHIFT (2U)
|
|
#define DCP_CH2STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_ERROR_SETUP_MASK)
|
|
#define DCP_CH2STAT_ERROR_PACKET_MASK (0x8U)
|
|
#define DCP_CH2STAT_ERROR_PACKET_SHIFT (3U)
|
|
#define DCP_CH2STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_ERROR_PACKET_MASK)
|
|
#define DCP_CH2STAT_ERROR_SRC_MASK (0x10U)
|
|
#define DCP_CH2STAT_ERROR_SRC_SHIFT (4U)
|
|
#define DCP_CH2STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SRC_SHIFT)) & DCP_CH2STAT_ERROR_SRC_MASK)
|
|
#define DCP_CH2STAT_ERROR_DST_MASK (0x20U)
|
|
#define DCP_CH2STAT_ERROR_DST_SHIFT (5U)
|
|
#define DCP_CH2STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_DST_SHIFT)) & DCP_CH2STAT_ERROR_DST_MASK)
|
|
#define DCP_CH2STAT_ERROR_PAGEFAULT_MASK (0x40U)
|
|
#define DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT (6U)
|
|
#define DCP_CH2STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_ERROR_PAGEFAULT_MASK)
|
|
#define DCP_CH2STAT_ERROR_CODE_MASK (0xFF0000U)
|
|
#define DCP_CH2STAT_ERROR_CODE_SHIFT (16U)
|
|
/*! ERROR_CODE
|
|
* 0b00000001..Error is signalled because the next pointer is 0x00000000.
|
|
* 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
|
|
* 0b00000011..Error is signalled because an error was reported while reading/writing the context buffer.
|
|
* 0b00000100..Error is signalled because an error was reported while reading/writing the payload.
|
|
* 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash).
|
|
*/
|
|
#define DCP_CH2STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_CODE_SHIFT)) & DCP_CH2STAT_ERROR_CODE_MASK)
|
|
#define DCP_CH2STAT_TAG_MASK (0xFF000000U)
|
|
#define DCP_CH2STAT_TAG_SHIFT (24U)
|
|
#define DCP_CH2STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TAG_SHIFT)) & DCP_CH2STAT_TAG_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CH2OPTS - DCP channel 2 options register */
|
|
/*! @{ */
|
|
#define DCP_CH2OPTS_RECOVERY_TIMER_MASK (0xFFFFU)
|
|
#define DCP_CH2OPTS_RECOVERY_TIMER_SHIFT (0U)
|
|
#define DCP_CH2OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_RECOVERY_TIMER_MASK)
|
|
#define DCP_CH2OPTS_RSVD_MASK (0xFFFF0000U)
|
|
#define DCP_CH2OPTS_RSVD_SHIFT (16U)
|
|
#define DCP_CH2OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RSVD_SHIFT)) & DCP_CH2OPTS_RSVD_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CH3CMDPTR - DCP channel 3 command pointer address register */
|
|
/*! @{ */
|
|
#define DCP_CH3CMDPTR_ADDR_MASK (0xFFFFFFFFU)
|
|
#define DCP_CH3CMDPTR_ADDR_SHIFT (0U)
|
|
#define DCP_CH3CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3CMDPTR_ADDR_SHIFT)) & DCP_CH3CMDPTR_ADDR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CH3SEMA - DCP channel 3 semaphore register */
|
|
/*! @{ */
|
|
#define DCP_CH3SEMA_INCREMENT_MASK (0xFFU)
|
|
#define DCP_CH3SEMA_INCREMENT_SHIFT (0U)
|
|
#define DCP_CH3SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_INCREMENT_SHIFT)) & DCP_CH3SEMA_INCREMENT_MASK)
|
|
#define DCP_CH3SEMA_VALUE_MASK (0xFF0000U)
|
|
#define DCP_CH3SEMA_VALUE_SHIFT (16U)
|
|
#define DCP_CH3SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_VALUE_SHIFT)) & DCP_CH3SEMA_VALUE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CH3STAT - DCP channel 3 status register */
|
|
/*! @{ */
|
|
#define DCP_CH3STAT_RSVD_COMPLETE_MASK (0x1U)
|
|
#define DCP_CH3STAT_RSVD_COMPLETE_SHIFT (0U)
|
|
#define DCP_CH3STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_RSVD_COMPLETE_MASK)
|
|
#define DCP_CH3STAT_HASH_MISMATCH_MASK (0x2U)
|
|
#define DCP_CH3STAT_HASH_MISMATCH_SHIFT (1U)
|
|
#define DCP_CH3STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_HASH_MISMATCH_MASK)
|
|
#define DCP_CH3STAT_ERROR_SETUP_MASK (0x4U)
|
|
#define DCP_CH3STAT_ERROR_SETUP_SHIFT (2U)
|
|
#define DCP_CH3STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_ERROR_SETUP_MASK)
|
|
#define DCP_CH3STAT_ERROR_PACKET_MASK (0x8U)
|
|
#define DCP_CH3STAT_ERROR_PACKET_SHIFT (3U)
|
|
#define DCP_CH3STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_ERROR_PACKET_MASK)
|
|
#define DCP_CH3STAT_ERROR_SRC_MASK (0x10U)
|
|
#define DCP_CH3STAT_ERROR_SRC_SHIFT (4U)
|
|
#define DCP_CH3STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SRC_SHIFT)) & DCP_CH3STAT_ERROR_SRC_MASK)
|
|
#define DCP_CH3STAT_ERROR_DST_MASK (0x20U)
|
|
#define DCP_CH3STAT_ERROR_DST_SHIFT (5U)
|
|
#define DCP_CH3STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_DST_SHIFT)) & DCP_CH3STAT_ERROR_DST_MASK)
|
|
#define DCP_CH3STAT_ERROR_PAGEFAULT_MASK (0x40U)
|
|
#define DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT (6U)
|
|
#define DCP_CH3STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_ERROR_PAGEFAULT_MASK)
|
|
#define DCP_CH3STAT_ERROR_CODE_MASK (0xFF0000U)
|
|
#define DCP_CH3STAT_ERROR_CODE_SHIFT (16U)
|
|
/*! ERROR_CODE
|
|
* 0b00000001..Error is signalled because the next pointer is 0x00000000.
|
|
* 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
|
|
* 0b00000011..Error is signalled because an error was reported while reading/writing the context buffer.
|
|
* 0b00000100..Error is signalled because an error was reported while reading/writing the payload.
|
|
* 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash).
|
|
*/
|
|
#define DCP_CH3STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_CODE_SHIFT)) & DCP_CH3STAT_ERROR_CODE_MASK)
|
|
#define DCP_CH3STAT_TAG_MASK (0xFF000000U)
|
|
#define DCP_CH3STAT_TAG_SHIFT (24U)
|
|
#define DCP_CH3STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TAG_SHIFT)) & DCP_CH3STAT_TAG_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CH3OPTS - DCP channel 3 options register */
|
|
/*! @{ */
|
|
#define DCP_CH3OPTS_RECOVERY_TIMER_MASK (0xFFFFU)
|
|
#define DCP_CH3OPTS_RECOVERY_TIMER_SHIFT (0U)
|
|
#define DCP_CH3OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_RECOVERY_TIMER_MASK)
|
|
#define DCP_CH3OPTS_RSVD_MASK (0xFFFF0000U)
|
|
#define DCP_CH3OPTS_RSVD_SHIFT (16U)
|
|
#define DCP_CH3OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RSVD_SHIFT)) & DCP_CH3OPTS_RSVD_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DBGSELECT - DCP debug select register */
|
|
/*! @{ */
|
|
#define DCP_DBGSELECT_INDEX_MASK (0xFFU)
|
|
#define DCP_DBGSELECT_INDEX_SHIFT (0U)
|
|
/*! INDEX
|
|
* 0b00000001..CONTROL
|
|
* 0b00010000..OTPKEY0
|
|
* 0b00010001..OTPKEY1
|
|
* 0b00010010..OTPKEY2
|
|
* 0b00010011..OTPKEY3
|
|
*/
|
|
#define DCP_DBGSELECT_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_INDEX_SHIFT)) & DCP_DBGSELECT_INDEX_MASK)
|
|
#define DCP_DBGSELECT_RSVD_MASK (0xFFFFFF00U)
|
|
#define DCP_DBGSELECT_RSVD_SHIFT (8U)
|
|
#define DCP_DBGSELECT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_RSVD_SHIFT)) & DCP_DBGSELECT_RSVD_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DBGDATA - DCP debug data register */
|
|
/*! @{ */
|
|
#define DCP_DBGDATA_DATA_MASK (0xFFFFFFFFU)
|
|
#define DCP_DBGDATA_DATA_SHIFT (0U)
|
|
#define DCP_DBGDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGDATA_DATA_SHIFT)) & DCP_DBGDATA_DATA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PAGETABLE - DCP page table register */
|
|
/*! @{ */
|
|
#define DCP_PAGETABLE_ENABLE_MASK (0x1U)
|
|
#define DCP_PAGETABLE_ENABLE_SHIFT (0U)
|
|
#define DCP_PAGETABLE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_ENABLE_SHIFT)) & DCP_PAGETABLE_ENABLE_MASK)
|
|
#define DCP_PAGETABLE_FLUSH_MASK (0x2U)
|
|
#define DCP_PAGETABLE_FLUSH_SHIFT (1U)
|
|
#define DCP_PAGETABLE_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_FLUSH_SHIFT)) & DCP_PAGETABLE_FLUSH_MASK)
|
|
#define DCP_PAGETABLE_BASE_MASK (0xFFFFFFFCU)
|
|
#define DCP_PAGETABLE_BASE_SHIFT (2U)
|
|
#define DCP_PAGETABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_BASE_SHIFT)) & DCP_PAGETABLE_BASE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name VERSION - DCP version register */
|
|
/*! @{ */
|
|
#define DCP_VERSION_STEP_MASK (0xFFFFU)
|
|
#define DCP_VERSION_STEP_SHIFT (0U)
|
|
#define DCP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_STEP_SHIFT)) & DCP_VERSION_STEP_MASK)
|
|
#define DCP_VERSION_MINOR_MASK (0xFF0000U)
|
|
#define DCP_VERSION_MINOR_SHIFT (16U)
|
|
#define DCP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MINOR_SHIFT)) & DCP_VERSION_MINOR_MASK)
|
|
#define DCP_VERSION_MAJOR_MASK (0xFF000000U)
|
|
#define DCP_VERSION_MAJOR_SHIFT (24U)
|
|
#define DCP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MAJOR_SHIFT)) & DCP_VERSION_MAJOR_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group DCP_Register_Masks */
|
|
|
|
|
|
/* DCP - Peripheral instance base addresses */
|
|
/** Peripheral DCP base address */
|
|
#define DCP_BASE (0x402FC000u)
|
|
/** Peripheral DCP base pointer */
|
|
#define DCP ((DCP_Type *)DCP_BASE)
|
|
/** Array initializer of DCP peripheral base addresses */
|
|
#define DCP_BASE_ADDRS { DCP_BASE }
|
|
/** Array initializer of DCP peripheral base pointers */
|
|
#define DCP_BASE_PTRS { DCP }
|
|
/** Interrupt vectors for the DCP peripheral type */
|
|
#define DCP_IRQS { DCP_IRQn }
|
|
#define DCP_VMI_IRQS { DCP_VMI_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group DCP_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- DMA Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** DMA - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t CR; /**< Control Register, offset: 0x0 */
|
|
__I uint32_t ES; /**< Error Status Register, offset: 0x4 */
|
|
uint8_t RESERVED_0[4];
|
|
__IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
|
|
uint8_t RESERVED_1[4];
|
|
__IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
|
|
__O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
|
|
__O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
|
|
__O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
|
|
__O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
|
|
__O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
|
|
__O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
|
|
__O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
|
|
__O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
|
|
uint8_t RESERVED_2[4];
|
|
__IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
|
|
uint8_t RESERVED_3[4];
|
|
__IO uint32_t ERR; /**< Error Register, offset: 0x2C */
|
|
uint8_t RESERVED_4[4];
|
|
__I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
|
|
uint8_t RESERVED_5[12];
|
|
__IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */
|
|
uint8_t RESERVED_6[184];
|
|
__IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
|
|
__IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
|
|
__IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
|
|
__IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
|
|
__IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
|
|
__IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
|
|
__IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
|
|
__IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
|
|
__IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */
|
|
__IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */
|
|
__IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */
|
|
__IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */
|
|
__IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */
|
|
__IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */
|
|
__IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */
|
|
__IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */
|
|
__IO uint8_t DCHPRI19; /**< Channel n Priority Register, offset: 0x110 */
|
|
__IO uint8_t DCHPRI18; /**< Channel n Priority Register, offset: 0x111 */
|
|
__IO uint8_t DCHPRI17; /**< Channel n Priority Register, offset: 0x112 */
|
|
__IO uint8_t DCHPRI16; /**< Channel n Priority Register, offset: 0x113 */
|
|
__IO uint8_t DCHPRI23; /**< Channel n Priority Register, offset: 0x114 */
|
|
__IO uint8_t DCHPRI22; /**< Channel n Priority Register, offset: 0x115 */
|
|
__IO uint8_t DCHPRI21; /**< Channel n Priority Register, offset: 0x116 */
|
|
__IO uint8_t DCHPRI20; /**< Channel n Priority Register, offset: 0x117 */
|
|
__IO uint8_t DCHPRI27; /**< Channel n Priority Register, offset: 0x118 */
|
|
__IO uint8_t DCHPRI26; /**< Channel n Priority Register, offset: 0x119 */
|
|
__IO uint8_t DCHPRI25; /**< Channel n Priority Register, offset: 0x11A */
|
|
__IO uint8_t DCHPRI24; /**< Channel n Priority Register, offset: 0x11B */
|
|
__IO uint8_t DCHPRI31; /**< Channel n Priority Register, offset: 0x11C */
|
|
__IO uint8_t DCHPRI30; /**< Channel n Priority Register, offset: 0x11D */
|
|
__IO uint8_t DCHPRI29; /**< Channel n Priority Register, offset: 0x11E */
|
|
__IO uint8_t DCHPRI28; /**< Channel n Priority Register, offset: 0x11F */
|
|
uint8_t RESERVED_7[3808];
|
|
struct { /* offset: 0x1000, array step: 0x20 */
|
|
__IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
|
|
__IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
|
|
__IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
|
|
union { /* offset: 0x1008, array step: 0x20 */
|
|
__IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */
|
|
__IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
|
|
__IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */
|
|
};
|
|
__IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
|
|
__IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
|
|
__IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
|
|
union { /* offset: 0x1016, array step: 0x20 */
|
|
__IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
|
|
__IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
|
|
};
|
|
__IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
|
|
__IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
|
|
union { /* offset: 0x101E, array step: 0x20 */
|
|
__IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
|
|
__IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
|
|
};
|
|
} TCD[32];
|
|
} DMA_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- DMA Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup DMA_Register_Masks DMA Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name CR - Control Register */
|
|
/*! @{ */
|
|
#define DMA_CR_EDBG_MASK (0x2U)
|
|
#define DMA_CR_EDBG_SHIFT (1U)
|
|
/*! EDBG - Enable Debug
|
|
* 0b0..When in debug mode, the DMA continues to operate.
|
|
* 0b1..When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared.
|
|
*/
|
|
#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
|
|
#define DMA_CR_ERCA_MASK (0x4U)
|
|
#define DMA_CR_ERCA_SHIFT (2U)
|
|
/*! ERCA - Enable Round Robin Channel Arbitration
|
|
* 0b0..Fixed priority arbitration is used for channel selection within each group.
|
|
* 0b1..Round robin arbitration is used for channel selection within each group.
|
|
*/
|
|
#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
|
|
#define DMA_CR_ERGA_MASK (0x8U)
|
|
#define DMA_CR_ERGA_SHIFT (3U)
|
|
/*! ERGA - Enable Round Robin Group Arbitration
|
|
* 0b0..Fixed priority arbitration is used for selection among the groups.
|
|
* 0b1..Round robin arbitration is used for selection among the groups.
|
|
*/
|
|
#define DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)
|
|
#define DMA_CR_HOE_MASK (0x10U)
|
|
#define DMA_CR_HOE_SHIFT (4U)
|
|
/*! HOE - Halt On Error
|
|
* 0b0..Normal operation
|
|
* 0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.
|
|
*/
|
|
#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
|
|
#define DMA_CR_HALT_MASK (0x20U)
|
|
#define DMA_CR_HALT_SHIFT (5U)
|
|
/*! HALT - Halt DMA Operations
|
|
* 0b0..Normal operation
|
|
* 0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared.
|
|
*/
|
|
#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
|
|
#define DMA_CR_CLM_MASK (0x40U)
|
|
#define DMA_CR_CLM_SHIFT (6U)
|
|
/*! CLM - Continuous Link Mode
|
|
* 0b0..A minor loop channel link made to itself goes through channel arbitration before being activated again.
|
|
* 0b1..A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop.
|
|
*/
|
|
#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
|
|
#define DMA_CR_EMLM_MASK (0x80U)
|
|
#define DMA_CR_EMLM_SHIFT (7U)
|
|
/*! EMLM - Enable Minor Loop Mapping
|
|
* 0b0..Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
|
|
* 0b1..Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled.
|
|
*/
|
|
#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
|
|
#define DMA_CR_GRP0PRI_MASK (0x100U)
|
|
#define DMA_CR_GRP0PRI_SHIFT (8U)
|
|
#define DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)
|
|
#define DMA_CR_GRP1PRI_MASK (0x400U)
|
|
#define DMA_CR_GRP1PRI_SHIFT (10U)
|
|
#define DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)
|
|
#define DMA_CR_ECX_MASK (0x10000U)
|
|
#define DMA_CR_ECX_SHIFT (16U)
|
|
/*! ECX - Error Cancel Transfer
|
|
* 0b0..Normal operation
|
|
* 0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt.
|
|
*/
|
|
#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
|
|
#define DMA_CR_CX_MASK (0x20000U)
|
|
#define DMA_CR_CX_SHIFT (17U)
|
|
/*! CX - Cancel Transfer
|
|
* 0b0..Normal operation
|
|
* 0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed.
|
|
*/
|
|
#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
|
|
#define DMA_CR_ACTIVE_MASK (0x80000000U)
|
|
#define DMA_CR_ACTIVE_SHIFT (31U)
|
|
/*! ACTIVE - DMA Active Status
|
|
* 0b0..eDMA is idle.
|
|
* 0b1..eDMA is executing a channel.
|
|
*/
|
|
#define DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ES - Error Status Register */
|
|
/*! @{ */
|
|
#define DMA_ES_DBE_MASK (0x1U)
|
|
#define DMA_ES_DBE_SHIFT (0U)
|
|
/*! DBE - Destination Bus Error
|
|
* 0b0..No destination bus error
|
|
* 0b1..The last recorded error was a bus error on a destination write
|
|
*/
|
|
#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
|
|
#define DMA_ES_SBE_MASK (0x2U)
|
|
#define DMA_ES_SBE_SHIFT (1U)
|
|
/*! SBE - Source Bus Error
|
|
* 0b0..No source bus error
|
|
* 0b1..The last recorded error was a bus error on a source read
|
|
*/
|
|
#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
|
|
#define DMA_ES_SGE_MASK (0x4U)
|
|
#define DMA_ES_SGE_SHIFT (2U)
|
|
/*! SGE - Scatter/Gather Configuration Error
|
|
* 0b0..No scatter/gather configuration error
|
|
* 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary.
|
|
*/
|
|
#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
|
|
#define DMA_ES_NCE_MASK (0x8U)
|
|
#define DMA_ES_NCE_SHIFT (3U)
|
|
/*! NCE - NBYTES/CITER Configuration Error
|
|
* 0b0..No NBYTES/CITER configuration error
|
|
* 0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
|
|
*/
|
|
#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
|
|
#define DMA_ES_DOE_MASK (0x10U)
|
|
#define DMA_ES_DOE_SHIFT (4U)
|
|
/*! DOE - Destination Offset Error
|
|
* 0b0..No destination offset configuration error
|
|
* 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
|
|
*/
|
|
#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
|
|
#define DMA_ES_DAE_MASK (0x20U)
|
|
#define DMA_ES_DAE_SHIFT (5U)
|
|
/*! DAE - Destination Address Error
|
|
* 0b0..No destination address configuration error
|
|
* 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
|
|
*/
|
|
#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
|
|
#define DMA_ES_SOE_MASK (0x40U)
|
|
#define DMA_ES_SOE_SHIFT (6U)
|
|
/*! SOE - Source Offset Error
|
|
* 0b0..No source offset configuration error
|
|
* 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
|
|
*/
|
|
#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
|
|
#define DMA_ES_SAE_MASK (0x80U)
|
|
#define DMA_ES_SAE_SHIFT (7U)
|
|
/*! SAE - Source Address Error
|
|
* 0b0..No source address configuration error.
|
|
* 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
|
|
*/
|
|
#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
|
|
#define DMA_ES_ERRCHN_MASK (0x1F00U)
|
|
#define DMA_ES_ERRCHN_SHIFT (8U)
|
|
#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
|
|
#define DMA_ES_CPE_MASK (0x4000U)
|
|
#define DMA_ES_CPE_SHIFT (14U)
|
|
/*! CPE - Channel Priority Error
|
|
* 0b0..No channel priority error
|
|
* 0b1..The last recorded error was a configuration error in the channel priorities within a group. Channel priorities within a group are not unique.
|
|
*/
|
|
#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
|
|
#define DMA_ES_GPE_MASK (0x8000U)
|
|
#define DMA_ES_GPE_SHIFT (15U)
|
|
/*! GPE - Group Priority Error
|
|
* 0b0..No group priority error
|
|
* 0b1..The last recorded error was a configuration error among the group priorities. All group priorities are not unique.
|
|
*/
|
|
#define DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)
|
|
#define DMA_ES_ECX_MASK (0x10000U)
|
|
#define DMA_ES_ECX_SHIFT (16U)
|
|
/*! ECX - Transfer Canceled
|
|
* 0b0..No canceled transfers
|
|
* 0b1..The last recorded entry was a canceled transfer by the error cancel transfer input
|
|
*/
|
|
#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
|
|
#define DMA_ES_VLD_MASK (0x80000000U)
|
|
#define DMA_ES_VLD_SHIFT (31U)
|
|
/*! VLD - VLD
|
|
* 0b0..No ERR bits are set.
|
|
* 0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared.
|
|
*/
|
|
#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ERQ - Enable Request Register */
|
|
/*! @{ */
|
|
#define DMA_ERQ_ERQ0_MASK (0x1U)
|
|
#define DMA_ERQ_ERQ0_SHIFT (0U)
|
|
/*! ERQ0 - Enable DMA Request 0
|
|
* 0b0..The DMA request signal for the corresponding channel is disabled
|
|
* 0b1..The DMA request signal for the corresponding channel is enabled
|
|
*/
|
|
#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
|
|
#define DMA_ERQ_ERQ1_MASK (0x2U)
|
|
#define DMA_ERQ_ERQ1_SHIFT (1U)
|
|
/*! ERQ1 - Enable DMA Request 1
|
|
* 0b0..The DMA request signal for the corresponding channel is disabled
|
|
* 0b1..The DMA request signal for the corresponding channel is enabled
|
|
*/
|
|
#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
|
|
#define DMA_ERQ_ERQ2_MASK (0x4U)
|
|
#define DMA_ERQ_ERQ2_SHIFT (2U)
|
|
/*! ERQ2 - Enable DMA Request 2
|
|
* 0b0..The DMA request signal for the corresponding channel is disabled
|
|
* 0b1..The DMA request signal for the corresponding channel is enabled
|
|
*/
|
|
#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
|
|
#define DMA_ERQ_ERQ3_MASK (0x8U)
|
|
#define DMA_ERQ_ERQ3_SHIFT (3U)
|
|
/*! ERQ3 - Enable DMA Request 3
|
|
* 0b0..The DMA request signal for the corresponding channel is disabled
|
|
* 0b1..The DMA request signal for the corresponding channel is enabled
|
|
*/
|
|
#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
|
|
#define DMA_ERQ_ERQ4_MASK (0x10U)
|
|
#define DMA_ERQ_ERQ4_SHIFT (4U)
|
|
/*! ERQ4 - Enable DMA Request 4
|
|
* 0b0..The DMA request signal for the corresponding channel is disabled
|
|
* 0b1..The DMA request signal for the corresponding channel is enabled
|
|
*/
|
|
#define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
|
|
#define DMA_ERQ_ERQ5_MASK (0x20U)
|
|
#define DMA_ERQ_ERQ5_SHIFT (5U)
|
|
/*! ERQ5 - Enable DMA Request 5
|
|
* 0b0..The DMA request signal for the corresponding channel is disabled
|
|
* 0b1..The DMA request signal for the corresponding channel is enabled
|
|
*/
|
|
#define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
|
|
#define DMA_ERQ_ERQ6_MASK (0x40U)
|
|
#define DMA_ERQ_ERQ6_SHIFT (6U)
|
|
/*! ERQ6 - Enable DMA Request 6
|
|
* 0b0..The DMA request signal for the corresponding channel is disabled
|
|
* 0b1..The DMA request signal for the corresponding channel is enabled
|
|
*/
|
|
#define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
|
|
#define DMA_ERQ_ERQ7_MASK (0x80U)
|
|
#define DMA_ERQ_ERQ7_SHIFT (7U)
|
|
/*! ERQ7 - Enable DMA Request 7
|
|
* 0b0..The DMA request signal for the corresponding channel is disabled
|
|
* 0b1..The DMA request signal for the corresponding channel is enabled
|
|
*/
|
|
#define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
|
|
#define DMA_ERQ_ERQ8_MASK (0x100U)
|
|
#define DMA_ERQ_ERQ8_SHIFT (8U)
|
|
/*! ERQ8 - Enable DMA Request 8
|
|
* 0b0..The DMA request signal for the corresponding channel is disabled
|
|
* 0b1..The DMA request signal for the corresponding channel is enabled
|
|
*/
|
|
#define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
|
|
#define DMA_ERQ_ERQ9_MASK (0x200U)
|
|
#define DMA_ERQ_ERQ9_SHIFT (9U)
|
|
/*! ERQ9 - Enable DMA Request 9
|
|
* 0b0..The DMA request signal for the corresponding channel is disabled
|
|
* 0b1..The DMA request signal for the corresponding channel is enabled
|
|
*/
|
|
#define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
|
|
#define DMA_ERQ_ERQ10_MASK (0x400U)
|
|
#define DMA_ERQ_ERQ10_SHIFT (10U)
|
|
/*! ERQ10 - Enable DMA Request 10
|
|
* 0b0..The DMA request signal for the corresponding channel is disabled
|
|
* 0b1..The DMA request signal for the corresponding channel is enabled
|
|
*/
|
|
#define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
|
|
#define DMA_ERQ_ERQ11_MASK (0x800U)
|
|
#define DMA_ERQ_ERQ11_SHIFT (11U)
|
|
/*! ERQ11 - Enable DMA Request 11
|
|
* 0b0..The DMA request signal for the corresponding channel is disabled
|
|
* 0b1..The DMA request signal for the corresponding channel is enabled
|
|
*/
|
|
#define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
|
|
#define DMA_ERQ_ERQ12_MASK (0x1000U)
|
|
#define DMA_ERQ_ERQ12_SHIFT (12U)
|
|
/*! ERQ12 - Enable DMA Request 12
|
|
* 0b0..The DMA request signal for the corresponding channel is disabled
|
|
* 0b1..The DMA request signal for the corresponding channel is enabled
|
|
*/
|
|
#define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
|
|
#define DMA_ERQ_ERQ13_MASK (0x2000U)
|
|
#define DMA_ERQ_ERQ13_SHIFT (13U)
|
|
/*! ERQ13 - Enable DMA Request 13
|
|
* 0b0..The DMA request signal for the corresponding channel is disabled
|
|
* 0b1..The DMA request signal for the corresponding channel is enabled
|
|
*/
|
|
#define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
|
|
#define DMA_ERQ_ERQ14_MASK (0x4000U)
|
|
#define DMA_ERQ_ERQ14_SHIFT (14U)
|
|
/*! ERQ14 - Enable DMA Request 14
|
|
* 0b0..The DMA request signal for the corresponding channel is disabled
|
|
* 0b1..The DMA request signal for the corresponding channel is enabled
|
|
*/
|
|
#define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
|
|
#define DMA_ERQ_ERQ15_MASK (0x8000U)
|
|
#define DMA_ERQ_ERQ15_SHIFT (15U)
|
|
/*! ERQ15 - Enable DMA Request 15
|
|
* 0b0..The DMA request signal for the corresponding channel is disabled
|
|
* 0b1..The DMA request signal for the corresponding channel is enabled
|
|
*/
|
|
#define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
|
|
#define DMA_ERQ_ERQ16_MASK (0x10000U)
|
|
#define DMA_ERQ_ERQ16_SHIFT (16U)
|
|
/*! ERQ16 - Enable DMA Request 16
|
|
* 0b0..The DMA request signal for the corresponding channel is disabled
|
|
* 0b1..The DMA request signal for the corresponding channel is enabled
|
|
*/
|
|
#define DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)
|
|
#define DMA_ERQ_ERQ17_MASK (0x20000U)
|
|
#define DMA_ERQ_ERQ17_SHIFT (17U)
|
|
/*! ERQ17 - Enable DMA Request 17
|
|
* 0b0..The DMA request signal for the corresponding channel is disabled
|
|
* 0b1..The DMA request signal for the corresponding channel is enabled
|
|
*/
|
|
#define DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)
|
|
#define DMA_ERQ_ERQ18_MASK (0x40000U)
|
|
#define DMA_ERQ_ERQ18_SHIFT (18U)
|
|
/*! ERQ18 - Enable DMA Request 18
|
|
* 0b0..The DMA request signal for the corresponding channel is disabled
|
|
* 0b1..The DMA request signal for the corresponding channel is enabled
|
|
*/
|
|
#define DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)
|
|
#define DMA_ERQ_ERQ19_MASK (0x80000U)
|
|
#define DMA_ERQ_ERQ19_SHIFT (19U)
|
|
/*! ERQ19 - Enable DMA Request 19
|
|
* 0b0..The DMA request signal for the corresponding channel is disabled
|
|
* 0b1..The DMA request signal for the corresponding channel is enabled
|
|
*/
|
|
#define DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)
|
|
#define DMA_ERQ_ERQ20_MASK (0x100000U)
|
|
#define DMA_ERQ_ERQ20_SHIFT (20U)
|
|
/*! ERQ20 - Enable DMA Request 20
|
|
* 0b0..The DMA request signal for the corresponding channel is disabled
|
|
* 0b1..The DMA request signal for the corresponding channel is enabled
|
|
*/
|
|
#define DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)
|
|
#define DMA_ERQ_ERQ21_MASK (0x200000U)
|
|
#define DMA_ERQ_ERQ21_SHIFT (21U)
|
|
/*! ERQ21 - Enable DMA Request 21
|
|
* 0b0..The DMA request signal for the corresponding channel is disabled
|
|
* 0b1..The DMA request signal for the corresponding channel is enabled
|
|
*/
|
|
#define DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)
|
|
#define DMA_ERQ_ERQ22_MASK (0x400000U)
|
|
#define DMA_ERQ_ERQ22_SHIFT (22U)
|
|
/*! ERQ22 - Enable DMA Request 22
|
|
* 0b0..The DMA request signal for the corresponding channel is disabled
|
|
* 0b1..The DMA request signal for the corresponding channel is enabled
|
|
*/
|
|
#define DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)
|
|
#define DMA_ERQ_ERQ23_MASK (0x800000U)
|
|
#define DMA_ERQ_ERQ23_SHIFT (23U)
|
|
/*! ERQ23 - Enable DMA Request 23
|
|
* 0b0..The DMA request signal for the corresponding channel is disabled
|
|
* 0b1..The DMA request signal for the corresponding channel is enabled
|
|
*/
|
|
#define DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)
|
|
#define DMA_ERQ_ERQ24_MASK (0x1000000U)
|
|
#define DMA_ERQ_ERQ24_SHIFT (24U)
|
|
/*! ERQ24 - Enable DMA Request 24
|
|
* 0b0..The DMA request signal for the corresponding channel is disabled
|
|
* 0b1..The DMA request signal for the corresponding channel is enabled
|
|
*/
|
|
#define DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)
|
|
#define DMA_ERQ_ERQ25_MASK (0x2000000U)
|
|
#define DMA_ERQ_ERQ25_SHIFT (25U)
|
|
/*! ERQ25 - Enable DMA Request 25
|
|
* 0b0..The DMA request signal for the corresponding channel is disabled
|
|
* 0b1..The DMA request signal for the corresponding channel is enabled
|
|
*/
|
|
#define DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)
|
|
#define DMA_ERQ_ERQ26_MASK (0x4000000U)
|
|
#define DMA_ERQ_ERQ26_SHIFT (26U)
|
|
/*! ERQ26 - Enable DMA Request 26
|
|
* 0b0..The DMA request signal for the corresponding channel is disabled
|
|
* 0b1..The DMA request signal for the corresponding channel is enabled
|
|
*/
|
|
#define DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)
|
|
#define DMA_ERQ_ERQ27_MASK (0x8000000U)
|
|
#define DMA_ERQ_ERQ27_SHIFT (27U)
|
|
/*! ERQ27 - Enable DMA Request 27
|
|
* 0b0..The DMA request signal for the corresponding channel is disabled
|
|
* 0b1..The DMA request signal for the corresponding channel is enabled
|
|
*/
|
|
#define DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)
|
|
#define DMA_ERQ_ERQ28_MASK (0x10000000U)
|
|
#define DMA_ERQ_ERQ28_SHIFT (28U)
|
|
/*! ERQ28 - Enable DMA Request 28
|
|
* 0b0..The DMA request signal for the corresponding channel is disabled
|
|
* 0b1..The DMA request signal for the corresponding channel is enabled
|
|
*/
|
|
#define DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)
|
|
#define DMA_ERQ_ERQ29_MASK (0x20000000U)
|
|
#define DMA_ERQ_ERQ29_SHIFT (29U)
|
|
/*! ERQ29 - Enable DMA Request 29
|
|
* 0b0..The DMA request signal for the corresponding channel is disabled
|
|
* 0b1..The DMA request signal for the corresponding channel is enabled
|
|
*/
|
|
#define DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)
|
|
#define DMA_ERQ_ERQ30_MASK (0x40000000U)
|
|
#define DMA_ERQ_ERQ30_SHIFT (30U)
|
|
/*! ERQ30 - Enable DMA Request 30
|
|
* 0b0..The DMA request signal for the corresponding channel is disabled
|
|
* 0b1..The DMA request signal for the corresponding channel is enabled
|
|
*/
|
|
#define DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)
|
|
#define DMA_ERQ_ERQ31_MASK (0x80000000U)
|
|
#define DMA_ERQ_ERQ31_SHIFT (31U)
|
|
/*! ERQ31 - Enable DMA Request 31
|
|
* 0b0..The DMA request signal for the corresponding channel is disabled
|
|
* 0b1..The DMA request signal for the corresponding channel is enabled
|
|
*/
|
|
#define DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name EEI - Enable Error Interrupt Register */
|
|
/*! @{ */
|
|
#define DMA_EEI_EEI0_MASK (0x1U)
|
|
#define DMA_EEI_EEI0_SHIFT (0U)
|
|
/*! EEI0 - Enable Error Interrupt 0
|
|
* 0b0..The error signal for corresponding channel does not generate an error interrupt
|
|
* 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
|
|
*/
|
|
#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
|
|
#define DMA_EEI_EEI1_MASK (0x2U)
|
|
#define DMA_EEI_EEI1_SHIFT (1U)
|
|
/*! EEI1 - Enable Error Interrupt 1
|
|
* 0b0..The error signal for corresponding channel does not generate an error interrupt
|
|
* 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
|
|
*/
|
|
#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
|
|
#define DMA_EEI_EEI2_MASK (0x4U)
|
|
#define DMA_EEI_EEI2_SHIFT (2U)
|
|
/*! EEI2 - Enable Error Interrupt 2
|
|
* 0b0..The error signal for corresponding channel does not generate an error interrupt
|
|
* 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
|
|
*/
|
|
#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
|
|
#define DMA_EEI_EEI3_MASK (0x8U)
|
|
#define DMA_EEI_EEI3_SHIFT (3U)
|
|
/*! EEI3 - Enable Error Interrupt 3
|
|
* 0b0..The error signal for corresponding channel does not generate an error interrupt
|
|
* 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
|
|
*/
|
|
#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
|
|
#define DMA_EEI_EEI4_MASK (0x10U)
|
|
#define DMA_EEI_EEI4_SHIFT (4U)
|
|
/*! EEI4 - Enable Error Interrupt 4
|
|
* 0b0..The error signal for corresponding channel does not generate an error interrupt
|
|
* 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
|
|
*/
|
|
#define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
|
|
#define DMA_EEI_EEI5_MASK (0x20U)
|
|
#define DMA_EEI_EEI5_SHIFT (5U)
|
|
/*! EEI5 - Enable Error Interrupt 5
|
|
* 0b0..The error signal for corresponding channel does not generate an error interrupt
|
|
* 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
|
|
*/
|
|
#define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
|
|
#define DMA_EEI_EEI6_MASK (0x40U)
|
|
#define DMA_EEI_EEI6_SHIFT (6U)
|
|
/*! EEI6 - Enable Error Interrupt 6
|
|
* 0b0..The error signal for corresponding channel does not generate an error interrupt
|
|
* 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
|
|
*/
|
|
#define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
|
|
#define DMA_EEI_EEI7_MASK (0x80U)
|
|
#define DMA_EEI_EEI7_SHIFT (7U)
|
|
/*! EEI7 - Enable Error Interrupt 7
|
|
* 0b0..The error signal for corresponding channel does not generate an error interrupt
|
|
* 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
|
|
*/
|
|
#define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
|
|
#define DMA_EEI_EEI8_MASK (0x100U)
|
|
#define DMA_EEI_EEI8_SHIFT (8U)
|
|
/*! EEI8 - Enable Error Interrupt 8
|
|
* 0b0..The error signal for corresponding channel does not generate an error interrupt
|
|
* 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
|
|
*/
|
|
#define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
|
|
#define DMA_EEI_EEI9_MASK (0x200U)
|
|
#define DMA_EEI_EEI9_SHIFT (9U)
|
|
/*! EEI9 - Enable Error Interrupt 9
|
|
* 0b0..The error signal for corresponding channel does not generate an error interrupt
|
|
* 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
|
|
*/
|
|
#define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
|
|
#define DMA_EEI_EEI10_MASK (0x400U)
|
|
#define DMA_EEI_EEI10_SHIFT (10U)
|
|
/*! EEI10 - Enable Error Interrupt 10
|
|
* 0b0..The error signal for corresponding channel does not generate an error interrupt
|
|
* 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
|
|
*/
|
|
#define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
|
|
#define DMA_EEI_EEI11_MASK (0x800U)
|
|
#define DMA_EEI_EEI11_SHIFT (11U)
|
|
/*! EEI11 - Enable Error Interrupt 11
|
|
* 0b0..The error signal for corresponding channel does not generate an error interrupt
|
|
* 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
|
|
*/
|
|
#define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
|
|
#define DMA_EEI_EEI12_MASK (0x1000U)
|
|
#define DMA_EEI_EEI12_SHIFT (12U)
|
|
/*! EEI12 - Enable Error Interrupt 12
|
|
* 0b0..The error signal for corresponding channel does not generate an error interrupt
|
|
* 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
|
|
*/
|
|
#define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
|
|
#define DMA_EEI_EEI13_MASK (0x2000U)
|
|
#define DMA_EEI_EEI13_SHIFT (13U)
|
|
/*! EEI13 - Enable Error Interrupt 13
|
|
* 0b0..The error signal for corresponding channel does not generate an error interrupt
|
|
* 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
|
|
*/
|
|
#define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
|
|
#define DMA_EEI_EEI14_MASK (0x4000U)
|
|
#define DMA_EEI_EEI14_SHIFT (14U)
|
|
/*! EEI14 - Enable Error Interrupt 14
|
|
* 0b0..The error signal for corresponding channel does not generate an error interrupt
|
|
* 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
|
|
*/
|
|
#define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
|
|
#define DMA_EEI_EEI15_MASK (0x8000U)
|
|
#define DMA_EEI_EEI15_SHIFT (15U)
|
|
/*! EEI15 - Enable Error Interrupt 15
|
|
* 0b0..The error signal for corresponding channel does not generate an error interrupt
|
|
* 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
|
|
*/
|
|
#define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
|
|
#define DMA_EEI_EEI16_MASK (0x10000U)
|
|
#define DMA_EEI_EEI16_SHIFT (16U)
|
|
/*! EEI16 - Enable Error Interrupt 16
|
|
* 0b0..The error signal for corresponding channel does not generate an error interrupt
|
|
* 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
|
|
*/
|
|
#define DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)
|
|
#define DMA_EEI_EEI17_MASK (0x20000U)
|
|
#define DMA_EEI_EEI17_SHIFT (17U)
|
|
/*! EEI17 - Enable Error Interrupt 17
|
|
* 0b0..The error signal for corresponding channel does not generate an error interrupt
|
|
* 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
|
|
*/
|
|
#define DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)
|
|
#define DMA_EEI_EEI18_MASK (0x40000U)
|
|
#define DMA_EEI_EEI18_SHIFT (18U)
|
|
/*! EEI18 - Enable Error Interrupt 18
|
|
* 0b0..The error signal for corresponding channel does not generate an error interrupt
|
|
* 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
|
|
*/
|
|
#define DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)
|
|
#define DMA_EEI_EEI19_MASK (0x80000U)
|
|
#define DMA_EEI_EEI19_SHIFT (19U)
|
|
/*! EEI19 - Enable Error Interrupt 19
|
|
* 0b0..The error signal for corresponding channel does not generate an error interrupt
|
|
* 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
|
|
*/
|
|
#define DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)
|
|
#define DMA_EEI_EEI20_MASK (0x100000U)
|
|
#define DMA_EEI_EEI20_SHIFT (20U)
|
|
/*! EEI20 - Enable Error Interrupt 20
|
|
* 0b0..The error signal for corresponding channel does not generate an error interrupt
|
|
* 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
|
|
*/
|
|
#define DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)
|
|
#define DMA_EEI_EEI21_MASK (0x200000U)
|
|
#define DMA_EEI_EEI21_SHIFT (21U)
|
|
/*! EEI21 - Enable Error Interrupt 21
|
|
* 0b0..The error signal for corresponding channel does not generate an error interrupt
|
|
* 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
|
|
*/
|
|
#define DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)
|
|
#define DMA_EEI_EEI22_MASK (0x400000U)
|
|
#define DMA_EEI_EEI22_SHIFT (22U)
|
|
/*! EEI22 - Enable Error Interrupt 22
|
|
* 0b0..The error signal for corresponding channel does not generate an error interrupt
|
|
* 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
|
|
*/
|
|
#define DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)
|
|
#define DMA_EEI_EEI23_MASK (0x800000U)
|
|
#define DMA_EEI_EEI23_SHIFT (23U)
|
|
/*! EEI23 - Enable Error Interrupt 23
|
|
* 0b0..The error signal for corresponding channel does not generate an error interrupt
|
|
* 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
|
|
*/
|
|
#define DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)
|
|
#define DMA_EEI_EEI24_MASK (0x1000000U)
|
|
#define DMA_EEI_EEI24_SHIFT (24U)
|
|
/*! EEI24 - Enable Error Interrupt 24
|
|
* 0b0..The error signal for corresponding channel does not generate an error interrupt
|
|
* 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
|
|
*/
|
|
#define DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)
|
|
#define DMA_EEI_EEI25_MASK (0x2000000U)
|
|
#define DMA_EEI_EEI25_SHIFT (25U)
|
|
/*! EEI25 - Enable Error Interrupt 25
|
|
* 0b0..The error signal for corresponding channel does not generate an error interrupt
|
|
* 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
|
|
*/
|
|
#define DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)
|
|
#define DMA_EEI_EEI26_MASK (0x4000000U)
|
|
#define DMA_EEI_EEI26_SHIFT (26U)
|
|
/*! EEI26 - Enable Error Interrupt 26
|
|
* 0b0..The error signal for corresponding channel does not generate an error interrupt
|
|
* 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
|
|
*/
|
|
#define DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)
|
|
#define DMA_EEI_EEI27_MASK (0x8000000U)
|
|
#define DMA_EEI_EEI27_SHIFT (27U)
|
|
/*! EEI27 - Enable Error Interrupt 27
|
|
* 0b0..The error signal for corresponding channel does not generate an error interrupt
|
|
* 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
|
|
*/
|
|
#define DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)
|
|
#define DMA_EEI_EEI28_MASK (0x10000000U)
|
|
#define DMA_EEI_EEI28_SHIFT (28U)
|
|
/*! EEI28 - Enable Error Interrupt 28
|
|
* 0b0..The error signal for corresponding channel does not generate an error interrupt
|
|
* 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
|
|
*/
|
|
#define DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)
|
|
#define DMA_EEI_EEI29_MASK (0x20000000U)
|
|
#define DMA_EEI_EEI29_SHIFT (29U)
|
|
/*! EEI29 - Enable Error Interrupt 29
|
|
* 0b0..The error signal for corresponding channel does not generate an error interrupt
|
|
* 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
|
|
*/
|
|
#define DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)
|
|
#define DMA_EEI_EEI30_MASK (0x40000000U)
|
|
#define DMA_EEI_EEI30_SHIFT (30U)
|
|
/*! EEI30 - Enable Error Interrupt 30
|
|
* 0b0..The error signal for corresponding channel does not generate an error interrupt
|
|
* 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
|
|
*/
|
|
#define DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)
|
|
#define DMA_EEI_EEI31_MASK (0x80000000U)
|
|
#define DMA_EEI_EEI31_SHIFT (31U)
|
|
/*! EEI31 - Enable Error Interrupt 31
|
|
* 0b0..The error signal for corresponding channel does not generate an error interrupt
|
|
* 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
|
|
*/
|
|
#define DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CEEI - Clear Enable Error Interrupt Register */
|
|
/*! @{ */
|
|
#define DMA_CEEI_CEEI_MASK (0x1FU)
|
|
#define DMA_CEEI_CEEI_SHIFT (0U)
|
|
#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
|
|
#define DMA_CEEI_CAEE_MASK (0x40U)
|
|
#define DMA_CEEI_CAEE_SHIFT (6U)
|
|
/*! CAEE - Clear All Enable Error Interrupts
|
|
* 0b0..Clear only the EEI bit specified in the CEEI field
|
|
* 0b1..Clear all bits in EEI
|
|
*/
|
|
#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
|
|
#define DMA_CEEI_NOP_MASK (0x80U)
|
|
#define DMA_CEEI_NOP_SHIFT (7U)
|
|
/*! NOP - No Op enable
|
|
* 0b0..Normal operation
|
|
* 0b1..No operation, ignore the other bits in this register
|
|
*/
|
|
#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEEI - Set Enable Error Interrupt Register */
|
|
/*! @{ */
|
|
#define DMA_SEEI_SEEI_MASK (0x1FU)
|
|
#define DMA_SEEI_SEEI_SHIFT (0U)
|
|
#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
|
|
#define DMA_SEEI_SAEE_MASK (0x40U)
|
|
#define DMA_SEEI_SAEE_SHIFT (6U)
|
|
/*! SAEE - Sets All Enable Error Interrupts
|
|
* 0b0..Set only the EEI bit specified in the SEEI field.
|
|
* 0b1..Sets all bits in EEI
|
|
*/
|
|
#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
|
|
#define DMA_SEEI_NOP_MASK (0x80U)
|
|
#define DMA_SEEI_NOP_SHIFT (7U)
|
|
/*! NOP - No Op enable
|
|
* 0b0..Normal operation
|
|
* 0b1..No operation, ignore the other bits in this register
|
|
*/
|
|
#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CERQ - Clear Enable Request Register */
|
|
/*! @{ */
|
|
#define DMA_CERQ_CERQ_MASK (0x1FU)
|
|
#define DMA_CERQ_CERQ_SHIFT (0U)
|
|
#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
|
|
#define DMA_CERQ_CAER_MASK (0x40U)
|
|
#define DMA_CERQ_CAER_SHIFT (6U)
|
|
/*! CAER - Clear All Enable Requests
|
|
* 0b0..Clear only the ERQ bit specified in the CERQ field
|
|
* 0b1..Clear all bits in ERQ
|
|
*/
|
|
#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
|
|
#define DMA_CERQ_NOP_MASK (0x80U)
|
|
#define DMA_CERQ_NOP_SHIFT (7U)
|
|
/*! NOP - No Op enable
|
|
* 0b0..Normal operation
|
|
* 0b1..No operation, ignore the other bits in this register
|
|
*/
|
|
#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SERQ - Set Enable Request Register */
|
|
/*! @{ */
|
|
#define DMA_SERQ_SERQ_MASK (0x1FU)
|
|
#define DMA_SERQ_SERQ_SHIFT (0U)
|
|
#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
|
|
#define DMA_SERQ_SAER_MASK (0x40U)
|
|
#define DMA_SERQ_SAER_SHIFT (6U)
|
|
/*! SAER - Set All Enable Requests
|
|
* 0b0..Set only the ERQ bit specified in the SERQ field
|
|
* 0b1..Set all bits in ERQ
|
|
*/
|
|
#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
|
|
#define DMA_SERQ_NOP_MASK (0x80U)
|
|
#define DMA_SERQ_NOP_SHIFT (7U)
|
|
/*! NOP - No Op enable
|
|
* 0b0..Normal operation
|
|
* 0b1..No operation, ignore the other bits in this register
|
|
*/
|
|
#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CDNE - Clear DONE Status Bit Register */
|
|
/*! @{ */
|
|
#define DMA_CDNE_CDNE_MASK (0x1FU)
|
|
#define DMA_CDNE_CDNE_SHIFT (0U)
|
|
#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
|
|
#define DMA_CDNE_CADN_MASK (0x40U)
|
|
#define DMA_CDNE_CADN_SHIFT (6U)
|
|
/*! CADN - Clears All DONE Bits
|
|
* 0b0..Clears only the TCDn_CSR[DONE] bit specified in the CDNE field
|
|
* 0b1..Clears all bits in TCDn_CSR[DONE]
|
|
*/
|
|
#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
|
|
#define DMA_CDNE_NOP_MASK (0x80U)
|
|
#define DMA_CDNE_NOP_SHIFT (7U)
|
|
/*! NOP - No Op enable
|
|
* 0b0..Normal operation
|
|
* 0b1..No operation, ignore the other bits in this register
|
|
*/
|
|
#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SSRT - Set START Bit Register */
|
|
/*! @{ */
|
|
#define DMA_SSRT_SSRT_MASK (0x1FU)
|
|
#define DMA_SSRT_SSRT_SHIFT (0U)
|
|
#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
|
|
#define DMA_SSRT_SAST_MASK (0x40U)
|
|
#define DMA_SSRT_SAST_SHIFT (6U)
|
|
/*! SAST - Set All START Bits (activates all channels)
|
|
* 0b0..Set only the TCDn_CSR[START] bit specified in the SSRT field
|
|
* 0b1..Set all bits in TCDn_CSR[START]
|
|
*/
|
|
#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
|
|
#define DMA_SSRT_NOP_MASK (0x80U)
|
|
#define DMA_SSRT_NOP_SHIFT (7U)
|
|
/*! NOP - No Op enable
|
|
* 0b0..Normal operation
|
|
* 0b1..No operation, ignore the other bits in this register
|
|
*/
|
|
#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CERR - Clear Error Register */
|
|
/*! @{ */
|
|
#define DMA_CERR_CERR_MASK (0x1FU)
|
|
#define DMA_CERR_CERR_SHIFT (0U)
|
|
#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
|
|
#define DMA_CERR_CAEI_MASK (0x40U)
|
|
#define DMA_CERR_CAEI_SHIFT (6U)
|
|
/*! CAEI - Clear All Error Indicators
|
|
* 0b0..Clear only the ERR bit specified in the CERR field
|
|
* 0b1..Clear all bits in ERR
|
|
*/
|
|
#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
|
|
#define DMA_CERR_NOP_MASK (0x80U)
|
|
#define DMA_CERR_NOP_SHIFT (7U)
|
|
/*! NOP - No Op enable
|
|
* 0b0..Normal operation
|
|
* 0b1..No operation, ignore the other bits in this register
|
|
*/
|
|
#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CINT - Clear Interrupt Request Register */
|
|
/*! @{ */
|
|
#define DMA_CINT_CINT_MASK (0x1FU)
|
|
#define DMA_CINT_CINT_SHIFT (0U)
|
|
#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
|
|
#define DMA_CINT_CAIR_MASK (0x40U)
|
|
#define DMA_CINT_CAIR_SHIFT (6U)
|
|
/*! CAIR - Clear All Interrupt Requests
|
|
* 0b0..Clear only the INT bit specified in the CINT field
|
|
* 0b1..Clear all bits in INT
|
|
*/
|
|
#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
|
|
#define DMA_CINT_NOP_MASK (0x80U)
|
|
#define DMA_CINT_NOP_SHIFT (7U)
|
|
/*! NOP - No Op enable
|
|
* 0b0..Normal operation
|
|
* 0b1..No operation, ignore the other bits in this register
|
|
*/
|
|
#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name INT - Interrupt Request Register */
|
|
/*! @{ */
|
|
#define DMA_INT_INT0_MASK (0x1U)
|
|
#define DMA_INT_INT0_SHIFT (0U)
|
|
/*! INT0 - Interrupt Request 0
|
|
* 0b0..The interrupt request for corresponding channel is cleared
|
|
* 0b1..The interrupt request for corresponding channel is active
|
|
*/
|
|
#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
|
|
#define DMA_INT_INT1_MASK (0x2U)
|
|
#define DMA_INT_INT1_SHIFT (1U)
|
|
/*! INT1 - Interrupt Request 1
|
|
* 0b0..The interrupt request for corresponding channel is cleared
|
|
* 0b1..The interrupt request for corresponding channel is active
|
|
*/
|
|
#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
|
|
#define DMA_INT_INT2_MASK (0x4U)
|
|
#define DMA_INT_INT2_SHIFT (2U)
|
|
/*! INT2 - Interrupt Request 2
|
|
* 0b0..The interrupt request for corresponding channel is cleared
|
|
* 0b1..The interrupt request for corresponding channel is active
|
|
*/
|
|
#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
|
|
#define DMA_INT_INT3_MASK (0x8U)
|
|
#define DMA_INT_INT3_SHIFT (3U)
|
|
/*! INT3 - Interrupt Request 3
|
|
* 0b0..The interrupt request for corresponding channel is cleared
|
|
* 0b1..The interrupt request for corresponding channel is active
|
|
*/
|
|
#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
|
|
#define DMA_INT_INT4_MASK (0x10U)
|
|
#define DMA_INT_INT4_SHIFT (4U)
|
|
/*! INT4 - Interrupt Request 4
|
|
* 0b0..The interrupt request for corresponding channel is cleared
|
|
* 0b1..The interrupt request for corresponding channel is active
|
|
*/
|
|
#define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
|
|
#define DMA_INT_INT5_MASK (0x20U)
|
|
#define DMA_INT_INT5_SHIFT (5U)
|
|
/*! INT5 - Interrupt Request 5
|
|
* 0b0..The interrupt request for corresponding channel is cleared
|
|
* 0b1..The interrupt request for corresponding channel is active
|
|
*/
|
|
#define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
|
|
#define DMA_INT_INT6_MASK (0x40U)
|
|
#define DMA_INT_INT6_SHIFT (6U)
|
|
/*! INT6 - Interrupt Request 6
|
|
* 0b0..The interrupt request for corresponding channel is cleared
|
|
* 0b1..The interrupt request for corresponding channel is active
|
|
*/
|
|
#define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
|
|
#define DMA_INT_INT7_MASK (0x80U)
|
|
#define DMA_INT_INT7_SHIFT (7U)
|
|
/*! INT7 - Interrupt Request 7
|
|
* 0b0..The interrupt request for corresponding channel is cleared
|
|
* 0b1..The interrupt request for corresponding channel is active
|
|
*/
|
|
#define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
|
|
#define DMA_INT_INT8_MASK (0x100U)
|
|
#define DMA_INT_INT8_SHIFT (8U)
|
|
/*! INT8 - Interrupt Request 8
|
|
* 0b0..The interrupt request for corresponding channel is cleared
|
|
* 0b1..The interrupt request for corresponding channel is active
|
|
*/
|
|
#define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
|
|
#define DMA_INT_INT9_MASK (0x200U)
|
|
#define DMA_INT_INT9_SHIFT (9U)
|
|
/*! INT9 - Interrupt Request 9
|
|
* 0b0..The interrupt request for corresponding channel is cleared
|
|
* 0b1..The interrupt request for corresponding channel is active
|
|
*/
|
|
#define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
|
|
#define DMA_INT_INT10_MASK (0x400U)
|
|
#define DMA_INT_INT10_SHIFT (10U)
|
|
/*! INT10 - Interrupt Request 10
|
|
* 0b0..The interrupt request for corresponding channel is cleared
|
|
* 0b1..The interrupt request for corresponding channel is active
|
|
*/
|
|
#define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
|
|
#define DMA_INT_INT11_MASK (0x800U)
|
|
#define DMA_INT_INT11_SHIFT (11U)
|
|
/*! INT11 - Interrupt Request 11
|
|
* 0b0..The interrupt request for corresponding channel is cleared
|
|
* 0b1..The interrupt request for corresponding channel is active
|
|
*/
|
|
#define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
|
|
#define DMA_INT_INT12_MASK (0x1000U)
|
|
#define DMA_INT_INT12_SHIFT (12U)
|
|
/*! INT12 - Interrupt Request 12
|
|
* 0b0..The interrupt request for corresponding channel is cleared
|
|
* 0b1..The interrupt request for corresponding channel is active
|
|
*/
|
|
#define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
|
|
#define DMA_INT_INT13_MASK (0x2000U)
|
|
#define DMA_INT_INT13_SHIFT (13U)
|
|
/*! INT13 - Interrupt Request 13
|
|
* 0b0..The interrupt request for corresponding channel is cleared
|
|
* 0b1..The interrupt request for corresponding channel is active
|
|
*/
|
|
#define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
|
|
#define DMA_INT_INT14_MASK (0x4000U)
|
|
#define DMA_INT_INT14_SHIFT (14U)
|
|
/*! INT14 - Interrupt Request 14
|
|
* 0b0..The interrupt request for corresponding channel is cleared
|
|
* 0b1..The interrupt request for corresponding channel is active
|
|
*/
|
|
#define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
|
|
#define DMA_INT_INT15_MASK (0x8000U)
|
|
#define DMA_INT_INT15_SHIFT (15U)
|
|
/*! INT15 - Interrupt Request 15
|
|
* 0b0..The interrupt request for corresponding channel is cleared
|
|
* 0b1..The interrupt request for corresponding channel is active
|
|
*/
|
|
#define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
|
|
#define DMA_INT_INT16_MASK (0x10000U)
|
|
#define DMA_INT_INT16_SHIFT (16U)
|
|
/*! INT16 - Interrupt Request 16
|
|
* 0b0..The interrupt request for corresponding channel is cleared
|
|
* 0b1..The interrupt request for corresponding channel is active
|
|
*/
|
|
#define DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)
|
|
#define DMA_INT_INT17_MASK (0x20000U)
|
|
#define DMA_INT_INT17_SHIFT (17U)
|
|
/*! INT17 - Interrupt Request 17
|
|
* 0b0..The interrupt request for corresponding channel is cleared
|
|
* 0b1..The interrupt request for corresponding channel is active
|
|
*/
|
|
#define DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)
|
|
#define DMA_INT_INT18_MASK (0x40000U)
|
|
#define DMA_INT_INT18_SHIFT (18U)
|
|
/*! INT18 - Interrupt Request 18
|
|
* 0b0..The interrupt request for corresponding channel is cleared
|
|
* 0b1..The interrupt request for corresponding channel is active
|
|
*/
|
|
#define DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)
|
|
#define DMA_INT_INT19_MASK (0x80000U)
|
|
#define DMA_INT_INT19_SHIFT (19U)
|
|
/*! INT19 - Interrupt Request 19
|
|
* 0b0..The interrupt request for corresponding channel is cleared
|
|
* 0b1..The interrupt request for corresponding channel is active
|
|
*/
|
|
#define DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)
|
|
#define DMA_INT_INT20_MASK (0x100000U)
|
|
#define DMA_INT_INT20_SHIFT (20U)
|
|
/*! INT20 - Interrupt Request 20
|
|
* 0b0..The interrupt request for corresponding channel is cleared
|
|
* 0b1..The interrupt request for corresponding channel is active
|
|
*/
|
|
#define DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)
|
|
#define DMA_INT_INT21_MASK (0x200000U)
|
|
#define DMA_INT_INT21_SHIFT (21U)
|
|
/*! INT21 - Interrupt Request 21
|
|
* 0b0..The interrupt request for corresponding channel is cleared
|
|
* 0b1..The interrupt request for corresponding channel is active
|
|
*/
|
|
#define DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)
|
|
#define DMA_INT_INT22_MASK (0x400000U)
|
|
#define DMA_INT_INT22_SHIFT (22U)
|
|
/*! INT22 - Interrupt Request 22
|
|
* 0b0..The interrupt request for corresponding channel is cleared
|
|
* 0b1..The interrupt request for corresponding channel is active
|
|
*/
|
|
#define DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)
|
|
#define DMA_INT_INT23_MASK (0x800000U)
|
|
#define DMA_INT_INT23_SHIFT (23U)
|
|
/*! INT23 - Interrupt Request 23
|
|
* 0b0..The interrupt request for corresponding channel is cleared
|
|
* 0b1..The interrupt request for corresponding channel is active
|
|
*/
|
|
#define DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)
|
|
#define DMA_INT_INT24_MASK (0x1000000U)
|
|
#define DMA_INT_INT24_SHIFT (24U)
|
|
/*! INT24 - Interrupt Request 24
|
|
* 0b0..The interrupt request for corresponding channel is cleared
|
|
* 0b1..The interrupt request for corresponding channel is active
|
|
*/
|
|
#define DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)
|
|
#define DMA_INT_INT25_MASK (0x2000000U)
|
|
#define DMA_INT_INT25_SHIFT (25U)
|
|
/*! INT25 - Interrupt Request 25
|
|
* 0b0..The interrupt request for corresponding channel is cleared
|
|
* 0b1..The interrupt request for corresponding channel is active
|
|
*/
|
|
#define DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)
|
|
#define DMA_INT_INT26_MASK (0x4000000U)
|
|
#define DMA_INT_INT26_SHIFT (26U)
|
|
/*! INT26 - Interrupt Request 26
|
|
* 0b0..The interrupt request for corresponding channel is cleared
|
|
* 0b1..The interrupt request for corresponding channel is active
|
|
*/
|
|
#define DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)
|
|
#define DMA_INT_INT27_MASK (0x8000000U)
|
|
#define DMA_INT_INT27_SHIFT (27U)
|
|
/*! INT27 - Interrupt Request 27
|
|
* 0b0..The interrupt request for corresponding channel is cleared
|
|
* 0b1..The interrupt request for corresponding channel is active
|
|
*/
|
|
#define DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)
|
|
#define DMA_INT_INT28_MASK (0x10000000U)
|
|
#define DMA_INT_INT28_SHIFT (28U)
|
|
/*! INT28 - Interrupt Request 28
|
|
* 0b0..The interrupt request for corresponding channel is cleared
|
|
* 0b1..The interrupt request for corresponding channel is active
|
|
*/
|
|
#define DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)
|
|
#define DMA_INT_INT29_MASK (0x20000000U)
|
|
#define DMA_INT_INT29_SHIFT (29U)
|
|
/*! INT29 - Interrupt Request 29
|
|
* 0b0..The interrupt request for corresponding channel is cleared
|
|
* 0b1..The interrupt request for corresponding channel is active
|
|
*/
|
|
#define DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)
|
|
#define DMA_INT_INT30_MASK (0x40000000U)
|
|
#define DMA_INT_INT30_SHIFT (30U)
|
|
/*! INT30 - Interrupt Request 30
|
|
* 0b0..The interrupt request for corresponding channel is cleared
|
|
* 0b1..The interrupt request for corresponding channel is active
|
|
*/
|
|
#define DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)
|
|
#define DMA_INT_INT31_MASK (0x80000000U)
|
|
#define DMA_INT_INT31_SHIFT (31U)
|
|
/*! INT31 - Interrupt Request 31
|
|
* 0b0..The interrupt request for corresponding channel is cleared
|
|
* 0b1..The interrupt request for corresponding channel is active
|
|
*/
|
|
#define DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ERR - Error Register */
|
|
/*! @{ */
|
|
#define DMA_ERR_ERR0_MASK (0x1U)
|
|
#define DMA_ERR_ERR0_SHIFT (0U)
|
|
/*! ERR0 - Error In Channel 0
|
|
* 0b0..An error in this channel has not occurred
|
|
* 0b1..An error in this channel has occurred
|
|
*/
|
|
#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
|
|
#define DMA_ERR_ERR1_MASK (0x2U)
|
|
#define DMA_ERR_ERR1_SHIFT (1U)
|
|
/*! ERR1 - Error In Channel 1
|
|
* 0b0..An error in this channel has not occurred
|
|
* 0b1..An error in this channel has occurred
|
|
*/
|
|
#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
|
|
#define DMA_ERR_ERR2_MASK (0x4U)
|
|
#define DMA_ERR_ERR2_SHIFT (2U)
|
|
/*! ERR2 - Error In Channel 2
|
|
* 0b0..An error in this channel has not occurred
|
|
* 0b1..An error in this channel has occurred
|
|
*/
|
|
#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
|
|
#define DMA_ERR_ERR3_MASK (0x8U)
|
|
#define DMA_ERR_ERR3_SHIFT (3U)
|
|
/*! ERR3 - Error In Channel 3
|
|
* 0b0..An error in this channel has not occurred
|
|
* 0b1..An error in this channel has occurred
|
|
*/
|
|
#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
|
|
#define DMA_ERR_ERR4_MASK (0x10U)
|
|
#define DMA_ERR_ERR4_SHIFT (4U)
|
|
/*! ERR4 - Error In Channel 4
|
|
* 0b0..An error in this channel has not occurred
|
|
* 0b1..An error in this channel has occurred
|
|
*/
|
|
#define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
|
|
#define DMA_ERR_ERR5_MASK (0x20U)
|
|
#define DMA_ERR_ERR5_SHIFT (5U)
|
|
/*! ERR5 - Error In Channel 5
|
|
* 0b0..An error in this channel has not occurred
|
|
* 0b1..An error in this channel has occurred
|
|
*/
|
|
#define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
|
|
#define DMA_ERR_ERR6_MASK (0x40U)
|
|
#define DMA_ERR_ERR6_SHIFT (6U)
|
|
/*! ERR6 - Error In Channel 6
|
|
* 0b0..An error in this channel has not occurred
|
|
* 0b1..An error in this channel has occurred
|
|
*/
|
|
#define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
|
|
#define DMA_ERR_ERR7_MASK (0x80U)
|
|
#define DMA_ERR_ERR7_SHIFT (7U)
|
|
/*! ERR7 - Error In Channel 7
|
|
* 0b0..An error in this channel has not occurred
|
|
* 0b1..An error in this channel has occurred
|
|
*/
|
|
#define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
|
|
#define DMA_ERR_ERR8_MASK (0x100U)
|
|
#define DMA_ERR_ERR8_SHIFT (8U)
|
|
/*! ERR8 - Error In Channel 8
|
|
* 0b0..An error in this channel has not occurred
|
|
* 0b1..An error in this channel has occurred
|
|
*/
|
|
#define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
|
|
#define DMA_ERR_ERR9_MASK (0x200U)
|
|
#define DMA_ERR_ERR9_SHIFT (9U)
|
|
/*! ERR9 - Error In Channel 9
|
|
* 0b0..An error in this channel has not occurred
|
|
* 0b1..An error in this channel has occurred
|
|
*/
|
|
#define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
|
|
#define DMA_ERR_ERR10_MASK (0x400U)
|
|
#define DMA_ERR_ERR10_SHIFT (10U)
|
|
/*! ERR10 - Error In Channel 10
|
|
* 0b0..An error in this channel has not occurred
|
|
* 0b1..An error in this channel has occurred
|
|
*/
|
|
#define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
|
|
#define DMA_ERR_ERR11_MASK (0x800U)
|
|
#define DMA_ERR_ERR11_SHIFT (11U)
|
|
/*! ERR11 - Error In Channel 11
|
|
* 0b0..An error in this channel has not occurred
|
|
* 0b1..An error in this channel has occurred
|
|
*/
|
|
#define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
|
|
#define DMA_ERR_ERR12_MASK (0x1000U)
|
|
#define DMA_ERR_ERR12_SHIFT (12U)
|
|
/*! ERR12 - Error In Channel 12
|
|
* 0b0..An error in this channel has not occurred
|
|
* 0b1..An error in this channel has occurred
|
|
*/
|
|
#define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
|
|
#define DMA_ERR_ERR13_MASK (0x2000U)
|
|
#define DMA_ERR_ERR13_SHIFT (13U)
|
|
/*! ERR13 - Error In Channel 13
|
|
* 0b0..An error in this channel has not occurred
|
|
* 0b1..An error in this channel has occurred
|
|
*/
|
|
#define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
|
|
#define DMA_ERR_ERR14_MASK (0x4000U)
|
|
#define DMA_ERR_ERR14_SHIFT (14U)
|
|
/*! ERR14 - Error In Channel 14
|
|
* 0b0..An error in this channel has not occurred
|
|
* 0b1..An error in this channel has occurred
|
|
*/
|
|
#define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
|
|
#define DMA_ERR_ERR15_MASK (0x8000U)
|
|
#define DMA_ERR_ERR15_SHIFT (15U)
|
|
/*! ERR15 - Error In Channel 15
|
|
* 0b0..An error in this channel has not occurred
|
|
* 0b1..An error in this channel has occurred
|
|
*/
|
|
#define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
|
|
#define DMA_ERR_ERR16_MASK (0x10000U)
|
|
#define DMA_ERR_ERR16_SHIFT (16U)
|
|
/*! ERR16 - Error In Channel 16
|
|
* 0b0..An error in this channel has not occurred
|
|
* 0b1..An error in this channel has occurred
|
|
*/
|
|
#define DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)
|
|
#define DMA_ERR_ERR17_MASK (0x20000U)
|
|
#define DMA_ERR_ERR17_SHIFT (17U)
|
|
/*! ERR17 - Error In Channel 17
|
|
* 0b0..An error in this channel has not occurred
|
|
* 0b1..An error in this channel has occurred
|
|
*/
|
|
#define DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)
|
|
#define DMA_ERR_ERR18_MASK (0x40000U)
|
|
#define DMA_ERR_ERR18_SHIFT (18U)
|
|
/*! ERR18 - Error In Channel 18
|
|
* 0b0..An error in this channel has not occurred
|
|
* 0b1..An error in this channel has occurred
|
|
*/
|
|
#define DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)
|
|
#define DMA_ERR_ERR19_MASK (0x80000U)
|
|
#define DMA_ERR_ERR19_SHIFT (19U)
|
|
/*! ERR19 - Error In Channel 19
|
|
* 0b0..An error in this channel has not occurred
|
|
* 0b1..An error in this channel has occurred
|
|
*/
|
|
#define DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)
|
|
#define DMA_ERR_ERR20_MASK (0x100000U)
|
|
#define DMA_ERR_ERR20_SHIFT (20U)
|
|
/*! ERR20 - Error In Channel 20
|
|
* 0b0..An error in this channel has not occurred
|
|
* 0b1..An error in this channel has occurred
|
|
*/
|
|
#define DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)
|
|
#define DMA_ERR_ERR21_MASK (0x200000U)
|
|
#define DMA_ERR_ERR21_SHIFT (21U)
|
|
/*! ERR21 - Error In Channel 21
|
|
* 0b0..An error in this channel has not occurred
|
|
* 0b1..An error in this channel has occurred
|
|
*/
|
|
#define DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)
|
|
#define DMA_ERR_ERR22_MASK (0x400000U)
|
|
#define DMA_ERR_ERR22_SHIFT (22U)
|
|
/*! ERR22 - Error In Channel 22
|
|
* 0b0..An error in this channel has not occurred
|
|
* 0b1..An error in this channel has occurred
|
|
*/
|
|
#define DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)
|
|
#define DMA_ERR_ERR23_MASK (0x800000U)
|
|
#define DMA_ERR_ERR23_SHIFT (23U)
|
|
/*! ERR23 - Error In Channel 23
|
|
* 0b0..An error in this channel has not occurred
|
|
* 0b1..An error in this channel has occurred
|
|
*/
|
|
#define DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)
|
|
#define DMA_ERR_ERR24_MASK (0x1000000U)
|
|
#define DMA_ERR_ERR24_SHIFT (24U)
|
|
/*! ERR24 - Error In Channel 24
|
|
* 0b0..An error in this channel has not occurred
|
|
* 0b1..An error in this channel has occurred
|
|
*/
|
|
#define DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)
|
|
#define DMA_ERR_ERR25_MASK (0x2000000U)
|
|
#define DMA_ERR_ERR25_SHIFT (25U)
|
|
/*! ERR25 - Error In Channel 25
|
|
* 0b0..An error in this channel has not occurred
|
|
* 0b1..An error in this channel has occurred
|
|
*/
|
|
#define DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)
|
|
#define DMA_ERR_ERR26_MASK (0x4000000U)
|
|
#define DMA_ERR_ERR26_SHIFT (26U)
|
|
/*! ERR26 - Error In Channel 26
|
|
* 0b0..An error in this channel has not occurred
|
|
* 0b1..An error in this channel has occurred
|
|
*/
|
|
#define DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)
|
|
#define DMA_ERR_ERR27_MASK (0x8000000U)
|
|
#define DMA_ERR_ERR27_SHIFT (27U)
|
|
/*! ERR27 - Error In Channel 27
|
|
* 0b0..An error in this channel has not occurred
|
|
* 0b1..An error in this channel has occurred
|
|
*/
|
|
#define DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)
|
|
#define DMA_ERR_ERR28_MASK (0x10000000U)
|
|
#define DMA_ERR_ERR28_SHIFT (28U)
|
|
/*! ERR28 - Error In Channel 28
|
|
* 0b0..An error in this channel has not occurred
|
|
* 0b1..An error in this channel has occurred
|
|
*/
|
|
#define DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)
|
|
#define DMA_ERR_ERR29_MASK (0x20000000U)
|
|
#define DMA_ERR_ERR29_SHIFT (29U)
|
|
/*! ERR29 - Error In Channel 29
|
|
* 0b0..An error in this channel has not occurred
|
|
* 0b1..An error in this channel has occurred
|
|
*/
|
|
#define DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)
|
|
#define DMA_ERR_ERR30_MASK (0x40000000U)
|
|
#define DMA_ERR_ERR30_SHIFT (30U)
|
|
/*! ERR30 - Error In Channel 30
|
|
* 0b0..An error in this channel has not occurred
|
|
* 0b1..An error in this channel has occurred
|
|
*/
|
|
#define DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)
|
|
#define DMA_ERR_ERR31_MASK (0x80000000U)
|
|
#define DMA_ERR_ERR31_SHIFT (31U)
|
|
/*! ERR31 - Error In Channel 31
|
|
* 0b0..An error in this channel has not occurred
|
|
* 0b1..An error in this channel has occurred
|
|
*/
|
|
#define DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name HRS - Hardware Request Status Register */
|
|
/*! @{ */
|
|
#define DMA_HRS_HRS0_MASK (0x1U)
|
|
#define DMA_HRS_HRS0_SHIFT (0U)
|
|
/*! HRS0 - Hardware Request Status Channel 0
|
|
* 0b0..A hardware service request for channel 0 is not present
|
|
* 0b1..A hardware service request for channel 0 is present
|
|
*/
|
|
#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
|
|
#define DMA_HRS_HRS1_MASK (0x2U)
|
|
#define DMA_HRS_HRS1_SHIFT (1U)
|
|
/*! HRS1 - Hardware Request Status Channel 1
|
|
* 0b0..A hardware service request for channel 1 is not present
|
|
* 0b1..A hardware service request for channel 1 is present
|
|
*/
|
|
#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
|
|
#define DMA_HRS_HRS2_MASK (0x4U)
|
|
#define DMA_HRS_HRS2_SHIFT (2U)
|
|
/*! HRS2 - Hardware Request Status Channel 2
|
|
* 0b0..A hardware service request for channel 2 is not present
|
|
* 0b1..A hardware service request for channel 2 is present
|
|
*/
|
|
#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
|
|
#define DMA_HRS_HRS3_MASK (0x8U)
|
|
#define DMA_HRS_HRS3_SHIFT (3U)
|
|
/*! HRS3 - Hardware Request Status Channel 3
|
|
* 0b0..A hardware service request for channel 3 is not present
|
|
* 0b1..A hardware service request for channel 3 is present
|
|
*/
|
|
#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
|
|
#define DMA_HRS_HRS4_MASK (0x10U)
|
|
#define DMA_HRS_HRS4_SHIFT (4U)
|
|
/*! HRS4 - Hardware Request Status Channel 4
|
|
* 0b0..A hardware service request for channel 4 is not present
|
|
* 0b1..A hardware service request for channel 4 is present
|
|
*/
|
|
#define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
|
|
#define DMA_HRS_HRS5_MASK (0x20U)
|
|
#define DMA_HRS_HRS5_SHIFT (5U)
|
|
/*! HRS5 - Hardware Request Status Channel 5
|
|
* 0b0..A hardware service request for channel 5 is not present
|
|
* 0b1..A hardware service request for channel 5 is present
|
|
*/
|
|
#define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
|
|
#define DMA_HRS_HRS6_MASK (0x40U)
|
|
#define DMA_HRS_HRS6_SHIFT (6U)
|
|
/*! HRS6 - Hardware Request Status Channel 6
|
|
* 0b0..A hardware service request for channel 6 is not present
|
|
* 0b1..A hardware service request for channel 6 is present
|
|
*/
|
|
#define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
|
|
#define DMA_HRS_HRS7_MASK (0x80U)
|
|
#define DMA_HRS_HRS7_SHIFT (7U)
|
|
/*! HRS7 - Hardware Request Status Channel 7
|
|
* 0b0..A hardware service request for channel 7 is not present
|
|
* 0b1..A hardware service request for channel 7 is present
|
|
*/
|
|
#define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
|
|
#define DMA_HRS_HRS8_MASK (0x100U)
|
|
#define DMA_HRS_HRS8_SHIFT (8U)
|
|
/*! HRS8 - Hardware Request Status Channel 8
|
|
* 0b0..A hardware service request for channel 8 is not present
|
|
* 0b1..A hardware service request for channel 8 is present
|
|
*/
|
|
#define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
|
|
#define DMA_HRS_HRS9_MASK (0x200U)
|
|
#define DMA_HRS_HRS9_SHIFT (9U)
|
|
/*! HRS9 - Hardware Request Status Channel 9
|
|
* 0b0..A hardware service request for channel 9 is not present
|
|
* 0b1..A hardware service request for channel 9 is present
|
|
*/
|
|
#define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
|
|
#define DMA_HRS_HRS10_MASK (0x400U)
|
|
#define DMA_HRS_HRS10_SHIFT (10U)
|
|
/*! HRS10 - Hardware Request Status Channel 10
|
|
* 0b0..A hardware service request for channel 10 is not present
|
|
* 0b1..A hardware service request for channel 10 is present
|
|
*/
|
|
#define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
|
|
#define DMA_HRS_HRS11_MASK (0x800U)
|
|
#define DMA_HRS_HRS11_SHIFT (11U)
|
|
/*! HRS11 - Hardware Request Status Channel 11
|
|
* 0b0..A hardware service request for channel 11 is not present
|
|
* 0b1..A hardware service request for channel 11 is present
|
|
*/
|
|
#define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
|
|
#define DMA_HRS_HRS12_MASK (0x1000U)
|
|
#define DMA_HRS_HRS12_SHIFT (12U)
|
|
/*! HRS12 - Hardware Request Status Channel 12
|
|
* 0b0..A hardware service request for channel 12 is not present
|
|
* 0b1..A hardware service request for channel 12 is present
|
|
*/
|
|
#define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
|
|
#define DMA_HRS_HRS13_MASK (0x2000U)
|
|
#define DMA_HRS_HRS13_SHIFT (13U)
|
|
/*! HRS13 - Hardware Request Status Channel 13
|
|
* 0b0..A hardware service request for channel 13 is not present
|
|
* 0b1..A hardware service request for channel 13 is present
|
|
*/
|
|
#define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
|
|
#define DMA_HRS_HRS14_MASK (0x4000U)
|
|
#define DMA_HRS_HRS14_SHIFT (14U)
|
|
/*! HRS14 - Hardware Request Status Channel 14
|
|
* 0b0..A hardware service request for channel 14 is not present
|
|
* 0b1..A hardware service request for channel 14 is present
|
|
*/
|
|
#define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
|
|
#define DMA_HRS_HRS15_MASK (0x8000U)
|
|
#define DMA_HRS_HRS15_SHIFT (15U)
|
|
/*! HRS15 - Hardware Request Status Channel 15
|
|
* 0b0..A hardware service request for channel 15 is not present
|
|
* 0b1..A hardware service request for channel 15 is present
|
|
*/
|
|
#define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
|
|
#define DMA_HRS_HRS16_MASK (0x10000U)
|
|
#define DMA_HRS_HRS16_SHIFT (16U)
|
|
/*! HRS16 - Hardware Request Status Channel 16
|
|
* 0b0..A hardware service request for channel 16 is not present
|
|
* 0b1..A hardware service request for channel 16 is present
|
|
*/
|
|
#define DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)
|
|
#define DMA_HRS_HRS17_MASK (0x20000U)
|
|
#define DMA_HRS_HRS17_SHIFT (17U)
|
|
/*! HRS17 - Hardware Request Status Channel 17
|
|
* 0b0..A hardware service request for channel 17 is not present
|
|
* 0b1..A hardware service request for channel 17 is present
|
|
*/
|
|
#define DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)
|
|
#define DMA_HRS_HRS18_MASK (0x40000U)
|
|
#define DMA_HRS_HRS18_SHIFT (18U)
|
|
/*! HRS18 - Hardware Request Status Channel 18
|
|
* 0b0..A hardware service request for channel 18 is not present
|
|
* 0b1..A hardware service request for channel 18 is present
|
|
*/
|
|
#define DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)
|
|
#define DMA_HRS_HRS19_MASK (0x80000U)
|
|
#define DMA_HRS_HRS19_SHIFT (19U)
|
|
/*! HRS19 - Hardware Request Status Channel 19
|
|
* 0b0..A hardware service request for channel 19 is not present
|
|
* 0b1..A hardware service request for channel 19 is present
|
|
*/
|
|
#define DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)
|
|
#define DMA_HRS_HRS20_MASK (0x100000U)
|
|
#define DMA_HRS_HRS20_SHIFT (20U)
|
|
/*! HRS20 - Hardware Request Status Channel 20
|
|
* 0b0..A hardware service request for channel 20 is not present
|
|
* 0b1..A hardware service request for channel 20 is present
|
|
*/
|
|
#define DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)
|
|
#define DMA_HRS_HRS21_MASK (0x200000U)
|
|
#define DMA_HRS_HRS21_SHIFT (21U)
|
|
/*! HRS21 - Hardware Request Status Channel 21
|
|
* 0b0..A hardware service request for channel 21 is not present
|
|
* 0b1..A hardware service request for channel 21 is present
|
|
*/
|
|
#define DMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)
|
|
#define DMA_HRS_HRS22_MASK (0x400000U)
|
|
#define DMA_HRS_HRS22_SHIFT (22U)
|
|
/*! HRS22 - Hardware Request Status Channel 22
|
|
* 0b0..A hardware service request for channel 22 is not present
|
|
* 0b1..A hardware service request for channel 22 is present
|
|
*/
|
|
#define DMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)
|
|
#define DMA_HRS_HRS23_MASK (0x800000U)
|
|
#define DMA_HRS_HRS23_SHIFT (23U)
|
|
/*! HRS23 - Hardware Request Status Channel 23
|
|
* 0b0..A hardware service request for channel 23 is not present
|
|
* 0b1..A hardware service request for channel 23 is present
|
|
*/
|
|
#define DMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)
|
|
#define DMA_HRS_HRS24_MASK (0x1000000U)
|
|
#define DMA_HRS_HRS24_SHIFT (24U)
|
|
/*! HRS24 - Hardware Request Status Channel 24
|
|
* 0b0..A hardware service request for channel 24 is not present
|
|
* 0b1..A hardware service request for channel 24 is present
|
|
*/
|
|
#define DMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)
|
|
#define DMA_HRS_HRS25_MASK (0x2000000U)
|
|
#define DMA_HRS_HRS25_SHIFT (25U)
|
|
/*! HRS25 - Hardware Request Status Channel 25
|
|
* 0b0..A hardware service request for channel 25 is not present
|
|
* 0b1..A hardware service request for channel 25 is present
|
|
*/
|
|
#define DMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)
|
|
#define DMA_HRS_HRS26_MASK (0x4000000U)
|
|
#define DMA_HRS_HRS26_SHIFT (26U)
|
|
/*! HRS26 - Hardware Request Status Channel 26
|
|
* 0b0..A hardware service request for channel 26 is not present
|
|
* 0b1..A hardware service request for channel 26 is present
|
|
*/
|
|
#define DMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)
|
|
#define DMA_HRS_HRS27_MASK (0x8000000U)
|
|
#define DMA_HRS_HRS27_SHIFT (27U)
|
|
/*! HRS27 - Hardware Request Status Channel 27
|
|
* 0b0..A hardware service request for channel 27 is not present
|
|
* 0b1..A hardware service request for channel 27 is present
|
|
*/
|
|
#define DMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)
|
|
#define DMA_HRS_HRS28_MASK (0x10000000U)
|
|
#define DMA_HRS_HRS28_SHIFT (28U)
|
|
/*! HRS28 - Hardware Request Status Channel 28
|
|
* 0b0..A hardware service request for channel 28 is not present
|
|
* 0b1..A hardware service request for channel 28 is present
|
|
*/
|
|
#define DMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)
|
|
#define DMA_HRS_HRS29_MASK (0x20000000U)
|
|
#define DMA_HRS_HRS29_SHIFT (29U)
|
|
/*! HRS29 - Hardware Request Status Channel 29
|
|
* 0b0..A hardware service request for channel 29 is not preset
|
|
* 0b1..A hardware service request for channel 29 is present
|
|
*/
|
|
#define DMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)
|
|
#define DMA_HRS_HRS30_MASK (0x40000000U)
|
|
#define DMA_HRS_HRS30_SHIFT (30U)
|
|
/*! HRS30 - Hardware Request Status Channel 30
|
|
* 0b0..A hardware service request for channel 30 is not present
|
|
* 0b1..A hardware service request for channel 30 is present
|
|
*/
|
|
#define DMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)
|
|
#define DMA_HRS_HRS31_MASK (0x80000000U)
|
|
#define DMA_HRS_HRS31_SHIFT (31U)
|
|
/*! HRS31 - Hardware Request Status Channel 31
|
|
* 0b0..A hardware service request for channel 31 is not present
|
|
* 0b1..A hardware service request for channel 31 is present
|
|
*/
|
|
#define DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name EARS - Enable Asynchronous Request in Stop Register */
|
|
/*! @{ */
|
|
#define DMA_EARS_EDREQ_0_MASK (0x1U)
|
|
#define DMA_EARS_EDREQ_0_SHIFT (0U)
|
|
/*! EDREQ_0 - Enable asynchronous DMA request in stop mode for channel 0.
|
|
* 0b0..Disable asynchronous DMA request for channel 0.
|
|
* 0b1..Enable asynchronous DMA request for channel 0.
|
|
*/
|
|
#define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
|
|
#define DMA_EARS_EDREQ_1_MASK (0x2U)
|
|
#define DMA_EARS_EDREQ_1_SHIFT (1U)
|
|
/*! EDREQ_1 - Enable asynchronous DMA request in stop mode for channel 1.
|
|
* 0b0..Disable asynchronous DMA request for channel 1
|
|
* 0b1..Enable asynchronous DMA request for channel 1.
|
|
*/
|
|
#define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
|
|
#define DMA_EARS_EDREQ_2_MASK (0x4U)
|
|
#define DMA_EARS_EDREQ_2_SHIFT (2U)
|
|
/*! EDREQ_2 - Enable asynchronous DMA request in stop mode for channel 2.
|
|
* 0b0..Disable asynchronous DMA request for channel 2.
|
|
* 0b1..Enable asynchronous DMA request for channel 2.
|
|
*/
|
|
#define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
|
|
#define DMA_EARS_EDREQ_3_MASK (0x8U)
|
|
#define DMA_EARS_EDREQ_3_SHIFT (3U)
|
|
/*! EDREQ_3 - Enable asynchronous DMA request in stop mode for channel 3.
|
|
* 0b0..Disable asynchronous DMA request for channel 3.
|
|
* 0b1..Enable asynchronous DMA request for channel 3.
|
|
*/
|
|
#define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
|
|
#define DMA_EARS_EDREQ_4_MASK (0x10U)
|
|
#define DMA_EARS_EDREQ_4_SHIFT (4U)
|
|
/*! EDREQ_4 - Enable asynchronous DMA request in stop mode for channel 4
|
|
* 0b0..Disable asynchronous DMA request for channel 4.
|
|
* 0b1..Enable asynchronous DMA request for channel 4.
|
|
*/
|
|
#define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)
|
|
#define DMA_EARS_EDREQ_5_MASK (0x20U)
|
|
#define DMA_EARS_EDREQ_5_SHIFT (5U)
|
|
/*! EDREQ_5 - Enable asynchronous DMA request in stop mode for channel 5
|
|
* 0b0..Disable asynchronous DMA request for channel 5.
|
|
* 0b1..Enable asynchronous DMA request for channel 5.
|
|
*/
|
|
#define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)
|
|
#define DMA_EARS_EDREQ_6_MASK (0x40U)
|
|
#define DMA_EARS_EDREQ_6_SHIFT (6U)
|
|
/*! EDREQ_6 - Enable asynchronous DMA request in stop mode for channel 6
|
|
* 0b0..Disable asynchronous DMA request for channel 6.
|
|
* 0b1..Enable asynchronous DMA request for channel 6.
|
|
*/
|
|
#define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)
|
|
#define DMA_EARS_EDREQ_7_MASK (0x80U)
|
|
#define DMA_EARS_EDREQ_7_SHIFT (7U)
|
|
/*! EDREQ_7 - Enable asynchronous DMA request in stop mode for channel 7
|
|
* 0b0..Disable asynchronous DMA request for channel 7.
|
|
* 0b1..Enable asynchronous DMA request for channel 7.
|
|
*/
|
|
#define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)
|
|
#define DMA_EARS_EDREQ_8_MASK (0x100U)
|
|
#define DMA_EARS_EDREQ_8_SHIFT (8U)
|
|
/*! EDREQ_8 - Enable asynchronous DMA request in stop mode for channel 8
|
|
* 0b0..Disable asynchronous DMA request for channel 8.
|
|
* 0b1..Enable asynchronous DMA request for channel 8.
|
|
*/
|
|
#define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)
|
|
#define DMA_EARS_EDREQ_9_MASK (0x200U)
|
|
#define DMA_EARS_EDREQ_9_SHIFT (9U)
|
|
/*! EDREQ_9 - Enable asynchronous DMA request in stop mode for channel 9
|
|
* 0b0..Disable asynchronous DMA request for channel 9.
|
|
* 0b1..Enable asynchronous DMA request for channel 9.
|
|
*/
|
|
#define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)
|
|
#define DMA_EARS_EDREQ_10_MASK (0x400U)
|
|
#define DMA_EARS_EDREQ_10_SHIFT (10U)
|
|
/*! EDREQ_10 - Enable asynchronous DMA request in stop mode for channel 10
|
|
* 0b0..Disable asynchronous DMA request for channel 10.
|
|
* 0b1..Enable asynchronous DMA request for channel 10.
|
|
*/
|
|
#define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)
|
|
#define DMA_EARS_EDREQ_11_MASK (0x800U)
|
|
#define DMA_EARS_EDREQ_11_SHIFT (11U)
|
|
/*! EDREQ_11 - Enable asynchronous DMA request in stop mode for channel 11
|
|
* 0b0..Disable asynchronous DMA request for channel 11.
|
|
* 0b1..Enable asynchronous DMA request for channel 11.
|
|
*/
|
|
#define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)
|
|
#define DMA_EARS_EDREQ_12_MASK (0x1000U)
|
|
#define DMA_EARS_EDREQ_12_SHIFT (12U)
|
|
/*! EDREQ_12 - Enable asynchronous DMA request in stop mode for channel 12
|
|
* 0b0..Disable asynchronous DMA request for channel 12.
|
|
* 0b1..Enable asynchronous DMA request for channel 12.
|
|
*/
|
|
#define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)
|
|
#define DMA_EARS_EDREQ_13_MASK (0x2000U)
|
|
#define DMA_EARS_EDREQ_13_SHIFT (13U)
|
|
/*! EDREQ_13 - Enable asynchronous DMA request in stop mode for channel 13
|
|
* 0b0..Disable asynchronous DMA request for channel 13.
|
|
* 0b1..Enable asynchronous DMA request for channel 13.
|
|
*/
|
|
#define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)
|
|
#define DMA_EARS_EDREQ_14_MASK (0x4000U)
|
|
#define DMA_EARS_EDREQ_14_SHIFT (14U)
|
|
/*! EDREQ_14 - Enable asynchronous DMA request in stop mode for channel 14
|
|
* 0b0..Disable asynchronous DMA request for channel 14.
|
|
* 0b1..Enable asynchronous DMA request for channel 14.
|
|
*/
|
|
#define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)
|
|
#define DMA_EARS_EDREQ_15_MASK (0x8000U)
|
|
#define DMA_EARS_EDREQ_15_SHIFT (15U)
|
|
/*! EDREQ_15 - Enable asynchronous DMA request in stop mode for channel 15
|
|
* 0b0..Disable asynchronous DMA request for channel 15.
|
|
* 0b1..Enable asynchronous DMA request for channel 15.
|
|
*/
|
|
#define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)
|
|
#define DMA_EARS_EDREQ_16_MASK (0x10000U)
|
|
#define DMA_EARS_EDREQ_16_SHIFT (16U)
|
|
/*! EDREQ_16 - Enable asynchronous DMA request in stop mode for channel 16
|
|
* 0b0..Disable asynchronous DMA request for channel 16
|
|
* 0b1..Enable asynchronous DMA request for channel 16
|
|
*/
|
|
#define DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)
|
|
#define DMA_EARS_EDREQ_17_MASK (0x20000U)
|
|
#define DMA_EARS_EDREQ_17_SHIFT (17U)
|
|
/*! EDREQ_17 - Enable asynchronous DMA request in stop mode for channel 17
|
|
* 0b0..Disable asynchronous DMA request for channel 17
|
|
* 0b1..Enable asynchronous DMA request for channel 17
|
|
*/
|
|
#define DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)
|
|
#define DMA_EARS_EDREQ_18_MASK (0x40000U)
|
|
#define DMA_EARS_EDREQ_18_SHIFT (18U)
|
|
/*! EDREQ_18 - Enable asynchronous DMA request in stop mode for channel 18
|
|
* 0b0..Disable asynchronous DMA request for channel 18
|
|
* 0b1..Enable asynchronous DMA request for channel 18
|
|
*/
|
|
#define DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)
|
|
#define DMA_EARS_EDREQ_19_MASK (0x80000U)
|
|
#define DMA_EARS_EDREQ_19_SHIFT (19U)
|
|
/*! EDREQ_19 - Enable asynchronous DMA request in stop mode for channel 19
|
|
* 0b0..Disable asynchronous DMA request for channel 19
|
|
* 0b1..Enable asynchronous DMA request for channel 19
|
|
*/
|
|
#define DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)
|
|
#define DMA_EARS_EDREQ_20_MASK (0x100000U)
|
|
#define DMA_EARS_EDREQ_20_SHIFT (20U)
|
|
/*! EDREQ_20 - Enable asynchronous DMA request in stop mode for channel 20
|
|
* 0b0..Disable asynchronous DMA request for channel 20
|
|
* 0b1..Enable asynchronous DMA request for channel 20
|
|
*/
|
|
#define DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)
|
|
#define DMA_EARS_EDREQ_21_MASK (0x200000U)
|
|
#define DMA_EARS_EDREQ_21_SHIFT (21U)
|
|
/*! EDREQ_21 - Enable asynchronous DMA request in stop mode for channel 21
|
|
* 0b0..Disable asynchronous DMA request for channel 21
|
|
* 0b1..Enable asynchronous DMA request for channel 21
|
|
*/
|
|
#define DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)
|
|
#define DMA_EARS_EDREQ_22_MASK (0x400000U)
|
|
#define DMA_EARS_EDREQ_22_SHIFT (22U)
|
|
/*! EDREQ_22 - Enable asynchronous DMA request in stop mode for channel 22
|
|
* 0b0..Disable asynchronous DMA request for channel 22
|
|
* 0b1..Enable asynchronous DMA request for channel 22
|
|
*/
|
|
#define DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)
|
|
#define DMA_EARS_EDREQ_23_MASK (0x800000U)
|
|
#define DMA_EARS_EDREQ_23_SHIFT (23U)
|
|
/*! EDREQ_23 - Enable asynchronous DMA request in stop mode for channel 23
|
|
* 0b0..Disable asynchronous DMA request for channel 23
|
|
* 0b1..Enable asynchronous DMA request for channel 23
|
|
*/
|
|
#define DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)
|
|
#define DMA_EARS_EDREQ_24_MASK (0x1000000U)
|
|
#define DMA_EARS_EDREQ_24_SHIFT (24U)
|
|
/*! EDREQ_24 - Enable asynchronous DMA request in stop mode for channel 24
|
|
* 0b0..Disable asynchronous DMA request for channel 24
|
|
* 0b1..Enable asynchronous DMA request for channel 24
|
|
*/
|
|
#define DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)
|
|
#define DMA_EARS_EDREQ_25_MASK (0x2000000U)
|
|
#define DMA_EARS_EDREQ_25_SHIFT (25U)
|
|
/*! EDREQ_25 - Enable asynchronous DMA request in stop mode for channel 25
|
|
* 0b0..Disable asynchronous DMA request for channel 25
|
|
* 0b1..Enable asynchronous DMA request for channel 25
|
|
*/
|
|
#define DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)
|
|
#define DMA_EARS_EDREQ_26_MASK (0x4000000U)
|
|
#define DMA_EARS_EDREQ_26_SHIFT (26U)
|
|
/*! EDREQ_26 - Enable asynchronous DMA request in stop mode for channel 26
|
|
* 0b0..Disable asynchronous DMA request for channel 26
|
|
* 0b1..Enable asynchronous DMA request for channel 26
|
|
*/
|
|
#define DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)
|
|
#define DMA_EARS_EDREQ_27_MASK (0x8000000U)
|
|
#define DMA_EARS_EDREQ_27_SHIFT (27U)
|
|
/*! EDREQ_27 - Enable asynchronous DMA request in stop mode for channel 27
|
|
* 0b0..Disable asynchronous DMA request for channel 27
|
|
* 0b1..Enable asynchronous DMA request for channel 27
|
|
*/
|
|
#define DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)
|
|
#define DMA_EARS_EDREQ_28_MASK (0x10000000U)
|
|
#define DMA_EARS_EDREQ_28_SHIFT (28U)
|
|
/*! EDREQ_28 - Enable asynchronous DMA request in stop mode for channel 28
|
|
* 0b0..Disable asynchronous DMA request for channel 28
|
|
* 0b1..Enable asynchronous DMA request for channel 28
|
|
*/
|
|
#define DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)
|
|
#define DMA_EARS_EDREQ_29_MASK (0x20000000U)
|
|
#define DMA_EARS_EDREQ_29_SHIFT (29U)
|
|
/*! EDREQ_29 - Enable asynchronous DMA request in stop mode for channel 29
|
|
* 0b0..Disable asynchronous DMA request for channel 29
|
|
* 0b1..Enable asynchronous DMA request for channel 29
|
|
*/
|
|
#define DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)
|
|
#define DMA_EARS_EDREQ_30_MASK (0x40000000U)
|
|
#define DMA_EARS_EDREQ_30_SHIFT (30U)
|
|
/*! EDREQ_30 - Enable asynchronous DMA request in stop mode for channel 30
|
|
* 0b0..Disable asynchronous DMA request for channel 30
|
|
* 0b1..Enable asynchronous DMA request for channel 30
|
|
*/
|
|
#define DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)
|
|
#define DMA_EARS_EDREQ_31_MASK (0x80000000U)
|
|
#define DMA_EARS_EDREQ_31_SHIFT (31U)
|
|
/*! EDREQ_31 - Enable asynchronous DMA request in stop mode for channel 31
|
|
* 0b0..Disable asynchronous DMA request for channel 31
|
|
* 0b1..Enable asynchronous DMA request for channel 31
|
|
*/
|
|
#define DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DCHPRI3 - Channel n Priority Register */
|
|
/*! @{ */
|
|
#define DMA_DCHPRI3_CHPRI_MASK (0xFU)
|
|
#define DMA_DCHPRI3_CHPRI_SHIFT (0U)
|
|
#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
|
|
#define DMA_DCHPRI3_GRPPRI_MASK (0x30U)
|
|
#define DMA_DCHPRI3_GRPPRI_SHIFT (4U)
|
|
#define DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)
|
|
#define DMA_DCHPRI3_DPA_MASK (0x40U)
|
|
#define DMA_DCHPRI3_DPA_SHIFT (6U)
|
|
/*! DPA - Disable Preempt Ability. This field resets to 0.
|
|
* 0b0..Channel n can suspend a lower priority channel.
|
|
* 0b1..Channel n cannot suspend any channel, regardless of channel priority.
|
|
*/
|
|
#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
|
|
#define DMA_DCHPRI3_ECP_MASK (0x80U)
|
|
#define DMA_DCHPRI3_ECP_SHIFT (7U)
|
|
/*! ECP - Enable Channel Preemption. This field resets to 0.
|
|
* 0b0..Channel n cannot be suspended by a higher priority channel's service request.
|
|
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
|
|
*/
|
|
#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DCHPRI2 - Channel n Priority Register */
|
|
/*! @{ */
|
|
#define DMA_DCHPRI2_CHPRI_MASK (0xFU)
|
|
#define DMA_DCHPRI2_CHPRI_SHIFT (0U)
|
|
#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
|
|
#define DMA_DCHPRI2_GRPPRI_MASK (0x30U)
|
|
#define DMA_DCHPRI2_GRPPRI_SHIFT (4U)
|
|
#define DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)
|
|
#define DMA_DCHPRI2_DPA_MASK (0x40U)
|
|
#define DMA_DCHPRI2_DPA_SHIFT (6U)
|
|
/*! DPA - Disable Preempt Ability. This field resets to 0.
|
|
* 0b0..Channel n can suspend a lower priority channel.
|
|
* 0b1..Channel n cannot suspend any channel, regardless of channel priority.
|
|
*/
|
|
#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
|
|
#define DMA_DCHPRI2_ECP_MASK (0x80U)
|
|
#define DMA_DCHPRI2_ECP_SHIFT (7U)
|
|
/*! ECP - Enable Channel Preemption. This field resets to 0.
|
|
* 0b0..Channel n cannot be suspended by a higher priority channel's service request.
|
|
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
|
|
*/
|
|
#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DCHPRI1 - Channel n Priority Register */
|
|
/*! @{ */
|
|
#define DMA_DCHPRI1_CHPRI_MASK (0xFU)
|
|
#define DMA_DCHPRI1_CHPRI_SHIFT (0U)
|
|
#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
|
|
#define DMA_DCHPRI1_GRPPRI_MASK (0x30U)
|
|
#define DMA_DCHPRI1_GRPPRI_SHIFT (4U)
|
|
#define DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)
|
|
#define DMA_DCHPRI1_DPA_MASK (0x40U)
|
|
#define DMA_DCHPRI1_DPA_SHIFT (6U)
|
|
/*! DPA - Disable Preempt Ability. This field resets to 0.
|
|
* 0b0..Channel n can suspend a lower priority channel.
|
|
* 0b1..Channel n cannot suspend any channel, regardless of channel priority.
|
|
*/
|
|
#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
|
|
#define DMA_DCHPRI1_ECP_MASK (0x80U)
|
|
#define DMA_DCHPRI1_ECP_SHIFT (7U)
|
|
/*! ECP - Enable Channel Preemption. This field resets to 0.
|
|
* 0b0..Channel n cannot be suspended by a higher priority channel's service request.
|
|
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
|
|
*/
|
|
#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DCHPRI0 - Channel n Priority Register */
|
|
/*! @{ */
|
|
#define DMA_DCHPRI0_CHPRI_MASK (0xFU)
|
|
#define DMA_DCHPRI0_CHPRI_SHIFT (0U)
|
|
#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
|
|
#define DMA_DCHPRI0_GRPPRI_MASK (0x30U)
|
|
#define DMA_DCHPRI0_GRPPRI_SHIFT (4U)
|
|
#define DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)
|
|
#define DMA_DCHPRI0_DPA_MASK (0x40U)
|
|
#define DMA_DCHPRI0_DPA_SHIFT (6U)
|
|
/*! DPA - Disable Preempt Ability. This field resets to 0.
|
|
* 0b0..Channel n can suspend a lower priority channel.
|
|
* 0b1..Channel n cannot suspend any channel, regardless of channel priority.
|
|
*/
|
|
#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
|
|
#define DMA_DCHPRI0_ECP_MASK (0x80U)
|
|
#define DMA_DCHPRI0_ECP_SHIFT (7U)
|
|
/*! ECP - Enable Channel Preemption. This field resets to 0.
|
|
* 0b0..Channel n cannot be suspended by a higher priority channel's service request.
|
|
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
|
|
*/
|
|
#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DCHPRI7 - Channel n Priority Register */
|
|
/*! @{ */
|
|
#define DMA_DCHPRI7_CHPRI_MASK (0xFU)
|
|
#define DMA_DCHPRI7_CHPRI_SHIFT (0U)
|
|
#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
|
|
#define DMA_DCHPRI7_GRPPRI_MASK (0x30U)
|
|
#define DMA_DCHPRI7_GRPPRI_SHIFT (4U)
|
|
#define DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)
|
|
#define DMA_DCHPRI7_DPA_MASK (0x40U)
|
|
#define DMA_DCHPRI7_DPA_SHIFT (6U)
|
|
/*! DPA - Disable Preempt Ability. This field resets to 0.
|
|
* 0b0..Channel n can suspend a lower priority channel.
|
|
* 0b1..Channel n cannot suspend any channel, regardless of channel priority.
|
|
*/
|
|
#define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
|
|
#define DMA_DCHPRI7_ECP_MASK (0x80U)
|
|
#define DMA_DCHPRI7_ECP_SHIFT (7U)
|
|
/*! ECP - Enable Channel Preemption. This field resets to 0.
|
|
* 0b0..Channel n cannot be suspended by a higher priority channel's service request.
|
|
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
|
|
*/
|
|
#define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DCHPRI6 - Channel n Priority Register */
|
|
/*! @{ */
|
|
#define DMA_DCHPRI6_CHPRI_MASK (0xFU)
|
|
#define DMA_DCHPRI6_CHPRI_SHIFT (0U)
|
|
#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
|
|
#define DMA_DCHPRI6_GRPPRI_MASK (0x30U)
|
|
#define DMA_DCHPRI6_GRPPRI_SHIFT (4U)
|
|
#define DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)
|
|
#define DMA_DCHPRI6_DPA_MASK (0x40U)
|
|
#define DMA_DCHPRI6_DPA_SHIFT (6U)
|
|
/*! DPA - Disable Preempt Ability. This field resets to 0.
|
|
* 0b0..Channel n can suspend a lower priority channel.
|
|
* 0b1..Channel n cannot suspend any channel, regardless of channel priority.
|
|
*/
|
|
#define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
|
|
#define DMA_DCHPRI6_ECP_MASK (0x80U)
|
|
#define DMA_DCHPRI6_ECP_SHIFT (7U)
|
|
/*! ECP - Enable Channel Preemption. This field resets to 0.
|
|
* 0b0..Channel n cannot be suspended by a higher priority channel's service request.
|
|
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
|
|
*/
|
|
#define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DCHPRI5 - Channel n Priority Register */
|
|
/*! @{ */
|
|
#define DMA_DCHPRI5_CHPRI_MASK (0xFU)
|
|
#define DMA_DCHPRI5_CHPRI_SHIFT (0U)
|
|
#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
|
|
#define DMA_DCHPRI5_GRPPRI_MASK (0x30U)
|
|
#define DMA_DCHPRI5_GRPPRI_SHIFT (4U)
|
|
#define DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)
|
|
#define DMA_DCHPRI5_DPA_MASK (0x40U)
|
|
#define DMA_DCHPRI5_DPA_SHIFT (6U)
|
|
/*! DPA - Disable Preempt Ability. This field resets to 0.
|
|
* 0b0..Channel n can suspend a lower priority channel.
|
|
* 0b1..Channel n cannot suspend any channel, regardless of channel priority.
|
|
*/
|
|
#define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
|
|
#define DMA_DCHPRI5_ECP_MASK (0x80U)
|
|
#define DMA_DCHPRI5_ECP_SHIFT (7U)
|
|
/*! ECP - Enable Channel Preemption. This field resets to 0.
|
|
* 0b0..Channel n cannot be suspended by a higher priority channel's service request.
|
|
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
|
|
*/
|
|
#define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DCHPRI4 - Channel n Priority Register */
|
|
/*! @{ */
|
|
#define DMA_DCHPRI4_CHPRI_MASK (0xFU)
|
|
#define DMA_DCHPRI4_CHPRI_SHIFT (0U)
|
|
#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
|
|
#define DMA_DCHPRI4_GRPPRI_MASK (0x30U)
|
|
#define DMA_DCHPRI4_GRPPRI_SHIFT (4U)
|
|
#define DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)
|
|
#define DMA_DCHPRI4_DPA_MASK (0x40U)
|
|
#define DMA_DCHPRI4_DPA_SHIFT (6U)
|
|
/*! DPA - Disable Preempt Ability. This field resets to 0.
|
|
* 0b0..Channel n can suspend a lower priority channel.
|
|
* 0b1..Channel n cannot suspend any channel, regardless of channel priority.
|
|
*/
|
|
#define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
|
|
#define DMA_DCHPRI4_ECP_MASK (0x80U)
|
|
#define DMA_DCHPRI4_ECP_SHIFT (7U)
|
|
/*! ECP - Enable Channel Preemption. This field resets to 0.
|
|
* 0b0..Channel n cannot be suspended by a higher priority channel's service request.
|
|
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
|
|
*/
|
|
#define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DCHPRI11 - Channel n Priority Register */
|
|
/*! @{ */
|
|
#define DMA_DCHPRI11_CHPRI_MASK (0xFU)
|
|
#define DMA_DCHPRI11_CHPRI_SHIFT (0U)
|
|
#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)
|
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#define DMA_DCHPRI11_GRPPRI_MASK (0x30U)
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#define DMA_DCHPRI11_GRPPRI_SHIFT (4U)
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#define DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)
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#define DMA_DCHPRI11_DPA_MASK (0x40U)
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#define DMA_DCHPRI11_DPA_SHIFT (6U)
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/*! DPA - Disable Preempt Ability. This field resets to 0.
|
|
* 0b0..Channel n can suspend a lower priority channel.
|
|
* 0b1..Channel n cannot suspend any channel, regardless of channel priority.
|
|
*/
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#define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
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#define DMA_DCHPRI11_ECP_MASK (0x80U)
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#define DMA_DCHPRI11_ECP_SHIFT (7U)
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/*! ECP - Enable Channel Preemption. This field resets to 0.
|
|
* 0b0..Channel n cannot be suspended by a higher priority channel's service request.
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|
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
|
|
*/
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#define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)
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/*! @} */
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|
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/*! @name DCHPRI10 - Channel n Priority Register */
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|
/*! @{ */
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#define DMA_DCHPRI10_CHPRI_MASK (0xFU)
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#define DMA_DCHPRI10_CHPRI_SHIFT (0U)
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#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)
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#define DMA_DCHPRI10_GRPPRI_MASK (0x30U)
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#define DMA_DCHPRI10_GRPPRI_SHIFT (4U)
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#define DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)
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#define DMA_DCHPRI10_DPA_MASK (0x40U)
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#define DMA_DCHPRI10_DPA_SHIFT (6U)
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/*! DPA - Disable Preempt Ability. This field resets to 0.
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* 0b0..Channel n can suspend a lower priority channel.
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* 0b1..Channel n cannot suspend any channel, regardless of channel priority.
|
|
*/
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#define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
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#define DMA_DCHPRI10_ECP_MASK (0x80U)
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#define DMA_DCHPRI10_ECP_SHIFT (7U)
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/*! ECP - Enable Channel Preemption. This field resets to 0.
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* 0b0..Channel n cannot be suspended by a higher priority channel's service request.
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* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
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|
*/
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#define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)
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/*! @} */
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/*! @name DCHPRI9 - Channel n Priority Register */
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/*! @{ */
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#define DMA_DCHPRI9_CHPRI_MASK (0xFU)
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#define DMA_DCHPRI9_CHPRI_SHIFT (0U)
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#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)
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#define DMA_DCHPRI9_GRPPRI_MASK (0x30U)
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#define DMA_DCHPRI9_GRPPRI_SHIFT (4U)
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#define DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)
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#define DMA_DCHPRI9_DPA_MASK (0x40U)
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#define DMA_DCHPRI9_DPA_SHIFT (6U)
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/*! DPA - Disable Preempt Ability. This field resets to 0.
|
|
* 0b0..Channel n can suspend a lower priority channel.
|
|
* 0b1..Channel n cannot suspend any channel, regardless of channel priority.
|
|
*/
|
|
#define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
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#define DMA_DCHPRI9_ECP_MASK (0x80U)
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#define DMA_DCHPRI9_ECP_SHIFT (7U)
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/*! ECP - Enable Channel Preemption. This field resets to 0.
|
|
* 0b0..Channel n cannot be suspended by a higher priority channel's service request.
|
|
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
|
|
*/
|
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#define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)
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/*! @} */
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|
|
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/*! @name DCHPRI8 - Channel n Priority Register */
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|
/*! @{ */
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|
#define DMA_DCHPRI8_CHPRI_MASK (0xFU)
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#define DMA_DCHPRI8_CHPRI_SHIFT (0U)
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#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)
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#define DMA_DCHPRI8_GRPPRI_MASK (0x30U)
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#define DMA_DCHPRI8_GRPPRI_SHIFT (4U)
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#define DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)
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|
#define DMA_DCHPRI8_DPA_MASK (0x40U)
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|
#define DMA_DCHPRI8_DPA_SHIFT (6U)
|
|
/*! DPA - Disable Preempt Ability. This field resets to 0.
|
|
* 0b0..Channel n can suspend a lower priority channel.
|
|
* 0b1..Channel n cannot suspend any channel, regardless of channel priority.
|
|
*/
|
|
#define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
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|
#define DMA_DCHPRI8_ECP_MASK (0x80U)
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|
#define DMA_DCHPRI8_ECP_SHIFT (7U)
|
|
/*! ECP - Enable Channel Preemption. This field resets to 0.
|
|
* 0b0..Channel n cannot be suspended by a higher priority channel's service request.
|
|
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
|
|
*/
|
|
#define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)
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|
/*! @} */
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|
|
|
/*! @name DCHPRI15 - Channel n Priority Register */
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|
/*! @{ */
|
|
#define DMA_DCHPRI15_CHPRI_MASK (0xFU)
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|
#define DMA_DCHPRI15_CHPRI_SHIFT (0U)
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|
#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)
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|
#define DMA_DCHPRI15_GRPPRI_MASK (0x30U)
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|
#define DMA_DCHPRI15_GRPPRI_SHIFT (4U)
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|
#define DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)
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|
#define DMA_DCHPRI15_DPA_MASK (0x40U)
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|
#define DMA_DCHPRI15_DPA_SHIFT (6U)
|
|
/*! DPA - Disable Preempt Ability. This field resets to 0.
|
|
* 0b0..Channel n can suspend a lower priority channel.
|
|
* 0b1..Channel n cannot suspend any channel, regardless of channel priority.
|
|
*/
|
|
#define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
|
|
#define DMA_DCHPRI15_ECP_MASK (0x80U)
|
|
#define DMA_DCHPRI15_ECP_SHIFT (7U)
|
|
/*! ECP - Enable Channel Preemption. This field resets to 0.
|
|
* 0b0..Channel n cannot be suspended by a higher priority channel's service request.
|
|
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
|
|
*/
|
|
#define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DCHPRI14 - Channel n Priority Register */
|
|
/*! @{ */
|
|
#define DMA_DCHPRI14_CHPRI_MASK (0xFU)
|
|
#define DMA_DCHPRI14_CHPRI_SHIFT (0U)
|
|
#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)
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|
#define DMA_DCHPRI14_GRPPRI_MASK (0x30U)
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|
#define DMA_DCHPRI14_GRPPRI_SHIFT (4U)
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|
#define DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)
|
|
#define DMA_DCHPRI14_DPA_MASK (0x40U)
|
|
#define DMA_DCHPRI14_DPA_SHIFT (6U)
|
|
/*! DPA - Disable Preempt Ability. This field resets to 0.
|
|
* 0b0..Channel n can suspend a lower priority channel.
|
|
* 0b1..Channel n cannot suspend any channel, regardless of channel priority.
|
|
*/
|
|
#define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
|
|
#define DMA_DCHPRI14_ECP_MASK (0x80U)
|
|
#define DMA_DCHPRI14_ECP_SHIFT (7U)
|
|
/*! ECP - Enable Channel Preemption. This field resets to 0.
|
|
* 0b0..Channel n cannot be suspended by a higher priority channel's service request.
|
|
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
|
|
*/
|
|
#define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DCHPRI13 - Channel n Priority Register */
|
|
/*! @{ */
|
|
#define DMA_DCHPRI13_CHPRI_MASK (0xFU)
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|
#define DMA_DCHPRI13_CHPRI_SHIFT (0U)
|
|
#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)
|
|
#define DMA_DCHPRI13_GRPPRI_MASK (0x30U)
|
|
#define DMA_DCHPRI13_GRPPRI_SHIFT (4U)
|
|
#define DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)
|
|
#define DMA_DCHPRI13_DPA_MASK (0x40U)
|
|
#define DMA_DCHPRI13_DPA_SHIFT (6U)
|
|
/*! DPA - Disable Preempt Ability. This field resets to 0.
|
|
* 0b0..Channel n can suspend a lower priority channel.
|
|
* 0b1..Channel n cannot suspend any channel, regardless of channel priority.
|
|
*/
|
|
#define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
|
|
#define DMA_DCHPRI13_ECP_MASK (0x80U)
|
|
#define DMA_DCHPRI13_ECP_SHIFT (7U)
|
|
/*! ECP - Enable Channel Preemption. This field resets to 0.
|
|
* 0b0..Channel n cannot be suspended by a higher priority channel's service request.
|
|
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
|
|
*/
|
|
#define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DCHPRI12 - Channel n Priority Register */
|
|
/*! @{ */
|
|
#define DMA_DCHPRI12_CHPRI_MASK (0xFU)
|
|
#define DMA_DCHPRI12_CHPRI_SHIFT (0U)
|
|
#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)
|
|
#define DMA_DCHPRI12_GRPPRI_MASK (0x30U)
|
|
#define DMA_DCHPRI12_GRPPRI_SHIFT (4U)
|
|
#define DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)
|
|
#define DMA_DCHPRI12_DPA_MASK (0x40U)
|
|
#define DMA_DCHPRI12_DPA_SHIFT (6U)
|
|
/*! DPA - Disable Preempt Ability. This field resets to 0.
|
|
* 0b0..Channel n can suspend a lower priority channel.
|
|
* 0b1..Channel n cannot suspend any channel, regardless of channel priority.
|
|
*/
|
|
#define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
|
|
#define DMA_DCHPRI12_ECP_MASK (0x80U)
|
|
#define DMA_DCHPRI12_ECP_SHIFT (7U)
|
|
/*! ECP - Enable Channel Preemption. This field resets to 0.
|
|
* 0b0..Channel n cannot be suspended by a higher priority channel's service request.
|
|
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
|
|
*/
|
|
#define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DCHPRI19 - Channel n Priority Register */
|
|
/*! @{ */
|
|
#define DMA_DCHPRI19_CHPRI_MASK (0xFU)
|
|
#define DMA_DCHPRI19_CHPRI_SHIFT (0U)
|
|
#define DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)
|
|
#define DMA_DCHPRI19_GRPPRI_MASK (0x30U)
|
|
#define DMA_DCHPRI19_GRPPRI_SHIFT (4U)
|
|
#define DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)
|
|
#define DMA_DCHPRI19_DPA_MASK (0x40U)
|
|
#define DMA_DCHPRI19_DPA_SHIFT (6U)
|
|
/*! DPA - Disable Preempt Ability. This field resets to 0.
|
|
* 0b0..Channel n can suspend a lower priority channel.
|
|
* 0b1..Channel n cannot suspend any channel, regardless of channel priority.
|
|
*/
|
|
#define DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)
|
|
#define DMA_DCHPRI19_ECP_MASK (0x80U)
|
|
#define DMA_DCHPRI19_ECP_SHIFT (7U)
|
|
/*! ECP - Enable Channel Preemption. This field resets to 0.
|
|
* 0b0..Channel n cannot be suspended by a higher priority channel's service request.
|
|
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
|
|
*/
|
|
#define DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DCHPRI18 - Channel n Priority Register */
|
|
/*! @{ */
|
|
#define DMA_DCHPRI18_CHPRI_MASK (0xFU)
|
|
#define DMA_DCHPRI18_CHPRI_SHIFT (0U)
|
|
#define DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)
|
|
#define DMA_DCHPRI18_GRPPRI_MASK (0x30U)
|
|
#define DMA_DCHPRI18_GRPPRI_SHIFT (4U)
|
|
#define DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)
|
|
#define DMA_DCHPRI18_DPA_MASK (0x40U)
|
|
#define DMA_DCHPRI18_DPA_SHIFT (6U)
|
|
/*! DPA - Disable Preempt Ability. This field resets to 0.
|
|
* 0b0..Channel n can suspend a lower priority channel.
|
|
* 0b1..Channel n cannot suspend any channel, regardless of channel priority.
|
|
*/
|
|
#define DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)
|
|
#define DMA_DCHPRI18_ECP_MASK (0x80U)
|
|
#define DMA_DCHPRI18_ECP_SHIFT (7U)
|
|
/*! ECP - Enable Channel Preemption. This field resets to 0.
|
|
* 0b0..Channel n cannot be suspended by a higher priority channel's service request.
|
|
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
|
|
*/
|
|
#define DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DCHPRI17 - Channel n Priority Register */
|
|
/*! @{ */
|
|
#define DMA_DCHPRI17_CHPRI_MASK (0xFU)
|
|
#define DMA_DCHPRI17_CHPRI_SHIFT (0U)
|
|
#define DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)
|
|
#define DMA_DCHPRI17_GRPPRI_MASK (0x30U)
|
|
#define DMA_DCHPRI17_GRPPRI_SHIFT (4U)
|
|
#define DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)
|
|
#define DMA_DCHPRI17_DPA_MASK (0x40U)
|
|
#define DMA_DCHPRI17_DPA_SHIFT (6U)
|
|
/*! DPA - Disable Preempt Ability. This field resets to 0.
|
|
* 0b0..Channel n can suspend a lower priority channel.
|
|
* 0b1..Channel n cannot suspend any channel, regardless of channel priority.
|
|
*/
|
|
#define DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)
|
|
#define DMA_DCHPRI17_ECP_MASK (0x80U)
|
|
#define DMA_DCHPRI17_ECP_SHIFT (7U)
|
|
/*! ECP - Enable Channel Preemption. This field resets to 0.
|
|
* 0b0..Channel n cannot be suspended by a higher priority channel's service request.
|
|
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
|
|
*/
|
|
#define DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DCHPRI16 - Channel n Priority Register */
|
|
/*! @{ */
|
|
#define DMA_DCHPRI16_CHPRI_MASK (0xFU)
|
|
#define DMA_DCHPRI16_CHPRI_SHIFT (0U)
|
|
#define DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)
|
|
#define DMA_DCHPRI16_GRPPRI_MASK (0x30U)
|
|
#define DMA_DCHPRI16_GRPPRI_SHIFT (4U)
|
|
#define DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)
|
|
#define DMA_DCHPRI16_DPA_MASK (0x40U)
|
|
#define DMA_DCHPRI16_DPA_SHIFT (6U)
|
|
/*! DPA - Disable Preempt Ability. This field resets to 0.
|
|
* 0b0..Channel n can suspend a lower priority channel.
|
|
* 0b1..Channel n cannot suspend any channel, regardless of channel priority.
|
|
*/
|
|
#define DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)
|
|
#define DMA_DCHPRI16_ECP_MASK (0x80U)
|
|
#define DMA_DCHPRI16_ECP_SHIFT (7U)
|
|
/*! ECP - Enable Channel Preemption. This field resets to 0.
|
|
* 0b0..Channel n cannot be suspended by a higher priority channel's service request.
|
|
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
|
|
*/
|
|
#define DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DCHPRI23 - Channel n Priority Register */
|
|
/*! @{ */
|
|
#define DMA_DCHPRI23_CHPRI_MASK (0xFU)
|
|
#define DMA_DCHPRI23_CHPRI_SHIFT (0U)
|
|
#define DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)
|
|
#define DMA_DCHPRI23_GRPPRI_MASK (0x30U)
|
|
#define DMA_DCHPRI23_GRPPRI_SHIFT (4U)
|
|
#define DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)
|
|
#define DMA_DCHPRI23_DPA_MASK (0x40U)
|
|
#define DMA_DCHPRI23_DPA_SHIFT (6U)
|
|
/*! DPA - Disable Preempt Ability. This field resets to 0.
|
|
* 0b0..Channel n can suspend a lower priority channel.
|
|
* 0b1..Channel n cannot suspend any channel, regardless of channel priority.
|
|
*/
|
|
#define DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)
|
|
#define DMA_DCHPRI23_ECP_MASK (0x80U)
|
|
#define DMA_DCHPRI23_ECP_SHIFT (7U)
|
|
/*! ECP - Enable Channel Preemption. This field resets to 0.
|
|
* 0b0..Channel n cannot be suspended by a higher priority channel's service request.
|
|
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
|
|
*/
|
|
#define DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DCHPRI22 - Channel n Priority Register */
|
|
/*! @{ */
|
|
#define DMA_DCHPRI22_CHPRI_MASK (0xFU)
|
|
#define DMA_DCHPRI22_CHPRI_SHIFT (0U)
|
|
#define DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)
|
|
#define DMA_DCHPRI22_GRPPRI_MASK (0x30U)
|
|
#define DMA_DCHPRI22_GRPPRI_SHIFT (4U)
|
|
#define DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)
|
|
#define DMA_DCHPRI22_DPA_MASK (0x40U)
|
|
#define DMA_DCHPRI22_DPA_SHIFT (6U)
|
|
/*! DPA - Disable Preempt Ability. This field resets to 0.
|
|
* 0b0..Channel n can suspend a lower priority channel.
|
|
* 0b1..Channel n cannot suspend any channel, regardless of channel priority.
|
|
*/
|
|
#define DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)
|
|
#define DMA_DCHPRI22_ECP_MASK (0x80U)
|
|
#define DMA_DCHPRI22_ECP_SHIFT (7U)
|
|
/*! ECP - Enable Channel Preemption. This field resets to 0.
|
|
* 0b0..Channel n cannot be suspended by a higher priority channel's service request.
|
|
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
|
|
*/
|
|
#define DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DCHPRI21 - Channel n Priority Register */
|
|
/*! @{ */
|
|
#define DMA_DCHPRI21_CHPRI_MASK (0xFU)
|
|
#define DMA_DCHPRI21_CHPRI_SHIFT (0U)
|
|
#define DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)
|
|
#define DMA_DCHPRI21_GRPPRI_MASK (0x30U)
|
|
#define DMA_DCHPRI21_GRPPRI_SHIFT (4U)
|
|
#define DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)
|
|
#define DMA_DCHPRI21_DPA_MASK (0x40U)
|
|
#define DMA_DCHPRI21_DPA_SHIFT (6U)
|
|
/*! DPA - Disable Preempt Ability. This field resets to 0.
|
|
* 0b0..Channel n can suspend a lower priority channel.
|
|
* 0b1..Channel n cannot suspend any channel, regardless of channel priority.
|
|
*/
|
|
#define DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)
|
|
#define DMA_DCHPRI21_ECP_MASK (0x80U)
|
|
#define DMA_DCHPRI21_ECP_SHIFT (7U)
|
|
/*! ECP - Enable Channel Preemption. This field resets to 0.
|
|
* 0b0..Channel n cannot be suspended by a higher priority channel's service request.
|
|
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
|
|
*/
|
|
#define DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DCHPRI20 - Channel n Priority Register */
|
|
/*! @{ */
|
|
#define DMA_DCHPRI20_CHPRI_MASK (0xFU)
|
|
#define DMA_DCHPRI20_CHPRI_SHIFT (0U)
|
|
#define DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)
|
|
#define DMA_DCHPRI20_GRPPRI_MASK (0x30U)
|
|
#define DMA_DCHPRI20_GRPPRI_SHIFT (4U)
|
|
#define DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)
|
|
#define DMA_DCHPRI20_DPA_MASK (0x40U)
|
|
#define DMA_DCHPRI20_DPA_SHIFT (6U)
|
|
/*! DPA - Disable Preempt Ability. This field resets to 0.
|
|
* 0b0..Channel n can suspend a lower priority channel.
|
|
* 0b1..Channel n cannot suspend any channel, regardless of channel priority.
|
|
*/
|
|
#define DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)
|
|
#define DMA_DCHPRI20_ECP_MASK (0x80U)
|
|
#define DMA_DCHPRI20_ECP_SHIFT (7U)
|
|
/*! ECP - Enable Channel Preemption. This field resets to 0.
|
|
* 0b0..Channel n cannot be suspended by a higher priority channel's service request.
|
|
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
|
|
*/
|
|
#define DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DCHPRI27 - Channel n Priority Register */
|
|
/*! @{ */
|
|
#define DMA_DCHPRI27_CHPRI_MASK (0xFU)
|
|
#define DMA_DCHPRI27_CHPRI_SHIFT (0U)
|
|
#define DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)
|
|
#define DMA_DCHPRI27_GRPPRI_MASK (0x30U)
|
|
#define DMA_DCHPRI27_GRPPRI_SHIFT (4U)
|
|
#define DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)
|
|
#define DMA_DCHPRI27_DPA_MASK (0x40U)
|
|
#define DMA_DCHPRI27_DPA_SHIFT (6U)
|
|
/*! DPA - Disable Preempt Ability. This field resets to 0.
|
|
* 0b0..Channel n can suspend a lower priority channel.
|
|
* 0b1..Channel n cannot suspend any channel, regardless of channel priority.
|
|
*/
|
|
#define DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)
|
|
#define DMA_DCHPRI27_ECP_MASK (0x80U)
|
|
#define DMA_DCHPRI27_ECP_SHIFT (7U)
|
|
/*! ECP - Enable Channel Preemption. This field resets to 0.
|
|
* 0b0..Channel n cannot be suspended by a higher priority channel's service request.
|
|
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
|
|
*/
|
|
#define DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DCHPRI26 - Channel n Priority Register */
|
|
/*! @{ */
|
|
#define DMA_DCHPRI26_CHPRI_MASK (0xFU)
|
|
#define DMA_DCHPRI26_CHPRI_SHIFT (0U)
|
|
#define DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)
|
|
#define DMA_DCHPRI26_GRPPRI_MASK (0x30U)
|
|
#define DMA_DCHPRI26_GRPPRI_SHIFT (4U)
|
|
#define DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)
|
|
#define DMA_DCHPRI26_DPA_MASK (0x40U)
|
|
#define DMA_DCHPRI26_DPA_SHIFT (6U)
|
|
/*! DPA - Disable Preempt Ability. This field resets to 0.
|
|
* 0b0..Channel n can suspend a lower priority channel.
|
|
* 0b1..Channel n cannot suspend any channel, regardless of channel priority.
|
|
*/
|
|
#define DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)
|
|
#define DMA_DCHPRI26_ECP_MASK (0x80U)
|
|
#define DMA_DCHPRI26_ECP_SHIFT (7U)
|
|
/*! ECP - Enable Channel Preemption. This field resets to 0.
|
|
* 0b0..Channel n cannot be suspended by a higher priority channel's service request.
|
|
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
|
|
*/
|
|
#define DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DCHPRI25 - Channel n Priority Register */
|
|
/*! @{ */
|
|
#define DMA_DCHPRI25_CHPRI_MASK (0xFU)
|
|
#define DMA_DCHPRI25_CHPRI_SHIFT (0U)
|
|
#define DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)
|
|
#define DMA_DCHPRI25_GRPPRI_MASK (0x30U)
|
|
#define DMA_DCHPRI25_GRPPRI_SHIFT (4U)
|
|
#define DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)
|
|
#define DMA_DCHPRI25_DPA_MASK (0x40U)
|
|
#define DMA_DCHPRI25_DPA_SHIFT (6U)
|
|
/*! DPA - Disable Preempt Ability. This field resets to 0.
|
|
* 0b0..Channel n can suspend a lower priority channel.
|
|
* 0b1..Channel n cannot suspend any channel, regardless of channel priority.
|
|
*/
|
|
#define DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)
|
|
#define DMA_DCHPRI25_ECP_MASK (0x80U)
|
|
#define DMA_DCHPRI25_ECP_SHIFT (7U)
|
|
/*! ECP - Enable Channel Preemption. This field resets to 0.
|
|
* 0b0..Channel n cannot be suspended by a higher priority channel's service request.
|
|
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
|
|
*/
|
|
#define DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DCHPRI24 - Channel n Priority Register */
|
|
/*! @{ */
|
|
#define DMA_DCHPRI24_CHPRI_MASK (0xFU)
|
|
#define DMA_DCHPRI24_CHPRI_SHIFT (0U)
|
|
#define DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)
|
|
#define DMA_DCHPRI24_GRPPRI_MASK (0x30U)
|
|
#define DMA_DCHPRI24_GRPPRI_SHIFT (4U)
|
|
#define DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)
|
|
#define DMA_DCHPRI24_DPA_MASK (0x40U)
|
|
#define DMA_DCHPRI24_DPA_SHIFT (6U)
|
|
/*! DPA - Disable Preempt Ability. This field resets to 0.
|
|
* 0b0..Channel n can suspend a lower priority channel.
|
|
* 0b1..Channel n cannot suspend any channel, regardless of channel priority.
|
|
*/
|
|
#define DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)
|
|
#define DMA_DCHPRI24_ECP_MASK (0x80U)
|
|
#define DMA_DCHPRI24_ECP_SHIFT (7U)
|
|
/*! ECP - Enable Channel Preemption. This field resets to 0.
|
|
* 0b0..Channel n cannot be suspended by a higher priority channel's service request.
|
|
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
|
|
*/
|
|
#define DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DCHPRI31 - Channel n Priority Register */
|
|
/*! @{ */
|
|
#define DMA_DCHPRI31_CHPRI_MASK (0xFU)
|
|
#define DMA_DCHPRI31_CHPRI_SHIFT (0U)
|
|
#define DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
|
|
#define DMA_DCHPRI31_GRPPRI_MASK (0x30U)
|
|
#define DMA_DCHPRI31_GRPPRI_SHIFT (4U)
|
|
#define DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)
|
|
#define DMA_DCHPRI31_DPA_MASK (0x40U)
|
|
#define DMA_DCHPRI31_DPA_SHIFT (6U)
|
|
/*! DPA - Disable Preempt Ability. This field resets to 0.
|
|
* 0b0..Channel n can suspend a lower priority channel.
|
|
* 0b1..Channel n cannot suspend any channel, regardless of channel priority.
|
|
*/
|
|
#define DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)
|
|
#define DMA_DCHPRI31_ECP_MASK (0x80U)
|
|
#define DMA_DCHPRI31_ECP_SHIFT (7U)
|
|
/*! ECP - Enable Channel Preemption. This field resets to 0.
|
|
* 0b0..Channel n cannot be suspended by a higher priority channel's service request.
|
|
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
|
|
*/
|
|
#define DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DCHPRI30 - Channel n Priority Register */
|
|
/*! @{ */
|
|
#define DMA_DCHPRI30_CHPRI_MASK (0xFU)
|
|
#define DMA_DCHPRI30_CHPRI_SHIFT (0U)
|
|
#define DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)
|
|
#define DMA_DCHPRI30_GRPPRI_MASK (0x30U)
|
|
#define DMA_DCHPRI30_GRPPRI_SHIFT (4U)
|
|
#define DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)
|
|
#define DMA_DCHPRI30_DPA_MASK (0x40U)
|
|
#define DMA_DCHPRI30_DPA_SHIFT (6U)
|
|
/*! DPA - Disable Preempt Ability. This field resets to 0.
|
|
* 0b0..Channel n can suspend a lower priority channel.
|
|
* 0b1..Channel n cannot suspend any channel, regardless of channel priority.
|
|
*/
|
|
#define DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)
|
|
#define DMA_DCHPRI30_ECP_MASK (0x80U)
|
|
#define DMA_DCHPRI30_ECP_SHIFT (7U)
|
|
/*! ECP - Enable Channel Preemption. This field resets to 0.
|
|
* 0b0..Channel n cannot be suspended by a higher priority channel's service request.
|
|
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
|
|
*/
|
|
#define DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DCHPRI29 - Channel n Priority Register */
|
|
/*! @{ */
|
|
#define DMA_DCHPRI29_CHPRI_MASK (0xFU)
|
|
#define DMA_DCHPRI29_CHPRI_SHIFT (0U)
|
|
#define DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)
|
|
#define DMA_DCHPRI29_GRPPRI_MASK (0x30U)
|
|
#define DMA_DCHPRI29_GRPPRI_SHIFT (4U)
|
|
#define DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)
|
|
#define DMA_DCHPRI29_DPA_MASK (0x40U)
|
|
#define DMA_DCHPRI29_DPA_SHIFT (6U)
|
|
/*! DPA - Disable Preempt Ability. This field resets to 0.
|
|
* 0b0..Channel n can suspend a lower priority channel.
|
|
* 0b1..Channel n cannot suspend any channel, regardless of channel priority.
|
|
*/
|
|
#define DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)
|
|
#define DMA_DCHPRI29_ECP_MASK (0x80U)
|
|
#define DMA_DCHPRI29_ECP_SHIFT (7U)
|
|
/*! ECP - Enable Channel Preemption. This field resets to 0.
|
|
* 0b0..Channel n cannot be suspended by a higher priority channel's service request.
|
|
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
|
|
*/
|
|
#define DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DCHPRI28 - Channel n Priority Register */
|
|
/*! @{ */
|
|
#define DMA_DCHPRI28_CHPRI_MASK (0xFU)
|
|
#define DMA_DCHPRI28_CHPRI_SHIFT (0U)
|
|
#define DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)
|
|
#define DMA_DCHPRI28_GRPPRI_MASK (0x30U)
|
|
#define DMA_DCHPRI28_GRPPRI_SHIFT (4U)
|
|
#define DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)
|
|
#define DMA_DCHPRI28_DPA_MASK (0x40U)
|
|
#define DMA_DCHPRI28_DPA_SHIFT (6U)
|
|
/*! DPA - Disable Preempt Ability. This field resets to 0.
|
|
* 0b0..Channel n can suspend a lower priority channel.
|
|
* 0b1..Channel n cannot suspend any channel, regardless of channel priority.
|
|
*/
|
|
#define DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)
|
|
#define DMA_DCHPRI28_ECP_MASK (0x80U)
|
|
#define DMA_DCHPRI28_ECP_SHIFT (7U)
|
|
/*! ECP - Enable Channel Preemption. This field resets to 0.
|
|
* 0b0..Channel n cannot be suspended by a higher priority channel's service request.
|
|
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
|
|
*/
|
|
#define DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SADDR - TCD Source Address */
|
|
/*! @{ */
|
|
#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
|
|
#define DMA_SADDR_SADDR_SHIFT (0U)
|
|
#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of DMA_SADDR */
|
|
#define DMA_SADDR_COUNT (32U)
|
|
|
|
/*! @name SOFF - TCD Signed Source Address Offset */
|
|
/*! @{ */
|
|
#define DMA_SOFF_SOFF_MASK (0xFFFFU)
|
|
#define DMA_SOFF_SOFF_SHIFT (0U)
|
|
#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of DMA_SOFF */
|
|
#define DMA_SOFF_COUNT (32U)
|
|
|
|
/*! @name ATTR - TCD Transfer Attributes */
|
|
/*! @{ */
|
|
#define DMA_ATTR_DSIZE_MASK (0x7U)
|
|
#define DMA_ATTR_DSIZE_SHIFT (0U)
|
|
#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
|
|
#define DMA_ATTR_DMOD_MASK (0xF8U)
|
|
#define DMA_ATTR_DMOD_SHIFT (3U)
|
|
#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
|
|
#define DMA_ATTR_SSIZE_MASK (0x700U)
|
|
#define DMA_ATTR_SSIZE_SHIFT (8U)
|
|
/*! SSIZE - Source data transfer size
|
|
* 0b000..8-bit
|
|
* 0b001..16-bit
|
|
* 0b010..32-bit
|
|
* 0b011..64-bit
|
|
* 0b100..Reserved
|
|
* 0b101..32-byte burst (4 beats of 64 bits)
|
|
* 0b110..Reserved
|
|
* 0b111..Reserved
|
|
*/
|
|
#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
|
|
#define DMA_ATTR_SMOD_MASK (0xF800U)
|
|
#define DMA_ATTR_SMOD_SHIFT (11U)
|
|
/*! SMOD - Source Address Modulo
|
|
* 0b00000..Source address modulo feature is disabled
|
|
* 0b00001-0b11111..This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
|
|
*/
|
|
#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of DMA_ATTR */
|
|
#define DMA_ATTR_COUNT (32U)
|
|
|
|
/*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */
|
|
/*! @{ */
|
|
#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
|
|
#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
|
|
#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of DMA_NBYTES_MLNO */
|
|
#define DMA_NBYTES_MLNO_COUNT (32U)
|
|
|
|
/*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */
|
|
/*! @{ */
|
|
#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
|
|
#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
|
|
#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
|
|
#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
|
|
#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
|
|
/*! DMLOE - Destination Minor Loop Offset enable
|
|
* 0b0..The minor loop offset is not applied to the DADDR
|
|
* 0b1..The minor loop offset is applied to the DADDR
|
|
*/
|
|
#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
|
|
#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
|
|
#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
|
|
/*! SMLOE - Source Minor Loop Offset Enable
|
|
* 0b0..The minor loop offset is not applied to the SADDR
|
|
* 0b1..The minor loop offset is applied to the SADDR
|
|
*/
|
|
#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of DMA_NBYTES_MLOFFNO */
|
|
#define DMA_NBYTES_MLOFFNO_COUNT (32U)
|
|
|
|
/*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */
|
|
/*! @{ */
|
|
#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
|
|
#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
|
|
#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
|
|
#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
|
|
#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
|
|
#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
|
|
#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
|
|
#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
|
|
/*! DMLOE - Destination Minor Loop Offset enable
|
|
* 0b0..The minor loop offset is not applied to the DADDR
|
|
* 0b1..The minor loop offset is applied to the DADDR
|
|
*/
|
|
#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
|
|
#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
|
|
#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
|
|
/*! SMLOE - Source Minor Loop Offset Enable
|
|
* 0b0..The minor loop offset is not applied to the SADDR
|
|
* 0b1..The minor loop offset is applied to the SADDR
|
|
*/
|
|
#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of DMA_NBYTES_MLOFFYES */
|
|
#define DMA_NBYTES_MLOFFYES_COUNT (32U)
|
|
|
|
/*! @name SLAST - TCD Last Source Address Adjustment */
|
|
/*! @{ */
|
|
#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
|
|
#define DMA_SLAST_SLAST_SHIFT (0U)
|
|
#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of DMA_SLAST */
|
|
#define DMA_SLAST_COUNT (32U)
|
|
|
|
/*! @name DADDR - TCD Destination Address */
|
|
/*! @{ */
|
|
#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
|
|
#define DMA_DADDR_DADDR_SHIFT (0U)
|
|
#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of DMA_DADDR */
|
|
#define DMA_DADDR_COUNT (32U)
|
|
|
|
/*! @name DOFF - TCD Signed Destination Address Offset */
|
|
/*! @{ */
|
|
#define DMA_DOFF_DOFF_MASK (0xFFFFU)
|
|
#define DMA_DOFF_DOFF_SHIFT (0U)
|
|
#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of DMA_DOFF */
|
|
#define DMA_DOFF_COUNT (32U)
|
|
|
|
/*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
|
|
/*! @{ */
|
|
#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
|
|
#define DMA_CITER_ELINKNO_CITER_SHIFT (0U)
|
|
#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
|
|
#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
|
|
#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
|
|
/*! ELINK - Enable channel-to-channel linking on minor-loop complete
|
|
* 0b0..The channel-to-channel linking is disabled
|
|
* 0b1..The channel-to-channel linking is enabled
|
|
*/
|
|
#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of DMA_CITER_ELINKNO */
|
|
#define DMA_CITER_ELINKNO_COUNT (32U)
|
|
|
|
/*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
|
|
/*! @{ */
|
|
#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
|
|
#define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
|
|
#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
|
|
#define DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U)
|
|
#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
|
|
#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
|
|
#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
|
|
#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
|
|
/*! ELINK - Enable channel-to-channel linking on minor-loop complete
|
|
* 0b0..The channel-to-channel linking is disabled
|
|
* 0b1..The channel-to-channel linking is enabled
|
|
*/
|
|
#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of DMA_CITER_ELINKYES */
|
|
#define DMA_CITER_ELINKYES_COUNT (32U)
|
|
|
|
/*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */
|
|
/*! @{ */
|
|
#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
|
|
#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
|
|
#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of DMA_DLAST_SGA */
|
|
#define DMA_DLAST_SGA_COUNT (32U)
|
|
|
|
/*! @name CSR - TCD Control and Status */
|
|
/*! @{ */
|
|
#define DMA_CSR_START_MASK (0x1U)
|
|
#define DMA_CSR_START_SHIFT (0U)
|
|
/*! START - Channel Start
|
|
* 0b0..The channel is not explicitly started.
|
|
* 0b1..The channel is explicitly started via a software initiated service request.
|
|
*/
|
|
#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
|
|
#define DMA_CSR_INTMAJOR_MASK (0x2U)
|
|
#define DMA_CSR_INTMAJOR_SHIFT (1U)
|
|
/*! INTMAJOR - Enable an interrupt when major iteration count completes.
|
|
* 0b0..The end-of-major loop interrupt is disabled.
|
|
* 0b1..The end-of-major loop interrupt is enabled.
|
|
*/
|
|
#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
|
|
#define DMA_CSR_INTHALF_MASK (0x4U)
|
|
#define DMA_CSR_INTHALF_SHIFT (2U)
|
|
/*! INTHALF - Enable an interrupt when major counter is half complete.
|
|
* 0b0..The half-point interrupt is disabled.
|
|
* 0b1..The half-point interrupt is enabled.
|
|
*/
|
|
#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
|
|
#define DMA_CSR_DREQ_MASK (0x8U)
|
|
#define DMA_CSR_DREQ_SHIFT (3U)
|
|
/*! DREQ - Disable Request
|
|
* 0b0..The channel's ERQ bit is not affected.
|
|
* 0b1..The channel's ERQ bit is cleared when the major loop is complete.
|
|
*/
|
|
#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
|
|
#define DMA_CSR_ESG_MASK (0x10U)
|
|
#define DMA_CSR_ESG_SHIFT (4U)
|
|
/*! ESG - Enable Scatter/Gather Processing
|
|
* 0b0..The current channel's TCD is normal format.
|
|
* 0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
|
|
*/
|
|
#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
|
|
#define DMA_CSR_MAJORELINK_MASK (0x20U)
|
|
#define DMA_CSR_MAJORELINK_SHIFT (5U)
|
|
/*! MAJORELINK - Enable channel-to-channel linking on major loop complete
|
|
* 0b0..The channel-to-channel linking is disabled.
|
|
* 0b1..The channel-to-channel linking is enabled.
|
|
*/
|
|
#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
|
|
#define DMA_CSR_ACTIVE_MASK (0x40U)
|
|
#define DMA_CSR_ACTIVE_SHIFT (6U)
|
|
#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
|
|
#define DMA_CSR_DONE_MASK (0x80U)
|
|
#define DMA_CSR_DONE_SHIFT (7U)
|
|
#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
|
|
#define DMA_CSR_MAJORLINKCH_MASK (0x1F00U)
|
|
#define DMA_CSR_MAJORLINKCH_SHIFT (8U)
|
|
#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
|
|
#define DMA_CSR_BWC_MASK (0xC000U)
|
|
#define DMA_CSR_BWC_SHIFT (14U)
|
|
/*! BWC - Bandwidth Control
|
|
* 0b00..No eDMA engine stalls.
|
|
* 0b01..Reserved
|
|
* 0b10..eDMA engine stalls for 4 cycles after each R/W.
|
|
* 0b11..eDMA engine stalls for 8 cycles after each R/W.
|
|
*/
|
|
#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of DMA_CSR */
|
|
#define DMA_CSR_COUNT (32U)
|
|
|
|
/*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
|
|
/*! @{ */
|
|
#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
|
|
#define DMA_BITER_ELINKNO_BITER_SHIFT (0U)
|
|
#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
|
|
#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
|
|
#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
|
|
/*! ELINK - Enables channel-to-channel linking on minor loop complete
|
|
* 0b0..The channel-to-channel linking is disabled
|
|
* 0b1..The channel-to-channel linking is enabled
|
|
*/
|
|
#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of DMA_BITER_ELINKNO */
|
|
#define DMA_BITER_ELINKNO_COUNT (32U)
|
|
|
|
/*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
|
|
/*! @{ */
|
|
#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
|
|
#define DMA_BITER_ELINKYES_BITER_SHIFT (0U)
|
|
#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
|
|
#define DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U)
|
|
#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
|
|
#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
|
|
#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
|
|
#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
|
|
/*! ELINK - Enables channel-to-channel linking on minor loop complete
|
|
* 0b0..The channel-to-channel linking is disabled
|
|
* 0b1..The channel-to-channel linking is enabled
|
|
*/
|
|
#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of DMA_BITER_ELINKYES */
|
|
#define DMA_BITER_ELINKYES_COUNT (32U)
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group DMA_Register_Masks */
|
|
|
|
|
|
/* DMA - Peripheral instance base addresses */
|
|
/** Peripheral DMA0 base address */
|
|
#define DMA0_BASE (0x400E8000u)
|
|
/** Peripheral DMA0 base pointer */
|
|
#define DMA0 ((DMA_Type *)DMA0_BASE)
|
|
/** Array initializer of DMA peripheral base addresses */
|
|
#define DMA_BASE_ADDRS { DMA0_BASE }
|
|
/** Array initializer of DMA peripheral base pointers */
|
|
#define DMA_BASE_PTRS { DMA0 }
|
|
/** Interrupt vectors for the DMA peripheral type */
|
|
#define DMA_CHN_IRQS { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } }
|
|
#define DMA_ERROR_IRQS { DMA_ERROR_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group DMA_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- DMAMUX Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** DMAMUX - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t CHCFG[32]; /**< Channel 0 Configuration Register..Channel 31 Configuration Register, array offset: 0x0, array step: 0x4 */
|
|
} DMAMUX_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- DMAMUX Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name CHCFG - Channel 0 Configuration Register..Channel 31 Configuration Register */
|
|
/*! @{ */
|
|
#define DMAMUX_CHCFG_SOURCE_MASK (0x7FU)
|
|
#define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
|
|
#define DMAMUX_CHCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
|
|
#define DMAMUX_CHCFG_A_ON_MASK (0x20000000U)
|
|
#define DMAMUX_CHCFG_A_ON_SHIFT (29U)
|
|
/*! A_ON - DMA Channel Always Enable
|
|
* 0b0..DMA Channel Always ON function is disabled
|
|
* 0b1..DMA Channel Always ON function is enabled
|
|
*/
|
|
#define DMAMUX_CHCFG_A_ON(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_A_ON_SHIFT)) & DMAMUX_CHCFG_A_ON_MASK)
|
|
#define DMAMUX_CHCFG_TRIG_MASK (0x40000000U)
|
|
#define DMAMUX_CHCFG_TRIG_SHIFT (30U)
|
|
/*! TRIG - DMA Channel Trigger Enable
|
|
* 0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
|
|
* 0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
|
|
*/
|
|
#define DMAMUX_CHCFG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
|
|
#define DMAMUX_CHCFG_ENBL_MASK (0x80000000U)
|
|
#define DMAMUX_CHCFG_ENBL_SHIFT (31U)
|
|
/*! ENBL - DMA Mux Channel Enable
|
|
* 0b0..DMA Mux channel is disabled
|
|
* 0b1..DMA Mux channel is enabled
|
|
*/
|
|
#define DMAMUX_CHCFG_ENBL(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of DMAMUX_CHCFG */
|
|
#define DMAMUX_CHCFG_COUNT (32U)
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group DMAMUX_Register_Masks */
|
|
|
|
|
|
/* DMAMUX - Peripheral instance base addresses */
|
|
/** Peripheral DMAMUX base address */
|
|
#define DMAMUX_BASE (0x400EC000u)
|
|
/** Peripheral DMAMUX base pointer */
|
|
#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
|
|
/** Array initializer of DMAMUX peripheral base addresses */
|
|
#define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
|
|
/** Array initializer of DMAMUX peripheral base pointers */
|
|
#define DMAMUX_BASE_PTRS { DMAMUX }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group DMAMUX_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- ENC Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup ENC_Peripheral_Access_Layer ENC Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** ENC - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint16_t CTRL; /**< Control Register, offset: 0x0 */
|
|
__IO uint16_t FILT; /**< Input Filter Register, offset: 0x2 */
|
|
__IO uint16_t WTR; /**< Watchdog Timeout Register, offset: 0x4 */
|
|
__IO uint16_t POSD; /**< Position Difference Counter Register, offset: 0x6 */
|
|
__I uint16_t POSDH; /**< Position Difference Hold Register, offset: 0x8 */
|
|
__IO uint16_t REV; /**< Revolution Counter Register, offset: 0xA */
|
|
__I uint16_t REVH; /**< Revolution Hold Register, offset: 0xC */
|
|
__IO uint16_t UPOS; /**< Upper Position Counter Register, offset: 0xE */
|
|
__IO uint16_t LPOS; /**< Lower Position Counter Register, offset: 0x10 */
|
|
__I uint16_t UPOSH; /**< Upper Position Hold Register, offset: 0x12 */
|
|
__I uint16_t LPOSH; /**< Lower Position Hold Register, offset: 0x14 */
|
|
__IO uint16_t UINIT; /**< Upper Initialization Register, offset: 0x16 */
|
|
__IO uint16_t LINIT; /**< Lower Initialization Register, offset: 0x18 */
|
|
__I uint16_t IMR; /**< Input Monitor Register, offset: 0x1A */
|
|
__IO uint16_t TST; /**< Test Register, offset: 0x1C */
|
|
__IO uint16_t CTRL2; /**< Control 2 Register, offset: 0x1E */
|
|
__IO uint16_t UMOD; /**< Upper Modulus Register, offset: 0x20 */
|
|
__IO uint16_t LMOD; /**< Lower Modulus Register, offset: 0x22 */
|
|
__IO uint16_t UCOMP; /**< Upper Position Compare Register, offset: 0x24 */
|
|
__IO uint16_t LCOMP; /**< Lower Position Compare Register, offset: 0x26 */
|
|
} ENC_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- ENC Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup ENC_Register_Masks ENC Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name CTRL - Control Register */
|
|
/*! @{ */
|
|
#define ENC_CTRL_CMPIE_MASK (0x1U)
|
|
#define ENC_CTRL_CMPIE_SHIFT (0U)
|
|
/*! CMPIE - Compare Interrupt Enable
|
|
* 0b0..Compare interrupt is disabled
|
|
* 0b1..Compare interrupt is enabled
|
|
*/
|
|
#define ENC_CTRL_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK)
|
|
#define ENC_CTRL_CMPIRQ_MASK (0x2U)
|
|
#define ENC_CTRL_CMPIRQ_SHIFT (1U)
|
|
/*! CMPIRQ - Compare Interrupt Request
|
|
* 0b0..No match has occurred
|
|
* 0b1..COMP match has occurred
|
|
*/
|
|
#define ENC_CTRL_CMPIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK)
|
|
#define ENC_CTRL_WDE_MASK (0x4U)
|
|
#define ENC_CTRL_WDE_SHIFT (2U)
|
|
/*! WDE - Watchdog Enable
|
|
* 0b0..Watchdog timer is disabled
|
|
* 0b1..Watchdog timer is enabled
|
|
*/
|
|
#define ENC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK)
|
|
#define ENC_CTRL_DIE_MASK (0x8U)
|
|
#define ENC_CTRL_DIE_SHIFT (3U)
|
|
/*! DIE - Watchdog Timeout Interrupt Enable
|
|
* 0b0..Watchdog timer interrupt is disabled
|
|
* 0b1..Watchdog timer interrupt is enabled
|
|
*/
|
|
#define ENC_CTRL_DIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK)
|
|
#define ENC_CTRL_DIRQ_MASK (0x10U)
|
|
#define ENC_CTRL_DIRQ_SHIFT (4U)
|
|
/*! DIRQ - Watchdog Timeout Interrupt Request
|
|
* 0b0..No interrupt has occurred
|
|
* 0b1..Watchdog timeout interrupt has occurred
|
|
*/
|
|
#define ENC_CTRL_DIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK)
|
|
#define ENC_CTRL_XNE_MASK (0x20U)
|
|
#define ENC_CTRL_XNE_SHIFT (5U)
|
|
/*! XNE - Use Negative Edge of INDEX Pulse
|
|
* 0b0..Use positive transition edge of INDEX pulse
|
|
* 0b1..Use negative transition edge of INDEX pulse
|
|
*/
|
|
#define ENC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK)
|
|
#define ENC_CTRL_XIP_MASK (0x40U)
|
|
#define ENC_CTRL_XIP_SHIFT (6U)
|
|
/*! XIP - INDEX Triggered Initialization of Position Counters UPOS and LPOS
|
|
* 0b0..No action
|
|
* 0b1..INDEX pulse initializes the position counter
|
|
*/
|
|
#define ENC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK)
|
|
#define ENC_CTRL_XIE_MASK (0x80U)
|
|
#define ENC_CTRL_XIE_SHIFT (7U)
|
|
/*! XIE - INDEX Pulse Interrupt Enable
|
|
* 0b0..INDEX pulse interrupt is disabled
|
|
* 0b1..INDEX pulse interrupt is enabled
|
|
*/
|
|
#define ENC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK)
|
|
#define ENC_CTRL_XIRQ_MASK (0x100U)
|
|
#define ENC_CTRL_XIRQ_SHIFT (8U)
|
|
/*! XIRQ - INDEX Pulse Interrupt Request
|
|
* 0b0..No interrupt has occurred
|
|
* 0b1..INDEX pulse interrupt has occurred
|
|
*/
|
|
#define ENC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK)
|
|
#define ENC_CTRL_PH1_MASK (0x200U)
|
|
#define ENC_CTRL_PH1_SHIFT (9U)
|
|
/*! PH1 - Enable Signal Phase Count Mode
|
|
* 0b0..Use standard quadrature decoder where PHASEA and PHASEB represent a two phase quadrature signal.
|
|
* 0b1..Bypass the quadrature decoder. A positive transition of the PHASEA input generates a count signal. The PHASEB input and the REV bit control the counter direction. If CTRL[REV] = 0, PHASEB = 0, then count up If CTRL[REV] = 0, PHASEB = 1, then count down If CTRL[REV] = 1, PHASEB = 0, then count down If CTRL[REV] = 1, PHASEB = 1, then count up
|
|
*/
|
|
#define ENC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK)
|
|
#define ENC_CTRL_REV_MASK (0x400U)
|
|
#define ENC_CTRL_REV_SHIFT (10U)
|
|
/*! REV - Enable Reverse Direction Counting
|
|
* 0b0..Count normally
|
|
* 0b1..Count in the reverse direction
|
|
*/
|
|
#define ENC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK)
|
|
#define ENC_CTRL_SWIP_MASK (0x800U)
|
|
#define ENC_CTRL_SWIP_SHIFT (11U)
|
|
/*! SWIP - Software Triggered Initialization of Position Counters UPOS and LPOS
|
|
* 0b0..No action
|
|
* 0b1..Initialize position counter
|
|
*/
|
|
#define ENC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK)
|
|
#define ENC_CTRL_HNE_MASK (0x1000U)
|
|
#define ENC_CTRL_HNE_SHIFT (12U)
|
|
/*! HNE - Use Negative Edge of HOME Input
|
|
* 0b0..Use positive going edge-to-trigger initialization of position counters UPOS and LPOS
|
|
* 0b1..Use negative going edge-to-trigger initialization of position counters UPOS and LPOS
|
|
*/
|
|
#define ENC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK)
|
|
#define ENC_CTRL_HIP_MASK (0x2000U)
|
|
#define ENC_CTRL_HIP_SHIFT (13U)
|
|
/*! HIP - Enable HOME to Initialize Position Counters UPOS and LPOS
|
|
* 0b0..No action
|
|
* 0b1..HOME signal initializes the position counter
|
|
*/
|
|
#define ENC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK)
|
|
#define ENC_CTRL_HIE_MASK (0x4000U)
|
|
#define ENC_CTRL_HIE_SHIFT (14U)
|
|
/*! HIE - HOME Interrupt Enable
|
|
* 0b0..Disable HOME interrupts
|
|
* 0b1..Enable HOME interrupts
|
|
*/
|
|
#define ENC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK)
|
|
#define ENC_CTRL_HIRQ_MASK (0x8000U)
|
|
#define ENC_CTRL_HIRQ_SHIFT (15U)
|
|
/*! HIRQ - HOME Signal Transition Interrupt Request
|
|
* 0b0..No interrupt
|
|
* 0b1..HOME signal transition interrupt request
|
|
*/
|
|
#define ENC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FILT - Input Filter Register */
|
|
/*! @{ */
|
|
#define ENC_FILT_FILT_PER_MASK (0xFFU)
|
|
#define ENC_FILT_FILT_PER_SHIFT (0U)
|
|
#define ENC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PER_SHIFT)) & ENC_FILT_FILT_PER_MASK)
|
|
#define ENC_FILT_FILT_CNT_MASK (0x700U)
|
|
#define ENC_FILT_FILT_CNT_SHIFT (8U)
|
|
#define ENC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_CNT_SHIFT)) & ENC_FILT_FILT_CNT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name WTR - Watchdog Timeout Register */
|
|
/*! @{ */
|
|
#define ENC_WTR_WDOG_MASK (0xFFFFU)
|
|
#define ENC_WTR_WDOG_SHIFT (0U)
|
|
#define ENC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << ENC_WTR_WDOG_SHIFT)) & ENC_WTR_WDOG_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name POSD - Position Difference Counter Register */
|
|
/*! @{ */
|
|
#define ENC_POSD_POSD_MASK (0xFFFFU)
|
|
#define ENC_POSD_POSD_SHIFT (0U)
|
|
#define ENC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSD_POSD_SHIFT)) & ENC_POSD_POSD_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name POSDH - Position Difference Hold Register */
|
|
/*! @{ */
|
|
#define ENC_POSDH_POSDH_MASK (0xFFFFU)
|
|
#define ENC_POSDH_POSDH_SHIFT (0U)
|
|
#define ENC_POSDH_POSDH(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDH_POSDH_SHIFT)) & ENC_POSDH_POSDH_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name REV - Revolution Counter Register */
|
|
/*! @{ */
|
|
#define ENC_REV_REV_MASK (0xFFFFU)
|
|
#define ENC_REV_REV_SHIFT (0U)
|
|
#define ENC_REV_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_REV_REV_SHIFT)) & ENC_REV_REV_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name REVH - Revolution Hold Register */
|
|
/*! @{ */
|
|
#define ENC_REVH_REVH_MASK (0xFFFFU)
|
|
#define ENC_REVH_REVH_SHIFT (0U)
|
|
#define ENC_REVH_REVH(x) (((uint16_t)(((uint16_t)(x)) << ENC_REVH_REVH_SHIFT)) & ENC_REVH_REVH_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name UPOS - Upper Position Counter Register */
|
|
/*! @{ */
|
|
#define ENC_UPOS_POS_MASK (0xFFFFU)
|
|
#define ENC_UPOS_POS_SHIFT (0U)
|
|
#define ENC_UPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOS_POS_SHIFT)) & ENC_UPOS_POS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name LPOS - Lower Position Counter Register */
|
|
/*! @{ */
|
|
#define ENC_LPOS_POS_MASK (0xFFFFU)
|
|
#define ENC_LPOS_POS_SHIFT (0U)
|
|
#define ENC_LPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOS_POS_SHIFT)) & ENC_LPOS_POS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name UPOSH - Upper Position Hold Register */
|
|
/*! @{ */
|
|
#define ENC_UPOSH_POSH_MASK (0xFFFFU)
|
|
#define ENC_UPOSH_POSH_SHIFT (0U)
|
|
#define ENC_UPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOSH_POSH_SHIFT)) & ENC_UPOSH_POSH_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name LPOSH - Lower Position Hold Register */
|
|
/*! @{ */
|
|
#define ENC_LPOSH_POSH_MASK (0xFFFFU)
|
|
#define ENC_LPOSH_POSH_SHIFT (0U)
|
|
#define ENC_LPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOSH_POSH_SHIFT)) & ENC_LPOSH_POSH_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name UINIT - Upper Initialization Register */
|
|
/*! @{ */
|
|
#define ENC_UINIT_INIT_MASK (0xFFFFU)
|
|
#define ENC_UINIT_INIT_SHIFT (0U)
|
|
#define ENC_UINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_UINIT_INIT_SHIFT)) & ENC_UINIT_INIT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name LINIT - Lower Initialization Register */
|
|
/*! @{ */
|
|
#define ENC_LINIT_INIT_MASK (0xFFFFU)
|
|
#define ENC_LINIT_INIT_SHIFT (0U)
|
|
#define ENC_LINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_LINIT_INIT_SHIFT)) & ENC_LINIT_INIT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name IMR - Input Monitor Register */
|
|
/*! @{ */
|
|
#define ENC_IMR_HOME_MASK (0x1U)
|
|
#define ENC_IMR_HOME_SHIFT (0U)
|
|
#define ENC_IMR_HOME(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_HOME_SHIFT)) & ENC_IMR_HOME_MASK)
|
|
#define ENC_IMR_INDEX_MASK (0x2U)
|
|
#define ENC_IMR_INDEX_SHIFT (1U)
|
|
#define ENC_IMR_INDEX(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_INDEX_SHIFT)) & ENC_IMR_INDEX_MASK)
|
|
#define ENC_IMR_PHB_MASK (0x4U)
|
|
#define ENC_IMR_PHB_SHIFT (2U)
|
|
#define ENC_IMR_PHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHB_SHIFT)) & ENC_IMR_PHB_MASK)
|
|
#define ENC_IMR_PHA_MASK (0x8U)
|
|
#define ENC_IMR_PHA_SHIFT (3U)
|
|
#define ENC_IMR_PHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHA_SHIFT)) & ENC_IMR_PHA_MASK)
|
|
#define ENC_IMR_FHOM_MASK (0x10U)
|
|
#define ENC_IMR_FHOM_SHIFT (4U)
|
|
#define ENC_IMR_FHOM(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FHOM_SHIFT)) & ENC_IMR_FHOM_MASK)
|
|
#define ENC_IMR_FIND_MASK (0x20U)
|
|
#define ENC_IMR_FIND_SHIFT (5U)
|
|
#define ENC_IMR_FIND(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FIND_SHIFT)) & ENC_IMR_FIND_MASK)
|
|
#define ENC_IMR_FPHB_MASK (0x40U)
|
|
#define ENC_IMR_FPHB_SHIFT (6U)
|
|
#define ENC_IMR_FPHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHB_SHIFT)) & ENC_IMR_FPHB_MASK)
|
|
#define ENC_IMR_FPHA_MASK (0x80U)
|
|
#define ENC_IMR_FPHA_SHIFT (7U)
|
|
#define ENC_IMR_FPHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHA_SHIFT)) & ENC_IMR_FPHA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TST - Test Register */
|
|
/*! @{ */
|
|
#define ENC_TST_TEST_COUNT_MASK (0xFFU)
|
|
#define ENC_TST_TEST_COUNT_SHIFT (0U)
|
|
#define ENC_TST_TEST_COUNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_COUNT_SHIFT)) & ENC_TST_TEST_COUNT_MASK)
|
|
#define ENC_TST_TEST_PERIOD_MASK (0x1F00U)
|
|
#define ENC_TST_TEST_PERIOD_SHIFT (8U)
|
|
#define ENC_TST_TEST_PERIOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_PERIOD_SHIFT)) & ENC_TST_TEST_PERIOD_MASK)
|
|
#define ENC_TST_QDN_MASK (0x2000U)
|
|
#define ENC_TST_QDN_SHIFT (13U)
|
|
/*! QDN - Quadrature Decoder Negative Signal
|
|
* 0b0..Leaves quadrature decoder signal in a positive direction
|
|
* 0b1..Generates a negative quadrature decoder signal
|
|
*/
|
|
#define ENC_TST_QDN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_QDN_SHIFT)) & ENC_TST_QDN_MASK)
|
|
#define ENC_TST_TCE_MASK (0x4000U)
|
|
#define ENC_TST_TCE_SHIFT (14U)
|
|
/*! TCE - Test Counter Enable
|
|
* 0b0..Test count is not enabled
|
|
* 0b1..Test count is enabled
|
|
*/
|
|
#define ENC_TST_TCE(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TCE_SHIFT)) & ENC_TST_TCE_MASK)
|
|
#define ENC_TST_TEN_MASK (0x8000U)
|
|
#define ENC_TST_TEN_SHIFT (15U)
|
|
/*! TEN - Test Mode Enable
|
|
* 0b0..Test module is not enabled
|
|
* 0b1..Test module is enabled
|
|
*/
|
|
#define ENC_TST_TEN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEN_SHIFT)) & ENC_TST_TEN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CTRL2 - Control 2 Register */
|
|
/*! @{ */
|
|
#define ENC_CTRL2_UPDHLD_MASK (0x1U)
|
|
#define ENC_CTRL2_UPDHLD_SHIFT (0U)
|
|
/*! UPDHLD - Update Hold Registers
|
|
* 0b0..Disable updates of hold registers on rising edge of TRIGGER
|
|
* 0b1..Enable updates of hold registers on rising edge of TRIGGER
|
|
*/
|
|
#define ENC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK)
|
|
#define ENC_CTRL2_UPDPOS_MASK (0x2U)
|
|
#define ENC_CTRL2_UPDPOS_SHIFT (1U)
|
|
/*! UPDPOS - Update Position Registers
|
|
* 0b0..No action for POSD, REV, UPOS and LPOS on rising edge of TRIGGER
|
|
* 0b1..Clear POSD, REV, UPOS and LPOS on rising edge of TRIGGER
|
|
*/
|
|
#define ENC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK)
|
|
#define ENC_CTRL2_MOD_MASK (0x4U)
|
|
#define ENC_CTRL2_MOD_SHIFT (2U)
|
|
/*! MOD - Enable Modulo Counting
|
|
* 0b0..Disable modulo counting
|
|
* 0b1..Enable modulo counting
|
|
*/
|
|
#define ENC_CTRL2_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK)
|
|
#define ENC_CTRL2_DIR_MASK (0x8U)
|
|
#define ENC_CTRL2_DIR_SHIFT (3U)
|
|
/*! DIR - Count Direction Flag
|
|
* 0b0..Last count was in the down direction
|
|
* 0b1..Last count was in the up direction
|
|
*/
|
|
#define ENC_CTRL2_DIR(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK)
|
|
#define ENC_CTRL2_RUIE_MASK (0x10U)
|
|
#define ENC_CTRL2_RUIE_SHIFT (4U)
|
|
/*! RUIE - Roll-under Interrupt Enable
|
|
* 0b0..Roll-under interrupt is disabled
|
|
* 0b1..Roll-under interrupt is enabled
|
|
*/
|
|
#define ENC_CTRL2_RUIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK)
|
|
#define ENC_CTRL2_RUIRQ_MASK (0x20U)
|
|
#define ENC_CTRL2_RUIRQ_SHIFT (5U)
|
|
/*! RUIRQ - Roll-under Interrupt Request
|
|
* 0b0..No roll-under has occurred
|
|
* 0b1..Roll-under has occurred
|
|
*/
|
|
#define ENC_CTRL2_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK)
|
|
#define ENC_CTRL2_ROIE_MASK (0x40U)
|
|
#define ENC_CTRL2_ROIE_SHIFT (6U)
|
|
/*! ROIE - Roll-over Interrupt Enable
|
|
* 0b0..Roll-over interrupt is disabled
|
|
* 0b1..Roll-over interrupt is enabled
|
|
*/
|
|
#define ENC_CTRL2_ROIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK)
|
|
#define ENC_CTRL2_ROIRQ_MASK (0x80U)
|
|
#define ENC_CTRL2_ROIRQ_SHIFT (7U)
|
|
/*! ROIRQ - Roll-over Interrupt Request
|
|
* 0b0..No roll-over has occurred
|
|
* 0b1..Roll-over has occurred
|
|
*/
|
|
#define ENC_CTRL2_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK)
|
|
#define ENC_CTRL2_REVMOD_MASK (0x100U)
|
|
#define ENC_CTRL2_REVMOD_SHIFT (8U)
|
|
/*! REVMOD - Revolution Counter Modulus Enable
|
|
* 0b0..Use INDEX pulse to increment/decrement revolution counter (REV).
|
|
* 0b1..Use modulus counting roll-over/under to increment/decrement revolution counter (REV).
|
|
*/
|
|
#define ENC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK)
|
|
#define ENC_CTRL2_OUTCTL_MASK (0x200U)
|
|
#define ENC_CTRL2_OUTCTL_SHIFT (9U)
|
|
/*! OUTCTL - Output Control
|
|
* 0b0..POSMATCH pulses when a match occurs between the position counters (POS) and the compare value (COMP).
|
|
* 0b1..POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read.
|
|
*/
|
|
#define ENC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK)
|
|
#define ENC_CTRL2_SABIE_MASK (0x400U)
|
|
#define ENC_CTRL2_SABIE_SHIFT (10U)
|
|
/*! SABIE - Simultaneous PHASEA and PHASEB Change Interrupt Enable
|
|
* 0b0..Simultaneous PHASEA and PHASEB change interrupt disabled.
|
|
* 0b1..Simultaneous PHASEA and PHASEB change interrupt enabled.
|
|
*/
|
|
#define ENC_CTRL2_SABIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK)
|
|
#define ENC_CTRL2_SABIRQ_MASK (0x800U)
|
|
#define ENC_CTRL2_SABIRQ_SHIFT (11U)
|
|
/*! SABIRQ - Simultaneous PHASEA and PHASEB Change Interrupt Request
|
|
* 0b0..No simultaneous change of PHASEA and PHASEB has occurred.
|
|
* 0b1..A simultaneous change of PHASEA and PHASEB has occurred.
|
|
*/
|
|
#define ENC_CTRL2_SABIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name UMOD - Upper Modulus Register */
|
|
/*! @{ */
|
|
#define ENC_UMOD_MOD_MASK (0xFFFFU)
|
|
#define ENC_UMOD_MOD_SHIFT (0U)
|
|
#define ENC_UMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_UMOD_MOD_SHIFT)) & ENC_UMOD_MOD_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name LMOD - Lower Modulus Register */
|
|
/*! @{ */
|
|
#define ENC_LMOD_MOD_MASK (0xFFFFU)
|
|
#define ENC_LMOD_MOD_SHIFT (0U)
|
|
#define ENC_LMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_LMOD_MOD_SHIFT)) & ENC_LMOD_MOD_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name UCOMP - Upper Position Compare Register */
|
|
/*! @{ */
|
|
#define ENC_UCOMP_COMP_MASK (0xFFFFU)
|
|
#define ENC_UCOMP_COMP_SHIFT (0U)
|
|
#define ENC_UCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_UCOMP_COMP_SHIFT)) & ENC_UCOMP_COMP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name LCOMP - Lower Position Compare Register */
|
|
/*! @{ */
|
|
#define ENC_LCOMP_COMP_MASK (0xFFFFU)
|
|
#define ENC_LCOMP_COMP_SHIFT (0U)
|
|
#define ENC_LCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_LCOMP_COMP_SHIFT)) & ENC_LCOMP_COMP_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group ENC_Register_Masks */
|
|
|
|
|
|
/* ENC - Peripheral instance base addresses */
|
|
/** Peripheral ENC1 base address */
|
|
#define ENC1_BASE (0x403C8000u)
|
|
/** Peripheral ENC1 base pointer */
|
|
#define ENC1 ((ENC_Type *)ENC1_BASE)
|
|
/** Peripheral ENC2 base address */
|
|
#define ENC2_BASE (0x403CC000u)
|
|
/** Peripheral ENC2 base pointer */
|
|
#define ENC2 ((ENC_Type *)ENC2_BASE)
|
|
/** Peripheral ENC3 base address */
|
|
#define ENC3_BASE (0x403D0000u)
|
|
/** Peripheral ENC3 base pointer */
|
|
#define ENC3 ((ENC_Type *)ENC3_BASE)
|
|
/** Peripheral ENC4 base address */
|
|
#define ENC4_BASE (0x403D4000u)
|
|
/** Peripheral ENC4 base pointer */
|
|
#define ENC4 ((ENC_Type *)ENC4_BASE)
|
|
/** Array initializer of ENC peripheral base addresses */
|
|
#define ENC_BASE_ADDRS { 0u, ENC1_BASE, ENC2_BASE, ENC3_BASE, ENC4_BASE }
|
|
/** Array initializer of ENC peripheral base pointers */
|
|
#define ENC_BASE_PTRS { (ENC_Type *)0u, ENC1, ENC2, ENC3, ENC4 }
|
|
/** Interrupt vectors for the ENC peripheral type */
|
|
#define ENC_COMPARE_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
|
|
#define ENC_HOME_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
|
|
#define ENC_WDOG_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
|
|
#define ENC_INDEX_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
|
|
#define ENC_INPUT_SWITCH_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group ENC_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- ENET Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** ENET - Register Layout Typedef */
|
|
typedef struct {
|
|
uint8_t RESERVED_0[4];
|
|
__IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */
|
|
__IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */
|
|
uint8_t RESERVED_1[4];
|
|
__IO uint32_t RDAR; /**< Receive Descriptor Active Register, offset: 0x10 */
|
|
__IO uint32_t TDAR; /**< Transmit Descriptor Active Register, offset: 0x14 */
|
|
uint8_t RESERVED_2[12];
|
|
__IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */
|
|
uint8_t RESERVED_3[24];
|
|
__IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */
|
|
__IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */
|
|
uint8_t RESERVED_4[28];
|
|
__IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */
|
|
uint8_t RESERVED_5[28];
|
|
__IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */
|
|
uint8_t RESERVED_6[60];
|
|
__IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */
|
|
uint8_t RESERVED_7[28];
|
|
__IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */
|
|
__IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */
|
|
__IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */
|
|
__IO uint32_t TXIC; /**< Transmit Interrupt Coalescing Register, offset: 0xF0 */
|
|
uint8_t RESERVED_8[12];
|
|
__IO uint32_t RXIC; /**< Receive Interrupt Coalescing Register, offset: 0x100 */
|
|
uint8_t RESERVED_9[20];
|
|
__IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */
|
|
__IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */
|
|
__IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */
|
|
__IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */
|
|
uint8_t RESERVED_10[28];
|
|
__IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */
|
|
uint8_t RESERVED_11[56];
|
|
__IO uint32_t RDSR; /**< Receive Descriptor Ring Start Register, offset: 0x180 */
|
|
__IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */
|
|
__IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register, offset: 0x188 */
|
|
uint8_t RESERVED_12[4];
|
|
__IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */
|
|
__IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
|
|
__IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
|
|
__IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
|
|
__IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
|
|
__IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
|
|
__IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
|
|
__IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */
|
|
__IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */
|
|
uint8_t RESERVED_13[12];
|
|
__IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
|
|
__IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
|
|
uint8_t RESERVED_14[56];
|
|
uint32_t RMON_T_DROP; /**< Reserved Statistic Register, offset: 0x200 */
|
|
__I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */
|
|
__I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
|
|
__I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
|
|
__I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
|
|
__I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
|
|
__I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
|
|
__I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
|
|
__I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
|
|
__I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */
|
|
__I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
|
|
__I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
|
|
__I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
|
|
__I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
|
|
__I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
|
|
__I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
|
|
__I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
|
|
__I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */
|
|
uint32_t IEEE_T_DROP; /**< Reserved Statistic Register, offset: 0x248 */
|
|
__I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
|
|
__I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
|
|
__I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
|
|
__I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
|
|
__I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
|
|
__I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
|
|
__I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
|
|
__I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
|
|
__I uint32_t IEEE_T_SQE; /**< Reserved Statistic Register, offset: 0x26C */
|
|
__I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
|
|
__I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
|
|
uint8_t RESERVED_15[12];
|
|
__I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */
|
|
__I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
|
|
__I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
|
|
__I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
|
|
__I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
|
|
__I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
|
|
__I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
|
|
__I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
|
|
uint32_t RMON_R_RESVD_0; /**< Reserved Statistic Register, offset: 0x2A4 */
|
|
__I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
|
|
__I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
|
|
__I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
|
|
__I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
|
|
__I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
|
|
__I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
|
|
__I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
|
|
__I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */
|
|
__I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
|
|
__I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */
|
|
__I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
|
|
__I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
|
|
__I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
|
|
__I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
|
|
__I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
|
|
uint8_t RESERVED_16[284];
|
|
__IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */
|
|
__IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */
|
|
__IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */
|
|
__IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */
|
|
__IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */
|
|
__IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */
|
|
__I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
|
|
uint8_t RESERVED_17[488];
|
|
__IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */
|
|
struct { /* offset: 0x608, array step: 0x8 */
|
|
__IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
|
|
__IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
|
|
} CHANNEL[4];
|
|
} ENET_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- ENET Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup ENET_Register_Masks ENET Register Masks
|
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* @{
|
|
*/
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|
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/*! @name EIR - Interrupt Event Register */
|
|
/*! @{ */
|
|
#define ENET_EIR_TS_TIMER_MASK (0x8000U)
|
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#define ENET_EIR_TS_TIMER_SHIFT (15U)
|
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#define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)
|
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#define ENET_EIR_TS_AVAIL_MASK (0x10000U)
|
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#define ENET_EIR_TS_AVAIL_SHIFT (16U)
|
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#define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)
|
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#define ENET_EIR_WAKEUP_MASK (0x20000U)
|
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#define ENET_EIR_WAKEUP_SHIFT (17U)
|
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#define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)
|
|
#define ENET_EIR_PLR_MASK (0x40000U)
|
|
#define ENET_EIR_PLR_SHIFT (18U)
|
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#define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)
|
|
#define ENET_EIR_UN_MASK (0x80000U)
|
|
#define ENET_EIR_UN_SHIFT (19U)
|
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#define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)
|
|
#define ENET_EIR_RL_MASK (0x100000U)
|
|
#define ENET_EIR_RL_SHIFT (20U)
|
|
#define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)
|
|
#define ENET_EIR_LC_MASK (0x200000U)
|
|
#define ENET_EIR_LC_SHIFT (21U)
|
|
#define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)
|
|
#define ENET_EIR_EBERR_MASK (0x400000U)
|
|
#define ENET_EIR_EBERR_SHIFT (22U)
|
|
#define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)
|
|
#define ENET_EIR_MII_MASK (0x800000U)
|
|
#define ENET_EIR_MII_SHIFT (23U)
|
|
#define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)
|
|
#define ENET_EIR_RXB_MASK (0x1000000U)
|
|
#define ENET_EIR_RXB_SHIFT (24U)
|
|
#define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)
|
|
#define ENET_EIR_RXF_MASK (0x2000000U)
|
|
#define ENET_EIR_RXF_SHIFT (25U)
|
|
#define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)
|
|
#define ENET_EIR_TXB_MASK (0x4000000U)
|
|
#define ENET_EIR_TXB_SHIFT (26U)
|
|
#define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)
|
|
#define ENET_EIR_TXF_MASK (0x8000000U)
|
|
#define ENET_EIR_TXF_SHIFT (27U)
|
|
#define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)
|
|
#define ENET_EIR_GRA_MASK (0x10000000U)
|
|
#define ENET_EIR_GRA_SHIFT (28U)
|
|
#define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)
|
|
#define ENET_EIR_BABT_MASK (0x20000000U)
|
|
#define ENET_EIR_BABT_SHIFT (29U)
|
|
#define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)
|
|
#define ENET_EIR_BABR_MASK (0x40000000U)
|
|
#define ENET_EIR_BABR_SHIFT (30U)
|
|
#define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name EIMR - Interrupt Mask Register */
|
|
/*! @{ */
|
|
#define ENET_EIMR_TS_TIMER_MASK (0x8000U)
|
|
#define ENET_EIMR_TS_TIMER_SHIFT (15U)
|
|
#define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)
|
|
#define ENET_EIMR_TS_AVAIL_MASK (0x10000U)
|
|
#define ENET_EIMR_TS_AVAIL_SHIFT (16U)
|
|
#define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)
|
|
#define ENET_EIMR_WAKEUP_MASK (0x20000U)
|
|
#define ENET_EIMR_WAKEUP_SHIFT (17U)
|
|
#define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)
|
|
#define ENET_EIMR_PLR_MASK (0x40000U)
|
|
#define ENET_EIMR_PLR_SHIFT (18U)
|
|
#define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)
|
|
#define ENET_EIMR_UN_MASK (0x80000U)
|
|
#define ENET_EIMR_UN_SHIFT (19U)
|
|
#define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)
|
|
#define ENET_EIMR_RL_MASK (0x100000U)
|
|
#define ENET_EIMR_RL_SHIFT (20U)
|
|
#define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)
|
|
#define ENET_EIMR_LC_MASK (0x200000U)
|
|
#define ENET_EIMR_LC_SHIFT (21U)
|
|
#define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)
|
|
#define ENET_EIMR_EBERR_MASK (0x400000U)
|
|
#define ENET_EIMR_EBERR_SHIFT (22U)
|
|
#define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)
|
|
#define ENET_EIMR_MII_MASK (0x800000U)
|
|
#define ENET_EIMR_MII_SHIFT (23U)
|
|
#define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)
|
|
#define ENET_EIMR_RXB_MASK (0x1000000U)
|
|
#define ENET_EIMR_RXB_SHIFT (24U)
|
|
#define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)
|
|
#define ENET_EIMR_RXF_MASK (0x2000000U)
|
|
#define ENET_EIMR_RXF_SHIFT (25U)
|
|
#define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
|
|
#define ENET_EIMR_TXB_MASK (0x4000000U)
|
|
#define ENET_EIMR_TXB_SHIFT (26U)
|
|
/*! TXB - TXB Interrupt Mask
|
|
* 0b0..The corresponding interrupt source is masked.
|
|
* 0b1..The corresponding interrupt source is not masked.
|
|
*/
|
|
#define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
|
|
#define ENET_EIMR_TXF_MASK (0x8000000U)
|
|
#define ENET_EIMR_TXF_SHIFT (27U)
|
|
/*! TXF - TXF Interrupt Mask
|
|
* 0b0..The corresponding interrupt source is masked.
|
|
* 0b1..The corresponding interrupt source is not masked.
|
|
*/
|
|
#define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
|
|
#define ENET_EIMR_GRA_MASK (0x10000000U)
|
|
#define ENET_EIMR_GRA_SHIFT (28U)
|
|
/*! GRA - GRA Interrupt Mask
|
|
* 0b0..The corresponding interrupt source is masked.
|
|
* 0b1..The corresponding interrupt source is not masked.
|
|
*/
|
|
#define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
|
|
#define ENET_EIMR_BABT_MASK (0x20000000U)
|
|
#define ENET_EIMR_BABT_SHIFT (29U)
|
|
/*! BABT - BABT Interrupt Mask
|
|
* 0b0..The corresponding interrupt source is masked.
|
|
* 0b1..The corresponding interrupt source is not masked.
|
|
*/
|
|
#define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
|
|
#define ENET_EIMR_BABR_MASK (0x40000000U)
|
|
#define ENET_EIMR_BABR_SHIFT (30U)
|
|
/*! BABR - BABR Interrupt Mask
|
|
* 0b0..The corresponding interrupt source is masked.
|
|
* 0b1..The corresponding interrupt source is not masked.
|
|
*/
|
|
#define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RDAR - Receive Descriptor Active Register */
|
|
/*! @{ */
|
|
#define ENET_RDAR_RDAR_MASK (0x1000000U)
|
|
#define ENET_RDAR_RDAR_SHIFT (24U)
|
|
#define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TDAR - Transmit Descriptor Active Register */
|
|
/*! @{ */
|
|
#define ENET_TDAR_TDAR_MASK (0x1000000U)
|
|
#define ENET_TDAR_TDAR_SHIFT (24U)
|
|
#define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ECR - Ethernet Control Register */
|
|
/*! @{ */
|
|
#define ENET_ECR_RESET_MASK (0x1U)
|
|
#define ENET_ECR_RESET_SHIFT (0U)
|
|
#define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
|
|
#define ENET_ECR_ETHEREN_MASK (0x2U)
|
|
#define ENET_ECR_ETHEREN_SHIFT (1U)
|
|
/*! ETHEREN - Ethernet Enable
|
|
* 0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame.
|
|
* 0b1..MAC is enabled, and reception and transmission are possible.
|
|
*/
|
|
#define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
|
|
#define ENET_ECR_MAGICEN_MASK (0x4U)
|
|
#define ENET_ECR_MAGICEN_SHIFT (2U)
|
|
/*! MAGICEN - Magic Packet Detection Enable
|
|
* 0b0..Magic detection logic disabled.
|
|
* 0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected.
|
|
*/
|
|
#define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
|
|
#define ENET_ECR_SLEEP_MASK (0x8U)
|
|
#define ENET_ECR_SLEEP_SHIFT (3U)
|
|
/*! SLEEP - Sleep Mode Enable
|
|
* 0b0..Normal operating mode.
|
|
* 0b1..Sleep mode.
|
|
*/
|
|
#define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
|
|
#define ENET_ECR_EN1588_MASK (0x10U)
|
|
#define ENET_ECR_EN1588_SHIFT (4U)
|
|
/*! EN1588 - EN1588 Enable
|
|
* 0b0..Legacy FEC buffer descriptors and functions enabled.
|
|
* 0b1..Enhanced frame time-stamping functions enabled.
|
|
*/
|
|
#define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
|
|
#define ENET_ECR_DBGEN_MASK (0x40U)
|
|
#define ENET_ECR_DBGEN_SHIFT (6U)
|
|
/*! DBGEN - Debug Enable
|
|
* 0b0..MAC continues operation in debug mode.
|
|
* 0b1..MAC enters hardware freeze mode when the processor is in debug mode.
|
|
*/
|
|
#define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
|
|
#define ENET_ECR_DBSWP_MASK (0x100U)
|
|
#define ENET_ECR_DBSWP_SHIFT (8U)
|
|
/*! DBSWP - Descriptor Byte Swapping Enable
|
|
* 0b0..The buffer descriptor bytes are not swapped to support big-endian devices.
|
|
* 0b1..The buffer descriptor bytes are swapped to support little-endian devices.
|
|
*/
|
|
#define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MMFR - MII Management Frame Register */
|
|
/*! @{ */
|
|
#define ENET_MMFR_DATA_MASK (0xFFFFU)
|
|
#define ENET_MMFR_DATA_SHIFT (0U)
|
|
#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
|
|
#define ENET_MMFR_TA_MASK (0x30000U)
|
|
#define ENET_MMFR_TA_SHIFT (16U)
|
|
#define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
|
|
#define ENET_MMFR_RA_MASK (0x7C0000U)
|
|
#define ENET_MMFR_RA_SHIFT (18U)
|
|
#define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
|
|
#define ENET_MMFR_PA_MASK (0xF800000U)
|
|
#define ENET_MMFR_PA_SHIFT (23U)
|
|
#define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
|
|
#define ENET_MMFR_OP_MASK (0x30000000U)
|
|
#define ENET_MMFR_OP_SHIFT (28U)
|
|
#define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
|
|
#define ENET_MMFR_ST_MASK (0xC0000000U)
|
|
#define ENET_MMFR_ST_SHIFT (30U)
|
|
#define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MSCR - MII Speed Control Register */
|
|
/*! @{ */
|
|
#define ENET_MSCR_MII_SPEED_MASK (0x7EU)
|
|
#define ENET_MSCR_MII_SPEED_SHIFT (1U)
|
|
#define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
|
|
#define ENET_MSCR_DIS_PRE_MASK (0x80U)
|
|
#define ENET_MSCR_DIS_PRE_SHIFT (7U)
|
|
/*! DIS_PRE - Disable Preamble
|
|
* 0b0..Preamble enabled.
|
|
* 0b1..Preamble (32 ones) is not prepended to the MII management frame.
|
|
*/
|
|
#define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
|
|
#define ENET_MSCR_HOLDTIME_MASK (0x700U)
|
|
#define ENET_MSCR_HOLDTIME_SHIFT (8U)
|
|
/*! HOLDTIME - Hold time On MDIO Output
|
|
* 0b000..1 internal module clock cycle
|
|
* 0b001..2 internal module clock cycles
|
|
* 0b010..3 internal module clock cycles
|
|
* 0b111..8 internal module clock cycles
|
|
*/
|
|
#define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MIBC - MIB Control Register */
|
|
/*! @{ */
|
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#define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U)
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#define ENET_MIBC_MIB_CLEAR_SHIFT (29U)
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/*! MIB_CLEAR - MIB Clear
|
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* 0b0..See note above.
|
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* 0b1..All statistics counters are reset to 0.
|
|
*/
|
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#define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
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#define ENET_MIBC_MIB_IDLE_MASK (0x40000000U)
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#define ENET_MIBC_MIB_IDLE_SHIFT (30U)
|
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/*! MIB_IDLE - MIB Idle
|
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* 0b0..The MIB block is updating MIB counters.
|
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* 0b1..The MIB block is not currently updating any MIB counters.
|
|
*/
|
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#define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
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#define ENET_MIBC_MIB_DIS_MASK (0x80000000U)
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#define ENET_MIBC_MIB_DIS_SHIFT (31U)
|
|
/*! MIB_DIS - Disable MIB Logic
|
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* 0b0..MIB logic is enabled.
|
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* 0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters.
|
|
*/
|
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#define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)
|
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/*! @} */
|
|
|
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/*! @name RCR - Receive Control Register */
|
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/*! @{ */
|
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#define ENET_RCR_LOOP_MASK (0x1U)
|
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#define ENET_RCR_LOOP_SHIFT (0U)
|
|
/*! LOOP - Internal Loopback
|
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* 0b0..Loopback disabled.
|
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* 0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared.
|
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*/
|
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#define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
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#define ENET_RCR_DRT_MASK (0x2U)
|
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#define ENET_RCR_DRT_SHIFT (1U)
|
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/*! DRT - Disable Receive On Transmit
|
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* 0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode.
|
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* 0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.)
|
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*/
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#define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
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#define ENET_RCR_MII_MODE_MASK (0x4U)
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#define ENET_RCR_MII_MODE_SHIFT (2U)
|
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/*! MII_MODE - Media Independent Interface Mode
|
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* 0b0..Reserved.
|
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* 0b1..MII or RMII mode, as indicated by the RMII_MODE field.
|
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*/
|
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#define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
|
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#define ENET_RCR_PROM_MASK (0x8U)
|
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#define ENET_RCR_PROM_SHIFT (3U)
|
|
/*! PROM - Promiscuous Mode
|
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* 0b0..Disabled.
|
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* 0b1..Enabled.
|
|
*/
|
|
#define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
|
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#define ENET_RCR_BC_REJ_MASK (0x10U)
|
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#define ENET_RCR_BC_REJ_SHIFT (4U)
|
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#define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)
|
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#define ENET_RCR_FCE_MASK (0x20U)
|
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#define ENET_RCR_FCE_SHIFT (5U)
|
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#define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
|
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#define ENET_RCR_RMII_MODE_MASK (0x100U)
|
|
#define ENET_RCR_RMII_MODE_SHIFT (8U)
|
|
/*! RMII_MODE - RMII Mode Enable
|
|
* 0b0..MAC configured for MII mode.
|
|
* 0b1..MAC configured for RMII operation.
|
|
*/
|
|
#define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
|
|
#define ENET_RCR_RMII_10T_MASK (0x200U)
|
|
#define ENET_RCR_RMII_10T_SHIFT (9U)
|
|
/*! RMII_10T
|
|
* 0b0..100-Mbit/s operation.
|
|
* 0b1..10-Mbit/s operation.
|
|
*/
|
|
#define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
|
|
#define ENET_RCR_PADEN_MASK (0x1000U)
|
|
#define ENET_RCR_PADEN_SHIFT (12U)
|
|
/*! PADEN - Enable Frame Padding Remove On Receive
|
|
* 0b0..No padding is removed on receive by the MAC.
|
|
* 0b1..Padding is removed from received frames.
|
|
*/
|
|
#define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
|
|
#define ENET_RCR_PAUFWD_MASK (0x2000U)
|
|
#define ENET_RCR_PAUFWD_SHIFT (13U)
|
|
/*! PAUFWD - Terminate/Forward Pause Frames
|
|
* 0b0..Pause frames are terminated and discarded in the MAC.
|
|
* 0b1..Pause frames are forwarded to the user application.
|
|
*/
|
|
#define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
|
|
#define ENET_RCR_CRCFWD_MASK (0x4000U)
|
|
#define ENET_RCR_CRCFWD_SHIFT (14U)
|
|
/*! CRCFWD - Terminate/Forward Received CRC
|
|
* 0b0..The CRC field of received frames is transmitted to the user application.
|
|
* 0b1..The CRC field is stripped from the frame.
|
|
*/
|
|
#define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
|
|
#define ENET_RCR_CFEN_MASK (0x8000U)
|
|
#define ENET_RCR_CFEN_SHIFT (15U)
|
|
/*! CFEN - MAC Control Frame Enable
|
|
* 0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface.
|
|
* 0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded.
|
|
*/
|
|
#define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
|
|
#define ENET_RCR_MAX_FL_MASK (0x3FFF0000U)
|
|
#define ENET_RCR_MAX_FL_SHIFT (16U)
|
|
#define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
|
|
#define ENET_RCR_NLC_MASK (0x40000000U)
|
|
#define ENET_RCR_NLC_SHIFT (30U)
|
|
/*! NLC - Payload Length Check Disable
|
|
* 0b0..The payload length check is disabled.
|
|
* 0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLR] field.
|
|
*/
|
|
#define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
|
|
#define ENET_RCR_GRS_MASK (0x80000000U)
|
|
#define ENET_RCR_GRS_SHIFT (31U)
|
|
#define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TCR - Transmit Control Register */
|
|
/*! @{ */
|
|
#define ENET_TCR_GTS_MASK (0x1U)
|
|
#define ENET_TCR_GTS_SHIFT (0U)
|
|
#define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)
|
|
#define ENET_TCR_FDEN_MASK (0x4U)
|
|
#define ENET_TCR_FDEN_SHIFT (2U)
|
|
#define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
|
|
#define ENET_TCR_TFC_PAUSE_MASK (0x8U)
|
|
#define ENET_TCR_TFC_PAUSE_SHIFT (3U)
|
|
/*! TFC_PAUSE - Transmit Frame Control Pause
|
|
* 0b0..No PAUSE frame transmitted.
|
|
* 0b1..The MAC stops transmission of data frames after the current transmission is complete.
|
|
*/
|
|
#define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
|
|
#define ENET_TCR_RFC_PAUSE_MASK (0x10U)
|
|
#define ENET_TCR_RFC_PAUSE_SHIFT (4U)
|
|
#define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
|
|
#define ENET_TCR_ADDSEL_MASK (0xE0U)
|
|
#define ENET_TCR_ADDSEL_SHIFT (5U)
|
|
/*! ADDSEL - Source MAC Address Select On Transmit
|
|
* 0b000..Node MAC address programmed on PADDR1/2 registers.
|
|
* 0b100..Reserved.
|
|
* 0b101..Reserved.
|
|
* 0b110..Reserved.
|
|
*/
|
|
#define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
|
|
#define ENET_TCR_ADDINS_MASK (0x100U)
|
|
#define ENET_TCR_ADDINS_SHIFT (8U)
|
|
/*! ADDINS - Set MAC Address On Transmit
|
|
* 0b0..The source MAC address is not modified by the MAC.
|
|
* 0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL.
|
|
*/
|
|
#define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
|
|
#define ENET_TCR_CRCFWD_MASK (0x200U)
|
|
#define ENET_TCR_CRCFWD_SHIFT (9U)
|
|
/*! CRCFWD - Forward Frame From Application With CRC
|
|
* 0b0..TxBD[TC] controls whether the frame has a CRC from the application.
|
|
* 0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application.
|
|
*/
|
|
#define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PALR - Physical Address Lower Register */
|
|
/*! @{ */
|
|
#define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU)
|
|
#define ENET_PALR_PADDR1_SHIFT (0U)
|
|
#define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PAUR - Physical Address Upper Register */
|
|
/*! @{ */
|
|
#define ENET_PAUR_TYPE_MASK (0xFFFFU)
|
|
#define ENET_PAUR_TYPE_SHIFT (0U)
|
|
#define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
|
|
#define ENET_PAUR_PADDR2_MASK (0xFFFF0000U)
|
|
#define ENET_PAUR_PADDR2_SHIFT (16U)
|
|
#define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name OPD - Opcode/Pause Duration Register */
|
|
/*! @{ */
|
|
#define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU)
|
|
#define ENET_OPD_PAUSE_DUR_SHIFT (0U)
|
|
#define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
|
|
#define ENET_OPD_OPCODE_MASK (0xFFFF0000U)
|
|
#define ENET_OPD_OPCODE_SHIFT (16U)
|
|
#define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TXIC - Transmit Interrupt Coalescing Register */
|
|
/*! @{ */
|
|
#define ENET_TXIC_ICTT_MASK (0xFFFFU)
|
|
#define ENET_TXIC_ICTT_SHIFT (0U)
|
|
#define ENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK)
|
|
#define ENET_TXIC_ICFT_MASK (0xFF00000U)
|
|
#define ENET_TXIC_ICFT_SHIFT (20U)
|
|
#define ENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK)
|
|
#define ENET_TXIC_ICCS_MASK (0x40000000U)
|
|
#define ENET_TXIC_ICCS_SHIFT (30U)
|
|
/*! ICCS - Interrupt Coalescing Timer Clock Source Select
|
|
* 0b0..Use MII/GMII TX clocks.
|
|
* 0b1..Use ENET system clock.
|
|
*/
|
|
#define ENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK)
|
|
#define ENET_TXIC_ICEN_MASK (0x80000000U)
|
|
#define ENET_TXIC_ICEN_SHIFT (31U)
|
|
/*! ICEN - Interrupt Coalescing Enable
|
|
* 0b0..Disable Interrupt coalescing.
|
|
* 0b1..Enable Interrupt coalescing.
|
|
*/
|
|
#define ENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RXIC - Receive Interrupt Coalescing Register */
|
|
/*! @{ */
|
|
#define ENET_RXIC_ICTT_MASK (0xFFFFU)
|
|
#define ENET_RXIC_ICTT_SHIFT (0U)
|
|
#define ENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK)
|
|
#define ENET_RXIC_ICFT_MASK (0xFF00000U)
|
|
#define ENET_RXIC_ICFT_SHIFT (20U)
|
|
#define ENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK)
|
|
#define ENET_RXIC_ICCS_MASK (0x40000000U)
|
|
#define ENET_RXIC_ICCS_SHIFT (30U)
|
|
/*! ICCS - Interrupt Coalescing Timer Clock Source Select
|
|
* 0b0..Use MII/GMII TX clocks.
|
|
* 0b1..Use ENET system clock.
|
|
*/
|
|
#define ENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK)
|
|
#define ENET_RXIC_ICEN_MASK (0x80000000U)
|
|
#define ENET_RXIC_ICEN_SHIFT (31U)
|
|
/*! ICEN - Interrupt Coalescing Enable
|
|
* 0b0..Disable Interrupt coalescing.
|
|
* 0b1..Enable Interrupt coalescing.
|
|
*/
|
|
#define ENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name IAUR - Descriptor Individual Upper Address Register */
|
|
/*! @{ */
|
|
#define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU)
|
|
#define ENET_IAUR_IADDR1_SHIFT (0U)
|
|
#define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name IALR - Descriptor Individual Lower Address Register */
|
|
/*! @{ */
|
|
#define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU)
|
|
#define ENET_IALR_IADDR2_SHIFT (0U)
|
|
#define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GAUR - Descriptor Group Upper Address Register */
|
|
/*! @{ */
|
|
#define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU)
|
|
#define ENET_GAUR_GADDR1_SHIFT (0U)
|
|
#define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GALR - Descriptor Group Lower Address Register */
|
|
/*! @{ */
|
|
#define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU)
|
|
#define ENET_GALR_GADDR2_SHIFT (0U)
|
|
#define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TFWR - Transmit FIFO Watermark Register */
|
|
/*! @{ */
|
|
#define ENET_TFWR_TFWR_MASK (0x3FU)
|
|
#define ENET_TFWR_TFWR_SHIFT (0U)
|
|
/*! TFWR - Transmit FIFO Write
|
|
* 0b000000..64 bytes written.
|
|
* 0b000001..64 bytes written.
|
|
* 0b000010..128 bytes written.
|
|
* 0b000011..192 bytes written.
|
|
* 0b011111..1984 bytes written.
|
|
*/
|
|
#define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
|
|
#define ENET_TFWR_STRFWD_MASK (0x100U)
|
|
#define ENET_TFWR_STRFWD_SHIFT (8U)
|
|
/*! STRFWD - Store And Forward Enable
|
|
* 0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR].
|
|
* 0b1..Enabled.
|
|
*/
|
|
#define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RDSR - Receive Descriptor Ring Start Register */
|
|
/*! @{ */
|
|
#define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U)
|
|
#define ENET_RDSR_R_DES_START_SHIFT (3U)
|
|
#define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TDSR - Transmit Buffer Descriptor Ring Start Register */
|
|
/*! @{ */
|
|
#define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U)
|
|
#define ENET_TDSR_X_DES_START_SHIFT (3U)
|
|
#define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MRBR - Maximum Receive Buffer Size Register */
|
|
/*! @{ */
|
|
#define ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U)
|
|
#define ENET_MRBR_R_BUF_SIZE_SHIFT (4U)
|
|
#define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RSFL - Receive FIFO Section Full Threshold */
|
|
/*! @{ */
|
|
#define ENET_RSFL_RX_SECTION_FULL_MASK (0xFFU)
|
|
#define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U)
|
|
#define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RSEM - Receive FIFO Section Empty Threshold */
|
|
/*! @{ */
|
|
#define ENET_RSEM_RX_SECTION_EMPTY_MASK (0xFFU)
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#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U)
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#define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)
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#define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U)
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#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U)
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#define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)
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|
/*! @} */
|
|
|
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/*! @name RAEM - Receive FIFO Almost Empty Threshold */
|
|
/*! @{ */
|
|
#define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0xFFU)
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|
#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U)
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#define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)
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|
/*! @} */
|
|
|
|
/*! @name RAFL - Receive FIFO Almost Full Threshold */
|
|
/*! @{ */
|
|
#define ENET_RAFL_RX_ALMOST_FULL_MASK (0xFFU)
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#define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U)
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#define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)
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|
/*! @} */
|
|
|
|
/*! @name TSEM - Transmit FIFO Section Empty Threshold */
|
|
/*! @{ */
|
|
#define ENET_TSEM_TX_SECTION_EMPTY_MASK (0xFFU)
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|
#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U)
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#define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)
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|
/*! @} */
|
|
|
|
/*! @name TAEM - Transmit FIFO Almost Empty Threshold */
|
|
/*! @{ */
|
|
#define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0xFFU)
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|
#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U)
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|
#define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)
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|
/*! @} */
|
|
|
|
/*! @name TAFL - Transmit FIFO Almost Full Threshold */
|
|
/*! @{ */
|
|
#define ENET_TAFL_TX_ALMOST_FULL_MASK (0xFFU)
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|
#define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U)
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|
#define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)
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|
/*! @} */
|
|
|
|
/*! @name TIPG - Transmit Inter-Packet Gap */
|
|
/*! @{ */
|
|
#define ENET_TIPG_IPG_MASK (0x1FU)
|
|
#define ENET_TIPG_IPG_SHIFT (0U)
|
|
#define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
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|
/*! @} */
|
|
|
|
/*! @name FTRL - Frame Truncation Length */
|
|
/*! @{ */
|
|
#define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU)
|
|
#define ENET_FTRL_TRUNC_FL_SHIFT (0U)
|
|
#define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TACC - Transmit Accelerator Function Configuration */
|
|
/*! @{ */
|
|
#define ENET_TACC_SHIFT16_MASK (0x1U)
|
|
#define ENET_TACC_SHIFT16_SHIFT (0U)
|
|
/*! SHIFT16 - TX FIFO Shift-16
|
|
* 0b0..Disabled.
|
|
* 0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is extended to a 16-byte header.
|
|
*/
|
|
#define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
|
|
#define ENET_TACC_IPCHK_MASK (0x8U)
|
|
#define ENET_TACC_IPCHK_SHIFT (3U)
|
|
/*! IPCHK
|
|
* 0b0..Checksum is not inserted.
|
|
* 0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must be cleared. If a non-IP frame is transmitted the frame is not modified.
|
|
*/
|
|
#define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
|
|
#define ENET_TACC_PROCHK_MASK (0x10U)
|
|
#define ENET_TACC_PROCHK_SHIFT (4U)
|
|
/*! PROCHK
|
|
* 0b0..Checksum not inserted.
|
|
* 0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the frame. The checksum field must be cleared. The other frames are not modified.
|
|
*/
|
|
#define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RACC - Receive Accelerator Function Configuration */
|
|
/*! @{ */
|
|
#define ENET_RACC_PADREM_MASK (0x1U)
|
|
#define ENET_RACC_PADREM_SHIFT (0U)
|
|
/*! PADREM - Enable Padding Removal For Short IP Frames
|
|
* 0b0..Padding not removed.
|
|
* 0b1..Any bytes following the IP payload section of the frame are removed from the frame.
|
|
*/
|
|
#define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
|
|
#define ENET_RACC_IPDIS_MASK (0x2U)
|
|
#define ENET_RACC_IPDIS_SHIFT (1U)
|
|
/*! IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum
|
|
* 0b0..Frames with wrong IPv4 header checksum are not discarded.
|
|
* 0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared).
|
|
*/
|
|
#define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
|
|
#define ENET_RACC_PRODIS_MASK (0x4U)
|
|
#define ENET_RACC_PRODIS_SHIFT (2U)
|
|
/*! PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum
|
|
* 0b0..Frames with wrong checksum are not discarded.
|
|
* 0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared).
|
|
*/
|
|
#define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
|
|
#define ENET_RACC_LINEDIS_MASK (0x40U)
|
|
#define ENET_RACC_LINEDIS_SHIFT (6U)
|
|
/*! LINEDIS - Enable Discard Of Frames With MAC Layer Errors
|
|
* 0b0..Frames with errors are not discarded.
|
|
* 0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface.
|
|
*/
|
|
#define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
|
|
#define ENET_RACC_SHIFT16_MASK (0x80U)
|
|
#define ENET_RACC_SHIFT16_SHIFT (7U)
|
|
/*! SHIFT16 - RX FIFO Shift-16
|
|
* 0b0..Disabled.
|
|
* 0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO.
|
|
*/
|
|
#define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */
|
|
/*! @{ */
|
|
#define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU)
|
|
#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U)
|
|
#define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */
|
|
/*! @{ */
|
|
#define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU)
|
|
#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U)
|
|
#define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */
|
|
/*! @{ */
|
|
#define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU)
|
|
#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U)
|
|
#define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */
|
|
/*! @{ */
|
|
#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU)
|
|
#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U)
|
|
#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */
|
|
/*! @{ */
|
|
#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU)
|
|
#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U)
|
|
#define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */
|
|
/*! @{ */
|
|
#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU)
|
|
#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U)
|
|
#define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
|
|
/*! @{ */
|
|
#define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU)
|
|
#define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U)
|
|
#define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */
|
|
/*! @{ */
|
|
#define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU)
|
|
#define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U)
|
|
#define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RMON_T_COL - Tx Collision Count Statistic Register */
|
|
/*! @{ */
|
|
#define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU)
|
|
#define ENET_RMON_T_COL_TXPKTS_SHIFT (0U)
|
|
#define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */
|
|
/*! @{ */
|
|
#define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU)
|
|
#define ENET_RMON_T_P64_TXPKTS_SHIFT (0U)
|
|
#define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */
|
|
/*! @{ */
|
|
#define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU)
|
|
#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U)
|
|
#define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */
|
|
/*! @{ */
|
|
#define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU)
|
|
#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U)
|
|
#define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */
|
|
/*! @{ */
|
|
#define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU)
|
|
#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U)
|
|
#define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */
|
|
/*! @{ */
|
|
#define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU)
|
|
#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U)
|
|
#define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */
|
|
/*! @{ */
|
|
#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU)
|
|
#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U)
|
|
#define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */
|
|
/*! @{ */
|
|
#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU)
|
|
#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U)
|
|
#define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RMON_T_OCTETS - Tx Octets Statistic Register */
|
|
/*! @{ */
|
|
#define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU)
|
|
#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U)
|
|
#define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */
|
|
/*! @{ */
|
|
#define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU)
|
|
#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U)
|
|
#define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */
|
|
/*! @{ */
|
|
#define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU)
|
|
#define ENET_IEEE_T_1COL_COUNT_SHIFT (0U)
|
|
#define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */
|
|
/*! @{ */
|
|
#define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU)
|
|
#define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U)
|
|
#define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */
|
|
/*! @{ */
|
|
#define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU)
|
|
#define ENET_IEEE_T_DEF_COUNT_SHIFT (0U)
|
|
#define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */
|
|
/*! @{ */
|
|
#define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU)
|
|
#define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U)
|
|
#define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */
|
|
/*! @{ */
|
|
#define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU)
|
|
#define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U)
|
|
#define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */
|
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/*! @{ */
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#define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU)
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#define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U)
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#define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
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/*! @} */
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/*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */
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/*! @{ */
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#define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU)
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#define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U)
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#define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
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/*! @} */
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/*! @name IEEE_T_SQE - Reserved Statistic Register */
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/*! @{ */
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#define ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU)
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#define ENET_IEEE_T_SQE_COUNT_SHIFT (0U)
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#define ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)
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/*! @} */
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/*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */
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/*! @{ */
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#define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU)
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#define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U)
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#define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
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/*! @} */
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/*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */
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/*! @{ */
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#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
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#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U)
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#define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
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/*! @} */
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/*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */
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/*! @{ */
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#define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU)
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#define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U)
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#define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
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/*! @} */
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/*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */
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/*! @{ */
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#define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU)
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#define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U)
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#define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
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/*! @} */
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/*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */
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/*! @{ */
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#define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU)
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#define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U)
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#define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
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/*! @} */
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/*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */
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/*! @{ */
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#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU)
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#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U)
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#define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
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/*! @} */
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/*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */
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/*! @{ */
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#define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU)
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#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U)
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#define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
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/*! @} */
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/*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */
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/*! @{ */
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#define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU)
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#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U)
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#define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
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/*! @} */
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/*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
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/*! @{ */
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#define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU)
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#define ENET_RMON_R_FRAG_COUNT_SHIFT (0U)
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#define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
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/*! @} */
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/*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */
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/*! @{ */
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#define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU)
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#define ENET_RMON_R_JAB_COUNT_SHIFT (0U)
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#define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
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/*! @} */
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/*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */
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/*! @{ */
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#define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU)
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#define ENET_RMON_R_P64_COUNT_SHIFT (0U)
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#define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
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/*! @} */
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/*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */
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/*! @{ */
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#define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU)
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#define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U)
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#define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
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/*! @} */
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/*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */
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/*! @{ */
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#define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU)
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#define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U)
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#define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
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/*! @} */
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/*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */
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/*! @{ */
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#define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU)
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#define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U)
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#define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
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/*! @} */
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/*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */
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/*! @{ */
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#define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU)
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#define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U)
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#define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
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/*! @} */
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/*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */
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/*! @{ */
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#define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU)
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#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U)
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#define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
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/*! @} */
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/*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */
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/*! @{ */
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#define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU)
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#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U)
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#define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
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/*! @} */
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/*! @name RMON_R_OCTETS - Rx Octets Statistic Register */
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/*! @{ */
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#define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU)
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#define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U)
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#define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)
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/*! @} */
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/*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */
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/*! @{ */
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#define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU)
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#define ENET_IEEE_R_DROP_COUNT_SHIFT (0U)
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#define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
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/*! @} */
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/*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */
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/*! @{ */
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#define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU)
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#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U)
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#define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
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/*! @} */
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/*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */
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/*! @{ */
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#define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU)
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#define ENET_IEEE_R_CRC_COUNT_SHIFT (0U)
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#define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
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/*! @} */
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/*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */
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/*! @{ */
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#define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU)
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#define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U)
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#define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
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/*! @} */
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/*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */
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/*! @{ */
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#define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU)
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#define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U)
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#define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
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/*! @} */
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/*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */
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/*! @{ */
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#define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU)
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#define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U)
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#define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
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/*! @} */
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/*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */
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/*! @{ */
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#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
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#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U)
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#define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
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/*! @} */
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/*! @name ATCR - Adjustable Timer Control Register */
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/*! @{ */
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#define ENET_ATCR_EN_MASK (0x1U)
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#define ENET_ATCR_EN_SHIFT (0U)
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/*! EN - Enable Timer
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* 0b0..The timer stops at the current value.
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* 0b1..The timer starts incrementing.
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*/
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#define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
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#define ENET_ATCR_OFFEN_MASK (0x4U)
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#define ENET_ATCR_OFFEN_SHIFT (2U)
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/*! OFFEN - Enable One-Shot Offset Event
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* 0b0..Disable.
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* 0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared when the offset event is reached, so no further event occurs until the field is set again. The timer offset value must be set before setting this field.
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*/
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#define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
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#define ENET_ATCR_OFFRST_MASK (0x8U)
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#define ENET_ATCR_OFFRST_SHIFT (3U)
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/*! OFFRST - Reset Timer On Offset Event
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* 0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached.
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* 0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt.
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*/
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#define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
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#define ENET_ATCR_PEREN_MASK (0x10U)
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#define ENET_ATCR_PEREN_SHIFT (4U)
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/*! PEREN - Enable Periodical Event
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* 0b0..Disable.
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* 0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when the timer wraps around according to the periodic setting ATPER. The timer period value must be set before setting this bit. Not all devices contain the event signal output. See the chip configuration details.
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*/
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#define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
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#define ENET_ATCR_PINPER_MASK (0x80U)
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#define ENET_ATCR_PINPER_SHIFT (7U)
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/*! PINPER
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* 0b0..Disable.
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* 0b1..Enable.
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*/
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#define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
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#define ENET_ATCR_RESTART_MASK (0x200U)
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#define ENET_ATCR_RESTART_SHIFT (9U)
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#define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
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#define ENET_ATCR_CAPTURE_MASK (0x800U)
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#define ENET_ATCR_CAPTURE_SHIFT (11U)
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/*! CAPTURE - Capture Timer Value
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* 0b0..No effect.
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* 0b1..The current time is captured and can be read from the ATVR register.
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*/
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#define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
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#define ENET_ATCR_SLAVE_MASK (0x2000U)
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#define ENET_ATCR_SLAVE_SHIFT (13U)
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/*! SLAVE - Enable Timer Slave Mode
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* 0b0..The timer is active and all configuration fields in this register are relevant.
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* 0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value.
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*/
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#define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)
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/*! @} */
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/*! @name ATVR - Timer Value Register */
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/*! @{ */
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#define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU)
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#define ENET_ATVR_ATIME_SHIFT (0U)
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#define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)
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/*! @} */
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/*! @name ATOFF - Timer Offset Register */
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/*! @{ */
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#define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU)
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#define ENET_ATOFF_OFFSET_SHIFT (0U)
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#define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)
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/*! @} */
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/*! @name ATPER - Timer Period Register */
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/*! @{ */
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#define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU)
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#define ENET_ATPER_PERIOD_SHIFT (0U)
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#define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)
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/*! @} */
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/*! @name ATCOR - Timer Correction Register */
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/*! @{ */
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#define ENET_ATCOR_COR_MASK (0x7FFFFFFFU)
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#define ENET_ATCOR_COR_SHIFT (0U)
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#define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
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/*! @} */
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/*! @name ATINC - Time-Stamping Clock Period Register */
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/*! @{ */
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#define ENET_ATINC_INC_MASK (0x7FU)
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#define ENET_ATINC_INC_SHIFT (0U)
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#define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
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#define ENET_ATINC_INC_CORR_MASK (0x7F00U)
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#define ENET_ATINC_INC_CORR_SHIFT (8U)
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#define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
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/*! @} */
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/*! @name ATSTMP - Timestamp of Last Transmitted Frame */
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/*! @{ */
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#define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU)
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#define ENET_ATSTMP_TIMESTAMP_SHIFT (0U)
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#define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)
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/*! @} */
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/*! @name TGSR - Timer Global Status Register */
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/*! @{ */
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#define ENET_TGSR_TF0_MASK (0x1U)
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#define ENET_TGSR_TF0_SHIFT (0U)
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/*! TF0 - Copy Of Timer Flag For Channel 0
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* 0b0..Timer Flag for Channel 0 is clear
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* 0b1..Timer Flag for Channel 0 is set
|
|
*/
|
|
#define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
|
|
#define ENET_TGSR_TF1_MASK (0x2U)
|
|
#define ENET_TGSR_TF1_SHIFT (1U)
|
|
/*! TF1 - Copy Of Timer Flag For Channel 1
|
|
* 0b0..Timer Flag for Channel 1 is clear
|
|
* 0b1..Timer Flag for Channel 1 is set
|
|
*/
|
|
#define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
|
|
#define ENET_TGSR_TF2_MASK (0x4U)
|
|
#define ENET_TGSR_TF2_SHIFT (2U)
|
|
/*! TF2 - Copy Of Timer Flag For Channel 2
|
|
* 0b0..Timer Flag for Channel 2 is clear
|
|
* 0b1..Timer Flag for Channel 2 is set
|
|
*/
|
|
#define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
|
|
#define ENET_TGSR_TF3_MASK (0x8U)
|
|
#define ENET_TGSR_TF3_SHIFT (3U)
|
|
/*! TF3 - Copy Of Timer Flag For Channel 3
|
|
* 0b0..Timer Flag for Channel 3 is clear
|
|
* 0b1..Timer Flag for Channel 3 is set
|
|
*/
|
|
#define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TCSR - Timer Control Status Register */
|
|
/*! @{ */
|
|
#define ENET_TCSR_TDRE_MASK (0x1U)
|
|
#define ENET_TCSR_TDRE_SHIFT (0U)
|
|
/*! TDRE - Timer DMA Request Enable
|
|
* 0b0..DMA request is disabled
|
|
* 0b1..DMA request is enabled
|
|
*/
|
|
#define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
|
|
#define ENET_TCSR_TMODE_MASK (0x3CU)
|
|
#define ENET_TCSR_TMODE_SHIFT (2U)
|
|
/*! TMODE - Timer Mode
|
|
* 0b0000..Timer Channel is disabled.
|
|
* 0b0001..Timer Channel is configured for Input Capture on rising edge.
|
|
* 0b0010..Timer Channel is configured for Input Capture on falling edge.
|
|
* 0b0011..Timer Channel is configured for Input Capture on both edges.
|
|
* 0b0100..Timer Channel is configured for Output Compare - software only.
|
|
* 0b0101..Timer Channel is configured for Output Compare - toggle output on compare.
|
|
* 0b0110..Timer Channel is configured for Output Compare - clear output on compare.
|
|
* 0b0111..Timer Channel is configured for Output Compare - set output on compare.
|
|
* 0b1000..Reserved
|
|
* 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow.
|
|
* 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow.
|
|
* 0b110x..Reserved
|
|
* 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC.
|
|
* 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC.
|
|
*/
|
|
#define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
|
|
#define ENET_TCSR_TIE_MASK (0x40U)
|
|
#define ENET_TCSR_TIE_SHIFT (6U)
|
|
/*! TIE - Timer Interrupt Enable
|
|
* 0b0..Interrupt is disabled
|
|
* 0b1..Interrupt is enabled
|
|
*/
|
|
#define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
|
|
#define ENET_TCSR_TF_MASK (0x80U)
|
|
#define ENET_TCSR_TF_SHIFT (7U)
|
|
/*! TF - Timer Flag
|
|
* 0b0..Input Capture or Output Compare has not occurred.
|
|
* 0b1..Input Capture or Output Compare has occurred.
|
|
*/
|
|
#define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)
|
|
#define ENET_TCSR_TPWC_MASK (0xF800U)
|
|
#define ENET_TCSR_TPWC_SHIFT (11U)
|
|
/*! TPWC - Timer PulseWidth Control
|
|
* 0b00000..Pulse width is one 1588-clock cycle.
|
|
* 0b00001..Pulse width is two 1588-clock cycles.
|
|
* 0b00010..Pulse width is three 1588-clock cycles.
|
|
* 0b00011..Pulse width is four 1588-clock cycles.
|
|
* 0b11111..Pulse width is 32 1588-clock cycles.
|
|
*/
|
|
#define ENET_TCSR_TPWC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of ENET_TCSR */
|
|
#define ENET_TCSR_COUNT (4U)
|
|
|
|
/*! @name TCCR - Timer Compare Capture Register */
|
|
/*! @{ */
|
|
#define ENET_TCCR_TCC_MASK (0xFFFFFFFFU)
|
|
#define ENET_TCCR_TCC_SHIFT (0U)
|
|
#define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of ENET_TCCR */
|
|
#define ENET_TCCR_COUNT (4U)
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group ENET_Register_Masks */
|
|
|
|
|
|
/* ENET - Peripheral instance base addresses */
|
|
/** Peripheral ENET base address */
|
|
#define ENET_BASE (0x402D8000u)
|
|
/** Peripheral ENET base pointer */
|
|
#define ENET ((ENET_Type *)ENET_BASE)
|
|
/** Array initializer of ENET peripheral base addresses */
|
|
#define ENET_BASE_ADDRS { ENET_BASE }
|
|
/** Array initializer of ENET peripheral base pointers */
|
|
#define ENET_BASE_PTRS { ENET }
|
|
/** Interrupt vectors for the ENET peripheral type */
|
|
#define ENET_Transmit_IRQS { ENET_IRQn }
|
|
#define ENET_Receive_IRQS { ENET_IRQn }
|
|
#define ENET_Error_IRQS { ENET_IRQn }
|
|
#define ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn }
|
|
/* ENET Buffer Descriptor and Buffer Address Alignment. */
|
|
#define ENET_BUFF_ALIGNMENT (64U)
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group ENET_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- EWM Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** EWM - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
|
|
__O uint8_t SERV; /**< Service Register, offset: 0x1 */
|
|
__IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
|
|
__IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
|
|
__IO uint8_t CLKCTRL; /**< Clock Control Register, offset: 0x4 */
|
|
__IO uint8_t CLKPRESCALER; /**< Clock Prescaler Register, offset: 0x5 */
|
|
} EWM_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- EWM Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup EWM_Register_Masks EWM Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name CTRL - Control Register */
|
|
/*! @{ */
|
|
#define EWM_CTRL_EWMEN_MASK (0x1U)
|
|
#define EWM_CTRL_EWMEN_SHIFT (0U)
|
|
#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
|
|
#define EWM_CTRL_ASSIN_MASK (0x2U)
|
|
#define EWM_CTRL_ASSIN_SHIFT (1U)
|
|
#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
|
|
#define EWM_CTRL_INEN_MASK (0x4U)
|
|
#define EWM_CTRL_INEN_SHIFT (2U)
|
|
#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
|
|
#define EWM_CTRL_INTEN_MASK (0x8U)
|
|
#define EWM_CTRL_INTEN_SHIFT (3U)
|
|
#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SERV - Service Register */
|
|
/*! @{ */
|
|
#define EWM_SERV_SERVICE_MASK (0xFFU)
|
|
#define EWM_SERV_SERVICE_SHIFT (0U)
|
|
#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CMPL - Compare Low Register */
|
|
/*! @{ */
|
|
#define EWM_CMPL_COMPAREL_MASK (0xFFU)
|
|
#define EWM_CMPL_COMPAREL_SHIFT (0U)
|
|
#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CMPH - Compare High Register */
|
|
/*! @{ */
|
|
#define EWM_CMPH_COMPAREH_MASK (0xFFU)
|
|
#define EWM_CMPH_COMPAREH_SHIFT (0U)
|
|
#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CLKCTRL - Clock Control Register */
|
|
/*! @{ */
|
|
#define EWM_CLKCTRL_CLKSEL_MASK (0x3U)
|
|
#define EWM_CLKCTRL_CLKSEL_SHIFT (0U)
|
|
#define EWM_CLKCTRL_CLKSEL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CLKPRESCALER - Clock Prescaler Register */
|
|
/*! @{ */
|
|
#define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU)
|
|
#define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U)
|
|
#define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group EWM_Register_Masks */
|
|
|
|
|
|
/* EWM - Peripheral instance base addresses */
|
|
/** Peripheral EWM base address */
|
|
#define EWM_BASE (0x400B4000u)
|
|
/** Peripheral EWM base pointer */
|
|
#define EWM ((EWM_Type *)EWM_BASE)
|
|
/** Array initializer of EWM peripheral base addresses */
|
|
#define EWM_BASE_ADDRS { EWM_BASE }
|
|
/** Array initializer of EWM peripheral base pointers */
|
|
#define EWM_BASE_PTRS { EWM }
|
|
/** Interrupt vectors for the EWM peripheral type */
|
|
#define EWM_IRQS { EWM_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group EWM_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- FLEXIO Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** FLEXIO - Register Layout Typedef */
|
|
typedef struct {
|
|
__I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
|
|
__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
|
|
__IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */
|
|
__I uint32_t PIN; /**< Pin State Register, offset: 0xC */
|
|
__IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */
|
|
__IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */
|
|
__IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */
|
|
uint8_t RESERVED_0[4];
|
|
__IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */
|
|
__IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */
|
|
__IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */
|
|
uint8_t RESERVED_1[4];
|
|
__IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */
|
|
uint8_t RESERVED_2[12];
|
|
__IO uint32_t SHIFTSTATE; /**< Shifter State Register, offset: 0x40 */
|
|
uint8_t RESERVED_3[60];
|
|
__IO uint32_t SHIFTCTL[4]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */
|
|
uint8_t RESERVED_4[112];
|
|
__IO uint32_t SHIFTCFG[4]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */
|
|
uint8_t RESERVED_5[240];
|
|
__IO uint32_t SHIFTBUF[4]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */
|
|
uint8_t RESERVED_6[112];
|
|
__IO uint32_t SHIFTBUFBIS[4]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */
|
|
uint8_t RESERVED_7[112];
|
|
__IO uint32_t SHIFTBUFBYS[4]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */
|
|
uint8_t RESERVED_8[112];
|
|
__IO uint32_t SHIFTBUFBBS[4]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */
|
|
uint8_t RESERVED_9[112];
|
|
__IO uint32_t TIMCTL[4]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */
|
|
uint8_t RESERVED_10[112];
|
|
__IO uint32_t TIMCFG[4]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */
|
|
uint8_t RESERVED_11[112];
|
|
__IO uint32_t TIMCMP[4]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */
|
|
uint8_t RESERVED_12[368];
|
|
__IO uint32_t SHIFTBUFNBS[4]; /**< Shifter Buffer N Nibble Byte Swapped Register, array offset: 0x680, array step: 0x4 */
|
|
uint8_t RESERVED_13[112];
|
|
__IO uint32_t SHIFTBUFHWS[4]; /**< Shifter Buffer N Half Word Swapped Register, array offset: 0x700, array step: 0x4 */
|
|
uint8_t RESERVED_14[112];
|
|
__IO uint32_t SHIFTBUFNIS[4]; /**< Shifter Buffer N Nibble Swapped Register, array offset: 0x780, array step: 0x4 */
|
|
} FLEXIO_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- FLEXIO Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name VERID - Version ID Register */
|
|
/*! @{ */
|
|
#define FLEXIO_VERID_FEATURE_MASK (0xFFFFU)
|
|
#define FLEXIO_VERID_FEATURE_SHIFT (0U)
|
|
/*! FEATURE - Feature Specification Number
|
|
* 0b0000000000000000..Standard features implemented.
|
|
* 0b0000000000000001..Supports state, logic and parallel modes.
|
|
*/
|
|
#define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)
|
|
#define FLEXIO_VERID_MINOR_MASK (0xFF0000U)
|
|
#define FLEXIO_VERID_MINOR_SHIFT (16U)
|
|
#define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)
|
|
#define FLEXIO_VERID_MAJOR_MASK (0xFF000000U)
|
|
#define FLEXIO_VERID_MAJOR_SHIFT (24U)
|
|
#define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PARAM - Parameter Register */
|
|
/*! @{ */
|
|
#define FLEXIO_PARAM_SHIFTER_MASK (0xFFU)
|
|
#define FLEXIO_PARAM_SHIFTER_SHIFT (0U)
|
|
#define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)
|
|
#define FLEXIO_PARAM_TIMER_MASK (0xFF00U)
|
|
#define FLEXIO_PARAM_TIMER_SHIFT (8U)
|
|
#define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)
|
|
#define FLEXIO_PARAM_PIN_MASK (0xFF0000U)
|
|
#define FLEXIO_PARAM_PIN_SHIFT (16U)
|
|
#define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)
|
|
#define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U)
|
|
#define FLEXIO_PARAM_TRIGGER_SHIFT (24U)
|
|
#define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CTRL - FlexIO Control Register */
|
|
/*! @{ */
|
|
#define FLEXIO_CTRL_FLEXEN_MASK (0x1U)
|
|
#define FLEXIO_CTRL_FLEXEN_SHIFT (0U)
|
|
/*! FLEXEN - FlexIO Enable
|
|
* 0b0..FlexIO module is disabled.
|
|
* 0b1..FlexIO module is enabled.
|
|
*/
|
|
#define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)
|
|
#define FLEXIO_CTRL_SWRST_MASK (0x2U)
|
|
#define FLEXIO_CTRL_SWRST_SHIFT (1U)
|
|
/*! SWRST - Software Reset
|
|
* 0b0..Software reset is disabled
|
|
* 0b1..Software reset is enabled, all FlexIO registers except the Control Register are reset.
|
|
*/
|
|
#define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)
|
|
#define FLEXIO_CTRL_FASTACC_MASK (0x4U)
|
|
#define FLEXIO_CTRL_FASTACC_SHIFT (2U)
|
|
/*! FASTACC - Fast Access
|
|
* 0b0..Configures for normal register accesses to FlexIO
|
|
* 0b1..Configures for fast register accesses to FlexIO
|
|
*/
|
|
#define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)
|
|
#define FLEXIO_CTRL_DBGE_MASK (0x40000000U)
|
|
#define FLEXIO_CTRL_DBGE_SHIFT (30U)
|
|
/*! DBGE - Debug Enable
|
|
* 0b0..FlexIO is disabled in debug modes.
|
|
* 0b1..FlexIO is enabled in debug modes
|
|
*/
|
|
#define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)
|
|
#define FLEXIO_CTRL_DOZEN_MASK (0x80000000U)
|
|
#define FLEXIO_CTRL_DOZEN_SHIFT (31U)
|
|
/*! DOZEN - Doze Enable
|
|
* 0b0..FlexIO enabled in Doze modes.
|
|
* 0b1..FlexIO disabled in Doze modes.
|
|
*/
|
|
#define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PIN - Pin State Register */
|
|
/*! @{ */
|
|
#define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU)
|
|
#define FLEXIO_PIN_PDI_SHIFT (0U)
|
|
#define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SHIFTSTAT - Shifter Status Register */
|
|
/*! @{ */
|
|
#define FLEXIO_SHIFTSTAT_SSF_MASK (0xFU)
|
|
#define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U)
|
|
#define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SHIFTERR - Shifter Error Register */
|
|
/*! @{ */
|
|
#define FLEXIO_SHIFTERR_SEF_MASK (0xFU)
|
|
#define FLEXIO_SHIFTERR_SEF_SHIFT (0U)
|
|
#define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TIMSTAT - Timer Status Register */
|
|
/*! @{ */
|
|
#define FLEXIO_TIMSTAT_TSF_MASK (0xFU)
|
|
#define FLEXIO_TIMSTAT_TSF_SHIFT (0U)
|
|
#define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SHIFTSIEN - Shifter Status Interrupt Enable */
|
|
/*! @{ */
|
|
#define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFU)
|
|
#define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U)
|
|
#define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SHIFTEIEN - Shifter Error Interrupt Enable */
|
|
/*! @{ */
|
|
#define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFU)
|
|
#define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U)
|
|
#define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TIMIEN - Timer Interrupt Enable Register */
|
|
/*! @{ */
|
|
#define FLEXIO_TIMIEN_TEIE_MASK (0xFU)
|
|
#define FLEXIO_TIMIEN_TEIE_SHIFT (0U)
|
|
#define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SHIFTSDEN - Shifter Status DMA Enable */
|
|
/*! @{ */
|
|
#define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFU)
|
|
#define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U)
|
|
#define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SHIFTSTATE - Shifter State Register */
|
|
/*! @{ */
|
|
#define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U)
|
|
#define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U)
|
|
#define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SHIFTCTL - Shifter Control N Register */
|
|
/*! @{ */
|
|
#define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U)
|
|
#define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U)
|
|
/*! SMOD - Shifter Mode
|
|
* 0b000..Disabled.
|
|
* 0b001..Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer.
|
|
* 0b010..Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer.
|
|
* 0b011..Reserved.
|
|
* 0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer.
|
|
* 0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents.
|
|
* 0b110..State mode. SHIFTBUF contents are used for storing programmable state attributes.
|
|
* 0b111..Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table.
|
|
*/
|
|
#define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)
|
|
#define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U)
|
|
#define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U)
|
|
/*! PINPOL - Shifter Pin Polarity
|
|
* 0b0..Pin is active high
|
|
* 0b1..Pin is active low
|
|
*/
|
|
#define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)
|
|
#define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U)
|
|
#define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U)
|
|
#define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK)
|
|
#define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U)
|
|
#define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U)
|
|
/*! PINCFG - Shifter Pin Configuration
|
|
* 0b00..Shifter pin output disabled
|
|
* 0b01..Shifter pin open drain or bidirectional output enable
|
|
* 0b10..Shifter pin bidirectional output data
|
|
* 0b11..Shifter pin output
|
|
*/
|
|
#define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)
|
|
#define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U)
|
|
#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U)
|
|
/*! TIMPOL - Timer Polarity
|
|
* 0b0..Shift on posedge of Shift clock
|
|
* 0b1..Shift on negedge of Shift clock
|
|
*/
|
|
#define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)
|
|
#define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x3000000U)
|
|
#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U)
|
|
#define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of FLEXIO_SHIFTCTL */
|
|
#define FLEXIO_SHIFTCTL_COUNT (4U)
|
|
|
|
/*! @name SHIFTCFG - Shifter Configuration N Register */
|
|
/*! @{ */
|
|
#define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U)
|
|
#define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U)
|
|
/*! SSTART - Shifter Start bit
|
|
* 0b00..Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable
|
|
* 0b01..Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift
|
|
* 0b10..Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0
|
|
* 0b11..Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1
|
|
*/
|
|
#define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)
|
|
#define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U)
|
|
#define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U)
|
|
/*! SSTOP - Shifter Stop bit
|
|
* 0b00..Stop bit disabled for transmitter/receiver/match store
|
|
* 0b01..Reserved for transmitter/receiver/match store
|
|
* 0b10..Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0
|
|
* 0b11..Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1
|
|
*/
|
|
#define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)
|
|
#define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U)
|
|
#define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U)
|
|
/*! INSRC - Input Source
|
|
* 0b0..Pin
|
|
* 0b1..Shifter N+1 Output
|
|
*/
|
|
#define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)
|
|
#define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U)
|
|
#define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U)
|
|
#define FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of FLEXIO_SHIFTCFG */
|
|
#define FLEXIO_SHIFTCFG_COUNT (4U)
|
|
|
|
/*! @name SHIFTBUF - Shifter Buffer N Register */
|
|
/*! @{ */
|
|
#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU)
|
|
#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U)
|
|
#define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of FLEXIO_SHIFTBUF */
|
|
#define FLEXIO_SHIFTBUF_COUNT (4U)
|
|
|
|
/*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */
|
|
/*! @{ */
|
|
#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU)
|
|
#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U)
|
|
#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of FLEXIO_SHIFTBUFBIS */
|
|
#define FLEXIO_SHIFTBUFBIS_COUNT (4U)
|
|
|
|
/*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */
|
|
/*! @{ */
|
|
#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU)
|
|
#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U)
|
|
#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of FLEXIO_SHIFTBUFBYS */
|
|
#define FLEXIO_SHIFTBUFBYS_COUNT (4U)
|
|
|
|
/*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */
|
|
/*! @{ */
|
|
#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU)
|
|
#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U)
|
|
#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of FLEXIO_SHIFTBUFBBS */
|
|
#define FLEXIO_SHIFTBUFBBS_COUNT (4U)
|
|
|
|
/*! @name TIMCTL - Timer Control N Register */
|
|
/*! @{ */
|
|
#define FLEXIO_TIMCTL_TIMOD_MASK (0x3U)
|
|
#define FLEXIO_TIMCTL_TIMOD_SHIFT (0U)
|
|
/*! TIMOD - Timer Mode
|
|
* 0b00..Timer Disabled.
|
|
* 0b01..Dual 8-bit counters baud mode.
|
|
* 0b10..Dual 8-bit counters PWM high mode.
|
|
* 0b11..Single 16-bit counter mode.
|
|
*/
|
|
#define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)
|
|
#define FLEXIO_TIMCTL_PINPOL_MASK (0x80U)
|
|
#define FLEXIO_TIMCTL_PINPOL_SHIFT (7U)
|
|
/*! PINPOL - Timer Pin Polarity
|
|
* 0b0..Pin is active high
|
|
* 0b1..Pin is active low
|
|
*/
|
|
#define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)
|
|
#define FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U)
|
|
#define FLEXIO_TIMCTL_PINSEL_SHIFT (8U)
|
|
#define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK)
|
|
#define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U)
|
|
#define FLEXIO_TIMCTL_PINCFG_SHIFT (16U)
|
|
/*! PINCFG - Timer Pin Configuration
|
|
* 0b00..Timer pin output disabled
|
|
* 0b01..Timer pin open drain or bidirectional output enable
|
|
* 0b10..Timer pin bidirectional output data
|
|
* 0b11..Timer pin output
|
|
*/
|
|
#define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)
|
|
#define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U)
|
|
#define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U)
|
|
/*! TRGSRC - Trigger Source
|
|
* 0b0..External trigger selected
|
|
* 0b1..Internal trigger selected
|
|
*/
|
|
#define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)
|
|
#define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U)
|
|
#define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U)
|
|
/*! TRGPOL - Trigger Polarity
|
|
* 0b0..Trigger active high
|
|
* 0b1..Trigger active low
|
|
*/
|
|
#define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)
|
|
#define FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U)
|
|
#define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U)
|
|
#define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of FLEXIO_TIMCTL */
|
|
#define FLEXIO_TIMCTL_COUNT (4U)
|
|
|
|
/*! @name TIMCFG - Timer Configuration N Register */
|
|
/*! @{ */
|
|
#define FLEXIO_TIMCFG_TSTART_MASK (0x2U)
|
|
#define FLEXIO_TIMCFG_TSTART_SHIFT (1U)
|
|
/*! TSTART - Timer Start Bit
|
|
* 0b0..Start bit disabled
|
|
* 0b1..Start bit enabled
|
|
*/
|
|
#define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)
|
|
#define FLEXIO_TIMCFG_TSTOP_MASK (0x30U)
|
|
#define FLEXIO_TIMCFG_TSTOP_SHIFT (4U)
|
|
/*! TSTOP - Timer Stop Bit
|
|
* 0b00..Stop bit disabled
|
|
* 0b01..Stop bit is enabled on timer compare
|
|
* 0b10..Stop bit is enabled on timer disable
|
|
* 0b11..Stop bit is enabled on timer compare and timer disable
|
|
*/
|
|
#define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)
|
|
#define FLEXIO_TIMCFG_TIMENA_MASK (0x700U)
|
|
#define FLEXIO_TIMCFG_TIMENA_SHIFT (8U)
|
|
/*! TIMENA - Timer Enable
|
|
* 0b000..Timer always enabled
|
|
* 0b001..Timer enabled on Timer N-1 enable
|
|
* 0b010..Timer enabled on Trigger high
|
|
* 0b011..Timer enabled on Trigger high and Pin high
|
|
* 0b100..Timer enabled on Pin rising edge
|
|
* 0b101..Timer enabled on Pin rising edge and Trigger high
|
|
* 0b110..Timer enabled on Trigger rising edge
|
|
* 0b111..Timer enabled on Trigger rising or falling edge
|
|
*/
|
|
#define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)
|
|
#define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U)
|
|
#define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U)
|
|
/*! TIMDIS - Timer Disable
|
|
* 0b000..Timer never disabled
|
|
* 0b001..Timer disabled on Timer N-1 disable
|
|
* 0b010..Timer disabled on Timer compare (upper 8-bits match and decrement)
|
|
* 0b011..Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low
|
|
* 0b100..Timer disabled on Pin rising or falling edge
|
|
* 0b101..Timer disabled on Pin rising or falling edge provided Trigger is high
|
|
* 0b110..Timer disabled on Trigger falling edge
|
|
* 0b111..Reserved
|
|
*/
|
|
#define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)
|
|
#define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U)
|
|
#define FLEXIO_TIMCFG_TIMRST_SHIFT (16U)
|
|
/*! TIMRST - Timer Reset
|
|
* 0b000..Timer never reset
|
|
* 0b001..Reserved
|
|
* 0b010..Timer reset on Timer Pin equal to Timer Output
|
|
* 0b011..Timer reset on Timer Trigger equal to Timer Output
|
|
* 0b100..Timer reset on Timer Pin rising edge
|
|
* 0b101..Reserved
|
|
* 0b110..Timer reset on Trigger rising edge
|
|
* 0b111..Timer reset on Trigger rising or falling edge
|
|
*/
|
|
#define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)
|
|
#define FLEXIO_TIMCFG_TIMDEC_MASK (0x300000U)
|
|
#define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U)
|
|
/*! TIMDEC - Timer Decrement
|
|
* 0b00..Decrement counter on FlexIO clock, Shift clock equals Timer output.
|
|
* 0b01..Decrement counter on Trigger input (both edges), Shift clock equals Timer output.
|
|
* 0b10..Decrement counter on Pin input (both edges), Shift clock equals Pin input.
|
|
* 0b11..Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.
|
|
*/
|
|
#define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)
|
|
#define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U)
|
|
#define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U)
|
|
/*! TIMOUT - Timer Output
|
|
* 0b00..Timer output is logic one when enabled and is not affected by timer reset
|
|
* 0b01..Timer output is logic zero when enabled and is not affected by timer reset
|
|
* 0b10..Timer output is logic one when enabled and on timer reset
|
|
* 0b11..Timer output is logic zero when enabled and on timer reset
|
|
*/
|
|
#define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of FLEXIO_TIMCFG */
|
|
#define FLEXIO_TIMCFG_COUNT (4U)
|
|
|
|
/*! @name TIMCMP - Timer Compare N Register */
|
|
/*! @{ */
|
|
#define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU)
|
|
#define FLEXIO_TIMCMP_CMP_SHIFT (0U)
|
|
#define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of FLEXIO_TIMCMP */
|
|
#define FLEXIO_TIMCMP_COUNT (4U)
|
|
|
|
/*! @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */
|
|
/*! @{ */
|
|
#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU)
|
|
#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U)
|
|
#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of FLEXIO_SHIFTBUFNBS */
|
|
#define FLEXIO_SHIFTBUFNBS_COUNT (4U)
|
|
|
|
/*! @name SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register */
|
|
/*! @{ */
|
|
#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU)
|
|
#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U)
|
|
#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of FLEXIO_SHIFTBUFHWS */
|
|
#define FLEXIO_SHIFTBUFHWS_COUNT (4U)
|
|
|
|
/*! @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */
|
|
/*! @{ */
|
|
#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU)
|
|
#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U)
|
|
#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of FLEXIO_SHIFTBUFNIS */
|
|
#define FLEXIO_SHIFTBUFNIS_COUNT (4U)
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group FLEXIO_Register_Masks */
|
|
|
|
|
|
/* FLEXIO - Peripheral instance base addresses */
|
|
/** Peripheral FLEXIO1 base address */
|
|
#define FLEXIO1_BASE (0x401AC000u)
|
|
/** Peripheral FLEXIO1 base pointer */
|
|
#define FLEXIO1 ((FLEXIO_Type *)FLEXIO1_BASE)
|
|
/** Peripheral FLEXIO2 base address */
|
|
#define FLEXIO2_BASE (0x401B0000u)
|
|
/** Peripheral FLEXIO2 base pointer */
|
|
#define FLEXIO2 ((FLEXIO_Type *)FLEXIO2_BASE)
|
|
/** Array initializer of FLEXIO peripheral base addresses */
|
|
#define FLEXIO_BASE_ADDRS { 0u, FLEXIO1_BASE, FLEXIO2_BASE }
|
|
/** Array initializer of FLEXIO peripheral base pointers */
|
|
#define FLEXIO_BASE_PTRS { (FLEXIO_Type *)0u, FLEXIO1, FLEXIO2 }
|
|
/** Interrupt vectors for the FLEXIO peripheral type */
|
|
#define FLEXIO_IRQS { NotAvail_IRQn, FLEXIO1_IRQn, FLEXIO2_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group FLEXIO_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- FLEXRAM Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup FLEXRAM_Peripheral_Access_Layer FLEXRAM Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** FLEXRAM - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t TCM_CTRL; /**< TCM CRTL Register, offset: 0x0 */
|
|
uint8_t RESERVED_0[12];
|
|
__IO uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0x10 */
|
|
__IO uint32_t INT_STAT_EN; /**< Interrupt Status Enable Register, offset: 0x14 */
|
|
__IO uint32_t INT_SIG_EN; /**< Interrupt Enable Register, offset: 0x18 */
|
|
} FLEXRAM_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- FLEXRAM Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup FLEXRAM_Register_Masks FLEXRAM Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name TCM_CTRL - TCM CRTL Register */
|
|
/*! @{ */
|
|
#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK (0x1U)
|
|
#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT (0U)
|
|
/*! TCM_WWAIT_EN - TCM Write Wait Mode Enable
|
|
* 0b0..TCM write fast mode: Write RAM accesses are expected to be finished in 1-cycle.
|
|
* 0b1..TCM write wait mode: Write RAM accesses are expected to be finished in 2-cycles.
|
|
*/
|
|
#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK)
|
|
#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK (0x2U)
|
|
#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT (1U)
|
|
/*! TCM_RWAIT_EN - TCM Read Wait Mode Enable
|
|
* 0b0..TCM read fast mode: Read RAM accesses are expected to be finished in 1-cycle.
|
|
* 0b1..TCM read wait mode: Read RAM accesses are expected to be finished in 2-cycles.
|
|
*/
|
|
#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK)
|
|
#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK (0x4U)
|
|
#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT (2U)
|
|
#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT)) & FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name INT_STATUS - Interrupt Status Register */
|
|
/*! @{ */
|
|
#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK (0x8U)
|
|
#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT (3U)
|
|
/*! ITCM_ERR_STATUS - ITCM Access Error Status
|
|
* 0b0..ITCM access error does not happen
|
|
* 0b1..ITCM access error happens.
|
|
*/
|
|
#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK)
|
|
#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK (0x10U)
|
|
#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT (4U)
|
|
/*! DTCM_ERR_STATUS - DTCM Access Error Status
|
|
* 0b0..DTCM access error does not happen
|
|
* 0b1..DTCM access error happens.
|
|
*/
|
|
#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK)
|
|
#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK (0x20U)
|
|
#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT (5U)
|
|
/*! OCRAM_ERR_STATUS - OCRAM Access Error Status
|
|
* 0b0..OCRAM access error does not happen
|
|
* 0b1..OCRAM access error happens.
|
|
*/
|
|
#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name INT_STAT_EN - Interrupt Status Enable Register */
|
|
/*! @{ */
|
|
#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK (0x8U)
|
|
#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT (3U)
|
|
/*! ITCM_ERR_STAT_EN - ITCM Access Error Status Enable
|
|
* 0b0..Masked
|
|
* 0b1..Enabled
|
|
*/
|
|
#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK)
|
|
#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK (0x10U)
|
|
#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT (4U)
|
|
/*! DTCM_ERR_STAT_EN - DTCM Access Error Status Enable
|
|
* 0b0..Masked
|
|
* 0b1..Enabled
|
|
*/
|
|
#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK)
|
|
#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK (0x20U)
|
|
#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT (5U)
|
|
/*! OCRAM_ERR_STAT_EN - OCRAM Access Error Status Enable
|
|
* 0b0..Masked
|
|
* 0b1..Enabled
|
|
*/
|
|
#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name INT_SIG_EN - Interrupt Enable Register */
|
|
/*! @{ */
|
|
#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK (0x8U)
|
|
#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT (3U)
|
|
/*! ITCM_ERR_SIG_EN - ITCM Access Error Interrupt Enable
|
|
* 0b0..Masked
|
|
* 0b1..Enabled
|
|
*/
|
|
#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK)
|
|
#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK (0x10U)
|
|
#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT (4U)
|
|
/*! DTCM_ERR_SIG_EN - DTCM Access Error Interrupt Enable
|
|
* 0b0..Masked
|
|
* 0b1..Enabled
|
|
*/
|
|
#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK)
|
|
#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK (0x20U)
|
|
#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT (5U)
|
|
/*! OCRAM_ERR_SIG_EN - OCRAM Access Error Interrupt Enable
|
|
* 0b0..Masked
|
|
* 0b1..Enabled
|
|
*/
|
|
#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group FLEXRAM_Register_Masks */
|
|
|
|
|
|
/* FLEXRAM - Peripheral instance base addresses */
|
|
/** Peripheral FLEXRAM base address */
|
|
#define FLEXRAM_BASE (0x400B0000u)
|
|
/** Peripheral FLEXRAM base pointer */
|
|
#define FLEXRAM ((FLEXRAM_Type *)FLEXRAM_BASE)
|
|
/** Array initializer of FLEXRAM peripheral base addresses */
|
|
#define FLEXRAM_BASE_ADDRS { FLEXRAM_BASE }
|
|
/** Array initializer of FLEXRAM peripheral base pointers */
|
|
#define FLEXRAM_BASE_PTRS { FLEXRAM }
|
|
/** Interrupt vectors for the FLEXRAM peripheral type */
|
|
#define FLEXRAM_IRQS { FLEXRAM_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group FLEXRAM_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- FLEXSPI Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup FLEXSPI_Peripheral_Access_Layer FLEXSPI Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** FLEXSPI - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t MCR0; /**< Module Control Register 0, offset: 0x0 */
|
|
__IO uint32_t MCR1; /**< Module Control Register 1, offset: 0x4 */
|
|
__IO uint32_t MCR2; /**< Module Control Register 2, offset: 0x8 */
|
|
__IO uint32_t AHBCR; /**< AHB Bus Control Register, offset: 0xC */
|
|
__IO uint32_t INTEN; /**< Interrupt Enable Register, offset: 0x10 */
|
|
__IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */
|
|
__IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x18 */
|
|
__IO uint32_t LUTCR; /**< LUT Control Register, offset: 0x1C */
|
|
__IO uint32_t AHBRXBUFCR0[4]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0, array offset: 0x20, array step: 0x4 */
|
|
uint8_t RESERVED_0[48];
|
|
__IO uint32_t FLSHCR0[4]; /**< Flash A1 Control Register 0..Flash B2 Control Register 0, array offset: 0x60, array step: 0x4 */
|
|
__IO uint32_t FLSHCR1[4]; /**< Flash A1 Control Register 1..Flash B2 Control Register 1, array offset: 0x70, array step: 0x4 */
|
|
__IO uint32_t FLSHCR2[4]; /**< Flash A1 Control Register 2..Flash B2 Control Register 2, array offset: 0x80, array step: 0x4 */
|
|
uint8_t RESERVED_1[4];
|
|
__IO uint32_t FLSHCR4; /**< Flash Control Register 4, offset: 0x94 */
|
|
uint8_t RESERVED_2[8];
|
|
__IO uint32_t IPCR0; /**< IP Control Register 0, offset: 0xA0 */
|
|
__IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */
|
|
uint8_t RESERVED_3[8];
|
|
__IO uint32_t IPCMD; /**< IP Command Register, offset: 0xB0 */
|
|
uint8_t RESERVED_4[4];
|
|
__IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */
|
|
__IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */
|
|
__IO uint32_t DLLCR[2]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */
|
|
uint8_t RESERVED_5[24];
|
|
__I uint32_t STS0; /**< Status Register 0, offset: 0xE0 */
|
|
__I uint32_t STS1; /**< Status Register 1, offset: 0xE4 */
|
|
__I uint32_t STS2; /**< Status Register 2, offset: 0xE8 */
|
|
__I uint32_t AHBSPNDSTS; /**< AHB Suspend Status Register, offset: 0xEC */
|
|
__I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */
|
|
__I uint32_t IPTXFSTS; /**< IP TX FIFO Status Register, offset: 0xF4 */
|
|
uint8_t RESERVED_6[8];
|
|
__I uint32_t RFDR[32]; /**< IP RX FIFO Data Register 0..IP RX FIFO Data Register 31, array offset: 0x100, array step: 0x4 */
|
|
__O uint32_t TFDR[32]; /**< IP TX FIFO Data Register 0..IP TX FIFO Data Register 31, array offset: 0x180, array step: 0x4 */
|
|
__IO uint32_t LUT[64]; /**< LUT 0..LUT 63, array offset: 0x200, array step: 0x4 */
|
|
} FLEXSPI_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- FLEXSPI Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup FLEXSPI_Register_Masks FLEXSPI Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name MCR0 - Module Control Register 0 */
|
|
/*! @{ */
|
|
#define FLEXSPI_MCR0_SWRESET_MASK (0x1U)
|
|
#define FLEXSPI_MCR0_SWRESET_SHIFT (0U)
|
|
#define FLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK)
|
|
#define FLEXSPI_MCR0_MDIS_MASK (0x2U)
|
|
#define FLEXSPI_MCR0_MDIS_SHIFT (1U)
|
|
#define FLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK)
|
|
#define FLEXSPI_MCR0_RXCLKSRC_MASK (0x30U)
|
|
#define FLEXSPI_MCR0_RXCLKSRC_SHIFT (4U)
|
|
/*! RXCLKSRC - Sample Clock source selection for Flash Reading
|
|
* 0b00..Dummy Read strobe generated by FlexSPI Controller and loopback internally.
|
|
* 0b01..Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad.
|
|
* 0b10..Reserved
|
|
* 0b11..Flash provided Read strobe and input from DQS pad
|
|
*/
|
|
#define FLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK)
|
|
#define FLEXSPI_MCR0_ARDFEN_MASK (0x40U)
|
|
#define FLEXSPI_MCR0_ARDFEN_SHIFT (6U)
|
|
/*! ARDFEN - Enable AHB bus Read Access to IP RX FIFO.
|
|
* 0b0..IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error response.
|
|
* 0b1..IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response.
|
|
*/
|
|
#define FLEXSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK)
|
|
#define FLEXSPI_MCR0_ATDFEN_MASK (0x80U)
|
|
#define FLEXSPI_MCR0_ATDFEN_SHIFT (7U)
|
|
/*! ATDFEN - Enable AHB bus Write Access to IP TX FIFO.
|
|
* 0b0..IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error response.
|
|
* 0b1..IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response.
|
|
*/
|
|
#define FLEXSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK)
|
|
#define FLEXSPI_MCR0_HSEN_MASK (0x800U)
|
|
#define FLEXSPI_MCR0_HSEN_SHIFT (11U)
|
|
/*! HSEN - Half Speed Serial Flash access Enable.
|
|
* 0b0..Disable divide by 2 of serial flash clock for half speed commands.
|
|
* 0b1..Enable divide by 2 of serial flash clock for half speed commands.
|
|
*/
|
|
#define FLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK)
|
|
#define FLEXSPI_MCR0_DOZEEN_MASK (0x1000U)
|
|
#define FLEXSPI_MCR0_DOZEEN_SHIFT (12U)
|
|
/*! DOZEEN - Doze mode enable bit
|
|
* 0b0..Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system.
|
|
* 0b1..Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system.
|
|
*/
|
|
#define FLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK)
|
|
#define FLEXSPI_MCR0_COMBINATIONEN_MASK (0x2000U)
|
|
#define FLEXSPI_MCR0_COMBINATIONEN_SHIFT (13U)
|
|
/*! COMBINATIONEN - This bit is to support Flash Octal mode access by combining Port A and B Data pins (SIOA[3:0] and SIOB[3:0]).
|
|
* 0b0..Disable.
|
|
* 0b1..Enable.
|
|
*/
|
|
#define FLEXSPI_MCR0_COMBINATIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK)
|
|
#define FLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U)
|
|
#define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U)
|
|
/*! SCKFREERUNEN - This bit is used to force SCK output free-running. For FPGA applications, external device may use SCK clock as reference clock to its internal PLL. If SCK free-running is enabled, data sampling with loopback clock from SCK pad is not supported (MCR0[RXCLKSRC]=2).
|
|
* 0b0..Disable.
|
|
* 0b1..Enable.
|
|
*/
|
|
#define FLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK)
|
|
#define FLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U)
|
|
#define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U)
|
|
#define FLEXSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK)
|
|
#define FLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U)
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#define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U)
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#define FLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK)
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/*! @} */
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/*! @name MCR1 - Module Control Register 1 */
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/*! @{ */
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#define FLEXSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU)
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#define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT (0U)
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#define FLEXSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK)
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#define FLEXSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U)
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#define FLEXSPI_MCR1_SEQWAIT_SHIFT (16U)
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#define FLEXSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK)
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/*! @} */
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/*! @name MCR2 - Module Control Register 2 */
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/*! @{ */
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#define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U)
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#define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U)
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/*! CLRAHBBUFOPT - This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned automaticaly when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid.
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* 0b0..AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK.
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* 0b1..AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK.
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*/
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#define FLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK)
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#define FLEXSPI_MCR2_CLRLEARNPHASE_MASK (0x4000U)
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#define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT (14U)
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#define FLEXSPI_MCR2_CLRLEARNPHASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK)
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#define FLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U)
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#define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U)
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/*! SAMEDEVICEEN - All external devices are same devices (both in types and size) for A1/A2/B1/B2.
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* 0b0..In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash A1/A2/B1/B2 seperately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1, FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register settings will be ignored.
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* 0b1..FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored.
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*/
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#define FLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK)
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#define FLEXSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U)
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#define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT (19U)
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/*! SCKBDIFFOPT - SCKB pad can be used as SCKA differential clock output (inverted clock to SCKA). In this case, port B flash access is not available. After change the value of this feild, MCR0[SWRESET] should be set.
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* 0b1..SCKB pad is used as port A SCK inverted clock output (Differential clock to SCKA). Port B flash access is not available.
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* 0b0..SCKB pad is used as port B SCK clock output. Port B flash access is available.
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*/
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#define FLEXSPI_MCR2_SCKBDIFFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK)
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#define FLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U)
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#define FLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U)
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#define FLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK)
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/*! @} */
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/*! @name AHBCR - AHB Bus Control Register */
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|
/*! @{ */
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#define FLEXSPI_AHBCR_APAREN_MASK (0x1U)
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#define FLEXSPI_AHBCR_APAREN_SHIFT (0U)
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/*! APAREN - Parallel mode enabled for AHB triggered Command (both read and write) .
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* 0b0..Flash will be accessed in Individual mode.
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* 0b1..Flash will be accessed in Parallel mode.
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*/
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#define FLEXSPI_AHBCR_APAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK)
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#define FLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U)
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#define FLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U)
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/*! CACHABLEEN - Enable AHB bus cachable read access support.
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* 0b0..Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer.
|
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* 0b1..Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first.
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|
*/
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#define FLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK)
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#define FLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U)
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#define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U)
|
|
/*! BUFFERABLEEN - Enable AHB bus bufferable write access support. This field affects the last beat of AHB write access, refer for more details about AHB bufferable write.
|
|
* 0b0..Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus ready after all data is transmitted to External device and AHB command finished.
|
|
* 0b1..Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is granted by arbitrator and will not wait for AHB command finished.
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|
*/
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|
#define FLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK)
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#define FLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U)
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|
#define FLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U)
|
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#define FLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK)
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#define FLEXSPI_AHBCR_READADDROPT_MASK (0x40U)
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|
#define FLEXSPI_AHBCR_READADDROPT_SHIFT (6U)
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|
/*! READADDROPT - AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation.
|
|
* 0b0..There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is wordaddressable.
|
|
* 0b1..There is no AHB read burst start address alignment limitation. FlexSPI will fetch more datas than AHB burst required to meet the alignment requirement.
|
|
*/
|
|
#define FLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK)
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/*! @} */
|
|
|
|
/*! @name INTEN - Interrupt Enable Register */
|
|
/*! @{ */
|
|
#define FLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U)
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|
#define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U)
|
|
#define FLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK)
|
|
#define FLEXSPI_INTEN_IPCMDGEEN_MASK (0x2U)
|
|
#define FLEXSPI_INTEN_IPCMDGEEN_SHIFT (1U)
|
|
#define FLEXSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK)
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|
#define FLEXSPI_INTEN_AHBCMDGEEN_MASK (0x4U)
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|
#define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT (2U)
|
|
#define FLEXSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK)
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|
#define FLEXSPI_INTEN_IPCMDERREN_MASK (0x8U)
|
|
#define FLEXSPI_INTEN_IPCMDERREN_SHIFT (3U)
|
|
#define FLEXSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK)
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|
#define FLEXSPI_INTEN_AHBCMDERREN_MASK (0x10U)
|
|
#define FLEXSPI_INTEN_AHBCMDERREN_SHIFT (4U)
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|
#define FLEXSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK)
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|
#define FLEXSPI_INTEN_IPRXWAEN_MASK (0x20U)
|
|
#define FLEXSPI_INTEN_IPRXWAEN_SHIFT (5U)
|
|
#define FLEXSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK)
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#define FLEXSPI_INTEN_IPTXWEEN_MASK (0x40U)
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|
#define FLEXSPI_INTEN_IPTXWEEN_SHIFT (6U)
|
|
#define FLEXSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK)
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|
#define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U)
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|
#define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U)
|
|
#define FLEXSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK)
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|
#define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U)
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|
#define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U)
|
|
#define FLEXSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK)
|
|
#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK (0x400U)
|
|
#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT (10U)
|
|
#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK)
|
|
#define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U)
|
|
#define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U)
|
|
#define FLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name INTR - Interrupt Register */
|
|
/*! @{ */
|
|
#define FLEXSPI_INTR_IPCMDDONE_MASK (0x1U)
|
|
#define FLEXSPI_INTR_IPCMDDONE_SHIFT (0U)
|
|
#define FLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK)
|
|
#define FLEXSPI_INTR_IPCMDGE_MASK (0x2U)
|
|
#define FLEXSPI_INTR_IPCMDGE_SHIFT (1U)
|
|
#define FLEXSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK)
|
|
#define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U)
|
|
#define FLEXSPI_INTR_AHBCMDGE_SHIFT (2U)
|
|
#define FLEXSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
|
|
#define FLEXSPI_INTR_IPCMDERR_MASK (0x8U)
|
|
#define FLEXSPI_INTR_IPCMDERR_SHIFT (3U)
|
|
#define FLEXSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK)
|
|
#define FLEXSPI_INTR_AHBCMDERR_MASK (0x10U)
|
|
#define FLEXSPI_INTR_AHBCMDERR_SHIFT (4U)
|
|
#define FLEXSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK)
|
|
#define FLEXSPI_INTR_IPRXWA_MASK (0x20U)
|
|
#define FLEXSPI_INTR_IPRXWA_SHIFT (5U)
|
|
#define FLEXSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK)
|
|
#define FLEXSPI_INTR_IPTXWE_MASK (0x40U)
|
|
#define FLEXSPI_INTR_IPTXWE_SHIFT (6U)
|
|
#define FLEXSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK)
|
|
#define FLEXSPI_INTR_SCKSTOPBYRD_MASK (0x100U)
|
|
#define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT (8U)
|
|
#define FLEXSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK)
|
|
#define FLEXSPI_INTR_SCKSTOPBYWR_MASK (0x200U)
|
|
#define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT (9U)
|
|
#define FLEXSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK)
|
|
#define FLEXSPI_INTR_AHBBUSTIMEOUT_MASK (0x400U)
|
|
#define FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT (10U)
|
|
#define FLEXSPI_INTR_AHBBUSTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK)
|
|
#define FLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U)
|
|
#define FLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U)
|
|
#define FLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name LUTKEY - LUT Key Register */
|
|
/*! @{ */
|
|
#define FLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU)
|
|
#define FLEXSPI_LUTKEY_KEY_SHIFT (0U)
|
|
#define FLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name LUTCR - LUT Control Register */
|
|
/*! @{ */
|
|
#define FLEXSPI_LUTCR_LOCK_MASK (0x1U)
|
|
#define FLEXSPI_LUTCR_LOCK_SHIFT (0U)
|
|
#define FLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK)
|
|
#define FLEXSPI_LUTCR_UNLOCK_MASK (0x2U)
|
|
#define FLEXSPI_LUTCR_UNLOCK_SHIFT (1U)
|
|
#define FLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0 */
|
|
/*! @{ */
|
|
#define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0xFFU)
|
|
#define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U)
|
|
#define FLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK)
|
|
#define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U)
|
|
#define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U)
|
|
#define FLEXSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK)
|
|
#define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x3000000U)
|
|
#define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U)
|
|
#define FLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK)
|
|
#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U)
|
|
#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U)
|
|
#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of FLEXSPI_AHBRXBUFCR0 */
|
|
#define FLEXSPI_AHBRXBUFCR0_COUNT (4U)
|
|
|
|
/*! @name FLSHCR0 - Flash A1 Control Register 0..Flash B2 Control Register 0 */
|
|
/*! @{ */
|
|
#define FLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU)
|
|
#define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U)
|
|
#define FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of FLEXSPI_FLSHCR0 */
|
|
#define FLEXSPI_FLSHCR0_COUNT (4U)
|
|
|
|
/*! @name FLSHCR1 - Flash A1 Control Register 1..Flash B2 Control Register 1 */
|
|
/*! @{ */
|
|
#define FLEXSPI_FLSHCR1_TCSS_MASK (0x1FU)
|
|
#define FLEXSPI_FLSHCR1_TCSS_SHIFT (0U)
|
|
#define FLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK)
|
|
#define FLEXSPI_FLSHCR1_TCSH_MASK (0x3E0U)
|
|
#define FLEXSPI_FLSHCR1_TCSH_SHIFT (5U)
|
|
#define FLEXSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK)
|
|
#define FLEXSPI_FLSHCR1_WA_MASK (0x400U)
|
|
#define FLEXSPI_FLSHCR1_WA_SHIFT (10U)
|
|
#define FLEXSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK)
|
|
#define FLEXSPI_FLSHCR1_CAS_MASK (0x7800U)
|
|
#define FLEXSPI_FLSHCR1_CAS_SHIFT (11U)
|
|
#define FLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK)
|
|
#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U)
|
|
#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U)
|
|
/*! CSINTERVALUNIT - CS interval unit
|
|
* 0b0..The CS interval unit is 1 serial clock cycle
|
|
* 0b1..The CS interval unit is 256 serial clock cycle
|
|
*/
|
|
#define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK)
|
|
#define FLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U)
|
|
#define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U)
|
|
#define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of FLEXSPI_FLSHCR1 */
|
|
#define FLEXSPI_FLSHCR1_COUNT (4U)
|
|
|
|
/*! @name FLSHCR2 - Flash A1 Control Register 2..Flash B2 Control Register 2 */
|
|
/*! @{ */
|
|
#define FLEXSPI_FLSHCR2_ARDSEQID_MASK (0xFU)
|
|
#define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U)
|
|
#define FLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK)
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#define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U)
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#define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U)
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#define FLEXSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
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#define FLEXSPI_FLSHCR2_AWRSEQID_MASK (0xF00U)
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#define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT (8U)
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#define FLEXSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK)
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#define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U)
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#define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U)
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#define FLEXSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK)
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#define FLEXSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U)
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#define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT (16U)
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#define FLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK)
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#define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U)
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#define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U)
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/*! AWRWAITUNIT - AWRWAIT unit
|
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* 0b000..The AWRWAIT unit is 2 ahb clock cycle
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* 0b001..The AWRWAIT unit is 8 ahb clock cycle
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* 0b010..The AWRWAIT unit is 32 ahb clock cycle
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* 0b011..The AWRWAIT unit is 128 ahb clock cycle
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* 0b100..The AWRWAIT unit is 512 ahb clock cycle
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* 0b101..The AWRWAIT unit is 2048 ahb clock cycle
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* 0b110..The AWRWAIT unit is 8192 ahb clock cycle
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* 0b111..The AWRWAIT unit is 32768 ahb clock cycle
|
|
*/
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#define FLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK)
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#define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U)
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#define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U)
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#define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK)
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/*! @} */
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/* The count of FLEXSPI_FLSHCR2 */
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#define FLEXSPI_FLSHCR2_COUNT (4U)
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/*! @name FLSHCR4 - Flash Control Register 4 */
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/*! @{ */
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#define FLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U)
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#define FLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U)
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/*! WMOPT1 - Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation.
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* 0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write burst start address alignment when flash is accessed in individual mode.
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* 0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write burst start address alignment when flash is accessed in individual mode.
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*/
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#define FLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK)
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#define FLEXSPI_FLSHCR4_WMENA_MASK (0x4U)
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#define FLEXSPI_FLSHCR4_WMENA_SHIFT (2U)
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/*! WMENA - Write mask enable bit for flash device on port A. When write mask function is needed for memory device on port A, this bit must be set.
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* 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device.
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* 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
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*/
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#define FLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK)
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#define FLEXSPI_FLSHCR4_WMENB_MASK (0x8U)
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#define FLEXSPI_FLSHCR4_WMENB_SHIFT (3U)
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/*! WMENB - Write mask enable bit for flash device on port B. When write mask function is needed for memory device on port B, this bit must be set.
|
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* 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device.
|
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* 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
|
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*/
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#define FLEXSPI_FLSHCR4_WMENB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK)
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/*! @} */
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/*! @name IPCR0 - IP Control Register 0 */
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/*! @{ */
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#define FLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU)
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#define FLEXSPI_IPCR0_SFAR_SHIFT (0U)
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#define FLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK)
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/*! @} */
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|
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/*! @name IPCR1 - IP Control Register 1 */
|
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/*! @{ */
|
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#define FLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU)
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#define FLEXSPI_IPCR1_IDATSZ_SHIFT (0U)
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#define FLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK)
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#define FLEXSPI_IPCR1_ISEQID_MASK (0xF0000U)
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#define FLEXSPI_IPCR1_ISEQID_SHIFT (16U)
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#define FLEXSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK)
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#define FLEXSPI_IPCR1_ISEQNUM_MASK (0x7000000U)
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#define FLEXSPI_IPCR1_ISEQNUM_SHIFT (24U)
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#define FLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK)
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#define FLEXSPI_IPCR1_IPAREN_MASK (0x80000000U)
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|
#define FLEXSPI_IPCR1_IPAREN_SHIFT (31U)
|
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/*! IPAREN - Parallel mode Enabled for IP command.
|
|
* 0b0..Flash will be accessed in Individual mode.
|
|
* 0b1..Flash will be accessed in Parallel mode.
|
|
*/
|
|
#define FLEXSPI_IPCR1_IPAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK)
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/*! @} */
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|
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/*! @name IPCMD - IP Command Register */
|
|
/*! @{ */
|
|
#define FLEXSPI_IPCMD_TRG_MASK (0x1U)
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#define FLEXSPI_IPCMD_TRG_SHIFT (0U)
|
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#define FLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK)
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|
/*! @} */
|
|
|
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/*! @name IPRXFCR - IP RX FIFO Control Register */
|
|
/*! @{ */
|
|
#define FLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U)
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|
#define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U)
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|
#define FLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK)
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|
#define FLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U)
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|
#define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U)
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|
/*! RXDMAEN - IP RX FIFO reading by DMA enabled.
|
|
* 0b0..IP RX FIFO would be read by processor.
|
|
* 0b1..IP RX FIFO would be read by DMA.
|
|
*/
|
|
#define FLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK)
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|
#define FLEXSPI_IPRXFCR_RXWMRK_MASK (0x3CU)
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|
#define FLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U)
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|
#define FLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK)
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|
/*! @} */
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|
|
|
/*! @name IPTXFCR - IP TX FIFO Control Register */
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|
/*! @{ */
|
|
#define FLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U)
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#define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U)
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#define FLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK)
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#define FLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U)
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|
#define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U)
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/*! TXDMAEN - IP TX FIFO filling by DMA enabled.
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|
* 0b0..IP TX FIFO would be filled by processor.
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|
* 0b1..IP TX FIFO would be filled by DMA.
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|
*/
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#define FLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK)
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#define FLEXSPI_IPTXFCR_TXWMRK_MASK (0x3CU)
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#define FLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U)
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#define FLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK)
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|
/*! @} */
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|
|
|
/*! @name DLLCR - DLL Control Register 0 */
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|
/*! @{ */
|
|
#define FLEXSPI_DLLCR_DLLEN_MASK (0x1U)
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|
#define FLEXSPI_DLLCR_DLLEN_SHIFT (0U)
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|
#define FLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK)
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#define FLEXSPI_DLLCR_DLLRESET_MASK (0x2U)
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#define FLEXSPI_DLLCR_DLLRESET_SHIFT (1U)
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|
#define FLEXSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK)
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|
#define FLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U)
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|
#define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U)
|
|
#define FLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK)
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#define FLEXSPI_DLLCR_OVRDEN_MASK (0x100U)
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|
#define FLEXSPI_DLLCR_OVRDEN_SHIFT (8U)
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|
#define FLEXSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK)
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|
#define FLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U)
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|
#define FLEXSPI_DLLCR_OVRDVAL_SHIFT (9U)
|
|
#define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of FLEXSPI_DLLCR */
|
|
#define FLEXSPI_DLLCR_COUNT (2U)
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|
|
|
/*! @name STS0 - Status Register 0 */
|
|
/*! @{ */
|
|
#define FLEXSPI_STS0_SEQIDLE_MASK (0x1U)
|
|
#define FLEXSPI_STS0_SEQIDLE_SHIFT (0U)
|
|
#define FLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK)
|
|
#define FLEXSPI_STS0_ARBIDLE_MASK (0x2U)
|
|
#define FLEXSPI_STS0_ARBIDLE_SHIFT (1U)
|
|
#define FLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK)
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|
#define FLEXSPI_STS0_ARBCMDSRC_MASK (0xCU)
|
|
#define FLEXSPI_STS0_ARBCMDSRC_SHIFT (2U)
|
|
/*! ARBCMDSRC - This status field indicates the trigger source of current command sequence granted by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1).
|
|
* 0b00..Triggered by AHB read command (triggered by AHB read).
|
|
* 0b01..Triggered by AHB write command (triggered by AHB Write).
|
|
* 0b10..Triggered by IP command (triggered by setting register bit IPCMD.TRG).
|
|
* 0b11..Triggered by suspended command (resumed).
|
|
*/
|
|
#define FLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name STS1 - Status Register 1 */
|
|
/*! @{ */
|
|
#define FLEXSPI_STS1_AHBCMDERRID_MASK (0xFU)
|
|
#define FLEXSPI_STS1_AHBCMDERRID_SHIFT (0U)
|
|
#define FLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK)
|
|
#define FLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U)
|
|
#define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U)
|
|
/*! AHBCMDERRCODE - Indicates the Error Code when AHB command Error detected. This field will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c).
|
|
* 0b0000..No error.
|
|
* 0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence.
|
|
* 0b0011..There is unknown instruction opcode in the sequence.
|
|
* 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.
|
|
* 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.
|
|
* 0b1110..Sequence execution timeout.
|
|
*/
|
|
#define FLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK)
|
|
#define FLEXSPI_STS1_IPCMDERRID_MASK (0xF0000U)
|
|
#define FLEXSPI_STS1_IPCMDERRID_SHIFT (16U)
|
|
#define FLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK)
|
|
#define FLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U)
|
|
#define FLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U)
|
|
/*! IPCMDERRCODE - Indicates the Error Code when IP command Error detected. This field will be cleared when INTR[IPCMDERR] is write-1-clear(w1c).
|
|
* 0b0000..No error.
|
|
* 0b0010..IP command with JMP_ON_CS instruction used in the sequence.
|
|
* 0b0011..There is unknown instruction opcode in the sequence.
|
|
* 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.
|
|
* 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.
|
|
* 0b0110..Flash access start address exceed the whole flash address range (A1/A2/B1/B2).
|
|
* 0b1110..Sequence execution timeout.
|
|
* 0b1111..Flash boundary crossed.
|
|
*/
|
|
#define FLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name STS2 - Status Register 2 */
|
|
/*! @{ */
|
|
#define FLEXSPI_STS2_ASLVLOCK_MASK (0x1U)
|
|
#define FLEXSPI_STS2_ASLVLOCK_SHIFT (0U)
|
|
#define FLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK)
|
|
#define FLEXSPI_STS2_AREFLOCK_MASK (0x2U)
|
|
#define FLEXSPI_STS2_AREFLOCK_SHIFT (1U)
|
|
#define FLEXSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK)
|
|
#define FLEXSPI_STS2_ASLVSEL_MASK (0xFCU)
|
|
#define FLEXSPI_STS2_ASLVSEL_SHIFT (2U)
|
|
#define FLEXSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK)
|
|
#define FLEXSPI_STS2_AREFSEL_MASK (0x3F00U)
|
|
#define FLEXSPI_STS2_AREFSEL_SHIFT (8U)
|
|
#define FLEXSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK)
|
|
#define FLEXSPI_STS2_BSLVLOCK_MASK (0x10000U)
|
|
#define FLEXSPI_STS2_BSLVLOCK_SHIFT (16U)
|
|
#define FLEXSPI_STS2_BSLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK)
|
|
#define FLEXSPI_STS2_BREFLOCK_MASK (0x20000U)
|
|
#define FLEXSPI_STS2_BREFLOCK_SHIFT (17U)
|
|
#define FLEXSPI_STS2_BREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK)
|
|
#define FLEXSPI_STS2_BSLVSEL_MASK (0xFC0000U)
|
|
#define FLEXSPI_STS2_BSLVSEL_SHIFT (18U)
|
|
#define FLEXSPI_STS2_BSLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK)
|
|
#define FLEXSPI_STS2_BREFSEL_MASK (0x3F000000U)
|
|
#define FLEXSPI_STS2_BREFSEL_SHIFT (24U)
|
|
#define FLEXSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name AHBSPNDSTS - AHB Suspend Status Register */
|
|
/*! @{ */
|
|
#define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U)
|
|
#define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U)
|
|
#define FLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK)
|
|
#define FLEXSPI_AHBSPNDSTS_BUFID_MASK (0xEU)
|
|
#define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT (1U)
|
|
#define FLEXSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK)
|
|
#define FLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U)
|
|
#define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U)
|
|
#define FLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name IPRXFSTS - IP RX FIFO Status Register */
|
|
/*! @{ */
|
|
#define FLEXSPI_IPRXFSTS_FILL_MASK (0xFFU)
|
|
#define FLEXSPI_IPRXFSTS_FILL_SHIFT (0U)
|
|
#define FLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK)
|
|
#define FLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U)
|
|
#define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U)
|
|
#define FLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name IPTXFSTS - IP TX FIFO Status Register */
|
|
/*! @{ */
|
|
#define FLEXSPI_IPTXFSTS_FILL_MASK (0xFFU)
|
|
#define FLEXSPI_IPTXFSTS_FILL_SHIFT (0U)
|
|
#define FLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK)
|
|
#define FLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U)
|
|
#define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U)
|
|
#define FLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31 */
|
|
/*! @{ */
|
|
#define FLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU)
|
|
#define FLEXSPI_RFDR_RXDATA_SHIFT (0U)
|
|
#define FLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of FLEXSPI_RFDR */
|
|
#define FLEXSPI_RFDR_COUNT (32U)
|
|
|
|
/*! @name TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31 */
|
|
/*! @{ */
|
|
#define FLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU)
|
|
#define FLEXSPI_TFDR_TXDATA_SHIFT (0U)
|
|
#define FLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of FLEXSPI_TFDR */
|
|
#define FLEXSPI_TFDR_COUNT (32U)
|
|
|
|
/*! @name LUT - LUT 0..LUT 63 */
|
|
/*! @{ */
|
|
#define FLEXSPI_LUT_OPERAND0_MASK (0xFFU)
|
|
#define FLEXSPI_LUT_OPERAND0_SHIFT (0U)
|
|
#define FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK)
|
|
#define FLEXSPI_LUT_NUM_PADS0_MASK (0x300U)
|
|
#define FLEXSPI_LUT_NUM_PADS0_SHIFT (8U)
|
|
#define FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK)
|
|
#define FLEXSPI_LUT_OPCODE0_MASK (0xFC00U)
|
|
#define FLEXSPI_LUT_OPCODE0_SHIFT (10U)
|
|
#define FLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK)
|
|
#define FLEXSPI_LUT_OPERAND1_MASK (0xFF0000U)
|
|
#define FLEXSPI_LUT_OPERAND1_SHIFT (16U)
|
|
#define FLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK)
|
|
#define FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U)
|
|
#define FLEXSPI_LUT_NUM_PADS1_SHIFT (24U)
|
|
#define FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK)
|
|
#define FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U)
|
|
#define FLEXSPI_LUT_OPCODE1_SHIFT (26U)
|
|
#define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of FLEXSPI_LUT */
|
|
#define FLEXSPI_LUT_COUNT (64U)
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group FLEXSPI_Register_Masks */
|
|
|
|
|
|
/* FLEXSPI - Peripheral instance base addresses */
|
|
/** Peripheral FLEXSPI base address */
|
|
#define FLEXSPI_BASE (0x402A8000u)
|
|
/** Peripheral FLEXSPI base pointer */
|
|
#define FLEXSPI ((FLEXSPI_Type *)FLEXSPI_BASE)
|
|
/** Array initializer of FLEXSPI peripheral base addresses */
|
|
#define FLEXSPI_BASE_ADDRS { FLEXSPI_BASE }
|
|
/** Array initializer of FLEXSPI peripheral base pointers */
|
|
#define FLEXSPI_BASE_PTRS { FLEXSPI }
|
|
/** Interrupt vectors for the FLEXSPI peripheral type */
|
|
#define FLEXSPI_IRQS { FLEXSPI_IRQn }
|
|
/* FlexSPI AMBA address. */
|
|
#define FlexSPI_AMBA_BASE (0x60000000U)
|
|
/* FlexSPI ASFM address. */
|
|
#define FlexSPI_ASFM_BASE (0x00000000U)
|
|
/* Base Address of AHB address space mapped to IP RX FIFO. */
|
|
#define FlexSPI_ARDF_BASE (0x7FC00000U)
|
|
/* Base Address of AHB address space mapped to IP TX FIFO. */
|
|
#define FlexSPI_ATDF_BASE (0x7F800000U)
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group FLEXSPI_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- GPC Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup GPC_Peripheral_Access_Layer GPC Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** GPC - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t CNTR; /**< GPC Interface control register, offset: 0x0 */
|
|
uint8_t RESERVED_0[4];
|
|
__IO uint32_t IMR[4]; /**< IRQ masking register 1..IRQ masking register 4, array offset: 0x8, array step: 0x4 */
|
|
__I uint32_t ISR[4]; /**< IRQ status resister 1..IRQ status resister 4, array offset: 0x18, array step: 0x4 */
|
|
uint8_t RESERVED_1[12];
|
|
__IO uint32_t IMR5; /**< IRQ masking register 5, offset: 0x34 */
|
|
__I uint32_t ISR5; /**< IRQ status resister 5, offset: 0x38 */
|
|
} GPC_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- GPC Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup GPC_Register_Masks GPC Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name CNTR - GPC Interface control register */
|
|
/*! @{ */
|
|
#define GPC_CNTR_MEGA_PDN_REQ_MASK (0x4U)
|
|
#define GPC_CNTR_MEGA_PDN_REQ_SHIFT (2U)
|
|
/*! MEGA_PDN_REQ
|
|
* 0b0..No Request
|
|
* 0b1..Request power down sequence
|
|
*/
|
|
#define GPC_CNTR_MEGA_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PDN_REQ_SHIFT)) & GPC_CNTR_MEGA_PDN_REQ_MASK)
|
|
#define GPC_CNTR_MEGA_PUP_REQ_MASK (0x8U)
|
|
#define GPC_CNTR_MEGA_PUP_REQ_SHIFT (3U)
|
|
/*! MEGA_PUP_REQ
|
|
* 0b0..No Request
|
|
* 0b1..Request power up sequence
|
|
*/
|
|
#define GPC_CNTR_MEGA_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PUP_REQ_SHIFT)) & GPC_CNTR_MEGA_PUP_REQ_MASK)
|
|
#define GPC_CNTR_PDRAM0_PGE_MASK (0x400000U)
|
|
#define GPC_CNTR_PDRAM0_PGE_SHIFT (22U)
|
|
/*! PDRAM0_PGE
|
|
* 0b1..FlexRAM PDRAM0 domain (bank1-7) will be power down once when CPU core is power down.
|
|
* 0b0..FlexRAM PDRAM0 domain (bank1-7) will keep power on even if CPU core is power down.
|
|
*/
|
|
#define GPC_CNTR_PDRAM0_PGE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_PDRAM0_PGE_SHIFT)) & GPC_CNTR_PDRAM0_PGE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name IMR - IRQ masking register 1..IRQ masking register 4 */
|
|
/*! @{ */
|
|
#define GPC_IMR_IMR1_MASK (0xFFFFFFFFU)
|
|
#define GPC_IMR_IMR1_SHIFT (0U)
|
|
#define GPC_IMR_IMR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK)
|
|
#define GPC_IMR_IMR2_MASK (0xFFFFFFFFU)
|
|
#define GPC_IMR_IMR2_SHIFT (0U)
|
|
#define GPC_IMR_IMR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR2_SHIFT)) & GPC_IMR_IMR2_MASK)
|
|
#define GPC_IMR_IMR3_MASK (0xFFFFFFFFU)
|
|
#define GPC_IMR_IMR3_SHIFT (0U)
|
|
#define GPC_IMR_IMR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR3_SHIFT)) & GPC_IMR_IMR3_MASK)
|
|
#define GPC_IMR_IMR4_MASK (0xFFFFFFFFU)
|
|
#define GPC_IMR_IMR4_SHIFT (0U)
|
|
#define GPC_IMR_IMR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of GPC_IMR */
|
|
#define GPC_IMR_COUNT (4U)
|
|
|
|
/*! @name ISR - IRQ status resister 1..IRQ status resister 4 */
|
|
/*! @{ */
|
|
#define GPC_ISR_ISR1_MASK (0xFFFFFFFFU)
|
|
#define GPC_ISR_ISR1_SHIFT (0U)
|
|
#define GPC_ISR_ISR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR1_SHIFT)) & GPC_ISR_ISR1_MASK)
|
|
#define GPC_ISR_ISR2_MASK (0xFFFFFFFFU)
|
|
#define GPC_ISR_ISR2_SHIFT (0U)
|
|
#define GPC_ISR_ISR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR2_SHIFT)) & GPC_ISR_ISR2_MASK)
|
|
#define GPC_ISR_ISR3_MASK (0xFFFFFFFFU)
|
|
#define GPC_ISR_ISR3_SHIFT (0U)
|
|
#define GPC_ISR_ISR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR3_SHIFT)) & GPC_ISR_ISR3_MASK)
|
|
#define GPC_ISR_ISR4_MASK (0xFFFFFFFFU)
|
|
#define GPC_ISR_ISR4_SHIFT (0U)
|
|
#define GPC_ISR_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR4_SHIFT)) & GPC_ISR_ISR4_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of GPC_ISR */
|
|
#define GPC_ISR_COUNT (4U)
|
|
|
|
/*! @name IMR5 - IRQ masking register 5 */
|
|
/*! @{ */
|
|
#define GPC_IMR5_IMR5_MASK (0xFFFFFFFFU)
|
|
#define GPC_IMR5_IMR5_SHIFT (0U)
|
|
#define GPC_IMR5_IMR5(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR5_IMR5_SHIFT)) & GPC_IMR5_IMR5_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ISR5 - IRQ status resister 5 */
|
|
/*! @{ */
|
|
#define GPC_ISR5_ISR4_MASK (0xFFFFFFFFU)
|
|
#define GPC_ISR5_ISR4_SHIFT (0U)
|
|
#define GPC_ISR5_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR5_ISR4_SHIFT)) & GPC_ISR5_ISR4_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group GPC_Register_Masks */
|
|
|
|
|
|
/* GPC - Peripheral instance base addresses */
|
|
/** Peripheral GPC base address */
|
|
#define GPC_BASE (0x400F4000u)
|
|
/** Peripheral GPC base pointer */
|
|
#define GPC ((GPC_Type *)GPC_BASE)
|
|
/** Array initializer of GPC peripheral base addresses */
|
|
#define GPC_BASE_ADDRS { GPC_BASE }
|
|
/** Array initializer of GPC peripheral base pointers */
|
|
#define GPC_BASE_PTRS { GPC }
|
|
/** Interrupt vectors for the GPC peripheral type */
|
|
#define GPC_IRQS { GPC_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group GPC_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- GPIO Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** GPIO - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t DR; /**< GPIO data register, offset: 0x0 */
|
|
__IO uint32_t GDIR; /**< GPIO direction register, offset: 0x4 */
|
|
__I uint32_t PSR; /**< GPIO pad status register, offset: 0x8 */
|
|
__IO uint32_t ICR1; /**< GPIO interrupt configuration register1, offset: 0xC */
|
|
__IO uint32_t ICR2; /**< GPIO interrupt configuration register2, offset: 0x10 */
|
|
__IO uint32_t IMR; /**< GPIO interrupt mask register, offset: 0x14 */
|
|
__IO uint32_t ISR; /**< GPIO interrupt status register, offset: 0x18 */
|
|
__IO uint32_t EDGE_SEL; /**< GPIO edge select register, offset: 0x1C */
|
|
uint8_t RESERVED_0[100];
|
|
__O uint32_t DR_SET; /**< GPIO data register SET, offset: 0x84 */
|
|
__O uint32_t DR_CLEAR; /**< GPIO data register CLEAR, offset: 0x88 */
|
|
__O uint32_t DR_TOGGLE; /**< GPIO data register TOGGLE, offset: 0x8C */
|
|
} GPIO_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- GPIO Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup GPIO_Register_Masks GPIO Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name DR - GPIO data register */
|
|
/*! @{ */
|
|
#define GPIO_DR_DR_MASK (0xFFFFFFFFU)
|
|
#define GPIO_DR_DR_SHIFT (0U)
|
|
#define GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GDIR - GPIO direction register */
|
|
/*! @{ */
|
|
#define GPIO_GDIR_GDIR_MASK (0xFFFFFFFFU)
|
|
#define GPIO_GDIR_GDIR_SHIFT (0U)
|
|
#define GPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PSR - GPIO pad status register */
|
|
/*! @{ */
|
|
#define GPIO_PSR_PSR_MASK (0xFFFFFFFFU)
|
|
#define GPIO_PSR_PSR_SHIFT (0U)
|
|
#define GPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ICR1 - GPIO interrupt configuration register1 */
|
|
/*! @{ */
|
|
#define GPIO_ICR1_ICR0_MASK (0x3U)
|
|
#define GPIO_ICR1_ICR0_SHIFT (0U)
|
|
/*! ICR0 - ICR0
|
|
* 0b00..Interrupt n is low-level sensitive.
|
|
* 0b01..Interrupt n is high-level sensitive.
|
|
* 0b10..Interrupt n is rising-edge sensitive.
|
|
* 0b11..Interrupt n is falling-edge sensitive.
|
|
*/
|
|
#define GPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
|
|
#define GPIO_ICR1_ICR1_MASK (0xCU)
|
|
#define GPIO_ICR1_ICR1_SHIFT (2U)
|
|
/*! ICR1 - ICR1
|
|
* 0b00..Interrupt n is low-level sensitive.
|
|
* 0b01..Interrupt n is high-level sensitive.
|
|
* 0b10..Interrupt n is rising-edge sensitive.
|
|
* 0b11..Interrupt n is falling-edge sensitive.
|
|
*/
|
|
#define GPIO_ICR1_ICR1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK)
|
|
#define GPIO_ICR1_ICR2_MASK (0x30U)
|
|
#define GPIO_ICR1_ICR2_SHIFT (4U)
|
|
/*! ICR2 - ICR2
|
|
* 0b00..Interrupt n is low-level sensitive.
|
|
* 0b01..Interrupt n is high-level sensitive.
|
|
* 0b10..Interrupt n is rising-edge sensitive.
|
|
* 0b11..Interrupt n is falling-edge sensitive.
|
|
*/
|
|
#define GPIO_ICR1_ICR2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK)
|
|
#define GPIO_ICR1_ICR3_MASK (0xC0U)
|
|
#define GPIO_ICR1_ICR3_SHIFT (6U)
|
|
/*! ICR3 - ICR3
|
|
* 0b00..Interrupt n is low-level sensitive.
|
|
* 0b01..Interrupt n is high-level sensitive.
|
|
* 0b10..Interrupt n is rising-edge sensitive.
|
|
* 0b11..Interrupt n is falling-edge sensitive.
|
|
*/
|
|
#define GPIO_ICR1_ICR3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK)
|
|
#define GPIO_ICR1_ICR4_MASK (0x300U)
|
|
#define GPIO_ICR1_ICR4_SHIFT (8U)
|
|
/*! ICR4 - ICR4
|
|
* 0b00..Interrupt n is low-level sensitive.
|
|
* 0b01..Interrupt n is high-level sensitive.
|
|
* 0b10..Interrupt n is rising-edge sensitive.
|
|
* 0b11..Interrupt n is falling-edge sensitive.
|
|
*/
|
|
#define GPIO_ICR1_ICR4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK)
|
|
#define GPIO_ICR1_ICR5_MASK (0xC00U)
|
|
#define GPIO_ICR1_ICR5_SHIFT (10U)
|
|
/*! ICR5 - ICR5
|
|
* 0b00..Interrupt n is low-level sensitive.
|
|
* 0b01..Interrupt n is high-level sensitive.
|
|
* 0b10..Interrupt n is rising-edge sensitive.
|
|
* 0b11..Interrupt n is falling-edge sensitive.
|
|
*/
|
|
#define GPIO_ICR1_ICR5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK)
|
|
#define GPIO_ICR1_ICR6_MASK (0x3000U)
|
|
#define GPIO_ICR1_ICR6_SHIFT (12U)
|
|
/*! ICR6 - ICR6
|
|
* 0b00..Interrupt n is low-level sensitive.
|
|
* 0b01..Interrupt n is high-level sensitive.
|
|
* 0b10..Interrupt n is rising-edge sensitive.
|
|
* 0b11..Interrupt n is falling-edge sensitive.
|
|
*/
|
|
#define GPIO_ICR1_ICR6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK)
|
|
#define GPIO_ICR1_ICR7_MASK (0xC000U)
|
|
#define GPIO_ICR1_ICR7_SHIFT (14U)
|
|
/*! ICR7 - ICR7
|
|
* 0b00..Interrupt n is low-level sensitive.
|
|
* 0b01..Interrupt n is high-level sensitive.
|
|
* 0b10..Interrupt n is rising-edge sensitive.
|
|
* 0b11..Interrupt n is falling-edge sensitive.
|
|
*/
|
|
#define GPIO_ICR1_ICR7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK)
|
|
#define GPIO_ICR1_ICR8_MASK (0x30000U)
|
|
#define GPIO_ICR1_ICR8_SHIFT (16U)
|
|
/*! ICR8 - ICR8
|
|
* 0b00..Interrupt n is low-level sensitive.
|
|
* 0b01..Interrupt n is high-level sensitive.
|
|
* 0b10..Interrupt n is rising-edge sensitive.
|
|
* 0b11..Interrupt n is falling-edge sensitive.
|
|
*/
|
|
#define GPIO_ICR1_ICR8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK)
|
|
#define GPIO_ICR1_ICR9_MASK (0xC0000U)
|
|
#define GPIO_ICR1_ICR9_SHIFT (18U)
|
|
/*! ICR9 - ICR9
|
|
* 0b00..Interrupt n is low-level sensitive.
|
|
* 0b01..Interrupt n is high-level sensitive.
|
|
* 0b10..Interrupt n is rising-edge sensitive.
|
|
* 0b11..Interrupt n is falling-edge sensitive.
|
|
*/
|
|
#define GPIO_ICR1_ICR9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK)
|
|
#define GPIO_ICR1_ICR10_MASK (0x300000U)
|
|
#define GPIO_ICR1_ICR10_SHIFT (20U)
|
|
/*! ICR10 - ICR10
|
|
* 0b00..Interrupt n is low-level sensitive.
|
|
* 0b01..Interrupt n is high-level sensitive.
|
|
* 0b10..Interrupt n is rising-edge sensitive.
|
|
* 0b11..Interrupt n is falling-edge sensitive.
|
|
*/
|
|
#define GPIO_ICR1_ICR10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK)
|
|
#define GPIO_ICR1_ICR11_MASK (0xC00000U)
|
|
#define GPIO_ICR1_ICR11_SHIFT (22U)
|
|
/*! ICR11 - ICR11
|
|
* 0b00..Interrupt n is low-level sensitive.
|
|
* 0b01..Interrupt n is high-level sensitive.
|
|
* 0b10..Interrupt n is rising-edge sensitive.
|
|
* 0b11..Interrupt n is falling-edge sensitive.
|
|
*/
|
|
#define GPIO_ICR1_ICR11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK)
|
|
#define GPIO_ICR1_ICR12_MASK (0x3000000U)
|
|
#define GPIO_ICR1_ICR12_SHIFT (24U)
|
|
/*! ICR12 - ICR12
|
|
* 0b00..Interrupt n is low-level sensitive.
|
|
* 0b01..Interrupt n is high-level sensitive.
|
|
* 0b10..Interrupt n is rising-edge sensitive.
|
|
* 0b11..Interrupt n is falling-edge sensitive.
|
|
*/
|
|
#define GPIO_ICR1_ICR12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK)
|
|
#define GPIO_ICR1_ICR13_MASK (0xC000000U)
|
|
#define GPIO_ICR1_ICR13_SHIFT (26U)
|
|
/*! ICR13 - ICR13
|
|
* 0b00..Interrupt n is low-level sensitive.
|
|
* 0b01..Interrupt n is high-level sensitive.
|
|
* 0b10..Interrupt n is rising-edge sensitive.
|
|
* 0b11..Interrupt n is falling-edge sensitive.
|
|
*/
|
|
#define GPIO_ICR1_ICR13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK)
|
|
#define GPIO_ICR1_ICR14_MASK (0x30000000U)
|
|
#define GPIO_ICR1_ICR14_SHIFT (28U)
|
|
/*! ICR14 - ICR14
|
|
* 0b00..Interrupt n is low-level sensitive.
|
|
* 0b01..Interrupt n is high-level sensitive.
|
|
* 0b10..Interrupt n is rising-edge sensitive.
|
|
* 0b11..Interrupt n is falling-edge sensitive.
|
|
*/
|
|
#define GPIO_ICR1_ICR14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK)
|
|
#define GPIO_ICR1_ICR15_MASK (0xC0000000U)
|
|
#define GPIO_ICR1_ICR15_SHIFT (30U)
|
|
/*! ICR15 - ICR15
|
|
* 0b00..Interrupt n is low-level sensitive.
|
|
* 0b01..Interrupt n is high-level sensitive.
|
|
* 0b10..Interrupt n is rising-edge sensitive.
|
|
* 0b11..Interrupt n is falling-edge sensitive.
|
|
*/
|
|
#define GPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ICR2 - GPIO interrupt configuration register2 */
|
|
/*! @{ */
|
|
#define GPIO_ICR2_ICR16_MASK (0x3U)
|
|
#define GPIO_ICR2_ICR16_SHIFT (0U)
|
|
/*! ICR16 - ICR16
|
|
* 0b00..Interrupt n is low-level sensitive.
|
|
* 0b01..Interrupt n is high-level sensitive.
|
|
* 0b10..Interrupt n is rising-edge sensitive.
|
|
* 0b11..Interrupt n is falling-edge sensitive.
|
|
*/
|
|
#define GPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK)
|
|
#define GPIO_ICR2_ICR17_MASK (0xCU)
|
|
#define GPIO_ICR2_ICR17_SHIFT (2U)
|
|
/*! ICR17 - ICR17
|
|
* 0b00..Interrupt n is low-level sensitive.
|
|
* 0b01..Interrupt n is high-level sensitive.
|
|
* 0b10..Interrupt n is rising-edge sensitive.
|
|
* 0b11..Interrupt n is falling-edge sensitive.
|
|
*/
|
|
#define GPIO_ICR2_ICR17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK)
|
|
#define GPIO_ICR2_ICR18_MASK (0x30U)
|
|
#define GPIO_ICR2_ICR18_SHIFT (4U)
|
|
/*! ICR18 - ICR18
|
|
* 0b00..Interrupt n is low-level sensitive.
|
|
* 0b01..Interrupt n is high-level sensitive.
|
|
* 0b10..Interrupt n is rising-edge sensitive.
|
|
* 0b11..Interrupt n is falling-edge sensitive.
|
|
*/
|
|
#define GPIO_ICR2_ICR18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK)
|
|
#define GPIO_ICR2_ICR19_MASK (0xC0U)
|
|
#define GPIO_ICR2_ICR19_SHIFT (6U)
|
|
/*! ICR19 - ICR19
|
|
* 0b00..Interrupt n is low-level sensitive.
|
|
* 0b01..Interrupt n is high-level sensitive.
|
|
* 0b10..Interrupt n is rising-edge sensitive.
|
|
* 0b11..Interrupt n is falling-edge sensitive.
|
|
*/
|
|
#define GPIO_ICR2_ICR19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK)
|
|
#define GPIO_ICR2_ICR20_MASK (0x300U)
|
|
#define GPIO_ICR2_ICR20_SHIFT (8U)
|
|
/*! ICR20 - ICR20
|
|
* 0b00..Interrupt n is low-level sensitive.
|
|
* 0b01..Interrupt n is high-level sensitive.
|
|
* 0b10..Interrupt n is rising-edge sensitive.
|
|
* 0b11..Interrupt n is falling-edge sensitive.
|
|
*/
|
|
#define GPIO_ICR2_ICR20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK)
|
|
#define GPIO_ICR2_ICR21_MASK (0xC00U)
|
|
#define GPIO_ICR2_ICR21_SHIFT (10U)
|
|
/*! ICR21 - ICR21
|
|
* 0b00..Interrupt n is low-level sensitive.
|
|
* 0b01..Interrupt n is high-level sensitive.
|
|
* 0b10..Interrupt n is rising-edge sensitive.
|
|
* 0b11..Interrupt n is falling-edge sensitive.
|
|
*/
|
|
#define GPIO_ICR2_ICR21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK)
|
|
#define GPIO_ICR2_ICR22_MASK (0x3000U)
|
|
#define GPIO_ICR2_ICR22_SHIFT (12U)
|
|
/*! ICR22 - ICR22
|
|
* 0b00..Interrupt n is low-level sensitive.
|
|
* 0b01..Interrupt n is high-level sensitive.
|
|
* 0b10..Interrupt n is rising-edge sensitive.
|
|
* 0b11..Interrupt n is falling-edge sensitive.
|
|
*/
|
|
#define GPIO_ICR2_ICR22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK)
|
|
#define GPIO_ICR2_ICR23_MASK (0xC000U)
|
|
#define GPIO_ICR2_ICR23_SHIFT (14U)
|
|
/*! ICR23 - ICR23
|
|
* 0b00..Interrupt n is low-level sensitive.
|
|
* 0b01..Interrupt n is high-level sensitive.
|
|
* 0b10..Interrupt n is rising-edge sensitive.
|
|
* 0b11..Interrupt n is falling-edge sensitive.
|
|
*/
|
|
#define GPIO_ICR2_ICR23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK)
|
|
#define GPIO_ICR2_ICR24_MASK (0x30000U)
|
|
#define GPIO_ICR2_ICR24_SHIFT (16U)
|
|
/*! ICR24 - ICR24
|
|
* 0b00..Interrupt n is low-level sensitive.
|
|
* 0b01..Interrupt n is high-level sensitive.
|
|
* 0b10..Interrupt n is rising-edge sensitive.
|
|
* 0b11..Interrupt n is falling-edge sensitive.
|
|
*/
|
|
#define GPIO_ICR2_ICR24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK)
|
|
#define GPIO_ICR2_ICR25_MASK (0xC0000U)
|
|
#define GPIO_ICR2_ICR25_SHIFT (18U)
|
|
/*! ICR25 - ICR25
|
|
* 0b00..Interrupt n is low-level sensitive.
|
|
* 0b01..Interrupt n is high-level sensitive.
|
|
* 0b10..Interrupt n is rising-edge sensitive.
|
|
* 0b11..Interrupt n is falling-edge sensitive.
|
|
*/
|
|
#define GPIO_ICR2_ICR25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK)
|
|
#define GPIO_ICR2_ICR26_MASK (0x300000U)
|
|
#define GPIO_ICR2_ICR26_SHIFT (20U)
|
|
/*! ICR26 - ICR26
|
|
* 0b00..Interrupt n is low-level sensitive.
|
|
* 0b01..Interrupt n is high-level sensitive.
|
|
* 0b10..Interrupt n is rising-edge sensitive.
|
|
* 0b11..Interrupt n is falling-edge sensitive.
|
|
*/
|
|
#define GPIO_ICR2_ICR26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK)
|
|
#define GPIO_ICR2_ICR27_MASK (0xC00000U)
|
|
#define GPIO_ICR2_ICR27_SHIFT (22U)
|
|
/*! ICR27 - ICR27
|
|
* 0b00..Interrupt n is low-level sensitive.
|
|
* 0b01..Interrupt n is high-level sensitive.
|
|
* 0b10..Interrupt n is rising-edge sensitive.
|
|
* 0b11..Interrupt n is falling-edge sensitive.
|
|
*/
|
|
#define GPIO_ICR2_ICR27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK)
|
|
#define GPIO_ICR2_ICR28_MASK (0x3000000U)
|
|
#define GPIO_ICR2_ICR28_SHIFT (24U)
|
|
/*! ICR28 - ICR28
|
|
* 0b00..Interrupt n is low-level sensitive.
|
|
* 0b01..Interrupt n is high-level sensitive.
|
|
* 0b10..Interrupt n is rising-edge sensitive.
|
|
* 0b11..Interrupt n is falling-edge sensitive.
|
|
*/
|
|
#define GPIO_ICR2_ICR28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK)
|
|
#define GPIO_ICR2_ICR29_MASK (0xC000000U)
|
|
#define GPIO_ICR2_ICR29_SHIFT (26U)
|
|
/*! ICR29 - ICR29
|
|
* 0b00..Interrupt n is low-level sensitive.
|
|
* 0b01..Interrupt n is high-level sensitive.
|
|
* 0b10..Interrupt n is rising-edge sensitive.
|
|
* 0b11..Interrupt n is falling-edge sensitive.
|
|
*/
|
|
#define GPIO_ICR2_ICR29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK)
|
|
#define GPIO_ICR2_ICR30_MASK (0x30000000U)
|
|
#define GPIO_ICR2_ICR30_SHIFT (28U)
|
|
/*! ICR30 - ICR30
|
|
* 0b00..Interrupt n is low-level sensitive.
|
|
* 0b01..Interrupt n is high-level sensitive.
|
|
* 0b10..Interrupt n is rising-edge sensitive.
|
|
* 0b11..Interrupt n is falling-edge sensitive.
|
|
*/
|
|
#define GPIO_ICR2_ICR30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK)
|
|
#define GPIO_ICR2_ICR31_MASK (0xC0000000U)
|
|
#define GPIO_ICR2_ICR31_SHIFT (30U)
|
|
/*! ICR31 - ICR31
|
|
* 0b00..Interrupt n is low-level sensitive.
|
|
* 0b01..Interrupt n is high-level sensitive.
|
|
* 0b10..Interrupt n is rising-edge sensitive.
|
|
* 0b11..Interrupt n is falling-edge sensitive.
|
|
*/
|
|
#define GPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name IMR - GPIO interrupt mask register */
|
|
/*! @{ */
|
|
#define GPIO_IMR_IMR_MASK (0xFFFFFFFFU)
|
|
#define GPIO_IMR_IMR_SHIFT (0U)
|
|
#define GPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ISR - GPIO interrupt status register */
|
|
/*! @{ */
|
|
#define GPIO_ISR_ISR_MASK (0xFFFFFFFFU)
|
|
#define GPIO_ISR_ISR_SHIFT (0U)
|
|
#define GPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name EDGE_SEL - GPIO edge select register */
|
|
/*! @{ */
|
|
#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK (0xFFFFFFFFU)
|
|
#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT (0U)
|
|
#define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DR_SET - GPIO data register SET */
|
|
/*! @{ */
|
|
#define GPIO_DR_SET_DR_SET_MASK (0xFFFFFFFFU)
|
|
#define GPIO_DR_SET_DR_SET_SHIFT (0U)
|
|
#define GPIO_DR_SET_DR_SET(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_SET_DR_SET_SHIFT)) & GPIO_DR_SET_DR_SET_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DR_CLEAR - GPIO data register CLEAR */
|
|
/*! @{ */
|
|
#define GPIO_DR_CLEAR_DR_CLEAR_MASK (0xFFFFFFFFU)
|
|
#define GPIO_DR_CLEAR_DR_CLEAR_SHIFT (0U)
|
|
#define GPIO_DR_CLEAR_DR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_CLEAR_DR_CLEAR_SHIFT)) & GPIO_DR_CLEAR_DR_CLEAR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DR_TOGGLE - GPIO data register TOGGLE */
|
|
/*! @{ */
|
|
#define GPIO_DR_TOGGLE_DR_TOGGLE_MASK (0xFFFFFFFFU)
|
|
#define GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT (0U)
|
|
#define GPIO_DR_TOGGLE_DR_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT)) & GPIO_DR_TOGGLE_DR_TOGGLE_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group GPIO_Register_Masks */
|
|
|
|
|
|
/* GPIO - Peripheral instance base addresses */
|
|
/** Peripheral GPIO1 base address */
|
|
#define GPIO1_BASE (0x401B8000u)
|
|
/** Peripheral GPIO1 base pointer */
|
|
#define GPIO1 ((GPIO_Type *)GPIO1_BASE)
|
|
/** Peripheral GPIO2 base address */
|
|
#define GPIO2_BASE (0x401BC000u)
|
|
/** Peripheral GPIO2 base pointer */
|
|
#define GPIO2 ((GPIO_Type *)GPIO2_BASE)
|
|
/** Peripheral GPIO3 base address */
|
|
#define GPIO3_BASE (0x401C0000u)
|
|
/** Peripheral GPIO3 base pointer */
|
|
#define GPIO3 ((GPIO_Type *)GPIO3_BASE)
|
|
/** Peripheral GPIO4 base address */
|
|
#define GPIO4_BASE (0x401C4000u)
|
|
/** Peripheral GPIO4 base pointer */
|
|
#define GPIO4 ((GPIO_Type *)GPIO4_BASE)
|
|
/** Peripheral GPIO5 base address */
|
|
#define GPIO5_BASE (0x400C0000u)
|
|
/** Peripheral GPIO5 base pointer */
|
|
#define GPIO5 ((GPIO_Type *)GPIO5_BASE)
|
|
/** Array initializer of GPIO peripheral base addresses */
|
|
#define GPIO_BASE_ADDRS { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE }
|
|
/** Array initializer of GPIO peripheral base pointers */
|
|
#define GPIO_BASE_PTRS { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 }
|
|
/** Interrupt vectors for the GPIO peripheral type */
|
|
#define GPIO_IRQS { NotAvail_IRQn, GPIO1_INT0_IRQn, GPIO1_INT1_IRQn, GPIO1_INT2_IRQn, GPIO1_INT3_IRQn, GPIO1_INT4_IRQn, GPIO1_INT5_IRQn, GPIO1_INT6_IRQn, GPIO1_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }
|
|
#define GPIO_COMBINED_LOW_IRQS { NotAvail_IRQn, GPIO1_Combined_0_15_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_0_15_IRQn, GPIO4_Combined_0_15_IRQn, GPIO5_Combined_0_15_IRQn }
|
|
#define GPIO_COMBINED_HIGH_IRQS { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO3_Combined_16_31_IRQn, GPIO4_Combined_16_31_IRQn, GPIO5_Combined_16_31_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group GPIO_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- GPT Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup GPT_Peripheral_Access_Layer GPT Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** GPT - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t CR; /**< GPT Control Register, offset: 0x0 */
|
|
__IO uint32_t PR; /**< GPT Prescaler Register, offset: 0x4 */
|
|
__IO uint32_t SR; /**< GPT Status Register, offset: 0x8 */
|
|
__IO uint32_t IR; /**< GPT Interrupt Register, offset: 0xC */
|
|
__IO uint32_t OCR[3]; /**< GPT Output Compare Register 1..GPT Output Compare Register 3, array offset: 0x10, array step: 0x4 */
|
|
__I uint32_t ICR[2]; /**< GPT Input Capture Register 1..GPT Input Capture Register 2, array offset: 0x1C, array step: 0x4 */
|
|
__I uint32_t CNT; /**< GPT Counter Register, offset: 0x24 */
|
|
} GPT_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- GPT Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup GPT_Register_Masks GPT Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name CR - GPT Control Register */
|
|
/*! @{ */
|
|
#define GPT_CR_EN_MASK (0x1U)
|
|
#define GPT_CR_EN_SHIFT (0U)
|
|
/*! EN
|
|
* 0b0..GPT is disabled.
|
|
* 0b1..GPT is enabled.
|
|
*/
|
|
#define GPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK)
|
|
#define GPT_CR_ENMOD_MASK (0x2U)
|
|
#define GPT_CR_ENMOD_SHIFT (1U)
|
|
/*! ENMOD
|
|
* 0b0..GPT counter will retain its value when it is disabled.
|
|
* 0b1..GPT counter value is reset to 0 when it is disabled.
|
|
*/
|
|
#define GPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK)
|
|
#define GPT_CR_DBGEN_MASK (0x4U)
|
|
#define GPT_CR_DBGEN_SHIFT (2U)
|
|
/*! DBGEN
|
|
* 0b0..GPT is disabled in debug mode.
|
|
* 0b1..GPT is enabled in debug mode.
|
|
*/
|
|
#define GPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK)
|
|
#define GPT_CR_WAITEN_MASK (0x8U)
|
|
#define GPT_CR_WAITEN_SHIFT (3U)
|
|
/*! WAITEN
|
|
* 0b0..GPT is disabled in wait mode.
|
|
* 0b1..GPT is enabled in wait mode.
|
|
*/
|
|
#define GPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK)
|
|
#define GPT_CR_DOZEEN_MASK (0x10U)
|
|
#define GPT_CR_DOZEEN_SHIFT (4U)
|
|
/*! DOZEEN
|
|
* 0b0..GPT is disabled in doze mode.
|
|
* 0b1..GPT is enabled in doze mode.
|
|
*/
|
|
#define GPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK)
|
|
#define GPT_CR_STOPEN_MASK (0x20U)
|
|
#define GPT_CR_STOPEN_SHIFT (5U)
|
|
/*! STOPEN
|
|
* 0b0..GPT is disabled in Stop mode.
|
|
* 0b1..GPT is enabled in Stop mode.
|
|
*/
|
|
#define GPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK)
|
|
#define GPT_CR_CLKSRC_MASK (0x1C0U)
|
|
#define GPT_CR_CLKSRC_SHIFT (6U)
|
|
/*! CLKSRC
|
|
* 0b000..No clock
|
|
* 0b001..Peripheral Clock (ipg_clk)
|
|
* 0b010..High Frequency Reference Clock (ipg_clk_highfreq)
|
|
* 0b011..External Clock
|
|
* 0b100..Low Frequency Reference Clock (ipg_clk_32k)
|
|
* 0b101..Crystal oscillator as Reference Clock (ipg_clk_24M)
|
|
*/
|
|
#define GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK)
|
|
#define GPT_CR_FRR_MASK (0x200U)
|
|
#define GPT_CR_FRR_SHIFT (9U)
|
|
/*! FRR
|
|
* 0b0..Restart mode
|
|
* 0b1..Free-Run mode
|
|
*/
|
|
#define GPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK)
|
|
#define GPT_CR_EN_24M_MASK (0x400U)
|
|
#define GPT_CR_EN_24M_SHIFT (10U)
|
|
/*! EN_24M
|
|
* 0b0..24M clock disabled
|
|
* 0b1..24M clock enabled
|
|
*/
|
|
#define GPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK)
|
|
#define GPT_CR_SWR_MASK (0x8000U)
|
|
#define GPT_CR_SWR_SHIFT (15U)
|
|
/*! SWR
|
|
* 0b0..GPT is not in reset state
|
|
* 0b1..GPT is in reset state
|
|
*/
|
|
#define GPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK)
|
|
#define GPT_CR_IM1_MASK (0x30000U)
|
|
#define GPT_CR_IM1_SHIFT (16U)
|
|
#define GPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK)
|
|
#define GPT_CR_IM2_MASK (0xC0000U)
|
|
#define GPT_CR_IM2_SHIFT (18U)
|
|
/*! IM2
|
|
* 0b00..capture disabled
|
|
* 0b01..capture on rising edge only
|
|
* 0b10..capture on falling edge only
|
|
* 0b11..capture on both edges
|
|
*/
|
|
#define GPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK)
|
|
#define GPT_CR_OM1_MASK (0x700000U)
|
|
#define GPT_CR_OM1_SHIFT (20U)
|
|
#define GPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK)
|
|
#define GPT_CR_OM2_MASK (0x3800000U)
|
|
#define GPT_CR_OM2_SHIFT (23U)
|
|
#define GPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK)
|
|
#define GPT_CR_OM3_MASK (0x1C000000U)
|
|
#define GPT_CR_OM3_SHIFT (26U)
|
|
/*! OM3
|
|
* 0b000..Output disconnected. No response on pin.
|
|
* 0b001..Toggle output pin
|
|
* 0b010..Clear output pin
|
|
* 0b011..Set output pin
|
|
* 0b1xx..Generate an active low pulse (that is one input clock wide) on the output pin.
|
|
*/
|
|
#define GPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK)
|
|
#define GPT_CR_FO1_MASK (0x20000000U)
|
|
#define GPT_CR_FO1_SHIFT (29U)
|
|
#define GPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK)
|
|
#define GPT_CR_FO2_MASK (0x40000000U)
|
|
#define GPT_CR_FO2_SHIFT (30U)
|
|
#define GPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK)
|
|
#define GPT_CR_FO3_MASK (0x80000000U)
|
|
#define GPT_CR_FO3_SHIFT (31U)
|
|
/*! FO3
|
|
* 0b0..Writing a 0 has no effect.
|
|
* 0b1..Causes the programmed pin action on the timer Output Compare n pin; the OFn flag is not set.
|
|
*/
|
|
#define GPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PR - GPT Prescaler Register */
|
|
/*! @{ */
|
|
#define GPT_PR_PRESCALER_MASK (0xFFFU)
|
|
#define GPT_PR_PRESCALER_SHIFT (0U)
|
|
/*! PRESCALER
|
|
* 0b000000000000..Divide by 1
|
|
* 0b000000000001..Divide by 2
|
|
* 0b111111111111..Divide by 4096
|
|
*/
|
|
#define GPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK)
|
|
#define GPT_PR_PRESCALER24M_MASK (0xF000U)
|
|
#define GPT_PR_PRESCALER24M_SHIFT (12U)
|
|
/*! PRESCALER24M
|
|
* 0b0000..Divide by 1
|
|
* 0b0001..Divide by 2
|
|
* 0b1111..Divide by 16
|
|
*/
|
|
#define GPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SR - GPT Status Register */
|
|
/*! @{ */
|
|
#define GPT_SR_OF1_MASK (0x1U)
|
|
#define GPT_SR_OF1_SHIFT (0U)
|
|
#define GPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK)
|
|
#define GPT_SR_OF2_MASK (0x2U)
|
|
#define GPT_SR_OF2_SHIFT (1U)
|
|
#define GPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK)
|
|
#define GPT_SR_OF3_MASK (0x4U)
|
|
#define GPT_SR_OF3_SHIFT (2U)
|
|
/*! OF3
|
|
* 0b0..Compare event has not occurred.
|
|
* 0b1..Compare event has occurred.
|
|
*/
|
|
#define GPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK)
|
|
#define GPT_SR_IF1_MASK (0x8U)
|
|
#define GPT_SR_IF1_SHIFT (3U)
|
|
#define GPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK)
|
|
#define GPT_SR_IF2_MASK (0x10U)
|
|
#define GPT_SR_IF2_SHIFT (4U)
|
|
/*! IF2
|
|
* 0b0..Capture event has not occurred.
|
|
* 0b1..Capture event has occurred.
|
|
*/
|
|
#define GPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK)
|
|
#define GPT_SR_ROV_MASK (0x20U)
|
|
#define GPT_SR_ROV_SHIFT (5U)
|
|
/*! ROV
|
|
* 0b0..Rollover has not occurred.
|
|
* 0b1..Rollover has occurred.
|
|
*/
|
|
#define GPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name IR - GPT Interrupt Register */
|
|
/*! @{ */
|
|
#define GPT_IR_OF1IE_MASK (0x1U)
|
|
#define GPT_IR_OF1IE_SHIFT (0U)
|
|
#define GPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK)
|
|
#define GPT_IR_OF2IE_MASK (0x2U)
|
|
#define GPT_IR_OF2IE_SHIFT (1U)
|
|
#define GPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK)
|
|
#define GPT_IR_OF3IE_MASK (0x4U)
|
|
#define GPT_IR_OF3IE_SHIFT (2U)
|
|
/*! OF3IE
|
|
* 0b0..Output Compare Channel n interrupt is disabled.
|
|
* 0b1..Output Compare Channel n interrupt is enabled.
|
|
*/
|
|
#define GPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK)
|
|
#define GPT_IR_IF1IE_MASK (0x8U)
|
|
#define GPT_IR_IF1IE_SHIFT (3U)
|
|
#define GPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK)
|
|
#define GPT_IR_IF2IE_MASK (0x10U)
|
|
#define GPT_IR_IF2IE_SHIFT (4U)
|
|
/*! IF2IE
|
|
* 0b0..IF2IE Input Capture n Interrupt Enable is disabled.
|
|
* 0b1..IF2IE Input Capture n Interrupt Enable is enabled.
|
|
*/
|
|
#define GPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK)
|
|
#define GPT_IR_ROVIE_MASK (0x20U)
|
|
#define GPT_IR_ROVIE_SHIFT (5U)
|
|
/*! ROVIE
|
|
* 0b0..Rollover interrupt is disabled.
|
|
* 0b1..Rollover interrupt enabled.
|
|
*/
|
|
#define GPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name OCR - GPT Output Compare Register 1..GPT Output Compare Register 3 */
|
|
/*! @{ */
|
|
#define GPT_OCR_COMP_MASK (0xFFFFFFFFU)
|
|
#define GPT_OCR_COMP_SHIFT (0U)
|
|
#define GPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of GPT_OCR */
|
|
#define GPT_OCR_COUNT (3U)
|
|
|
|
/*! @name ICR - GPT Input Capture Register 1..GPT Input Capture Register 2 */
|
|
/*! @{ */
|
|
#define GPT_ICR_CAPT_MASK (0xFFFFFFFFU)
|
|
#define GPT_ICR_CAPT_SHIFT (0U)
|
|
#define GPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of GPT_ICR */
|
|
#define GPT_ICR_COUNT (2U)
|
|
|
|
/*! @name CNT - GPT Counter Register */
|
|
/*! @{ */
|
|
#define GPT_CNT_COUNT_MASK (0xFFFFFFFFU)
|
|
#define GPT_CNT_COUNT_SHIFT (0U)
|
|
#define GPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group GPT_Register_Masks */
|
|
|
|
|
|
/* GPT - Peripheral instance base addresses */
|
|
/** Peripheral GPT1 base address */
|
|
#define GPT1_BASE (0x401EC000u)
|
|
/** Peripheral GPT1 base pointer */
|
|
#define GPT1 ((GPT_Type *)GPT1_BASE)
|
|
/** Peripheral GPT2 base address */
|
|
#define GPT2_BASE (0x401F0000u)
|
|
/** Peripheral GPT2 base pointer */
|
|
#define GPT2 ((GPT_Type *)GPT2_BASE)
|
|
/** Array initializer of GPT peripheral base addresses */
|
|
#define GPT_BASE_ADDRS { 0u, GPT1_BASE, GPT2_BASE }
|
|
/** Array initializer of GPT peripheral base pointers */
|
|
#define GPT_BASE_PTRS { (GPT_Type *)0u, GPT1, GPT2 }
|
|
/** Interrupt vectors for the GPT peripheral type */
|
|
#define GPT_IRQS { NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group GPT_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- I2S Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** I2S - Register Layout Typedef */
|
|
typedef struct {
|
|
__I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
|
|
__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
|
|
__IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x8 */
|
|
__IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0xC */
|
|
__IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x10 */
|
|
__IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0x14 */
|
|
__IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x18 */
|
|
__IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x1C */
|
|
__O uint32_t TDR[4]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
|
|
uint8_t RESERVED_0[16];
|
|
__I uint32_t TFR[4]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
|
|
uint8_t RESERVED_1[16];
|
|
__IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
|
|
uint8_t RESERVED_2[36];
|
|
__IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x88 */
|
|
__IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x8C */
|
|
__IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x90 */
|
|
__IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x94 */
|
|
__IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x98 */
|
|
__IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x9C */
|
|
__I uint32_t RDR[4]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
|
|
uint8_t RESERVED_3[16];
|
|
__I uint32_t RFR[4]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
|
|
uint8_t RESERVED_4[16];
|
|
__IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
|
|
} I2S_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- I2S Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup I2S_Register_Masks I2S Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name VERID - Version ID Register */
|
|
/*! @{ */
|
|
#define I2S_VERID_FEATURE_MASK (0xFFFFU)
|
|
#define I2S_VERID_FEATURE_SHIFT (0U)
|
|
/*! FEATURE - Feature Specification Number
|
|
* 0b0000000000000000..Standard feature set.
|
|
*/
|
|
#define I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK)
|
|
#define I2S_VERID_MINOR_MASK (0xFF0000U)
|
|
#define I2S_VERID_MINOR_SHIFT (16U)
|
|
#define I2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK)
|
|
#define I2S_VERID_MAJOR_MASK (0xFF000000U)
|
|
#define I2S_VERID_MAJOR_SHIFT (24U)
|
|
#define I2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PARAM - Parameter Register */
|
|
/*! @{ */
|
|
#define I2S_PARAM_DATALINE_MASK (0xFU)
|
|
#define I2S_PARAM_DATALINE_SHIFT (0U)
|
|
#define I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK)
|
|
#define I2S_PARAM_FIFO_MASK (0xF00U)
|
|
#define I2S_PARAM_FIFO_SHIFT (8U)
|
|
#define I2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK)
|
|
#define I2S_PARAM_FRAME_MASK (0xF0000U)
|
|
#define I2S_PARAM_FRAME_SHIFT (16U)
|
|
#define I2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TCSR - SAI Transmit Control Register */
|
|
/*! @{ */
|
|
#define I2S_TCSR_FRDE_MASK (0x1U)
|
|
#define I2S_TCSR_FRDE_SHIFT (0U)
|
|
/*! FRDE - FIFO Request DMA Enable
|
|
* 0b0..Disables the DMA request.
|
|
* 0b1..Enables the DMA request.
|
|
*/
|
|
#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
|
|
#define I2S_TCSR_FWDE_MASK (0x2U)
|
|
#define I2S_TCSR_FWDE_SHIFT (1U)
|
|
/*! FWDE - FIFO Warning DMA Enable
|
|
* 0b0..Disables the DMA request.
|
|
* 0b1..Enables the DMA request.
|
|
*/
|
|
#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
|
|
#define I2S_TCSR_FRIE_MASK (0x100U)
|
|
#define I2S_TCSR_FRIE_SHIFT (8U)
|
|
/*! FRIE - FIFO Request Interrupt Enable
|
|
* 0b0..Disables the interrupt.
|
|
* 0b1..Enables the interrupt.
|
|
*/
|
|
#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
|
|
#define I2S_TCSR_FWIE_MASK (0x200U)
|
|
#define I2S_TCSR_FWIE_SHIFT (9U)
|
|
/*! FWIE - FIFO Warning Interrupt Enable
|
|
* 0b0..Disables the interrupt.
|
|
* 0b1..Enables the interrupt.
|
|
*/
|
|
#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
|
|
#define I2S_TCSR_FEIE_MASK (0x400U)
|
|
#define I2S_TCSR_FEIE_SHIFT (10U)
|
|
/*! FEIE - FIFO Error Interrupt Enable
|
|
* 0b0..Disables the interrupt.
|
|
* 0b1..Enables the interrupt.
|
|
*/
|
|
#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
|
|
#define I2S_TCSR_SEIE_MASK (0x800U)
|
|
#define I2S_TCSR_SEIE_SHIFT (11U)
|
|
/*! SEIE - Sync Error Interrupt Enable
|
|
* 0b0..Disables interrupt.
|
|
* 0b1..Enables interrupt.
|
|
*/
|
|
#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
|
|
#define I2S_TCSR_WSIE_MASK (0x1000U)
|
|
#define I2S_TCSR_WSIE_SHIFT (12U)
|
|
/*! WSIE - Word Start Interrupt Enable
|
|
* 0b0..Disables interrupt.
|
|
* 0b1..Enables interrupt.
|
|
*/
|
|
#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
|
|
#define I2S_TCSR_FRF_MASK (0x10000U)
|
|
#define I2S_TCSR_FRF_SHIFT (16U)
|
|
/*! FRF - FIFO Request Flag
|
|
* 0b0..Transmit FIFO watermark has not been reached.
|
|
* 0b1..Transmit FIFO watermark has been reached.
|
|
*/
|
|
#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
|
|
#define I2S_TCSR_FWF_MASK (0x20000U)
|
|
#define I2S_TCSR_FWF_SHIFT (17U)
|
|
/*! FWF - FIFO Warning Flag
|
|
* 0b0..No enabled transmit FIFO is empty.
|
|
* 0b1..Enabled transmit FIFO is empty.
|
|
*/
|
|
#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
|
|
#define I2S_TCSR_FEF_MASK (0x40000U)
|
|
#define I2S_TCSR_FEF_SHIFT (18U)
|
|
/*! FEF - FIFO Error Flag
|
|
* 0b0..Transmit underrun not detected.
|
|
* 0b1..Transmit underrun detected.
|
|
*/
|
|
#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
|
|
#define I2S_TCSR_SEF_MASK (0x80000U)
|
|
#define I2S_TCSR_SEF_SHIFT (19U)
|
|
/*! SEF - Sync Error Flag
|
|
* 0b0..Sync error not detected.
|
|
* 0b1..Frame sync error detected.
|
|
*/
|
|
#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
|
|
#define I2S_TCSR_WSF_MASK (0x100000U)
|
|
#define I2S_TCSR_WSF_SHIFT (20U)
|
|
/*! WSF - Word Start Flag
|
|
* 0b0..Start of word not detected.
|
|
* 0b1..Start of word detected.
|
|
*/
|
|
#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
|
|
#define I2S_TCSR_SR_MASK (0x1000000U)
|
|
#define I2S_TCSR_SR_SHIFT (24U)
|
|
/*! SR - Software Reset
|
|
* 0b0..No effect.
|
|
* 0b1..Software reset.
|
|
*/
|
|
#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
|
|
#define I2S_TCSR_FR_MASK (0x2000000U)
|
|
#define I2S_TCSR_FR_SHIFT (25U)
|
|
/*! FR - FIFO Reset
|
|
* 0b0..No effect.
|
|
* 0b1..FIFO reset.
|
|
*/
|
|
#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
|
|
#define I2S_TCSR_BCE_MASK (0x10000000U)
|
|
#define I2S_TCSR_BCE_SHIFT (28U)
|
|
/*! BCE - Bit Clock Enable
|
|
* 0b0..Transmit bit clock is disabled.
|
|
* 0b1..Transmit bit clock is enabled.
|
|
*/
|
|
#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
|
|
#define I2S_TCSR_DBGE_MASK (0x20000000U)
|
|
#define I2S_TCSR_DBGE_SHIFT (29U)
|
|
/*! DBGE - Debug Enable
|
|
* 0b0..Transmitter is disabled in Debug mode, after completing the current frame.
|
|
* 0b1..Transmitter is enabled in Debug mode.
|
|
*/
|
|
#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
|
|
#define I2S_TCSR_STOPE_MASK (0x40000000U)
|
|
#define I2S_TCSR_STOPE_SHIFT (30U)
|
|
/*! STOPE - Stop Enable
|
|
* 0b0..Transmitter disabled in Stop mode.
|
|
* 0b1..Transmitter enabled in Stop mode.
|
|
*/
|
|
#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
|
|
#define I2S_TCSR_TE_MASK (0x80000000U)
|
|
#define I2S_TCSR_TE_SHIFT (31U)
|
|
/*! TE - Transmitter Enable
|
|
* 0b0..Transmitter is disabled.
|
|
* 0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.
|
|
*/
|
|
#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TCR1 - SAI Transmit Configuration 1 Register */
|
|
/*! @{ */
|
|
#define I2S_TCR1_TFW_MASK (0x1FU)
|
|
#define I2S_TCR1_TFW_SHIFT (0U)
|
|
#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TCR2 - SAI Transmit Configuration 2 Register */
|
|
/*! @{ */
|
|
#define I2S_TCR2_DIV_MASK (0xFFU)
|
|
#define I2S_TCR2_DIV_SHIFT (0U)
|
|
#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
|
|
#define I2S_TCR2_BCD_MASK (0x1000000U)
|
|
#define I2S_TCR2_BCD_SHIFT (24U)
|
|
/*! BCD - Bit Clock Direction
|
|
* 0b0..Bit clock is generated externally in Slave mode.
|
|
* 0b1..Bit clock is generated internally in Master mode.
|
|
*/
|
|
#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
|
|
#define I2S_TCR2_BCP_MASK (0x2000000U)
|
|
#define I2S_TCR2_BCP_SHIFT (25U)
|
|
/*! BCP - Bit Clock Polarity
|
|
* 0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge.
|
|
* 0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.
|
|
*/
|
|
#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
|
|
#define I2S_TCR2_MSEL_MASK (0xC000000U)
|
|
#define I2S_TCR2_MSEL_SHIFT (26U)
|
|
/*! MSEL - MCLK Select
|
|
* 0b00..Bus Clock selected.
|
|
* 0b01..Master Clock (MCLK) 1 option selected.
|
|
* 0b10..Master Clock (MCLK) 2 option selected.
|
|
* 0b11..Master Clock (MCLK) 3 option selected.
|
|
*/
|
|
#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
|
|
#define I2S_TCR2_BCI_MASK (0x10000000U)
|
|
#define I2S_TCR2_BCI_SHIFT (28U)
|
|
/*! BCI - Bit Clock Input
|
|
* 0b0..No effect.
|
|
* 0b1..Internal logic is clocked as if bit clock was externally generated.
|
|
*/
|
|
#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
|
|
#define I2S_TCR2_BCS_MASK (0x20000000U)
|
|
#define I2S_TCR2_BCS_SHIFT (29U)
|
|
/*! BCS - Bit Clock Swap
|
|
* 0b0..Use the normal bit clock source.
|
|
* 0b1..Swap the bit clock source.
|
|
*/
|
|
#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
|
|
#define I2S_TCR2_SYNC_MASK (0xC0000000U)
|
|
#define I2S_TCR2_SYNC_SHIFT (30U)
|
|
/*! SYNC - Synchronous Mode
|
|
* 0b00..Asynchronous mode.
|
|
* 0b01..Synchronous with receiver.
|
|
* 0b10..Reserved.
|
|
* 0b11..Reserved.
|
|
*/
|
|
#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TCR3 - SAI Transmit Configuration 3 Register */
|
|
/*! @{ */
|
|
#define I2S_TCR3_WDFL_MASK (0x1FU)
|
|
#define I2S_TCR3_WDFL_SHIFT (0U)
|
|
#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
|
|
#define I2S_TCR3_TCE_MASK (0xF0000U)
|
|
#define I2S_TCR3_TCE_SHIFT (16U)
|
|
#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
|
|
#define I2S_TCR3_CFR_MASK (0xF000000U)
|
|
#define I2S_TCR3_CFR_SHIFT (24U)
|
|
#define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TCR4 - SAI Transmit Configuration 4 Register */
|
|
/*! @{ */
|
|
#define I2S_TCR4_FSD_MASK (0x1U)
|
|
#define I2S_TCR4_FSD_SHIFT (0U)
|
|
/*! FSD - Frame Sync Direction
|
|
* 0b0..Frame sync is generated externally in Slave mode.
|
|
* 0b1..Frame sync is generated internally in Master mode.
|
|
*/
|
|
#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
|
|
#define I2S_TCR4_FSP_MASK (0x2U)
|
|
#define I2S_TCR4_FSP_SHIFT (1U)
|
|
/*! FSP - Frame Sync Polarity
|
|
* 0b0..Frame sync is active high.
|
|
* 0b1..Frame sync is active low.
|
|
*/
|
|
#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
|
|
#define I2S_TCR4_ONDEM_MASK (0x4U)
|
|
#define I2S_TCR4_ONDEM_SHIFT (2U)
|
|
/*! ONDEM - On Demand Mode
|
|
* 0b0..Internal frame sync is generated continuously.
|
|
* 0b1..Internal frame sync is generated when the FIFO warning flag is clear.
|
|
*/
|
|
#define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
|
|
#define I2S_TCR4_FSE_MASK (0x8U)
|
|
#define I2S_TCR4_FSE_SHIFT (3U)
|
|
/*! FSE - Frame Sync Early
|
|
* 0b0..Frame sync asserts with the first bit of the frame.
|
|
* 0b1..Frame sync asserts one bit before the first bit of the frame.
|
|
*/
|
|
#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
|
|
#define I2S_TCR4_MF_MASK (0x10U)
|
|
#define I2S_TCR4_MF_SHIFT (4U)
|
|
/*! MF - MSB First
|
|
* 0b0..LSB is transmitted first.
|
|
* 0b1..MSB is transmitted first.
|
|
*/
|
|
#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
|
|
#define I2S_TCR4_CHMOD_MASK (0x20U)
|
|
#define I2S_TCR4_CHMOD_SHIFT (5U)
|
|
/*! CHMOD - Channel Mode
|
|
* 0b0..TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled.
|
|
* 0b1..Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled.
|
|
*/
|
|
#define I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK)
|
|
#define I2S_TCR4_SYWD_MASK (0x1F00U)
|
|
#define I2S_TCR4_SYWD_SHIFT (8U)
|
|
#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
|
|
#define I2S_TCR4_FRSZ_MASK (0x1F0000U)
|
|
#define I2S_TCR4_FRSZ_SHIFT (16U)
|
|
#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
|
|
#define I2S_TCR4_FPACK_MASK (0x3000000U)
|
|
#define I2S_TCR4_FPACK_SHIFT (24U)
|
|
/*! FPACK - FIFO Packing Mode
|
|
* 0b00..FIFO packing is disabled
|
|
* 0b01..Reserved
|
|
* 0b10..8-bit FIFO packing is enabled
|
|
* 0b11..16-bit FIFO packing is enabled
|
|
*/
|
|
#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
|
|
#define I2S_TCR4_FCOMB_MASK (0xC000000U)
|
|
#define I2S_TCR4_FCOMB_SHIFT (26U)
|
|
/*! FCOMB - FIFO Combine Mode
|
|
* 0b00..FIFO combine mode disabled.
|
|
* 0b01..FIFO combine mode enabled on FIFO reads (from transmit shift registers).
|
|
* 0b10..FIFO combine mode enabled on FIFO writes (by software).
|
|
* 0b11..FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software).
|
|
*/
|
|
#define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
|
|
#define I2S_TCR4_FCONT_MASK (0x10000000U)
|
|
#define I2S_TCR4_FCONT_SHIFT (28U)
|
|
/*! FCONT - FIFO Continue on Error
|
|
* 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
|
|
* 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
|
|
*/
|
|
#define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TCR5 - SAI Transmit Configuration 5 Register */
|
|
/*! @{ */
|
|
#define I2S_TCR5_FBT_MASK (0x1F00U)
|
|
#define I2S_TCR5_FBT_SHIFT (8U)
|
|
#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
|
|
#define I2S_TCR5_W0W_MASK (0x1F0000U)
|
|
#define I2S_TCR5_W0W_SHIFT (16U)
|
|
#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
|
|
#define I2S_TCR5_WNW_MASK (0x1F000000U)
|
|
#define I2S_TCR5_WNW_SHIFT (24U)
|
|
#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TDR - SAI Transmit Data Register */
|
|
/*! @{ */
|
|
#define I2S_TDR_TDR_MASK (0xFFFFFFFFU)
|
|
#define I2S_TDR_TDR_SHIFT (0U)
|
|
#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of I2S_TDR */
|
|
#define I2S_TDR_COUNT (4U)
|
|
|
|
/*! @name TFR - SAI Transmit FIFO Register */
|
|
/*! @{ */
|
|
#define I2S_TFR_RFP_MASK (0x3FU)
|
|
#define I2S_TFR_RFP_SHIFT (0U)
|
|
#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
|
|
#define I2S_TFR_WFP_MASK (0x3F0000U)
|
|
#define I2S_TFR_WFP_SHIFT (16U)
|
|
#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
|
|
#define I2S_TFR_WCP_MASK (0x80000000U)
|
|
#define I2S_TFR_WCP_SHIFT (31U)
|
|
/*! WCP - Write Channel Pointer
|
|
* 0b0..No effect.
|
|
* 0b1..FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write.
|
|
*/
|
|
#define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of I2S_TFR */
|
|
#define I2S_TFR_COUNT (4U)
|
|
|
|
/*! @name TMR - SAI Transmit Mask Register */
|
|
/*! @{ */
|
|
#define I2S_TMR_TWM_MASK (0xFFFFFFFFU)
|
|
#define I2S_TMR_TWM_SHIFT (0U)
|
|
/*! TWM - Transmit Word Mask
|
|
* 0b00000000000000000000000000000000..Word N is enabled.
|
|
* 0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated or drive zero when masked.
|
|
*/
|
|
#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RCSR - SAI Receive Control Register */
|
|
/*! @{ */
|
|
#define I2S_RCSR_FRDE_MASK (0x1U)
|
|
#define I2S_RCSR_FRDE_SHIFT (0U)
|
|
/*! FRDE - FIFO Request DMA Enable
|
|
* 0b0..Disables the DMA request.
|
|
* 0b1..Enables the DMA request.
|
|
*/
|
|
#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
|
|
#define I2S_RCSR_FWDE_MASK (0x2U)
|
|
#define I2S_RCSR_FWDE_SHIFT (1U)
|
|
/*! FWDE - FIFO Warning DMA Enable
|
|
* 0b0..Disables the DMA request.
|
|
* 0b1..Enables the DMA request.
|
|
*/
|
|
#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
|
|
#define I2S_RCSR_FRIE_MASK (0x100U)
|
|
#define I2S_RCSR_FRIE_SHIFT (8U)
|
|
/*! FRIE - FIFO Request Interrupt Enable
|
|
* 0b0..Disables the interrupt.
|
|
* 0b1..Enables the interrupt.
|
|
*/
|
|
#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
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|
#define I2S_RCSR_FWIE_MASK (0x200U)
|
|
#define I2S_RCSR_FWIE_SHIFT (9U)
|
|
/*! FWIE - FIFO Warning Interrupt Enable
|
|
* 0b0..Disables the interrupt.
|
|
* 0b1..Enables the interrupt.
|
|
*/
|
|
#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
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#define I2S_RCSR_FEIE_MASK (0x400U)
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#define I2S_RCSR_FEIE_SHIFT (10U)
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/*! FEIE - FIFO Error Interrupt Enable
|
|
* 0b0..Disables the interrupt.
|
|
* 0b1..Enables the interrupt.
|
|
*/
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|
#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
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|
#define I2S_RCSR_SEIE_MASK (0x800U)
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|
#define I2S_RCSR_SEIE_SHIFT (11U)
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/*! SEIE - Sync Error Interrupt Enable
|
|
* 0b0..Disables interrupt.
|
|
* 0b1..Enables interrupt.
|
|
*/
|
|
#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
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#define I2S_RCSR_WSIE_MASK (0x1000U)
|
|
#define I2S_RCSR_WSIE_SHIFT (12U)
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|
/*! WSIE - Word Start Interrupt Enable
|
|
* 0b0..Disables interrupt.
|
|
* 0b1..Enables interrupt.
|
|
*/
|
|
#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
|
|
#define I2S_RCSR_FRF_MASK (0x10000U)
|
|
#define I2S_RCSR_FRF_SHIFT (16U)
|
|
/*! FRF - FIFO Request Flag
|
|
* 0b0..Receive FIFO watermark not reached.
|
|
* 0b1..Receive FIFO watermark has been reached.
|
|
*/
|
|
#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
|
|
#define I2S_RCSR_FWF_MASK (0x20000U)
|
|
#define I2S_RCSR_FWF_SHIFT (17U)
|
|
/*! FWF - FIFO Warning Flag
|
|
* 0b0..No enabled receive FIFO is full.
|
|
* 0b1..Enabled receive FIFO is full.
|
|
*/
|
|
#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
|
|
#define I2S_RCSR_FEF_MASK (0x40000U)
|
|
#define I2S_RCSR_FEF_SHIFT (18U)
|
|
/*! FEF - FIFO Error Flag
|
|
* 0b0..Receive overflow not detected.
|
|
* 0b1..Receive overflow detected.
|
|
*/
|
|
#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
|
|
#define I2S_RCSR_SEF_MASK (0x80000U)
|
|
#define I2S_RCSR_SEF_SHIFT (19U)
|
|
/*! SEF - Sync Error Flag
|
|
* 0b0..Sync error not detected.
|
|
* 0b1..Frame sync error detected.
|
|
*/
|
|
#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
|
|
#define I2S_RCSR_WSF_MASK (0x100000U)
|
|
#define I2S_RCSR_WSF_SHIFT (20U)
|
|
/*! WSF - Word Start Flag
|
|
* 0b0..Start of word not detected.
|
|
* 0b1..Start of word detected.
|
|
*/
|
|
#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
|
|
#define I2S_RCSR_SR_MASK (0x1000000U)
|
|
#define I2S_RCSR_SR_SHIFT (24U)
|
|
/*! SR - Software Reset
|
|
* 0b0..No effect.
|
|
* 0b1..Software reset.
|
|
*/
|
|
#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
|
|
#define I2S_RCSR_FR_MASK (0x2000000U)
|
|
#define I2S_RCSR_FR_SHIFT (25U)
|
|
/*! FR - FIFO Reset
|
|
* 0b0..No effect.
|
|
* 0b1..FIFO reset.
|
|
*/
|
|
#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
|
|
#define I2S_RCSR_BCE_MASK (0x10000000U)
|
|
#define I2S_RCSR_BCE_SHIFT (28U)
|
|
/*! BCE - Bit Clock Enable
|
|
* 0b0..Receive bit clock is disabled.
|
|
* 0b1..Receive bit clock is enabled.
|
|
*/
|
|
#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
|
|
#define I2S_RCSR_DBGE_MASK (0x20000000U)
|
|
#define I2S_RCSR_DBGE_SHIFT (29U)
|
|
/*! DBGE - Debug Enable
|
|
* 0b0..Receiver is disabled in Debug mode, after completing the current frame.
|
|
* 0b1..Receiver is enabled in Debug mode.
|
|
*/
|
|
#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
|
|
#define I2S_RCSR_STOPE_MASK (0x40000000U)
|
|
#define I2S_RCSR_STOPE_SHIFT (30U)
|
|
/*! STOPE - Stop Enable
|
|
* 0b0..Receiver disabled in Stop mode.
|
|
* 0b1..Receiver enabled in Stop mode.
|
|
*/
|
|
#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
|
|
#define I2S_RCSR_RE_MASK (0x80000000U)
|
|
#define I2S_RCSR_RE_SHIFT (31U)
|
|
/*! RE - Receiver Enable
|
|
* 0b0..Receiver is disabled.
|
|
* 0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.
|
|
*/
|
|
#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RCR1 - SAI Receive Configuration 1 Register */
|
|
/*! @{ */
|
|
#define I2S_RCR1_RFW_MASK (0x1FU)
|
|
#define I2S_RCR1_RFW_SHIFT (0U)
|
|
#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RCR2 - SAI Receive Configuration 2 Register */
|
|
/*! @{ */
|
|
#define I2S_RCR2_DIV_MASK (0xFFU)
|
|
#define I2S_RCR2_DIV_SHIFT (0U)
|
|
#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
|
|
#define I2S_RCR2_BCD_MASK (0x1000000U)
|
|
#define I2S_RCR2_BCD_SHIFT (24U)
|
|
/*! BCD - Bit Clock Direction
|
|
* 0b0..Bit clock is generated externally in Slave mode.
|
|
* 0b1..Bit clock is generated internally in Master mode.
|
|
*/
|
|
#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
|
|
#define I2S_RCR2_BCP_MASK (0x2000000U)
|
|
#define I2S_RCR2_BCP_SHIFT (25U)
|
|
/*! BCP - Bit Clock Polarity
|
|
* 0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge.
|
|
* 0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.
|
|
*/
|
|
#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
|
|
#define I2S_RCR2_MSEL_MASK (0xC000000U)
|
|
#define I2S_RCR2_MSEL_SHIFT (26U)
|
|
/*! MSEL - MCLK Select
|
|
* 0b00..Bus Clock selected.
|
|
* 0b01..Master Clock (MCLK) 1 option selected.
|
|
* 0b10..Master Clock (MCLK) 2 option selected.
|
|
* 0b11..Master Clock (MCLK) 3 option selected.
|
|
*/
|
|
#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
|
|
#define I2S_RCR2_BCI_MASK (0x10000000U)
|
|
#define I2S_RCR2_BCI_SHIFT (28U)
|
|
/*! BCI - Bit Clock Input
|
|
* 0b0..No effect.
|
|
* 0b1..Internal logic is clocked as if bit clock was externally generated.
|
|
*/
|
|
#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
|
|
#define I2S_RCR2_BCS_MASK (0x20000000U)
|
|
#define I2S_RCR2_BCS_SHIFT (29U)
|
|
/*! BCS - Bit Clock Swap
|
|
* 0b0..Use the normal bit clock source.
|
|
* 0b1..Swap the bit clock source.
|
|
*/
|
|
#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
|
|
#define I2S_RCR2_SYNC_MASK (0xC0000000U)
|
|
#define I2S_RCR2_SYNC_SHIFT (30U)
|
|
/*! SYNC - Synchronous Mode
|
|
* 0b00..Asynchronous mode.
|
|
* 0b01..Synchronous with transmitter.
|
|
* 0b10..Reserved.
|
|
* 0b11..Reserved.
|
|
*/
|
|
#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RCR3 - SAI Receive Configuration 3 Register */
|
|
/*! @{ */
|
|
#define I2S_RCR3_WDFL_MASK (0x1FU)
|
|
#define I2S_RCR3_WDFL_SHIFT (0U)
|
|
#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
|
|
#define I2S_RCR3_RCE_MASK (0xF0000U)
|
|
#define I2S_RCR3_RCE_SHIFT (16U)
|
|
#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
|
|
#define I2S_RCR3_CFR_MASK (0xF000000U)
|
|
#define I2S_RCR3_CFR_SHIFT (24U)
|
|
#define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RCR4 - SAI Receive Configuration 4 Register */
|
|
/*! @{ */
|
|
#define I2S_RCR4_FSD_MASK (0x1U)
|
|
#define I2S_RCR4_FSD_SHIFT (0U)
|
|
/*! FSD - Frame Sync Direction
|
|
* 0b0..Frame Sync is generated externally in Slave mode.
|
|
* 0b1..Frame Sync is generated internally in Master mode.
|
|
*/
|
|
#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
|
|
#define I2S_RCR4_FSP_MASK (0x2U)
|
|
#define I2S_RCR4_FSP_SHIFT (1U)
|
|
/*! FSP - Frame Sync Polarity
|
|
* 0b0..Frame sync is active high.
|
|
* 0b1..Frame sync is active low.
|
|
*/
|
|
#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
|
|
#define I2S_RCR4_ONDEM_MASK (0x4U)
|
|
#define I2S_RCR4_ONDEM_SHIFT (2U)
|
|
/*! ONDEM - On Demand Mode
|
|
* 0b0..Internal frame sync is generated continuously.
|
|
* 0b1..Internal frame sync is generated when the FIFO warning flag is clear.
|
|
*/
|
|
#define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
|
|
#define I2S_RCR4_FSE_MASK (0x8U)
|
|
#define I2S_RCR4_FSE_SHIFT (3U)
|
|
/*! FSE - Frame Sync Early
|
|
* 0b0..Frame sync asserts with the first bit of the frame.
|
|
* 0b1..Frame sync asserts one bit before the first bit of the frame.
|
|
*/
|
|
#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
|
|
#define I2S_RCR4_MF_MASK (0x10U)
|
|
#define I2S_RCR4_MF_SHIFT (4U)
|
|
/*! MF - MSB First
|
|
* 0b0..LSB is received first.
|
|
* 0b1..MSB is received first.
|
|
*/
|
|
#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
|
|
#define I2S_RCR4_SYWD_MASK (0x1F00U)
|
|
#define I2S_RCR4_SYWD_SHIFT (8U)
|
|
#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
|
|
#define I2S_RCR4_FRSZ_MASK (0x1F0000U)
|
|
#define I2S_RCR4_FRSZ_SHIFT (16U)
|
|
#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
|
|
#define I2S_RCR4_FPACK_MASK (0x3000000U)
|
|
#define I2S_RCR4_FPACK_SHIFT (24U)
|
|
/*! FPACK - FIFO Packing Mode
|
|
* 0b00..FIFO packing is disabled
|
|
* 0b01..Reserved.
|
|
* 0b10..8-bit FIFO packing is enabled
|
|
* 0b11..16-bit FIFO packing is enabled
|
|
*/
|
|
#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
|
|
#define I2S_RCR4_FCOMB_MASK (0xC000000U)
|
|
#define I2S_RCR4_FCOMB_SHIFT (26U)
|
|
/*! FCOMB - FIFO Combine Mode
|
|
* 0b00..FIFO combine mode disabled.
|
|
* 0b01..FIFO combine mode enabled on FIFO writes (from receive shift registers).
|
|
* 0b10..FIFO combine mode enabled on FIFO reads (by software).
|
|
* 0b11..FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software).
|
|
*/
|
|
#define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
|
|
#define I2S_RCR4_FCONT_MASK (0x10000000U)
|
|
#define I2S_RCR4_FCONT_SHIFT (28U)
|
|
/*! FCONT - FIFO Continue on Error
|
|
* 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
|
|
* 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
|
|
*/
|
|
#define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RCR5 - SAI Receive Configuration 5 Register */
|
|
/*! @{ */
|
|
#define I2S_RCR5_FBT_MASK (0x1F00U)
|
|
#define I2S_RCR5_FBT_SHIFT (8U)
|
|
#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
|
|
#define I2S_RCR5_W0W_MASK (0x1F0000U)
|
|
#define I2S_RCR5_W0W_SHIFT (16U)
|
|
#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
|
|
#define I2S_RCR5_WNW_MASK (0x1F000000U)
|
|
#define I2S_RCR5_WNW_SHIFT (24U)
|
|
#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RDR - SAI Receive Data Register */
|
|
/*! @{ */
|
|
#define I2S_RDR_RDR_MASK (0xFFFFFFFFU)
|
|
#define I2S_RDR_RDR_SHIFT (0U)
|
|
#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of I2S_RDR */
|
|
#define I2S_RDR_COUNT (4U)
|
|
|
|
/*! @name RFR - SAI Receive FIFO Register */
|
|
/*! @{ */
|
|
#define I2S_RFR_RFP_MASK (0x3FU)
|
|
#define I2S_RFR_RFP_SHIFT (0U)
|
|
#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
|
|
#define I2S_RFR_RCP_MASK (0x8000U)
|
|
#define I2S_RFR_RCP_SHIFT (15U)
|
|
/*! RCP - Receive Channel Pointer
|
|
* 0b0..No effect.
|
|
* 0b1..FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read.
|
|
*/
|
|
#define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
|
|
#define I2S_RFR_WFP_MASK (0x3F0000U)
|
|
#define I2S_RFR_WFP_SHIFT (16U)
|
|
#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of I2S_RFR */
|
|
#define I2S_RFR_COUNT (4U)
|
|
|
|
/*! @name RMR - SAI Receive Mask Register */
|
|
/*! @{ */
|
|
#define I2S_RMR_RWM_MASK (0xFFFFFFFFU)
|
|
#define I2S_RMR_RWM_SHIFT (0U)
|
|
/*! RWM - Receive Word Mask
|
|
* 0b00000000000000000000000000000000..Word N is enabled.
|
|
* 0b00000000000000000000000000000001..Word N is masked.
|
|
*/
|
|
#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group I2S_Register_Masks */
|
|
|
|
|
|
/* I2S - Peripheral instance base addresses */
|
|
/** Peripheral SAI1 base address */
|
|
#define SAI1_BASE (0x40384000u)
|
|
/** Peripheral SAI1 base pointer */
|
|
#define SAI1 ((I2S_Type *)SAI1_BASE)
|
|
/** Peripheral SAI2 base address */
|
|
#define SAI2_BASE (0x40388000u)
|
|
/** Peripheral SAI2 base pointer */
|
|
#define SAI2 ((I2S_Type *)SAI2_BASE)
|
|
/** Peripheral SAI3 base address */
|
|
#define SAI3_BASE (0x4038C000u)
|
|
/** Peripheral SAI3 base pointer */
|
|
#define SAI3 ((I2S_Type *)SAI3_BASE)
|
|
/** Array initializer of I2S peripheral base addresses */
|
|
#define I2S_BASE_ADDRS { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE }
|
|
/** Array initializer of I2S peripheral base pointers */
|
|
#define I2S_BASE_PTRS { (I2S_Type *)0u, SAI1, SAI2, SAI3 }
|
|
/** Interrupt vectors for the I2S peripheral type */
|
|
#define I2S_RX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_RX_IRQn }
|
|
#define I2S_TX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_TX_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group I2S_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- IOMUXC Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup IOMUXC_Peripheral_Access_Layer IOMUXC Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** IOMUXC - Register Layout Typedef */
|
|
typedef struct {
|
|
uint8_t RESERVED_0[20];
|
|
__IO uint32_t SW_MUX_CTL_PAD[124]; /**< SW_MUX_CTL_PAD_GPIO_EMC_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_SD_B1_11 SW MUX Control Register, array offset: 0x14, array step: 0x4 */
|
|
__IO uint32_t SW_PAD_CTL_PAD[124]; /**< SW_PAD_CTL_PAD_GPIO_EMC_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_SD_B1_11 SW PAD Control Register, array offset: 0x204, array step: 0x4 */
|
|
__IO uint32_t SELECT_INPUT[154]; /**< ANATOP_USB_OTG1_ID_SELECT_INPUT DAISY Register..XBAR1_IN23_SELECT_INPUT DAISY Register, array offset: 0x3F4, array step: 0x4 */
|
|
} IOMUXC_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- IOMUXC Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup IOMUXC_Register_Masks IOMUXC Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_GPIO_EMC_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_SD_B1_11 SW MUX Control Register */
|
|
/*! @{ */
|
|
#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0x7U)
|
|
#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U)
|
|
/*! MUX_MODE - MUX Mode Select Field.
|
|
* 0b000..Select mux mode: ALT0 mux port: LPI2C4_SCL of instance: lpi2c4
|
|
* 0b001..Select mux mode: ALT1 mux port: CCM_PMIC_READY of instance: ccm
|
|
* 0b010..Select mux mode: ALT2 mux port: LPUART1_TX of instance: lpuart1
|
|
* 0b011..Select mux mode: ALT3 mux port: WDOG2_WDOG_B of instance: wdog2
|
|
* 0b100..Select mux mode: ALT4 mux port: FLEXPWM1_PWMX02 of instance: flexpwm1
|
|
* 0b101..Select mux mode: ALT5 mux port: GPIO1_IO12 of instance: gpio1
|
|
* 0b110..Select mux mode: ALT6 mux port: ENET_1588_EVENT1_OUT of instance: enet
|
|
* 0b111..Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: nmi_glue
|
|
*/
|
|
#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK)
|
|
#define IOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U)
|
|
#define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U)
|
|
/*! SION - Software Input On Field.
|
|
* 0b1..Force input path of pad GPIO_SD_B1_11
|
|
* 0b0..Input Path is determined by functionality
|
|
*/
|
|
#define IOMUXC_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of IOMUXC_SW_MUX_CTL_PAD */
|
|
#define IOMUXC_SW_MUX_CTL_PAD_COUNT (124U)
|
|
|
|
/*! @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_GPIO_EMC_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_SD_B1_11 SW PAD Control Register */
|
|
/*! @{ */
|
|
#define IOMUXC_SW_PAD_CTL_PAD_SRE_MASK (0x1U)
|
|
#define IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT (0U)
|
|
/*! SRE - Slew Rate Field
|
|
* 0b0..Slow Slew Rate
|
|
* 0b1..Fast Slew Rate
|
|
*/
|
|
#define IOMUXC_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK)
|
|
#define IOMUXC_SW_PAD_CTL_PAD_DSE_MASK (0x38U)
|
|
#define IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT (3U)
|
|
/*! DSE - Drive Strength Field
|
|
* 0b000..output driver disabled;
|
|
* 0b001..R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)
|
|
* 0b010..R0/2
|
|
* 0b011..R0/3
|
|
* 0b100..R0/4
|
|
* 0b101..R0/5
|
|
* 0b110..R0/6
|
|
* 0b111..R0/7
|
|
*/
|
|
#define IOMUXC_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK)
|
|
#define IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK (0xC0U)
|
|
#define IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT (6U)
|
|
/*! SPEED - Speed Field
|
|
* 0b00..low(50MHz)
|
|
* 0b01..medium(100MHz)
|
|
* 0b10..medium(100MHz)
|
|
* 0b11..max(200MHz)
|
|
*/
|
|
#define IOMUXC_SW_PAD_CTL_PAD_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK)
|
|
#define IOMUXC_SW_PAD_CTL_PAD_ODE_MASK (0x800U)
|
|
#define IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT (11U)
|
|
/*! ODE - Open Drain Enable Field
|
|
* 0b0..Open Drain Disabled
|
|
* 0b1..Open Drain Enabled
|
|
*/
|
|
#define IOMUXC_SW_PAD_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK)
|
|
#define IOMUXC_SW_PAD_CTL_PAD_PKE_MASK (0x1000U)
|
|
#define IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT (12U)
|
|
/*! PKE - Pull / Keep Enable Field
|
|
* 0b0..Pull/Keeper Disabled
|
|
* 0b1..Pull/Keeper Enabled
|
|
*/
|
|
#define IOMUXC_SW_PAD_CTL_PAD_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PKE_MASK)
|
|
#define IOMUXC_SW_PAD_CTL_PAD_PUE_MASK (0x2000U)
|
|
#define IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT (13U)
|
|
/*! PUE - Pull / Keep Select Field
|
|
* 0b0..Keeper
|
|
* 0b1..Pull
|
|
*/
|
|
#define IOMUXC_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK)
|
|
#define IOMUXC_SW_PAD_CTL_PAD_PUS_MASK (0xC000U)
|
|
#define IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT (14U)
|
|
/*! PUS - Pull Up / Down Config. Field
|
|
* 0b00..100K Ohm Pull Down
|
|
* 0b01..47K Ohm Pull Up
|
|
* 0b10..100K Ohm Pull Up
|
|
* 0b11..22K Ohm Pull Up
|
|
*/
|
|
#define IOMUXC_SW_PAD_CTL_PAD_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK)
|
|
#define IOMUXC_SW_PAD_CTL_PAD_HYS_MASK (0x10000U)
|
|
#define IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT (16U)
|
|
/*! HYS - Hyst. Enable Field
|
|
* 0b0..Hysteresis Disabled
|
|
* 0b1..Hysteresis Enabled
|
|
*/
|
|
#define IOMUXC_SW_PAD_CTL_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_HYS_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of IOMUXC_SW_PAD_CTL_PAD */
|
|
#define IOMUXC_SW_PAD_CTL_PAD_COUNT (124U)
|
|
|
|
/*! @name SELECT_INPUT - ANATOP_USB_OTG1_ID_SELECT_INPUT DAISY Register..XBAR1_IN23_SELECT_INPUT DAISY Register */
|
|
/*! @{ */
|
|
#define IOMUXC_SELECT_INPUT_DAISY_MASK (0x7U) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */
|
|
#define IOMUXC_SELECT_INPUT_DAISY_SHIFT (0U)
|
|
/*! DAISY - Selecting Pads Involved in Daisy Chain.
|
|
* 0b000..Selecting Pad: GPIO_SD_B1_03 for Mode: ALT6
|
|
* 0b001..Selecting Pad: GPIO_AD_B0_12 for Mode: ALT1
|
|
* 0b010..Selecting Pad: GPIO_AD_B1_01 for Mode: ALT4
|
|
* 0b011..Selecting Pad: GPIO_AD_B1_08 for Mode: ALT3
|
|
* 0b100..Selecting Pad: GPIO_EMC_32 for Mode: ALT3
|
|
*/
|
|
#define IOMUXC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */
|
|
/*! @} */
|
|
|
|
/* The count of IOMUXC_SELECT_INPUT */
|
|
#define IOMUXC_SELECT_INPUT_COUNT (154U)
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group IOMUXC_Register_Masks */
|
|
|
|
|
|
/* IOMUXC - Peripheral instance base addresses */
|
|
/** Peripheral IOMUXC base address */
|
|
#define IOMUXC_BASE (0x401F8000u)
|
|
/** Peripheral IOMUXC base pointer */
|
|
#define IOMUXC ((IOMUXC_Type *)IOMUXC_BASE)
|
|
/** Array initializer of IOMUXC peripheral base addresses */
|
|
#define IOMUXC_BASE_ADDRS { IOMUXC_BASE }
|
|
/** Array initializer of IOMUXC peripheral base pointers */
|
|
#define IOMUXC_BASE_PTRS { IOMUXC }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group IOMUXC_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- IOMUXC_GPR Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup IOMUXC_GPR_Peripheral_Access_Layer IOMUXC_GPR Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** IOMUXC_GPR - Register Layout Typedef */
|
|
typedef struct {
|
|
uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */
|
|
__IO uint32_t GPR1; /**< GPR1 General Purpose Register, offset: 0x4 */
|
|
__IO uint32_t GPR2; /**< GPR2 General Purpose Register, offset: 0x8 */
|
|
__IO uint32_t GPR3; /**< GPR3 General Purpose Register, offset: 0xC */
|
|
__IO uint32_t GPR4; /**< GPR4 General Purpose Register, offset: 0x10 */
|
|
__IO uint32_t GPR5; /**< GPR5 General Purpose Register, offset: 0x14 */
|
|
__IO uint32_t GPR6; /**< GPR6 General Purpose Register, offset: 0x18 */
|
|
__IO uint32_t GPR7; /**< GPR7 General Purpose Register, offset: 0x1C */
|
|
__IO uint32_t GPR8; /**< GPR8 General Purpose Register, offset: 0x20 */
|
|
uint32_t GPR9; /**< GPR9 General Purpose Register, offset: 0x24 */
|
|
__IO uint32_t GPR10; /**< GPR10 General Purpose Register, offset: 0x28 */
|
|
__IO uint32_t GPR11; /**< GPR11 General Purpose Register, offset: 0x2C */
|
|
__IO uint32_t GPR12; /**< GPR12 General Purpose Register, offset: 0x30 */
|
|
__IO uint32_t GPR13; /**< GPR13 General Purpose Register, offset: 0x34 */
|
|
__IO uint32_t GPR14; /**< GPR14 General Purpose Register, offset: 0x38 */
|
|
uint32_t GPR15; /**< GPR15 General Purpose Register, offset: 0x3C */
|
|
__IO uint32_t GPR16; /**< GPR16 General Purpose Register, offset: 0x40 */
|
|
__IO uint32_t GPR17; /**< GPR17 General Purpose Register, offset: 0x44 */
|
|
__IO uint32_t GPR18; /**< GPR18 General Purpose Register, offset: 0x48 */
|
|
__IO uint32_t GPR19; /**< GPR19 General Purpose Register, offset: 0x4C */
|
|
__IO uint32_t GPR20; /**< GPR20 General Purpose Register, offset: 0x50 */
|
|
__IO uint32_t GPR21; /**< GPR21 General Purpose Register, offset: 0x54 */
|
|
__IO uint32_t GPR22; /**< GPR22 General Purpose Register, offset: 0x58 */
|
|
__IO uint32_t GPR23; /**< GPR23 General Purpose Register, offset: 0x5C */
|
|
__IO uint32_t GPR24; /**< GPR24 General Purpose Register, offset: 0x60 */
|
|
__IO uint32_t GPR25; /**< GPR25 General Purpose Register, offset: 0x64 */
|
|
} IOMUXC_GPR_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- IOMUXC_GPR Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup IOMUXC_GPR_Register_Masks IOMUXC_GPR Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name GPR1 - GPR1 General Purpose Register */
|
|
/*! @{ */
|
|
#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK (0x7U)
|
|
#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT (0U)
|
|
/*! SAI1_MCLK1_SEL
|
|
* 0b000..ccm.ssi1_clk_root
|
|
* 0b001..ccm.ssi2_clk_root
|
|
* 0b010..ccm.ssi3_clk_root
|
|
* 0b011..iomux.sai1_ipg_clk_sai_mclk
|
|
* 0b100..iomux.sai2_ipg_clk_sai_mclk
|
|
* 0b101..iomux.sai3_ipg_clk_sai_mclk
|
|
* 0b110..Reserved
|
|
* 0b111..Reserved
|
|
*/
|
|
#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK)
|
|
#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK (0x38U)
|
|
#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT (3U)
|
|
/*! SAI1_MCLK2_SEL
|
|
* 0b000..ccm.ssi1_clk_root
|
|
* 0b001..ccm.ssi2_clk_root
|
|
* 0b010..ccm.ssi3_clk_root
|
|
* 0b011..iomux.sai1_ipg_clk_sai_mclk
|
|
* 0b100..iomux.sai2_ipg_clk_sai_mclk
|
|
* 0b101..iomux.sai3_ipg_clk_sai_mclk
|
|
* 0b110..Reserved
|
|
* 0b111..Reserved
|
|
*/
|
|
#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK)
|
|
#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK (0xC0U)
|
|
#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT (6U)
|
|
/*! SAI1_MCLK3_SEL
|
|
* 0b00..ccm.spdif0_clk_root
|
|
* 0b01..iomux.spdif_tx_clk2
|
|
* 0b10..spdif.spdif_srclk
|
|
* 0b11..spdif.spdif_outclock
|
|
*/
|
|
#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK)
|
|
#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK (0x300U)
|
|
#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT (8U)
|
|
/*! SAI2_MCLK3_SEL
|
|
* 0b00..ccm.spdif0_clk_root
|
|
* 0b01..iomux.spdif_tx_clk2
|
|
* 0b10..spdif.spdif_srclk
|
|
* 0b11..spdif.spdif_outclock
|
|
*/
|
|
#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK)
|
|
#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK (0xC00U)
|
|
#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT (10U)
|
|
/*! SAI3_MCLK3_SEL
|
|
* 0b00..ccm.spdif0_clk_root
|
|
* 0b01..iomux.spdif_tx_clk2
|
|
* 0b10..spdif.spdif_srclk
|
|
* 0b11..spdif.spdif_outclock
|
|
*/
|
|
#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK)
|
|
#define IOMUXC_GPR_GPR1_GINT_MASK (0x1000U)
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#define IOMUXC_GPR_GPR1_GINT_SHIFT (12U)
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/*! GINT
|
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* 0b0..Global interrupt request is not asserted.
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* 0b1..Global interrupt request is asserted.
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*/
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#define IOMUXC_GPR_GPR1_GINT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GINT_SHIFT)) & IOMUXC_GPR_GPR1_GINT_MASK)
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#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK (0x2000U)
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#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT (13U)
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/*! ENET1_CLK_SEL
|
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* 0b0..ENET1 TX reference clock driven by ref_enetpll0. This clock is also output to pins via the IOMUX. ENET_REF_CLK1 function.
|
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* 0b1..Gets ENET1 TX reference clock from the ENET1_TX_CLK pin. In this use case, an external OSC provides the clock for both the external PHY and the internal controller.
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*/
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#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK)
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#define IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK (0x8000U)
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#define IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT (15U)
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/*! USB_EXP_MODE
|
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* 0b0..Exposure mode is disabled.
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* 0b1..Exposure mode is enabled.
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*/
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#define IOMUXC_GPR_GPR1_USB_EXP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT)) & IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK)
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#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK (0x20000U)
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#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT (17U)
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/*! ENET1_TX_CLK_DIR
|
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* 0b0..ENET1_TX_CLK output driver is disabled and ENET_REF_CLK1 is a clock input.
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* 0b1..ENET1_TX_CLK output driver is enabled and ENET_REF_CLK1 is an output driven by ref_enetpll0.
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*/
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#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)
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#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK (0x80000U)
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#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT (19U)
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/*! SAI1_MCLK_DIR
|
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* 0b0..sai1.MCLK is input signal
|
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* 0b1..sai1.MCLK is output signal
|
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*/
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#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK)
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#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK (0x100000U)
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#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT (20U)
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/*! SAI2_MCLK_DIR
|
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* 0b0..sai2.MCLK is input signal
|
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* 0b1..sai2.MCLK is output signal
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*/
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#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK)
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#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK (0x200000U)
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#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT (21U)
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/*! SAI3_MCLK_DIR
|
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* 0b0..sai3.MCLK is input signal
|
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* 0b1..sai3.MCLK is output signal
|
|
*/
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#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK)
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#define IOMUXC_GPR_GPR1_EXC_MON_MASK (0x400000U)
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|
#define IOMUXC_GPR_GPR1_EXC_MON_SHIFT (22U)
|
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/*! EXC_MON
|
|
* 0b0..OKAY response
|
|
* 0b1..SLVError response
|
|
*/
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|
#define IOMUXC_GPR_GPR1_EXC_MON(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR1_EXC_MON_MASK)
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#define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK (0x800000U)
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#define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT (23U)
|
|
/*! ENET_IPG_CLK_S_EN
|
|
* 0b0..ipg_clk_s is gated when there is no IPS access
|
|
* 0b1..ipg_clk_s is always on
|
|
*/
|
|
#define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT)) & IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK)
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#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK (0x80000000U)
|
|
#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT (31U)
|
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/*! CM7_FORCE_HCLK_EN
|
|
* 0b0..AHB clock is not running (gated)
|
|
* 0b1..AHB clock is running (enabled)
|
|
*/
|
|
#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK)
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/*! @} */
|
|
|
|
/*! @name GPR2 - GPR2 General Purpose Register */
|
|
/*! @{ */
|
|
#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK (0x1000U)
|
|
#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT (12U)
|
|
/*! L2_MEM_EN_POWERSAVING
|
|
* 0b0..none memory power saving features enabled, SHUTDOWN/DEEPSLEEP/LIGHTSLEEP will have no effect
|
|
* 0b1..memory power saving features enabled, set SHUTDOWN/DEEPSLEEP/LIGHTSLEEP(priority high to low) to enable power saving levels
|
|
*/
|
|
#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK)
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|
#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK (0x4000U)
|
|
#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT (14U)
|
|
/*! L2_MEM_DEEPSLEEP
|
|
* 0b0..no force sleep control supported, memory deep sleep mode only entered when whole system in stop mode
|
|
* 0b1..force memory into deep sleep mode
|
|
*/
|
|
#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK)
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|
#define IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK (0xFF0000U)
|
|
#define IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT (16U)
|
|
/*! MQS_CLK_DIV
|
|
* 0b00000000..mclk frequency = hmclk frequency
|
|
* 0b00000001..mclk frequency = 1/2 * hmclk frequency
|
|
* 0b00000010..mclk frequency = 1/3 * hmclk frequency
|
|
* 0b11111111..mclk frequency = 1/256 * hmclk frequency
|
|
*/
|
|
#define IOMUXC_GPR_GPR2_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK)
|
|
#define IOMUXC_GPR_GPR2_MQS_SW_RST_MASK (0x1000000U)
|
|
#define IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT (24U)
|
|
/*! MQS_SW_RST
|
|
* 0b0..Exit software reset for MQS
|
|
* 0b1..Enable software reset for MQS
|
|
*/
|
|
#define IOMUXC_GPR_GPR2_MQS_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR2_MQS_SW_RST_MASK)
|
|
#define IOMUXC_GPR_GPR2_MQS_EN_MASK (0x2000000U)
|
|
#define IOMUXC_GPR_GPR2_MQS_EN_SHIFT (25U)
|
|
/*! MQS_EN
|
|
* 0b0..Disable MQS
|
|
* 0b1..Enable MQS
|
|
*/
|
|
#define IOMUXC_GPR_GPR2_MQS_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR2_MQS_EN_MASK)
|
|
#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK (0x4000000U)
|
|
#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT (26U)
|
|
/*! MQS_OVERSAMPLE
|
|
* 0b0..32
|
|
* 0b1..64
|
|
*/
|
|
#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK)
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|
#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK (0x10000000U)
|
|
#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT (28U)
|
|
/*! QTIMER1_TMR_CNTS_FREEZE
|
|
* 0b0..timer counter work normally
|
|
* 0b1..reset counter and ouput flags
|
|
*/
|
|
#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK)
|
|
#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK (0x20000000U)
|
|
#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT (29U)
|
|
/*! QTIMER2_TMR_CNTS_FREEZE
|
|
* 0b0..timer counter work normally
|
|
* 0b1..reset counter and ouput flags
|
|
*/
|
|
#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK)
|
|
#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK (0x40000000U)
|
|
#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT (30U)
|
|
/*! QTIMER3_TMR_CNTS_FREEZE
|
|
* 0b0..timer counter work normally
|
|
* 0b1..reset counter and ouput flags
|
|
*/
|
|
#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK)
|
|
#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK (0x80000000U)
|
|
#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT (31U)
|
|
/*! QTIMER4_TMR_CNTS_FREEZE
|
|
* 0b0..timer counter work normally
|
|
* 0b1..reset counter and ouput flags
|
|
*/
|
|
#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GPR3 - GPR3 General Purpose Register */
|
|
/*! @{ */
|
|
#define IOMUXC_GPR_GPR3_OCRAM_CTL_MASK (0xFU)
|
|
#define IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT (0U)
|
|
#define IOMUXC_GPR_GPR3_OCRAM_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_CTL_MASK)
|
|
#define IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK (0x10U)
|
|
#define IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT (4U)
|
|
/*! DCP_KEY_SEL
|
|
* 0b0..Select [127:0] from snvs/ocotp key as dcp key
|
|
* 0b1..Select [255:128] from snvs/ocotp key as dcp key
|
|
*/
|
|
#define IOMUXC_GPR_GPR3_DCP_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT)) & IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK)
|
|
#define IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK (0xF0000U)
|
|
#define IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT (16U)
|
|
/*! OCRAM_STATUS
|
|
* 0b0000..read data pipeline configuration valid
|
|
* 0b0001..read data pipeline control bit changed
|
|
*/
|
|
#define IOMUXC_GPR_GPR3_OCRAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GPR4 - GPR4 General Purpose Register */
|
|
/*! @{ */
|
|
#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK (0x1U)
|
|
#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT (0U)
|
|
/*! EDMA_STOP_REQ
|
|
* 0b0..stop request off
|
|
* 0b1..stop request on
|
|
*/
|
|
#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK)
|
|
#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK (0x2U)
|
|
#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT (1U)
|
|
/*! CAN1_STOP_REQ
|
|
* 0b0..stop request off
|
|
* 0b1..stop request on
|
|
*/
|
|
#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK)
|
|
#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK (0x4U)
|
|
#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT (2U)
|
|
/*! CAN2_STOP_REQ
|
|
* 0b0..stop request off
|
|
* 0b1..stop request on
|
|
*/
|
|
#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK)
|
|
#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK (0x8U)
|
|
#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT (3U)
|
|
/*! TRNG_STOP_REQ
|
|
* 0b0..stop request off
|
|
* 0b1..stop request on
|
|
*/
|
|
#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK)
|
|
#define IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK (0x10U)
|
|
#define IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT (4U)
|
|
/*! ENET_STOP_REQ
|
|
* 0b0..stop request off
|
|
* 0b1..stop request on
|
|
*/
|
|
#define IOMUXC_GPR_GPR4_ENET_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK)
|
|
#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK (0x20U)
|
|
#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT (5U)
|
|
/*! SAI1_STOP_REQ
|
|
* 0b0..stop request off
|
|
* 0b1..stop request on
|
|
*/
|
|
#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK)
|
|
#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK (0x40U)
|
|
#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT (6U)
|
|
/*! SAI2_STOP_REQ
|
|
* 0b0..stop request off
|
|
* 0b1..stop request on
|
|
*/
|
|
#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK)
|
|
#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK (0x80U)
|
|
#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT (7U)
|
|
/*! SAI3_STOP_REQ
|
|
* 0b0..stop request off
|
|
* 0b1..stop request on
|
|
*/
|
|
#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK)
|
|
#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK (0x200U)
|
|
#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT (9U)
|
|
/*! SEMC_STOP_REQ
|
|
* 0b0..stop request off
|
|
* 0b1..stop request on
|
|
*/
|
|
#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK)
|
|
#define IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK (0x400U)
|
|
#define IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT (10U)
|
|
/*! PIT_STOP_REQ
|
|
* 0b0..stop request off
|
|
* 0b1..stop request on
|
|
*/
|
|
#define IOMUXC_GPR_GPR4_PIT_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK)
|
|
#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK (0x800U)
|
|
#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT (11U)
|
|
/*! FLEXSPI_STOP_REQ
|
|
* 0b0..stop request off
|
|
* 0b1..stop request on
|
|
*/
|
|
#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK)
|
|
#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK (0x1000U)
|
|
#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT (12U)
|
|
/*! FLEXIO1_STOP_REQ
|
|
* 0b0..stop request off
|
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* 0b1..stop request on
|
|
*/
|
|
#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK)
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#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK (0x2000U)
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#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT (13U)
|
|
/*! FLEXIO2_STOP_REQ
|
|
* 0b0..stop request off
|
|
* 0b1..stop request on
|
|
*/
|
|
#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK)
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#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK (0x10000U)
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|
#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT (16U)
|
|
/*! EDMA_STOP_ACK
|
|
* 0b0..EDMA stop acknowledge is not asserted
|
|
* 0b1..EDMA stop acknowledge is asserted (EDMA is in STOP mode).
|
|
*/
|
|
#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK)
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#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK (0x20000U)
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#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT (17U)
|
|
/*! CAN1_STOP_ACK
|
|
* 0b0..CAN1 stop acknowledge is not asserted
|
|
* 0b1..CAN1 stop acknowledge is asserted
|
|
*/
|
|
#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK)
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#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK (0x40000U)
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#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT (18U)
|
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/*! CAN2_STOP_ACK
|
|
* 0b0..CAN2 stop acknowledge is not asserted
|
|
* 0b1..CAN2 stop acknowledge is asserted
|
|
*/
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|
#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK)
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#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK (0x80000U)
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#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT (19U)
|
|
/*! TRNG_STOP_ACK
|
|
* 0b0..TRNG stop acknowledge is not asserted
|
|
* 0b1..TRNG stop acknowledge is asserted
|
|
*/
|
|
#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK)
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#define IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK (0x100000U)
|
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#define IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT (20U)
|
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/*! ENET_STOP_ACK
|
|
* 0b0..ENET stop acknowledge is not asserted
|
|
* 0b1..ENET stop acknowledge is asserted
|
|
*/
|
|
#define IOMUXC_GPR_GPR4_ENET_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK)
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#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK (0x200000U)
|
|
#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT (21U)
|
|
/*! SAI1_STOP_ACK
|
|
* 0b0..SAI1 stop acknowledge is not asserted
|
|
* 0b1..SAI1 stop acknowledge is asserted
|
|
*/
|
|
#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK)
|
|
#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK (0x400000U)
|
|
#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT (22U)
|
|
/*! SAI2_STOP_ACK
|
|
* 0b0..SAI2 stop acknowledge is not asserted
|
|
* 0b1..SAI2 stop acknowledge is asserted
|
|
*/
|
|
#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK)
|
|
#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK (0x800000U)
|
|
#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT (23U)
|
|
/*! SAI3_STOP_ACK
|
|
* 0b0..SAI3 stop acknowledge is not asserted
|
|
* 0b1..SAI3 stop acknowledge is asserted
|
|
*/
|
|
#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK)
|
|
#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK (0x2000000U)
|
|
#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT (25U)
|
|
/*! SEMC_STOP_ACK
|
|
* 0b0..SEMC stop acknowledge is not asserted
|
|
* 0b1..SEMC stop acknowledge is asserted
|
|
*/
|
|
#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK)
|
|
#define IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK (0x4000000U)
|
|
#define IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT (26U)
|
|
/*! PIT_STOP_ACK
|
|
* 0b0..PIT stop acknowledge is not asserted
|
|
* 0b1..PIT stop acknowledge is asserted
|
|
*/
|
|
#define IOMUXC_GPR_GPR4_PIT_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK)
|
|
#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK (0x8000000U)
|
|
#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT (27U)
|
|
/*! FLEXSPI_STOP_ACK
|
|
* 0b0..FLEXSPI stop acknowledge is not asserted
|
|
* 0b1..FLEXSPI stop acknowledge is asserted
|
|
*/
|
|
#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK)
|
|
#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK (0x10000000U)
|
|
#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT (28U)
|
|
/*! FLEXIO1_STOP_ACK
|
|
* 0b0..FLEXIO1 stop acknowledge is not asserted
|
|
* 0b1..FLEXIO1 stop acknowledge is asserted
|
|
*/
|
|
#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK)
|
|
#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK (0x20000000U)
|
|
#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT (29U)
|
|
/*! FLEXIO2_STOP_ACK
|
|
* 0b0..FLEXIO2 stop acknowledge is not asserted
|
|
* 0b1..FLEXIO2 stop acknowledge is asserted (FLEXIO2 is in STOP mode)
|
|
*/
|
|
#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GPR5 - GPR5 General Purpose Register */
|
|
/*! @{ */
|
|
#define IOMUXC_GPR_GPR5_WDOG1_MASK_MASK (0x40U)
|
|
#define IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT (6U)
|
|
/*! WDOG1_MASK
|
|
* 0b0..WDOG1 Timeout behaves normally
|
|
* 0b1..WDOG1 Timeout is masked
|
|
*/
|
|
#define IOMUXC_GPR_GPR5_WDOG1_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG1_MASK_MASK)
|
|
#define IOMUXC_GPR_GPR5_WDOG2_MASK_MASK (0x80U)
|
|
#define IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT (7U)
|
|
/*! WDOG2_MASK
|
|
* 0b0..WDOG2 Timeout behaves normally
|
|
* 0b1..WDOG2 Timeout is masked
|
|
*/
|
|
#define IOMUXC_GPR_GPR5_WDOG2_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG2_MASK_MASK)
|
|
#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK (0x800000U)
|
|
#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT (23U)
|
|
/*! GPT2_CAPIN1_SEL
|
|
* 0b0..source from pad
|
|
* 0b1..source from enet1.ipp_do_mac0_timer[3]
|
|
*/
|
|
#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK)
|
|
#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK (0x2000000U)
|
|
#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT (25U)
|
|
/*! ENET_EVENT3IN_SEL
|
|
* 0b0..event3 source input from pad
|
|
* 0b1..event3 source input from gpt2.ipp_do_cmpout1
|
|
*/
|
|
#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK)
|
|
#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK (0x10000000U)
|
|
#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT (28U)
|
|
/*! VREF_1M_CLK_GPT1
|
|
* 0b0..GPT1 ipg_clk_highfreq driven by IPG_PERCLK
|
|
* 0b1..GPT1 ipg_clk_highfreq driven by anatop 1 MHz clock
|
|
*/
|
|
#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK)
|
|
#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK (0x20000000U)
|
|
#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT (29U)
|
|
/*! VREF_1M_CLK_GPT2
|
|
* 0b0..GPT2 ipg_clk_highfreq driven by IPG_PERCLK
|
|
* 0b1..GPT2 ipg_clk_highfreq driven by anatop 1 MHz clock
|
|
*/
|
|
#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GPR6 - GPR6 General Purpose Register */
|
|
/*! @{ */
|
|
#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK (0x1U)
|
|
#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT (0U)
|
|
/*! QTIMER1_TRM0_INPUT_SEL
|
|
* 0b0..input from IOMUX
|
|
* 0b1..input from XBAR
|
|
*/
|
|
#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK)
|
|
#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK (0x2U)
|
|
#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT (1U)
|
|
/*! QTIMER1_TRM1_INPUT_SEL
|
|
* 0b0..input from IOMUX
|
|
* 0b1..input from XBAR
|
|
*/
|
|
#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK)
|
|
#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK (0x4U)
|
|
#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT (2U)
|
|
/*! QTIMER1_TRM2_INPUT_SEL
|
|
* 0b0..input from IOMUX
|
|
* 0b1..input from XBAR
|
|
*/
|
|
#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK)
|
|
#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK (0x8U)
|
|
#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT (3U)
|
|
/*! QTIMER1_TRM3_INPUT_SEL
|
|
* 0b0..input from IOMUX
|
|
* 0b1..input from XBAR
|
|
*/
|
|
#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK)
|
|
#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK (0x10U)
|
|
#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT (4U)
|
|
/*! QTIMER2_TRM0_INPUT_SEL
|
|
* 0b0..input from IOMUX
|
|
* 0b1..input from XBAR
|
|
*/
|
|
#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK)
|
|
#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK (0x20U)
|
|
#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT (5U)
|
|
/*! QTIMER2_TRM1_INPUT_SEL
|
|
* 0b0..input from IOMUX
|
|
* 0b1..input from XBAR
|
|
*/
|
|
#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK)
|
|
#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK (0x40U)
|
|
#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT (6U)
|
|
/*! QTIMER2_TRM2_INPUT_SEL
|
|
* 0b0..input from IOMUX
|
|
* 0b1..input from XBAR
|
|
*/
|
|
#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK)
|
|
#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK (0x80U)
|
|
#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT (7U)
|
|
/*! QTIMER2_TRM3_INPUT_SEL
|
|
* 0b0..input from IOMUX
|
|
* 0b1..input from XBAR
|
|
*/
|
|
#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK)
|
|
#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK (0x100U)
|
|
#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT (8U)
|
|
/*! QTIMER3_TRM0_INPUT_SEL
|
|
* 0b0..input from IOMUX
|
|
* 0b1..input from XBAR
|
|
*/
|
|
#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK)
|
|
#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK (0x200U)
|
|
#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT (9U)
|
|
/*! QTIMER3_TRM1_INPUT_SEL
|
|
* 0b0..input from IOMUX
|
|
* 0b1..input from XBAR
|
|
*/
|
|
#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK)
|
|
#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK (0x400U)
|
|
#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT (10U)
|
|
/*! QTIMER3_TRM2_INPUT_SEL
|
|
* 0b0..input from IOMUX
|
|
* 0b1..input from XBAR
|
|
*/
|
|
#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK)
|
|
#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK (0x800U)
|
|
#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT (11U)
|
|
/*! QTIMER3_TRM3_INPUT_SEL
|
|
* 0b0..input from IOMUX
|
|
* 0b1..input from XBAR
|
|
*/
|
|
#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK)
|
|
#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK (0x1000U)
|
|
#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT (12U)
|
|
/*! QTIMER4_TRM0_INPUT_SEL
|
|
* 0b0..input from IOMUX
|
|
* 0b1..input from XBAR
|
|
*/
|
|
#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK)
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#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK (0x2000U)
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#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT (13U)
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/*! QTIMER4_TRM1_INPUT_SEL
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* 0b0..input from IOMUX
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* 0b1..input from XBAR
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*/
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#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK)
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#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK (0x4000U)
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#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT (14U)
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/*! QTIMER4_TRM2_INPUT_SEL
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* 0b0..input from IOMUX
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* 0b1..input from XBAR
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*/
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#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK)
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#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK (0x8000U)
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#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT (15U)
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/*! QTIMER4_TRM3_INPUT_SEL
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* 0b0..input from IOMUX
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* 0b1..input from XBAR
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*/
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#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK)
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#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK (0x10000U)
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#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT (16U)
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/*! IOMUXC_XBAR_DIR_SEL_4
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* 0b0..XBAR_INOUT as input
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* 0b1..XBAR_INOUT as output
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*/
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#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK)
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#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK (0x20000U)
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#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT (17U)
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/*! IOMUXC_XBAR_DIR_SEL_5
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* 0b0..XBAR_INOUT as input
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* 0b1..XBAR_INOUT as output
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*/
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#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK)
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#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK (0x40000U)
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#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT (18U)
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/*! IOMUXC_XBAR_DIR_SEL_6
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* 0b0..XBAR_INOUT as input
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* 0b1..XBAR_INOUT as output
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*/
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#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK)
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#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK (0x80000U)
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#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT (19U)
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/*! IOMUXC_XBAR_DIR_SEL_7
|
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* 0b0..XBAR_INOUT as input
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* 0b1..XBAR_INOUT as output
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*/
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#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK)
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#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK (0x100000U)
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#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT (20U)
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/*! IOMUXC_XBAR_DIR_SEL_8
|
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* 0b0..XBAR_INOUT as input
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* 0b1..XBAR_INOUT as output
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*/
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#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK)
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#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK (0x200000U)
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#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT (21U)
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/*! IOMUXC_XBAR_DIR_SEL_9
|
|
* 0b0..XBAR_INOUT as input
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* 0b1..XBAR_INOUT as output
|
|
*/
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#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK)
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#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK (0x400000U)
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#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT (22U)
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/*! IOMUXC_XBAR_DIR_SEL_10
|
|
* 0b0..XBAR_INOUT as input
|
|
* 0b1..XBAR_INOUT as output
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|
*/
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#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK)
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#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK (0x800000U)
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#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT (23U)
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/*! IOMUXC_XBAR_DIR_SEL_11
|
|
* 0b0..XBAR_INOUT as input
|
|
* 0b1..XBAR_INOUT as output
|
|
*/
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#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK)
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#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK (0x1000000U)
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#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT (24U)
|
|
/*! IOMUXC_XBAR_DIR_SEL_12
|
|
* 0b0..XBAR_INOUT as input
|
|
* 0b1..XBAR_INOUT as output
|
|
*/
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#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK)
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#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK (0x2000000U)
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#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT (25U)
|
|
/*! IOMUXC_XBAR_DIR_SEL_13
|
|
* 0b0..XBAR_INOUT as input
|
|
* 0b1..XBAR_INOUT as output
|
|
*/
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|
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK)
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#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK (0x4000000U)
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#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT (26U)
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|
/*! IOMUXC_XBAR_DIR_SEL_14
|
|
* 0b0..XBAR_INOUT as input
|
|
* 0b1..XBAR_INOUT as output
|
|
*/
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#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK)
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#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK (0x8000000U)
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#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT (27U)
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/*! IOMUXC_XBAR_DIR_SEL_15
|
|
* 0b0..XBAR_INOUT as input
|
|
* 0b1..XBAR_INOUT as output
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|
*/
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|
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK)
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#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK (0x10000000U)
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#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT (28U)
|
|
/*! IOMUXC_XBAR_DIR_SEL_16
|
|
* 0b0..XBAR_INOUT as input
|
|
* 0b1..XBAR_INOUT as output
|
|
*/
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|
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK)
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#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK (0x20000000U)
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|
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT (29U)
|
|
/*! IOMUXC_XBAR_DIR_SEL_17
|
|
* 0b0..XBAR_INOUT as input
|
|
* 0b1..XBAR_INOUT as output
|
|
*/
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|
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK)
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#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK (0x40000000U)
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|
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT (30U)
|
|
/*! IOMUXC_XBAR_DIR_SEL_18
|
|
* 0b0..XBAR_INOUT as input
|
|
* 0b1..XBAR_INOUT as output
|
|
*/
|
|
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK)
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|
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK (0x80000000U)
|
|
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT (31U)
|
|
/*! IOMUXC_XBAR_DIR_SEL_19
|
|
* 0b0..XBAR_INOUT as input
|
|
* 0b1..XBAR_INOUT as output
|
|
*/
|
|
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK)
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/*! @} */
|
|
|
|
/*! @name GPR7 - GPR7 General Purpose Register */
|
|
/*! @{ */
|
|
#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK (0x1U)
|
|
#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT (0U)
|
|
/*! LPI2C1_STOP_REQ
|
|
* 0b0..stop request off
|
|
* 0b1..stop request on
|
|
*/
|
|
#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK)
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|
#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK (0x2U)
|
|
#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT (1U)
|
|
/*! LPI2C2_STOP_REQ
|
|
* 0b0..stop request off
|
|
* 0b1..stop request on
|
|
*/
|
|
#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK)
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|
#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK (0x4U)
|
|
#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT (2U)
|
|
/*! LPI2C3_STOP_REQ
|
|
* 0b0..stop request off
|
|
* 0b1..stop request on
|
|
*/
|
|
#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK)
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|
#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK (0x8U)
|
|
#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT (3U)
|
|
/*! LPI2C4_STOP_REQ
|
|
* 0b0..stop request off
|
|
* 0b1..stop request on
|
|
*/
|
|
#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK)
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|
#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK (0x10U)
|
|
#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT (4U)
|
|
/*! LPSPI1_STOP_REQ
|
|
* 0b0..stop request off
|
|
* 0b1..stop request on
|
|
*/
|
|
#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK)
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|
#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK (0x20U)
|
|
#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT (5U)
|
|
/*! LPSPI2_STOP_REQ
|
|
* 0b0..stop request off
|
|
* 0b1..stop request on
|
|
*/
|
|
#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK)
|
|
#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK (0x40U)
|
|
#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT (6U)
|
|
/*! LPSPI3_STOP_REQ
|
|
* 0b0..stop request off
|
|
* 0b1..stop request on
|
|
*/
|
|
#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK)
|
|
#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK (0x80U)
|
|
#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT (7U)
|
|
/*! LPSPI4_STOP_REQ
|
|
* 0b0..stop request off
|
|
* 0b1..stop request on
|
|
*/
|
|
#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK)
|
|
#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK (0x100U)
|
|
#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT (8U)
|
|
/*! LPUART1_STOP_REQ
|
|
* 0b0..stop request off
|
|
* 0b1..stop request on
|
|
*/
|
|
#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK)
|
|
#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK (0x200U)
|
|
#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT (9U)
|
|
/*! LPUART2_STOP_REQ
|
|
* 0b0..stop request off
|
|
* 0b1..stop request on
|
|
*/
|
|
#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK)
|
|
#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK (0x400U)
|
|
#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT (10U)
|
|
/*! LPUART3_STOP_REQ
|
|
* 0b0..stop request off
|
|
* 0b1..stop request on
|
|
*/
|
|
#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK)
|
|
#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK (0x800U)
|
|
#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT (11U)
|
|
/*! LPUART4_STOP_REQ
|
|
* 0b0..stop request off
|
|
* 0b1..stop request on
|
|
*/
|
|
#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK)
|
|
#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK (0x1000U)
|
|
#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT (12U)
|
|
/*! LPUART5_STOP_REQ
|
|
* 0b0..stop request off
|
|
* 0b1..stop request on
|
|
*/
|
|
#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK)
|
|
#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK (0x2000U)
|
|
#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT (13U)
|
|
/*! LPUART6_STOP_REQ
|
|
* 0b0..stop request off
|
|
* 0b1..stop request on
|
|
*/
|
|
#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK)
|
|
#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK (0x4000U)
|
|
#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT (14U)
|
|
/*! LPUART7_STOP_REQ
|
|
* 0b0..stop request off
|
|
* 0b1..stop request on
|
|
*/
|
|
#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK)
|
|
#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK (0x8000U)
|
|
#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT (15U)
|
|
/*! LPUART8_STOP_REQ
|
|
* 0b0..stop request off
|
|
* 0b1..stop request on
|
|
*/
|
|
#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK)
|
|
#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK (0x10000U)
|
|
#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT (16U)
|
|
/*! LPI2C1_STOP_ACK
|
|
* 0b0..stop acknowledge is not asserted
|
|
* 0b1..stop acknowledge is asserted (the module is in Stop mode)
|
|
*/
|
|
#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK)
|
|
#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK (0x20000U)
|
|
#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT (17U)
|
|
/*! LPI2C2_STOP_ACK
|
|
* 0b0..stop acknowledge is not asserted
|
|
* 0b1..stop acknowledge is asserted
|
|
*/
|
|
#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK)
|
|
#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK (0x40000U)
|
|
#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT (18U)
|
|
/*! LPI2C3_STOP_ACK
|
|
* 0b0..stop acknowledge is not asserted
|
|
* 0b1..stop acknowledge is asserted
|
|
*/
|
|
#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK)
|
|
#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK (0x80000U)
|
|
#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT (19U)
|
|
/*! LPI2C4_STOP_ACK
|
|
* 0b0..stop acknowledge is not asserted
|
|
* 0b1..stop acknowledge is asserted
|
|
*/
|
|
#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK)
|
|
#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK (0x100000U)
|
|
#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT (20U)
|
|
/*! LPSPI1_STOP_ACK
|
|
* 0b0..stop acknowledge is not asserted
|
|
* 0b1..stop acknowledge is asserted
|
|
*/
|
|
#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK)
|
|
#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK (0x200000U)
|
|
#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT (21U)
|
|
/*! LPSPI2_STOP_ACK
|
|
* 0b0..stop acknowledge is not asserted
|
|
* 0b1..stop acknowledge is asserted
|
|
*/
|
|
#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK)
|
|
#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK (0x400000U)
|
|
#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT (22U)
|
|
/*! LPSPI3_STOP_ACK
|
|
* 0b0..stop acknowledge is not asserted
|
|
* 0b1..stop acknowledge is asserted
|
|
*/
|
|
#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK)
|
|
#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK (0x800000U)
|
|
#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT (23U)
|
|
/*! LPSPI4_STOP_ACK
|
|
* 0b0..stop acknowledge is not asserted
|
|
* 0b1..stop acknowledge is asserted
|
|
*/
|
|
#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK)
|
|
#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK (0x1000000U)
|
|
#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT (24U)
|
|
/*! LPUART1_STOP_ACK
|
|
* 0b0..stop acknowledge is not asserted
|
|
* 0b1..stop acknowledge is asserted
|
|
*/
|
|
#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK)
|
|
#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK (0x2000000U)
|
|
#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT (25U)
|
|
/*! LPUART2_STOP_ACK
|
|
* 0b0..stop acknowledge is not asserted
|
|
* 0b1..stop acknowledge is asserted
|
|
*/
|
|
#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK)
|
|
#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK (0x4000000U)
|
|
#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT (26U)
|
|
/*! LPUART3_STOP_ACK
|
|
* 0b0..stop acknowledge is not asserted
|
|
* 0b1..stop acknowledge is asserted
|
|
*/
|
|
#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK)
|
|
#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK (0x8000000U)
|
|
#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT (27U)
|
|
/*! LPUART4_STOP_ACK
|
|
* 0b0..stop acknowledge is not asserted
|
|
* 0b1..stop acknowledge is asserted
|
|
*/
|
|
#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK)
|
|
#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK (0x10000000U)
|
|
#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT (28U)
|
|
/*! LPUART5_STOP_ACK
|
|
* 0b0..stop acknowledge is not asserted
|
|
* 0b1..stop acknowledge is asserted
|
|
*/
|
|
#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK)
|
|
#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK (0x20000000U)
|
|
#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT (29U)
|
|
/*! LPUART6_STOP_ACK
|
|
* 0b0..stop acknowledge is not asserted
|
|
* 0b1..stop acknowledge is asserted
|
|
*/
|
|
#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK)
|
|
#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK (0x40000000U)
|
|
#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT (30U)
|
|
/*! LPUART7_STOP_ACK
|
|
* 0b0..stop acknowledge is not asserted
|
|
* 0b1..stop acknowledge is asserted
|
|
*/
|
|
#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK)
|
|
#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK (0x80000000U)
|
|
#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT (31U)
|
|
/*! LPUART8_STOP_ACK
|
|
* 0b0..stop acknowledge is not asserted
|
|
* 0b1..stop acknowledge is asserted (the module is in Stop mode)
|
|
*/
|
|
#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GPR8 - GPR8 General Purpose Register */
|
|
/*! @{ */
|
|
#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK (0x1U)
|
|
#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT (0U)
|
|
/*! LPI2C1_IPG_STOP_MODE
|
|
* 0b0..the module is functional in Stop mode
|
|
* 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
|
|
*/
|
|
#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK)
|
|
#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK (0x2U)
|
|
#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT (1U)
|
|
/*! LPI2C1_IPG_DOZE
|
|
* 0b0..not in doze mode
|
|
* 0b1..in doze mode
|
|
*/
|
|
#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK)
|
|
#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK (0x4U)
|
|
#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT (2U)
|
|
/*! LPI2C2_IPG_STOP_MODE
|
|
* 0b0..the module is functional in Stop mode
|
|
* 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
|
|
*/
|
|
#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK)
|
|
#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK (0x8U)
|
|
#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT (3U)
|
|
/*! LPI2C2_IPG_DOZE
|
|
* 0b0..not in doze mode
|
|
* 0b1..in doze mode
|
|
*/
|
|
#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK)
|
|
#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK (0x10U)
|
|
#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT (4U)
|
|
/*! LPI2C3_IPG_STOP_MODE
|
|
* 0b0..the module is functional in Stop mode
|
|
* 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
|
|
*/
|
|
#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK)
|
|
#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK (0x20U)
|
|
#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT (5U)
|
|
/*! LPI2C3_IPG_DOZE
|
|
* 0b0..not in doze mode
|
|
* 0b1..in doze mode
|
|
*/
|
|
#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK)
|
|
#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK (0x40U)
|
|
#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT (6U)
|
|
/*! LPI2C4_IPG_STOP_MODE
|
|
* 0b0..the module is functional in Stop mode
|
|
* 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
|
|
*/
|
|
#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK)
|
|
#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK (0x80U)
|
|
#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT (7U)
|
|
/*! LPI2C4_IPG_DOZE
|
|
* 0b0..not in doze mode
|
|
* 0b1..in doze mode
|
|
*/
|
|
#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK)
|
|
#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK (0x100U)
|
|
#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT (8U)
|
|
/*! LPSPI1_IPG_STOP_MODE
|
|
* 0b0..the module is functional in Stop mode
|
|
* 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
|
|
*/
|
|
#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK)
|
|
#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK (0x200U)
|
|
#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT (9U)
|
|
/*! LPSPI1_IPG_DOZE
|
|
* 0b0..not in doze mode
|
|
* 0b1..in doze mode
|
|
*/
|
|
#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK)
|
|
#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK (0x400U)
|
|
#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT (10U)
|
|
/*! LPSPI2_IPG_STOP_MODE
|
|
* 0b0..the module is functional in Stop mode
|
|
* 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
|
|
*/
|
|
#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK)
|
|
#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK (0x800U)
|
|
#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT (11U)
|
|
/*! LPSPI2_IPG_DOZE
|
|
* 0b0..not in doze mode
|
|
* 0b1..in doze mode
|
|
*/
|
|
#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK)
|
|
#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK (0x1000U)
|
|
#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT (12U)
|
|
/*! LPSPI3_IPG_STOP_MODE
|
|
* 0b0..the module is functional in Stop mode
|
|
* 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
|
|
*/
|
|
#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK)
|
|
#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK (0x2000U)
|
|
#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT (13U)
|
|
/*! LPSPI3_IPG_DOZE
|
|
* 0b0..not in doze mode
|
|
* 0b1..in doze mode
|
|
*/
|
|
#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK)
|
|
#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK (0x4000U)
|
|
#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT (14U)
|
|
/*! LPSPI4_IPG_STOP_MODE
|
|
* 0b0..the module is functional in Stop mode
|
|
* 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
|
|
*/
|
|
#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK)
|
|
#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK (0x8000U)
|
|
#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT (15U)
|
|
/*! LPSPI4_IPG_DOZE
|
|
* 0b0..not in doze mode
|
|
* 0b1..in doze mode
|
|
*/
|
|
#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK)
|
|
#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK (0x10000U)
|
|
#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT (16U)
|
|
/*! LPUART1_IPG_STOP_MODE
|
|
* 0b0..the module is functional in Stop mode
|
|
* 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
|
|
*/
|
|
#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK)
|
|
#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK (0x20000U)
|
|
#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT (17U)
|
|
/*! LPUART1_IPG_DOZE
|
|
* 0b0..not in doze mode
|
|
* 0b1..in doze mode
|
|
*/
|
|
#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK)
|
|
#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK (0x40000U)
|
|
#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT (18U)
|
|
/*! LPUART2_IPG_STOP_MODE
|
|
* 0b0..the module is functional in Stop mode
|
|
* 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
|
|
*/
|
|
#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK)
|
|
#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK (0x80000U)
|
|
#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT (19U)
|
|
/*! LPUART2_IPG_DOZE
|
|
* 0b0..not in doze mode
|
|
* 0b1..in doze mode
|
|
*/
|
|
#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK)
|
|
#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK (0x100000U)
|
|
#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT (20U)
|
|
/*! LPUART3_IPG_STOP_MODE
|
|
* 0b0..the module is functional in Stop mode
|
|
* 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
|
|
*/
|
|
#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK)
|
|
#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK (0x200000U)
|
|
#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT (21U)
|
|
/*! LPUART3_IPG_DOZE
|
|
* 0b0..not in doze mode
|
|
* 0b1..in doze mode
|
|
*/
|
|
#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK)
|
|
#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK (0x400000U)
|
|
#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT (22U)
|
|
/*! LPUART4_IPG_STOP_MODE
|
|
* 0b0..the module is functional in Stop mode
|
|
* 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
|
|
*/
|
|
#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK)
|
|
#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK (0x800000U)
|
|
#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT (23U)
|
|
/*! LPUART4_IPG_DOZE
|
|
* 0b0..not in doze mode
|
|
* 0b1..in doze mode
|
|
*/
|
|
#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK)
|
|
#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK (0x1000000U)
|
|
#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT (24U)
|
|
/*! LPUART5_IPG_STOP_MODE
|
|
* 0b0..the module is functional in Stop mode
|
|
* 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
|
|
*/
|
|
#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK)
|
|
#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK (0x2000000U)
|
|
#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT (25U)
|
|
/*! LPUART5_IPG_DOZE
|
|
* 0b0..not in doze mode
|
|
* 0b1..in doze mode
|
|
*/
|
|
#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK)
|
|
#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK (0x4000000U)
|
|
#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT (26U)
|
|
/*! LPUART6_IPG_STOP_MODE
|
|
* 0b0..the module is functional in Stop mode
|
|
* 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
|
|
*/
|
|
#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK)
|
|
#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK (0x8000000U)
|
|
#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT (27U)
|
|
/*! LPUART6_IPG_DOZE
|
|
* 0b0..not in doze mode
|
|
* 0b1..in doze mode
|
|
*/
|
|
#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK)
|
|
#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK (0x10000000U)
|
|
#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT (28U)
|
|
/*! LPUART7_IPG_STOP_MODE
|
|
* 0b0..the module is functional in Stop mode
|
|
* 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
|
|
*/
|
|
#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK)
|
|
#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK (0x20000000U)
|
|
#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT (29U)
|
|
/*! LPUART7_IPG_DOZE
|
|
* 0b0..not in doze mode
|
|
* 0b1..in doze mode
|
|
*/
|
|
#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK)
|
|
#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK (0x40000000U)
|
|
#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT (30U)
|
|
/*! LPUART8_IPG_STOP_MODE
|
|
* 0b0..the module is functional in Stop mode
|
|
* 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
|
|
*/
|
|
#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK)
|
|
#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK (0x80000000U)
|
|
#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT (31U)
|
|
/*! LPUART8_IPG_DOZE
|
|
* 0b0..not in doze mode
|
|
* 0b1..in doze mode
|
|
*/
|
|
#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GPR10 - GPR10 General Purpose Register */
|
|
/*! @{ */
|
|
#define IOMUXC_GPR_GPR10_NIDEN_MASK (0x1U)
|
|
#define IOMUXC_GPR_GPR10_NIDEN_SHIFT (0U)
|
|
/*! NIDEN
|
|
* 0b0..Debug turned off.
|
|
* 0b1..Debug enabled (default).
|
|
*/
|
|
#define IOMUXC_GPR_GPR10_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_NIDEN_MASK)
|
|
#define IOMUXC_GPR_GPR10_DBG_EN_MASK (0x2U)
|
|
#define IOMUXC_GPR_GPR10_DBG_EN_SHIFT (1U)
|
|
/*! DBG_EN
|
|
* 0b0..Debug turned off.
|
|
* 0b1..Debug enabled (default).
|
|
*/
|
|
#define IOMUXC_GPR_GPR10_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_DBG_EN_MASK)
|
|
#define IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK (0x4U)
|
|
#define IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT (2U)
|
|
/*! SEC_ERR_RESP
|
|
* 0b0..OKEY response
|
|
* 0b1..SLVError (default)
|
|
*/
|
|
#define IOMUXC_GPR_GPR10_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK)
|
|
#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x10U)
|
|
#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (4U)
|
|
/*! DCPKEY_OCOTP_OR_KEYMUX
|
|
* 0b0..Select key from Key MUX (SNVS/OTPMK).
|
|
* 0b1..Select key from OCOTP (SW_GP2).
|
|
*/
|
|
#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK)
|
|
#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK (0x100U)
|
|
#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT (8U)
|
|
/*! OCRAM_TZ_EN
|
|
* 0b0..The TrustZone feature is disabled. Entire OCRAM space is available for all access types (secure/non-secure/user/supervisor).
|
|
* 0b1..The TrustZone feature is enabled. Access to address in the range specified by [ENDADDR:STARTADDR] follows the execution mode access policy described in CSU chapter.
|
|
*/
|
|
#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK)
|
|
#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK (0xFE00U)
|
|
#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT (9U)
|
|
#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK)
|
|
#define IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK (0x10000U)
|
|
#define IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT (16U)
|
|
/*! LOCK_NIDEN
|
|
* 0b0..Field is not locked
|
|
* 0b1..Field is locked (read access only)
|
|
*/
|
|
#define IOMUXC_GPR_GPR10_LOCK_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK)
|
|
#define IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK (0x20000U)
|
|
#define IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT (17U)
|
|
/*! LOCK_DBG_EN
|
|
* 0b0..Field is not locked
|
|
* 0b1..Field is locked (read access only)
|
|
*/
|
|
#define IOMUXC_GPR_GPR10_LOCK_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK)
|
|
#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK (0x40000U)
|
|
#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT (18U)
|
|
/*! LOCK_SEC_ERR_RESP
|
|
* 0b0..Field is not locked
|
|
* 0b1..Field is locked (read access only)
|
|
*/
|
|
#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK)
|
|
#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x100000U)
|
|
#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (20U)
|
|
/*! LOCK_DCPKEY_OCOTP_OR_KEYMUX
|
|
* 0b0..Field is not locked
|
|
* 0b1..Field is locked (read access only)
|
|
*/
|
|
#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK)
|
|
#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK (0x1000000U)
|
|
#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT (24U)
|
|
/*! LOCK_OCRAM_TZ_EN
|
|
* 0b0..Field is not locked
|
|
* 0b1..Field is locked (read access only)
|
|
*/
|
|
#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK)
|
|
#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK (0xFE000000U)
|
|
#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT (25U)
|
|
/*! LOCK_OCRAM_TZ_ADDR
|
|
* 0b0000000..Field is not locked
|
|
* 0b0000001..Field is locked (read access only)
|
|
*/
|
|
#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GPR11 - GPR11 General Purpose Register */
|
|
/*! @{ */
|
|
#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK (0x3U)
|
|
#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT (0U)
|
|
/*! M7_APC_AC_R0_CTRL
|
|
* 0b00..No access protection
|
|
* 0b01..M7 debug protection enabled
|
|
* 0b10..FlexSPI access protection
|
|
* 0b11..Both M7 debug and FlexSPI access are protected
|
|
*/
|
|
#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK)
|
|
#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK (0xCU)
|
|
#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT (2U)
|
|
/*! M7_APC_AC_R1_CTRL
|
|
* 0b00..No access protection
|
|
* 0b01..M7 debug protection enabled
|
|
* 0b10..FlexSPI access protection
|
|
* 0b11..Both M7 debug and FlexSPI access are protected
|
|
*/
|
|
#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK)
|
|
#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK (0x30U)
|
|
#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT (4U)
|
|
/*! M7_APC_AC_R2_CTRL
|
|
* 0b00..No access protection
|
|
* 0b01..M7 debug protection enabled
|
|
* 0b10..FlexSPI access protection
|
|
* 0b11..Both M7 debug and FlexSPI access are protected
|
|
*/
|
|
#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK)
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#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK (0xC0U)
|
|
#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT (6U)
|
|
/*! M7_APC_AC_R3_CTRL
|
|
* 0b00..No access protection
|
|
* 0b01..M7 debug protection enabled
|
|
* 0b10..FlexSPI access protection
|
|
* 0b11..Both M7 debug and FlexSPI access are protected
|
|
*/
|
|
#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK)
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#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK (0xF00U)
|
|
#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT (8U)
|
|
#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK)
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#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK (0x30000U)
|
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#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFT (16U)
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#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK)
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#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK (0xC0000U)
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#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFT (18U)
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#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK)
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#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK (0x300000U)
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#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFT (20U)
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#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK)
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#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK (0xC00000U)
|
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#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFT (22U)
|
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#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK)
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#define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK (0xF000000U)
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#define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT (24U)
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#define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK)
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/*! @} */
|
|
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/*! @name GPR12 - GPR12 General Purpose Register */
|
|
/*! @{ */
|
|
#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK (0x1U)
|
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#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT (0U)
|
|
/*! FLEXIO1_IPG_STOP_MODE
|
|
* 0b0..FlexIO1 is functional in Stop mode.
|
|
* 0b1..When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO1 is not functional in Stop mode.
|
|
*/
|
|
#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK)
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#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK (0x2U)
|
|
#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT (1U)
|
|
/*! FLEXIO1_IPG_DOZE
|
|
* 0b0..FLEXIO1 is not in doze mode
|
|
* 0b1..FLEXIO1 is in doze mode
|
|
*/
|
|
#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK)
|
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#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK (0x4U)
|
|
#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT (2U)
|
|
/*! FLEXIO2_IPG_STOP_MODE
|
|
* 0b0..FlexIO2 is functional in Stop mode.
|
|
* 0b1..When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO2 is not functional in Stop mode.
|
|
*/
|
|
#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK)
|
|
#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK (0x8U)
|
|
#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT (3U)
|
|
/*! FLEXIO2_IPG_DOZE
|
|
* 0b0..FLEXIO2 is not in doze mode
|
|
* 0b1..FLEXIO2 is in doze mode
|
|
*/
|
|
#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK)
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|
#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK (0x10U)
|
|
#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT (4U)
|
|
/*! ACMP_IPG_STOP_MODE
|
|
* 0b0..ACMP is functional in Stop mode.
|
|
* 0b1..When this bit is equal to 1'b1 and ipg_stop is asserted, ACMP is not functional in Stop mode.
|
|
*/
|
|
#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK)
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|
/*! @} */
|
|
|
|
/*! @name GPR13 - GPR13 General Purpose Register */
|
|
/*! @{ */
|
|
#define IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK (0x1U)
|
|
#define IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT (0U)
|
|
/*! ARCACHE_USDHC
|
|
* 0b0..Cacheable attribute is off for read transactions.
|
|
* 0b1..Cacheable attribute is on for read transactions.
|
|
*/
|
|
#define IOMUXC_GPR_GPR13_ARCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK)
|
|
#define IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK (0x2U)
|
|
#define IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT (1U)
|
|
/*! AWCACHE_USDHC
|
|
* 0b0..Cacheable attribute is off for write transactions.
|
|
* 0b1..Cacheable attribute is on for write transactions.
|
|
*/
|
|
#define IOMUXC_GPR_GPR13_AWCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK)
|
|
#define IOMUXC_GPR_GPR13_CACHE_ENET_MASK (0x80U)
|
|
#define IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT (7U)
|
|
/*! CACHE_ENET
|
|
* 0b0..Cacheable attribute is off for read/write transactions.
|
|
* 0b1..Cacheable attribute is on for read/write transactions.
|
|
*/
|
|
#define IOMUXC_GPR_GPR13_CACHE_ENET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_ENET_MASK)
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|
#define IOMUXC_GPR_GPR13_CACHE_USB_MASK (0x2000U)
|
|
#define IOMUXC_GPR_GPR13_CACHE_USB_SHIFT (13U)
|
|
/*! CACHE_USB
|
|
* 0b0..Cacheable attribute is off for read/write transactions.
|
|
* 0b1..Cacheable attribute is on for read/write transactions.
|
|
*/
|
|
#define IOMUXC_GPR_GPR13_CACHE_USB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_USB_MASK)
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|
/*! @} */
|
|
|
|
/*! @name GPR14 - GPR14 General Purpose Register */
|
|
/*! @{ */
|
|
#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK (0x1U)
|
|
#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT (0U)
|
|
/*! ACMP1_CMP_IGEN_TRIM_DN
|
|
* 0b0..no reduce
|
|
* 0b1..reduces
|
|
*/
|
|
#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK)
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|
#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK (0x2U)
|
|
#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT (1U)
|
|
/*! ACMP2_CMP_IGEN_TRIM_DN
|
|
* 0b0..no reduce
|
|
* 0b1..reduces
|
|
*/
|
|
#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK)
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|
#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK (0x4U)
|
|
#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT (2U)
|
|
/*! ACMP3_CMP_IGEN_TRIM_DN
|
|
* 0b0..no reduce
|
|
* 0b1..reduces
|
|
*/
|
|
#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK)
|
|
#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK (0x8U)
|
|
#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT (3U)
|
|
/*! ACMP4_CMP_IGEN_TRIM_DN
|
|
* 0b0..no reduce
|
|
* 0b1..reduces
|
|
*/
|
|
#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK)
|
|
#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK (0x10U)
|
|
#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT (4U)
|
|
/*! ACMP1_CMP_IGEN_TRIM_UP
|
|
* 0b0..no increase
|
|
* 0b1..increases
|
|
*/
|
|
#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK)
|
|
#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK (0x20U)
|
|
#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT (5U)
|
|
/*! ACMP2_CMP_IGEN_TRIM_UP
|
|
* 0b0..no increase
|
|
* 0b1..increases
|
|
*/
|
|
#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK)
|
|
#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK (0x40U)
|
|
#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT (6U)
|
|
/*! ACMP3_CMP_IGEN_TRIM_UP
|
|
* 0b0..no increase
|
|
* 0b1..increases
|
|
*/
|
|
#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK)
|
|
#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK (0x80U)
|
|
#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT (7U)
|
|
/*! ACMP4_CMP_IGEN_TRIM_UP
|
|
* 0b0..no increase
|
|
* 0b1..increases
|
|
*/
|
|
#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK)
|
|
#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK (0x100U)
|
|
#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT (8U)
|
|
/*! ACMP1_SAMPLE_SYNC_EN
|
|
* 0b0..select XBAR output
|
|
* 0b1..select synced sample_lv
|
|
*/
|
|
#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK)
|
|
#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK (0x200U)
|
|
#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT (9U)
|
|
/*! ACMP2_SAMPLE_SYNC_EN
|
|
* 0b0..select XBAR output
|
|
* 0b1..select synced sample_lv
|
|
*/
|
|
#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK)
|
|
#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK (0x400U)
|
|
#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT (10U)
|
|
/*! ACMP3_SAMPLE_SYNC_EN
|
|
* 0b0..select XBAR output
|
|
* 0b1..select synced sample_lv
|
|
*/
|
|
#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK)
|
|
#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK (0x800U)
|
|
#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT (11U)
|
|
/*! ACMP4_SAMPLE_SYNC_EN
|
|
* 0b0..select XBAR output
|
|
* 0b1..select synced sample_lv
|
|
*/
|
|
#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK)
|
|
#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK (0xF0000U)
|
|
#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT (16U)
|
|
/*! CM7_CFGITCMSZ
|
|
* 0b0000..0 KB (No ITCM)
|
|
* 0b0011..4 KB
|
|
* 0b0100..8 KB
|
|
* 0b0101..16 KB
|
|
* 0b0110..32 KB
|
|
* 0b0111..64 KB
|
|
* 0b1000..128 KB
|
|
* 0b1001..256 KB
|
|
* 0b1010..512 KB
|
|
*/
|
|
#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK)
|
|
#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK (0xF00000U)
|
|
#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT (20U)
|
|
/*! CM7_CFGDTCMSZ
|
|
* 0b0000..0 KB (No DTCM)
|
|
* 0b0011..4 KB
|
|
* 0b0100..8 KB
|
|
* 0b0101..16 KB
|
|
* 0b0110..32 KB
|
|
* 0b0111..64 KB
|
|
* 0b1000..128 KB
|
|
* 0b1001..256 KB
|
|
* 0b1010..512 KB
|
|
*/
|
|
#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GPR16 - GPR16 General Purpose Register */
|
|
/*! @{ */
|
|
#define IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK (0x1U)
|
|
#define IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT (0U)
|
|
/*! INIT_ITCM_EN
|
|
* 0b0..ITCM is disabled
|
|
* 0b1..ITCM is enabled
|
|
*/
|
|
#define IOMUXC_GPR_GPR16_INIT_ITCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK)
|
|
#define IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK (0x2U)
|
|
#define IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT (1U)
|
|
/*! INIT_DTCM_EN
|
|
* 0b0..DTCM is disabled
|
|
* 0b1..DTCM is enabled
|
|
*/
|
|
#define IOMUXC_GPR_GPR16_INIT_DTCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK)
|
|
#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK (0x4U)
|
|
#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT (2U)
|
|
/*! FLEXRAM_BANK_CFG_SEL
|
|
* 0b0..use fuse value to config
|
|
* 0b1..use FLEXRAM_BANK_CFG to config
|
|
*/
|
|
#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GPR17 - GPR17 General Purpose Register */
|
|
/*! @{ */
|
|
#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK (0xFFFFFFFFU)
|
|
#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT (0U)
|
|
#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT)) & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GPR18 - GPR18 General Purpose Register */
|
|
/*! @{ */
|
|
#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK (0x1U)
|
|
#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT (0U)
|
|
/*! LOCK_M7_APC_AC_R0_BOT
|
|
* 0b0..Register field [31:1] is not locked
|
|
* 0b1..Register field [31:1] is locked (read access only)
|
|
*/
|
|
#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK)
|
|
#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK (0xFFFFFFF8U)
|
|
#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT (3U)
|
|
#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GPR19 - GPR19 General Purpose Register */
|
|
/*! @{ */
|
|
#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK (0x1U)
|
|
#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT (0U)
|
|
/*! LOCK_M7_APC_AC_R0_TOP
|
|
* 0b0..Register field [31:1] is not locked
|
|
* 0b1..Register field [31:1] is locked (read access only)
|
|
*/
|
|
#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK)
|
|
#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK (0xFFFFFFF8U)
|
|
#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT (3U)
|
|
#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GPR20 - GPR20 General Purpose Register */
|
|
/*! @{ */
|
|
#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK (0x1U)
|
|
#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT (0U)
|
|
/*! LOCK_M7_APC_AC_R1_BOT
|
|
* 0b0..Register field [31:1] is not locked
|
|
* 0b1..Register field [31:1] is locked (read access only)
|
|
*/
|
|
#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK)
|
|
#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK (0xFFFFFFF8U)
|
|
#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT (3U)
|
|
#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GPR21 - GPR21 General Purpose Register */
|
|
/*! @{ */
|
|
#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK (0x1U)
|
|
#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT (0U)
|
|
/*! LOCK_M7_APC_AC_R1_TOP
|
|
* 0b0..Register field [31:1] is not locked
|
|
* 0b1..Register field [31:1] is locked (read access only)
|
|
*/
|
|
#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK)
|
|
#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK (0xFFFFFFF8U)
|
|
#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT (3U)
|
|
#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GPR22 - GPR22 General Purpose Register */
|
|
/*! @{ */
|
|
#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK (0x1U)
|
|
#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT (0U)
|
|
/*! LOCK_M7_APC_AC_R2_BOT
|
|
* 0b0..Register field [31:1] is not locked
|
|
* 0b1..Register field [31:1] is locked (read access only)
|
|
*/
|
|
#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK)
|
|
#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK (0xFFFFFFF8U)
|
|
#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT (3U)
|
|
#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GPR23 - GPR23 General Purpose Register */
|
|
/*! @{ */
|
|
#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK (0x1U)
|
|
#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT (0U)
|
|
/*! LOCK_M7_APC_AC_R2_TOP
|
|
* 0b0..Register field [31:1] is not locked
|
|
* 0b1..Register field [31:1] is locked (read access only)
|
|
*/
|
|
#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK)
|
|
#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK (0xFFFFFFF8U)
|
|
#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT (3U)
|
|
#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GPR24 - GPR24 General Purpose Register */
|
|
/*! @{ */
|
|
#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK (0x1U)
|
|
#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT (0U)
|
|
/*! LOCK_M7_APC_AC_R3_BOT
|
|
* 0b0..Register field [31:1] is not locked
|
|
* 0b1..Register field [31:1] is locked (read access only)
|
|
*/
|
|
#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK)
|
|
#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK (0xFFFFFFF8U)
|
|
#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT (3U)
|
|
#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GPR25 - GPR25 General Purpose Register */
|
|
/*! @{ */
|
|
#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK (0x1U)
|
|
#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT (0U)
|
|
/*! LOCK_M7_APC_AC_R3_TOP
|
|
* 0b0..Register field [31:1] is not locked
|
|
* 0b1..Register field [31:1] is locked (read access only)
|
|
*/
|
|
#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK)
|
|
#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK (0xFFFFFFF8U)
|
|
#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT (3U)
|
|
#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group IOMUXC_GPR_Register_Masks */
|
|
|
|
|
|
/* IOMUXC_GPR - Peripheral instance base addresses */
|
|
/** Peripheral IOMUXC_GPR base address */
|
|
#define IOMUXC_GPR_BASE (0x400AC000u)
|
|
/** Peripheral IOMUXC_GPR base pointer */
|
|
#define IOMUXC_GPR ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE)
|
|
/** Array initializer of IOMUXC_GPR peripheral base addresses */
|
|
#define IOMUXC_GPR_BASE_ADDRS { IOMUXC_GPR_BASE }
|
|
/** Array initializer of IOMUXC_GPR peripheral base pointers */
|
|
#define IOMUXC_GPR_BASE_PTRS { IOMUXC_GPR }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group IOMUXC_GPR_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- IOMUXC_SNVS Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup IOMUXC_SNVS_Peripheral_Access_Layer IOMUXC_SNVS Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** IOMUXC_SNVS - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t SW_MUX_CTL_PAD_WAKEUP; /**< SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register, offset: 0x0 */
|
|
__IO uint32_t SW_MUX_CTL_PAD_PMIC_ON_REQ; /**< SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register, offset: 0x4 */
|
|
__IO uint32_t SW_MUX_CTL_PAD_PMIC_STBY_REQ; /**< SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register, offset: 0x8 */
|
|
__IO uint32_t SW_PAD_CTL_PAD_TEST_MODE; /**< SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register, offset: 0xC */
|
|
__IO uint32_t SW_PAD_CTL_PAD_POR_B; /**< SW_PAD_CTL_PAD_POR_B SW PAD Control Register, offset: 0x10 */
|
|
__IO uint32_t SW_PAD_CTL_PAD_ONOFF; /**< SW_PAD_CTL_PAD_ONOFF SW PAD Control Register, offset: 0x14 */
|
|
__IO uint32_t SW_PAD_CTL_PAD_WAKEUP; /**< SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register, offset: 0x18 */
|
|
__IO uint32_t SW_PAD_CTL_PAD_PMIC_ON_REQ; /**< SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register, offset: 0x1C */
|
|
__IO uint32_t SW_PAD_CTL_PAD_PMIC_STBY_REQ; /**< SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register, offset: 0x20 */
|
|
} IOMUXC_SNVS_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- IOMUXC_SNVS Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup IOMUXC_SNVS_Register_Masks IOMUXC_SNVS Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name SW_MUX_CTL_PAD_WAKEUP - SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register */
|
|
/*! @{ */
|
|
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK (0x7U)
|
|
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT (0U)
|
|
/*! MUX_MODE - MUX Mode Select Field.
|
|
* 0b101..Select mux mode: ALT5 mux port: GPIO5_IO00 of instance: gpio5
|
|
* 0b111..Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: nmi_glue
|
|
*/
|
|
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK)
|
|
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK (0x10U)
|
|
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT (4U)
|
|
/*! SION - Software Input On Field.
|
|
* 0b1..Force input path of pad WAKEUP
|
|
* 0b0..Input Path is determined by functionality
|
|
*/
|
|
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SW_MUX_CTL_PAD_PMIC_ON_REQ - SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register */
|
|
/*! @{ */
|
|
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK (0x7U)
|
|
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT (0U)
|
|
/*! MUX_MODE - MUX Mode Select Field.
|
|
* 0b000..Select mux mode: ALT0 mux port: SNVS_LP_PMIC_ON_REQ of instance: snvs_lp
|
|
* 0b101..Select mux mode: ALT5 mux port: GPIO5_IO01 of instance: gpio5
|
|
*/
|
|
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK)
|
|
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK (0x10U)
|
|
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT (4U)
|
|
/*! SION - Software Input On Field.
|
|
* 0b1..Force input path of pad PMIC_ON_REQ
|
|
* 0b0..Input Path is determined by functionality
|
|
*/
|
|
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SW_MUX_CTL_PAD_PMIC_STBY_REQ - SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register */
|
|
/*! @{ */
|
|
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK (0x7U)
|
|
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT (0U)
|
|
/*! MUX_MODE - MUX Mode Select Field.
|
|
* 0b000..Select mux mode: ALT0 mux port: CCM_PMIC_VSTBY_REQ of instance: ccm
|
|
* 0b101..Select mux mode: ALT5 mux port: GPIO5_IO02 of instance: gpio5
|
|
*/
|
|
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK)
|
|
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK (0x10U)
|
|
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT (4U)
|
|
/*! SION - Software Input On Field.
|
|
* 0b1..Force input path of pad PMIC_STBY_REQ
|
|
* 0b0..Input Path is determined by functionality
|
|
*/
|
|
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SW_PAD_CTL_PAD_TEST_MODE - SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register */
|
|
/*! @{ */
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK (0x1U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT (0U)
|
|
/*! SRE - Slew Rate Field
|
|
* 0b0..Slow Slew Rate
|
|
* 0b1..Fast Slew Rate
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK (0x38U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT (3U)
|
|
/*! DSE - Drive Strength Field
|
|
* 0b000..output driver disabled;
|
|
* 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR)
|
|
* 0b010..R0/2
|
|
* 0b011..R0/3
|
|
* 0b100..R0/4
|
|
* 0b101..R0/5
|
|
* 0b110..R0/6
|
|
* 0b111..R0/7
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK (0xC0U)
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|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT (6U)
|
|
/*! SPEED - Speed Field
|
|
* 0b10..medium(100MHz)
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK)
|
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#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK (0x800U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT (11U)
|
|
/*! ODE - Open Drain Enable Field
|
|
* 0b0..Open Drain Disabled
|
|
* 0b1..Open Drain Enabled
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK)
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#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK (0x1000U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT (12U)
|
|
/*! PKE - Pull / Keep Enable Field
|
|
* 0b0..Pull/Keeper Disabled
|
|
* 0b1..Pull/Keeper Enabled
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK)
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#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK (0x2000U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT (13U)
|
|
/*! PUE - Pull / Keep Select Field
|
|
* 0b0..Keeper
|
|
* 0b1..Pull
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK)
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#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK (0xC000U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT (14U)
|
|
/*! PUS - Pull Up / Down Config. Field
|
|
* 0b00..100K Ohm Pull Down
|
|
* 0b01..47K Ohm Pull Up
|
|
* 0b10..100K Ohm Pull Up
|
|
* 0b11..22K Ohm Pull Up
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK)
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|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK (0x10000U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT (16U)
|
|
/*! HYS - Hyst. Enable Field
|
|
* 0b0..Hysteresis Disabled
|
|
* 0b1..Hysteresis Enabled
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SW_PAD_CTL_PAD_POR_B - SW_PAD_CTL_PAD_POR_B SW PAD Control Register */
|
|
/*! @{ */
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK (0x1U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT (0U)
|
|
/*! SRE - Slew Rate Field
|
|
* 0b0..Slow Slew Rate
|
|
* 0b1..Fast Slew Rate
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK (0x38U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT (3U)
|
|
/*! DSE - Drive Strength Field
|
|
* 0b000..output driver disabled;
|
|
* 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR)
|
|
* 0b010..R0/2
|
|
* 0b011..R0/3
|
|
* 0b100..R0/4
|
|
* 0b101..R0/5
|
|
* 0b110..R0/6
|
|
* 0b111..R0/7
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK (0xC0U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT (6U)
|
|
/*! SPEED - Speed Field
|
|
* 0b10..medium(100MHz)
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK (0x800U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT (11U)
|
|
/*! ODE - Open Drain Enable Field
|
|
* 0b0..Open Drain Disabled
|
|
* 0b1..Open Drain Enabled
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK (0x1000U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT (12U)
|
|
/*! PKE - Pull / Keep Enable Field
|
|
* 0b0..Pull/Keeper Disabled
|
|
* 0b1..Pull/Keeper Enabled
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK (0x2000U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT (13U)
|
|
/*! PUE - Pull / Keep Select Field
|
|
* 0b0..Keeper
|
|
* 0b1..Pull
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK (0xC000U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT (14U)
|
|
/*! PUS - Pull Up / Down Config. Field
|
|
* 0b00..100K Ohm Pull Down
|
|
* 0b01..47K Ohm Pull Up
|
|
* 0b10..100K Ohm Pull Up
|
|
* 0b11..22K Ohm Pull Up
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK (0x10000U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT (16U)
|
|
/*! HYS - Hyst. Enable Field
|
|
* 0b0..Hysteresis Disabled
|
|
* 0b1..Hysteresis Enabled
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SW_PAD_CTL_PAD_ONOFF - SW_PAD_CTL_PAD_ONOFF SW PAD Control Register */
|
|
/*! @{ */
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK (0x1U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT (0U)
|
|
/*! SRE - Slew Rate Field
|
|
* 0b0..Slow Slew Rate
|
|
* 0b1..Fast Slew Rate
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK (0x38U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT (3U)
|
|
/*! DSE - Drive Strength Field
|
|
* 0b000..output driver disabled;
|
|
* 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR)
|
|
* 0b010..R0/2
|
|
* 0b011..R0/3
|
|
* 0b100..R0/4
|
|
* 0b101..R0/5
|
|
* 0b110..R0/6
|
|
* 0b111..R0/7
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK (0xC0U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT (6U)
|
|
/*! SPEED - Speed Field
|
|
* 0b10..medium(100MHz)
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK (0x800U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT (11U)
|
|
/*! ODE - Open Drain Enable Field
|
|
* 0b0..Open Drain Disabled
|
|
* 0b1..Open Drain Enabled
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK (0x1000U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT (12U)
|
|
/*! PKE - Pull / Keep Enable Field
|
|
* 0b0..Pull/Keeper Disabled
|
|
* 0b1..Pull/Keeper Enabled
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK (0x2000U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT (13U)
|
|
/*! PUE - Pull / Keep Select Field
|
|
* 0b0..Keeper
|
|
* 0b1..Pull
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK (0xC000U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT (14U)
|
|
/*! PUS - Pull Up / Down Config. Field
|
|
* 0b00..100K Ohm Pull Down
|
|
* 0b01..47K Ohm Pull Up
|
|
* 0b10..100K Ohm Pull Up
|
|
* 0b11..22K Ohm Pull Up
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK (0x10000U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT (16U)
|
|
/*! HYS - Hyst. Enable Field
|
|
* 0b0..Hysteresis Disabled
|
|
* 0b1..Hysteresis Enabled
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SW_PAD_CTL_PAD_WAKEUP - SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register */
|
|
/*! @{ */
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK (0x1U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT (0U)
|
|
/*! SRE - Slew Rate Field
|
|
* 0b0..Slow Slew Rate
|
|
* 0b1..Fast Slew Rate
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK (0x38U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT (3U)
|
|
/*! DSE - Drive Strength Field
|
|
* 0b000..output driver disabled;
|
|
* 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR)
|
|
* 0b010..R0/2
|
|
* 0b011..R0/3
|
|
* 0b100..R0/4
|
|
* 0b101..R0/5
|
|
* 0b110..R0/6
|
|
* 0b111..R0/7
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK (0xC0U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT (6U)
|
|
/*! SPEED - Speed Field
|
|
* 0b10..medium(100MHz)
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK (0x800U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT (11U)
|
|
/*! ODE - Open Drain Enable Field
|
|
* 0b0..Open Drain Disabled
|
|
* 0b1..Open Drain Enabled
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK (0x1000U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT (12U)
|
|
/*! PKE - Pull / Keep Enable Field
|
|
* 0b0..Pull/Keeper Disabled
|
|
* 0b1..Pull/Keeper Enabled
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK (0x2000U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT (13U)
|
|
/*! PUE - Pull / Keep Select Field
|
|
* 0b0..Keeper
|
|
* 0b1..Pull
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK (0xC000U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT (14U)
|
|
/*! PUS - Pull Up / Down Config. Field
|
|
* 0b00..100K Ohm Pull Down
|
|
* 0b01..47K Ohm Pull Up
|
|
* 0b10..100K Ohm Pull Up
|
|
* 0b11..22K Ohm Pull Up
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK (0x10000U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT (16U)
|
|
/*! HYS - Hyst. Enable Field
|
|
* 0b0..Hysteresis Disabled
|
|
* 0b1..Hysteresis Enabled
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SW_PAD_CTL_PAD_PMIC_ON_REQ - SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register */
|
|
/*! @{ */
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK (0x1U)
|
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#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT (0U)
|
|
/*! SRE - Slew Rate Field
|
|
* 0b0..Slow Slew Rate
|
|
* 0b1..Fast Slew Rate
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK)
|
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#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK (0x38U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT (3U)
|
|
/*! DSE - Drive Strength Field
|
|
* 0b000..output driver disabled;
|
|
* 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR)
|
|
* 0b010..R0/2
|
|
* 0b011..R0/3
|
|
* 0b100..R0/4
|
|
* 0b101..R0/5
|
|
* 0b110..R0/6
|
|
* 0b111..R0/7
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK (0xC0U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT (6U)
|
|
/*! SPEED - Speed Field
|
|
* 0b10..medium(100MHz)
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK)
|
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#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK (0x800U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT (11U)
|
|
/*! ODE - Open Drain Enable Field
|
|
* 0b0..Open Drain Disabled
|
|
* 0b1..Open Drain Enabled
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK)
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|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK (0x1000U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT (12U)
|
|
/*! PKE - Pull / Keep Enable Field
|
|
* 0b0..Pull/Keeper Disabled
|
|
* 0b1..Pull/Keeper Enabled
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK)
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#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK (0x2000U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT (13U)
|
|
/*! PUE - Pull / Keep Select Field
|
|
* 0b0..Keeper
|
|
* 0b1..Pull
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK)
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#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK (0xC000U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT (14U)
|
|
/*! PUS - Pull Up / Down Config. Field
|
|
* 0b00..100K Ohm Pull Down
|
|
* 0b01..47K Ohm Pull Up
|
|
* 0b10..100K Ohm Pull Up
|
|
* 0b11..22K Ohm Pull Up
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK (0x10000U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT (16U)
|
|
/*! HYS - Hyst. Enable Field
|
|
* 0b0..Hysteresis Disabled
|
|
* 0b1..Hysteresis Enabled
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SW_PAD_CTL_PAD_PMIC_STBY_REQ - SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register */
|
|
/*! @{ */
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK (0x1U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT (0U)
|
|
/*! SRE - Slew Rate Field
|
|
* 0b0..Slow Slew Rate
|
|
* 0b1..Fast Slew Rate
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK (0x38U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT (3U)
|
|
/*! DSE - Drive Strength Field
|
|
* 0b000..output driver disabled;
|
|
* 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR)
|
|
* 0b010..R0/2
|
|
* 0b011..R0/3
|
|
* 0b100..R0/4
|
|
* 0b101..R0/5
|
|
* 0b110..R0/6
|
|
* 0b111..R0/7
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK (0xC0U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT (6U)
|
|
/*! SPEED - Speed Field
|
|
* 0b10..medium(100MHz)
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK (0x800U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT (11U)
|
|
/*! ODE - Open Drain Enable Field
|
|
* 0b0..Open Drain Disabled
|
|
* 0b1..Open Drain Enabled
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK (0x1000U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT (12U)
|
|
/*! PKE - Pull / Keep Enable Field
|
|
* 0b0..Pull/Keeper Disabled
|
|
* 0b1..Pull/Keeper Enabled
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK (0x2000U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT (13U)
|
|
/*! PUE - Pull / Keep Select Field
|
|
* 0b0..Keeper
|
|
* 0b1..Pull
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK (0xC000U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT (14U)
|
|
/*! PUS - Pull Up / Down Config. Field
|
|
* 0b00..100K Ohm Pull Down
|
|
* 0b01..47K Ohm Pull Up
|
|
* 0b10..100K Ohm Pull Up
|
|
* 0b11..22K Ohm Pull Up
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK (0x10000U)
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT (16U)
|
|
/*! HYS - Hyst. Enable Field
|
|
* 0b0..Hysteresis Disabled
|
|
* 0b1..Hysteresis Enabled
|
|
*/
|
|
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group IOMUXC_SNVS_Register_Masks */
|
|
|
|
|
|
/* IOMUXC_SNVS - Peripheral instance base addresses */
|
|
/** Peripheral IOMUXC_SNVS base address */
|
|
#define IOMUXC_SNVS_BASE (0x400A8000u)
|
|
/** Peripheral IOMUXC_SNVS base pointer */
|
|
#define IOMUXC_SNVS ((IOMUXC_SNVS_Type *)IOMUXC_SNVS_BASE)
|
|
/** Array initializer of IOMUXC_SNVS peripheral base addresses */
|
|
#define IOMUXC_SNVS_BASE_ADDRS { IOMUXC_SNVS_BASE }
|
|
/** Array initializer of IOMUXC_SNVS peripheral base pointers */
|
|
#define IOMUXC_SNVS_BASE_PTRS { IOMUXC_SNVS }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group IOMUXC_SNVS_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- IOMUXC_SNVS_GPR Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup IOMUXC_SNVS_GPR_Peripheral_Access_Layer IOMUXC_SNVS_GPR Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** IOMUXC_SNVS_GPR - Register Layout Typedef */
|
|
typedef struct {
|
|
uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */
|
|
uint32_t GPR1; /**< GPR1 General Purpose Register, offset: 0x4 */
|
|
uint32_t GPR2; /**< GPR2 General Purpose Register, offset: 0x8 */
|
|
__IO uint32_t GPR3; /**< GPR3 General Purpose Register, offset: 0xC */
|
|
} IOMUXC_SNVS_GPR_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- IOMUXC_SNVS_GPR Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup IOMUXC_SNVS_GPR_Register_Masks IOMUXC_SNVS_GPR Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name GPR3 - GPR3 General Purpose Register */
|
|
/*! @{ */
|
|
#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK (0x1U)
|
|
#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT (0U)
|
|
#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK)
|
|
#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK (0x2U)
|
|
#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT (1U)
|
|
#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK)
|
|
#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK (0xCU)
|
|
#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT (2U)
|
|
#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK)
|
|
#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK (0x10000U)
|
|
#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT (16U)
|
|
#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK)
|
|
#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK (0x20000U)
|
|
#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT (17U)
|
|
#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK)
|
|
#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK (0x40000U)
|
|
#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT (18U)
|
|
#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK)
|
|
#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK (0x80000U)
|
|
#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT (19U)
|
|
#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group IOMUXC_SNVS_GPR_Register_Masks */
|
|
|
|
|
|
/* IOMUXC_SNVS_GPR - Peripheral instance base addresses */
|
|
/** Peripheral IOMUXC_SNVS_GPR base address */
|
|
#define IOMUXC_SNVS_GPR_BASE (0x400A4000u)
|
|
/** Peripheral IOMUXC_SNVS_GPR base pointer */
|
|
#define IOMUXC_SNVS_GPR ((IOMUXC_SNVS_GPR_Type *)IOMUXC_SNVS_GPR_BASE)
|
|
/** Array initializer of IOMUXC_SNVS_GPR peripheral base addresses */
|
|
#define IOMUXC_SNVS_GPR_BASE_ADDRS { IOMUXC_SNVS_GPR_BASE }
|
|
/** Array initializer of IOMUXC_SNVS_GPR peripheral base pointers */
|
|
#define IOMUXC_SNVS_GPR_BASE_PTRS { IOMUXC_SNVS_GPR }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group IOMUXC_SNVS_GPR_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- KPP Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup KPP_Peripheral_Access_Layer KPP Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** KPP - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint16_t KPCR; /**< Keypad Control Register, offset: 0x0 */
|
|
__IO uint16_t KPSR; /**< Keypad Status Register, offset: 0x2 */
|
|
__IO uint16_t KDDR; /**< Keypad Data Direction Register, offset: 0x4 */
|
|
__IO uint16_t KPDR; /**< Keypad Data Register, offset: 0x6 */
|
|
} KPP_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- KPP Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup KPP_Register_Masks KPP Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name KPCR - Keypad Control Register */
|
|
/*! @{ */
|
|
#define KPP_KPCR_KRE_MASK (0xFFU)
|
|
#define KPP_KPCR_KRE_SHIFT (0U)
|
|
/*! KRE
|
|
* 0b00000000..Row is not included in the keypad key press detect.
|
|
* 0b00000001..Row is included in the keypad key press detect.
|
|
*/
|
|
#define KPP_KPCR_KRE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KRE_SHIFT)) & KPP_KPCR_KRE_MASK)
|
|
#define KPP_KPCR_KCO_MASK (0xFF00U)
|
|
#define KPP_KPCR_KCO_SHIFT (8U)
|
|
/*! KCO
|
|
* 0b00000000..Column strobe output is totem pole drive.
|
|
* 0b00000001..Column strobe output is open drain.
|
|
*/
|
|
#define KPP_KPCR_KCO(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KCO_SHIFT)) & KPP_KPCR_KCO_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name KPSR - Keypad Status Register */
|
|
/*! @{ */
|
|
#define KPP_KPSR_KPKD_MASK (0x1U)
|
|
#define KPP_KPSR_KPKD_SHIFT (0U)
|
|
/*! KPKD
|
|
* 0b0..No key presses detected
|
|
* 0b1..A key has been depressed
|
|
*/
|
|
#define KPP_KPSR_KPKD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKD_SHIFT)) & KPP_KPSR_KPKD_MASK)
|
|
#define KPP_KPSR_KPKR_MASK (0x2U)
|
|
#define KPP_KPSR_KPKR_SHIFT (1U)
|
|
/*! KPKR
|
|
* 0b0..No key release detected
|
|
* 0b1..All keys have been released
|
|
*/
|
|
#define KPP_KPSR_KPKR(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKR_SHIFT)) & KPP_KPSR_KPKR_MASK)
|
|
#define KPP_KPSR_KDSC_MASK (0x4U)
|
|
#define KPP_KPSR_KDSC_SHIFT (2U)
|
|
/*! KDSC
|
|
* 0b0..No effect
|
|
* 0b1..Set bits that clear the keypad depress synchronizer chain
|
|
*/
|
|
#define KPP_KPSR_KDSC(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDSC_SHIFT)) & KPP_KPSR_KDSC_MASK)
|
|
#define KPP_KPSR_KRSS_MASK (0x8U)
|
|
#define KPP_KPSR_KRSS_SHIFT (3U)
|
|
/*! KRSS
|
|
* 0b0..No effect
|
|
* 0b1..Set bits which sets keypad release synchronizer chain
|
|
*/
|
|
#define KPP_KPSR_KRSS(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRSS_SHIFT)) & KPP_KPSR_KRSS_MASK)
|
|
#define KPP_KPSR_KDIE_MASK (0x100U)
|
|
#define KPP_KPSR_KDIE_SHIFT (8U)
|
|
/*! KDIE
|
|
* 0b0..No interrupt request is generated when KPKD is set.
|
|
* 0b1..An interrupt request is generated when KPKD is set.
|
|
*/
|
|
#define KPP_KPSR_KDIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDIE_SHIFT)) & KPP_KPSR_KDIE_MASK)
|
|
#define KPP_KPSR_KRIE_MASK (0x200U)
|
|
#define KPP_KPSR_KRIE_SHIFT (9U)
|
|
/*! KRIE
|
|
* 0b0..No interrupt request is generated when KPKR is set.
|
|
* 0b1..An interrupt request is generated when KPKR is set.
|
|
*/
|
|
#define KPP_KPSR_KRIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRIE_SHIFT)) & KPP_KPSR_KRIE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name KDDR - Keypad Data Direction Register */
|
|
/*! @{ */
|
|
#define KPP_KDDR_KRDD_MASK (0xFFU)
|
|
#define KPP_KDDR_KRDD_SHIFT (0U)
|
|
/*! KRDD
|
|
* 0b00000000..ROWn pin configured as an input.
|
|
* 0b00000001..ROWn pin configured as an output.
|
|
*/
|
|
#define KPP_KDDR_KRDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KRDD_SHIFT)) & KPP_KDDR_KRDD_MASK)
|
|
#define KPP_KDDR_KCDD_MASK (0xFF00U)
|
|
#define KPP_KDDR_KCDD_SHIFT (8U)
|
|
/*! KCDD
|
|
* 0b00000000..COLn pin is configured as an input.
|
|
* 0b00000001..COLn pin is configured as an output.
|
|
*/
|
|
#define KPP_KDDR_KCDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KCDD_SHIFT)) & KPP_KDDR_KCDD_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name KPDR - Keypad Data Register */
|
|
/*! @{ */
|
|
#define KPP_KPDR_KRD_MASK (0xFFU)
|
|
#define KPP_KPDR_KRD_SHIFT (0U)
|
|
#define KPP_KPDR_KRD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KRD_SHIFT)) & KPP_KPDR_KRD_MASK)
|
|
#define KPP_KPDR_KCD_MASK (0xFF00U)
|
|
#define KPP_KPDR_KCD_SHIFT (8U)
|
|
#define KPP_KPDR_KCD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KCD_SHIFT)) & KPP_KPDR_KCD_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group KPP_Register_Masks */
|
|
|
|
|
|
/* KPP - Peripheral instance base addresses */
|
|
/** Peripheral KPP base address */
|
|
#define KPP_BASE (0x401FC000u)
|
|
/** Peripheral KPP base pointer */
|
|
#define KPP ((KPP_Type *)KPP_BASE)
|
|
/** Array initializer of KPP peripheral base addresses */
|
|
#define KPP_BASE_ADDRS { KPP_BASE }
|
|
/** Array initializer of KPP peripheral base pointers */
|
|
#define KPP_BASE_PTRS { KPP }
|
|
/** Interrupt vectors for the KPP peripheral type */
|
|
#define KPP_IRQS { KPP_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group KPP_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- LCDIF Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup LCDIF_Peripheral_Access_Layer LCDIF Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** LCDIF - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t CTRL; /**< LCDIF General Control Register, offset: 0x0 */
|
|
__IO uint32_t CTRL_SET; /**< LCDIF General Control Register, offset: 0x4 */
|
|
__IO uint32_t CTRL_CLR; /**< LCDIF General Control Register, offset: 0x8 */
|
|
__IO uint32_t CTRL_TOG; /**< LCDIF General Control Register, offset: 0xC */
|
|
__IO uint32_t CTRL1; /**< LCDIF General Control1 Register, offset: 0x10 */
|
|
__IO uint32_t CTRL1_SET; /**< LCDIF General Control1 Register, offset: 0x14 */
|
|
__IO uint32_t CTRL1_CLR; /**< LCDIF General Control1 Register, offset: 0x18 */
|
|
__IO uint32_t CTRL1_TOG; /**< LCDIF General Control1 Register, offset: 0x1C */
|
|
__IO uint32_t CTRL2; /**< LCDIF General Control2 Register, offset: 0x20 */
|
|
__IO uint32_t CTRL2_SET; /**< LCDIF General Control2 Register, offset: 0x24 */
|
|
__IO uint32_t CTRL2_CLR; /**< LCDIF General Control2 Register, offset: 0x28 */
|
|
__IO uint32_t CTRL2_TOG; /**< LCDIF General Control2 Register, offset: 0x2C */
|
|
__IO uint32_t TRANSFER_COUNT; /**< LCDIF Horizontal and Vertical Valid Data Count Register, offset: 0x30 */
|
|
uint8_t RESERVED_0[12];
|
|
__IO uint32_t CUR_BUF; /**< LCD Interface Current Buffer Address Register, offset: 0x40 */
|
|
uint8_t RESERVED_1[12];
|
|
__IO uint32_t NEXT_BUF; /**< LCD Interface Next Buffer Address Register, offset: 0x50 */
|
|
uint8_t RESERVED_2[28];
|
|
__IO uint32_t VDCTRL0; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x70 */
|
|
__IO uint32_t VDCTRL0_SET; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x74 */
|
|
__IO uint32_t VDCTRL0_CLR; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x78 */
|
|
__IO uint32_t VDCTRL0_TOG; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x7C */
|
|
__IO uint32_t VDCTRL1; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register1, offset: 0x80 */
|
|
uint8_t RESERVED_3[12];
|
|
__IO uint32_t VDCTRL2; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register2, offset: 0x90 */
|
|
uint8_t RESERVED_4[12];
|
|
__IO uint32_t VDCTRL3; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register3, offset: 0xA0 */
|
|
uint8_t RESERVED_5[12];
|
|
__IO uint32_t VDCTRL4; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register4, offset: 0xB0 */
|
|
uint8_t RESERVED_6[220];
|
|
__IO uint32_t BM_ERROR_STAT; /**< Bus Master Error Status Register, offset: 0x190 */
|
|
uint8_t RESERVED_7[12];
|
|
__IO uint32_t CRC_STAT; /**< CRC Status Register, offset: 0x1A0 */
|
|
uint8_t RESERVED_8[12];
|
|
__I uint32_t STAT; /**< LCD Interface Status Register, offset: 0x1B0 */
|
|
uint8_t RESERVED_9[76];
|
|
__IO uint32_t THRES; /**< LCDIF Threshold Register, offset: 0x200 */
|
|
uint8_t RESERVED_10[380];
|
|
__IO uint32_t PIGEONCTRL0; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x380 */
|
|
__IO uint32_t PIGEONCTRL0_SET; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x384 */
|
|
__IO uint32_t PIGEONCTRL0_CLR; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x388 */
|
|
__IO uint32_t PIGEONCTRL0_TOG; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x38C */
|
|
__IO uint32_t PIGEONCTRL1; /**< LCDIF Pigeon Mode Control1 Register, offset: 0x390 */
|
|
__IO uint32_t PIGEONCTRL1_SET; /**< LCDIF Pigeon Mode Control1 Register, offset: 0x394 */
|
|
__IO uint32_t PIGEONCTRL1_CLR; /**< LCDIF Pigeon Mode Control1 Register, offset: 0x398 */
|
|
__IO uint32_t PIGEONCTRL1_TOG; /**< LCDIF Pigeon Mode Control1 Register, offset: 0x39C */
|
|
__IO uint32_t PIGEONCTRL2; /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A0 */
|
|
__IO uint32_t PIGEONCTRL2_SET; /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A4 */
|
|
__IO uint32_t PIGEONCTRL2_CLR; /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A8 */
|
|
__IO uint32_t PIGEONCTRL2_TOG; /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3AC */
|
|
uint8_t RESERVED_11[1104];
|
|
struct { /* offset: 0x800, array step: 0x40 */
|
|
__IO uint32_t PIGEON_0; /**< Panel Interface Signal Generator Register, array offset: 0x800, array step: 0x40 */
|
|
uint8_t RESERVED_0[12];
|
|
__IO uint32_t PIGEON_1; /**< Panel Interface Signal Generator Register, array offset: 0x810, array step: 0x40 */
|
|
uint8_t RESERVED_1[12];
|
|
__IO uint32_t PIGEON_2; /**< Panel Interface Signal Generator Register, array offset: 0x820, array step: 0x40 */
|
|
uint8_t RESERVED_2[28];
|
|
} PIGEON[12];
|
|
__IO uint32_t LUT_CTRL; /**< Lookup Table Data Register., offset: 0xB00 */
|
|
uint8_t RESERVED_12[12];
|
|
__IO uint32_t LUT0_ADDR; /**< Lookup Table Control Register., offset: 0xB10 */
|
|
uint8_t RESERVED_13[12];
|
|
__IO uint32_t LUT0_DATA; /**< Lookup Table Data Register., offset: 0xB20 */
|
|
uint8_t RESERVED_14[12];
|
|
__IO uint32_t LUT1_ADDR; /**< Lookup Table Control Register., offset: 0xB30 */
|
|
uint8_t RESERVED_15[12];
|
|
__IO uint32_t LUT1_DATA; /**< Lookup Table Data Register., offset: 0xB40 */
|
|
} LCDIF_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- LCDIF Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup LCDIF_Register_Masks LCDIF Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name CTRL - LCDIF General Control Register */
|
|
/*! @{ */
|
|
#define LCDIF_CTRL_RUN_MASK (0x1U)
|
|
#define LCDIF_CTRL_RUN_SHIFT (0U)
|
|
#define LCDIF_CTRL_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK)
|
|
#define LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK (0x2U)
|
|
#define LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT (1U)
|
|
/*! DATA_FORMAT_24_BIT
|
|
* 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
|
|
* 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped.
|
|
*/
|
|
#define LCDIF_CTRL_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK)
|
|
#define LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK (0x4U)
|
|
#define LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT (2U)
|
|
/*! DATA_FORMAT_18_BIT
|
|
* 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data.
|
|
* 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.
|
|
*/
|
|
#define LCDIF_CTRL_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK)
|
|
#define LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK (0x8U)
|
|
#define LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT (3U)
|
|
#define LCDIF_CTRL_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK)
|
|
#define LCDIF_CTRL_RSRVD0_MASK (0x10U)
|
|
#define LCDIF_CTRL_RSRVD0_SHIFT (4U)
|
|
#define LCDIF_CTRL_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RSRVD0_SHIFT)) & LCDIF_CTRL_RSRVD0_MASK)
|
|
#define LCDIF_CTRL_MASTER_MASK (0x20U)
|
|
#define LCDIF_CTRL_MASTER_SHIFT (5U)
|
|
#define LCDIF_CTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_MASTER_SHIFT)) & LCDIF_CTRL_MASTER_MASK)
|
|
#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
|
|
#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
|
|
#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK)
|
|
#define LCDIF_CTRL_WORD_LENGTH_MASK (0x300U)
|
|
#define LCDIF_CTRL_WORD_LENGTH_SHIFT (8U)
|
|
/*! WORD_LENGTH
|
|
* 0b00..Input data is 16 bits per pixel.
|
|
* 0b01..Input data is 8 bits wide.
|
|
* 0b10..Input data is 18 bits per pixel.
|
|
* 0b11..Input data is 24 bits per pixel.
|
|
*/
|
|
#define LCDIF_CTRL_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK)
|
|
#define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0xC00U)
|
|
#define LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT (10U)
|
|
/*! LCD_DATABUS_WIDTH
|
|
* 0b00..16-bit data bus mode.
|
|
* 0b01..8-bit data bus mode.
|
|
* 0b10..18-bit data bus mode.
|
|
* 0b11..24-bit data bus mode.
|
|
*/
|
|
#define LCDIF_CTRL_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK)
|
|
#define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3000U)
|
|
#define LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT (12U)
|
|
/*! CSC_DATA_SWIZZLE
|
|
* 0b00..No byte swapping.(Little endian)
|
|
* 0b00..Little Endian byte ordering (same as NO_SWAP).
|
|
* 0b01..Big Endian swap (swap bytes 0,3 and 1,2).
|
|
* 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
|
|
* 0b10..Swap half-words.
|
|
* 0b11..Swap bytes within each half-word.
|
|
*/
|
|
#define LCDIF_CTRL_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK)
|
|
#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0xC000U)
|
|
#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT (14U)
|
|
/*! INPUT_DATA_SWIZZLE
|
|
* 0b00..No byte swapping.(Little endian)
|
|
* 0b00..Little Endian byte ordering (same as NO_SWAP).
|
|
* 0b01..Big Endian swap (swap bytes 0,3 and 1,2).
|
|
* 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
|
|
* 0b10..Swap half-words.
|
|
* 0b11..Swap bytes within each half-word.
|
|
*/
|
|
#define LCDIF_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK)
|
|
#define LCDIF_CTRL_DOTCLK_MODE_MASK (0x20000U)
|
|
#define LCDIF_CTRL_DOTCLK_MODE_SHIFT (17U)
|
|
#define LCDIF_CTRL_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_DOTCLK_MODE_MASK)
|
|
#define LCDIF_CTRL_BYPASS_COUNT_MASK (0x80000U)
|
|
#define LCDIF_CTRL_BYPASS_COUNT_SHIFT (19U)
|
|
#define LCDIF_CTRL_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_BYPASS_COUNT_MASK)
|
|
#define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x3E00000U)
|
|
#define LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT (21U)
|
|
#define LCDIF_CTRL_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SHIFT_NUM_BITS_MASK)
|
|
#define LCDIF_CTRL_DATA_SHIFT_DIR_MASK (0x4000000U)
|
|
#define LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT (26U)
|
|
/*! DATA_SHIFT_DIR
|
|
* 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
|
|
* 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
|
|
*/
|
|
#define LCDIF_CTRL_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK)
|
|
#define LCDIF_CTRL_CLKGATE_MASK (0x40000000U)
|
|
#define LCDIF_CTRL_CLKGATE_SHIFT (30U)
|
|
#define LCDIF_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLKGATE_SHIFT)) & LCDIF_CTRL_CLKGATE_MASK)
|
|
#define LCDIF_CTRL_SFTRST_MASK (0x80000000U)
|
|
#define LCDIF_CTRL_SFTRST_SHIFT (31U)
|
|
#define LCDIF_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SFTRST_SHIFT)) & LCDIF_CTRL_SFTRST_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CTRL_SET - LCDIF General Control Register */
|
|
/*! @{ */
|
|
#define LCDIF_CTRL_SET_RUN_MASK (0x1U)
|
|
#define LCDIF_CTRL_SET_RUN_SHIFT (0U)
|
|
#define LCDIF_CTRL_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RUN_SHIFT)) & LCDIF_CTRL_SET_RUN_MASK)
|
|
#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK (0x2U)
|
|
#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT (1U)
|
|
/*! DATA_FORMAT_24_BIT
|
|
* 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
|
|
* 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped.
|
|
*/
|
|
#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK)
|
|
#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK (0x4U)
|
|
#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT (2U)
|
|
/*! DATA_FORMAT_18_BIT
|
|
* 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data.
|
|
* 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.
|
|
*/
|
|
#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK)
|
|
#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK (0x8U)
|
|
#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT (3U)
|
|
#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK)
|
|
#define LCDIF_CTRL_SET_RSRVD0_MASK (0x10U)
|
|
#define LCDIF_CTRL_SET_RSRVD0_SHIFT (4U)
|
|
#define LCDIF_CTRL_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RSRVD0_SHIFT)) & LCDIF_CTRL_SET_RSRVD0_MASK)
|
|
#define LCDIF_CTRL_SET_MASTER_MASK (0x20U)
|
|
#define LCDIF_CTRL_SET_MASTER_SHIFT (5U)
|
|
#define LCDIF_CTRL_SET_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_MASTER_SHIFT)) & LCDIF_CTRL_SET_MASTER_MASK)
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#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
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#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
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#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK)
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#define LCDIF_CTRL_SET_WORD_LENGTH_MASK (0x300U)
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#define LCDIF_CTRL_SET_WORD_LENGTH_SHIFT (8U)
|
|
/*! WORD_LENGTH
|
|
* 0b00..Input data is 16 bits per pixel.
|
|
* 0b01..Input data is 8 bits wide.
|
|
* 0b10..Input data is 18 bits per pixel.
|
|
* 0b11..Input data is 24 bits per pixel.
|
|
*/
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#define LCDIF_CTRL_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK)
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#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK (0xC00U)
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#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT (10U)
|
|
/*! LCD_DATABUS_WIDTH
|
|
* 0b00..16-bit data bus mode.
|
|
* 0b01..8-bit data bus mode.
|
|
* 0b10..18-bit data bus mode.
|
|
* 0b11..24-bit data bus mode.
|
|
*/
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#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK)
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#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK (0x3000U)
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#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT (12U)
|
|
/*! CSC_DATA_SWIZZLE
|
|
* 0b00..No byte swapping.(Little endian)
|
|
* 0b00..Little Endian byte ordering (same as NO_SWAP).
|
|
* 0b01..Big Endian swap (swap bytes 0,3 and 1,2).
|
|
* 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
|
|
* 0b10..Swap half-words.
|
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* 0b11..Swap bytes within each half-word.
|
|
*/
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|
#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK)
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#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK (0xC000U)
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#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT (14U)
|
|
/*! INPUT_DATA_SWIZZLE
|
|
* 0b00..No byte swapping.(Little endian)
|
|
* 0b00..Little Endian byte ordering (same as NO_SWAP).
|
|
* 0b01..Big Endian swap (swap bytes 0,3 and 1,2).
|
|
* 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
|
|
* 0b10..Swap half-words.
|
|
* 0b11..Swap bytes within each half-word.
|
|
*/
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#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK)
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#define LCDIF_CTRL_SET_DOTCLK_MODE_MASK (0x20000U)
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#define LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT (17U)
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#define LCDIF_CTRL_SET_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_SET_DOTCLK_MODE_MASK)
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#define LCDIF_CTRL_SET_BYPASS_COUNT_MASK (0x80000U)
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#define LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT (19U)
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#define LCDIF_CTRL_SET_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_SET_BYPASS_COUNT_MASK)
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#define LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK (0x3E00000U)
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|
#define LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT (21U)
|
|
#define LCDIF_CTRL_SET_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK)
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|
#define LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK (0x4000000U)
|
|
#define LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT (26U)
|
|
/*! DATA_SHIFT_DIR
|
|
* 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
|
|
* 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
|
|
*/
|
|
#define LCDIF_CTRL_SET_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK)
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#define LCDIF_CTRL_SET_CLKGATE_MASK (0x40000000U)
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|
#define LCDIF_CTRL_SET_CLKGATE_SHIFT (30U)
|
|
#define LCDIF_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CLKGATE_SHIFT)) & LCDIF_CTRL_SET_CLKGATE_MASK)
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#define LCDIF_CTRL_SET_SFTRST_MASK (0x80000000U)
|
|
#define LCDIF_CTRL_SET_SFTRST_SHIFT (31U)
|
|
#define LCDIF_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SFTRST_SHIFT)) & LCDIF_CTRL_SET_SFTRST_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CTRL_CLR - LCDIF General Control Register */
|
|
/*! @{ */
|
|
#define LCDIF_CTRL_CLR_RUN_MASK (0x1U)
|
|
#define LCDIF_CTRL_CLR_RUN_SHIFT (0U)
|
|
#define LCDIF_CTRL_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RUN_SHIFT)) & LCDIF_CTRL_CLR_RUN_MASK)
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|
#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK (0x2U)
|
|
#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT (1U)
|
|
/*! DATA_FORMAT_24_BIT
|
|
* 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
|
|
* 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped.
|
|
*/
|
|
#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK)
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|
#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK (0x4U)
|
|
#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT (2U)
|
|
/*! DATA_FORMAT_18_BIT
|
|
* 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data.
|
|
* 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.
|
|
*/
|
|
#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK)
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|
#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK (0x8U)
|
|
#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT (3U)
|
|
#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK)
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|
#define LCDIF_CTRL_CLR_RSRVD0_MASK (0x10U)
|
|
#define LCDIF_CTRL_CLR_RSRVD0_SHIFT (4U)
|
|
#define LCDIF_CTRL_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL_CLR_RSRVD0_MASK)
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|
#define LCDIF_CTRL_CLR_MASTER_MASK (0x20U)
|
|
#define LCDIF_CTRL_CLR_MASTER_SHIFT (5U)
|
|
#define LCDIF_CTRL_CLR_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_MASTER_SHIFT)) & LCDIF_CTRL_CLR_MASTER_MASK)
|
|
#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
|
|
#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
|
|
#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK)
|
|
#define LCDIF_CTRL_CLR_WORD_LENGTH_MASK (0x300U)
|
|
#define LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT (8U)
|
|
/*! WORD_LENGTH
|
|
* 0b00..Input data is 16 bits per pixel.
|
|
* 0b01..Input data is 8 bits wide.
|
|
* 0b10..Input data is 18 bits per pixel.
|
|
* 0b11..Input data is 24 bits per pixel.
|
|
*/
|
|
#define LCDIF_CTRL_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK)
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|
#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK (0xC00U)
|
|
#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT (10U)
|
|
/*! LCD_DATABUS_WIDTH
|
|
* 0b00..16-bit data bus mode.
|
|
* 0b01..8-bit data bus mode.
|
|
* 0b10..18-bit data bus mode.
|
|
* 0b11..24-bit data bus mode.
|
|
*/
|
|
#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK)
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|
#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK (0x3000U)
|
|
#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT (12U)
|
|
/*! CSC_DATA_SWIZZLE
|
|
* 0b00..No byte swapping.(Little endian)
|
|
* 0b00..Little Endian byte ordering (same as NO_SWAP).
|
|
* 0b01..Big Endian swap (swap bytes 0,3 and 1,2).
|
|
* 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
|
|
* 0b10..Swap half-words.
|
|
* 0b11..Swap bytes within each half-word.
|
|
*/
|
|
#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK)
|
|
#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK (0xC000U)
|
|
#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT (14U)
|
|
/*! INPUT_DATA_SWIZZLE
|
|
* 0b00..No byte swapping.(Little endian)
|
|
* 0b00..Little Endian byte ordering (same as NO_SWAP).
|
|
* 0b01..Big Endian swap (swap bytes 0,3 and 1,2).
|
|
* 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
|
|
* 0b10..Swap half-words.
|
|
* 0b11..Swap bytes within each half-word.
|
|
*/
|
|
#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK)
|
|
#define LCDIF_CTRL_CLR_DOTCLK_MODE_MASK (0x20000U)
|
|
#define LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT (17U)
|
|
#define LCDIF_CTRL_CLR_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_CLR_DOTCLK_MODE_MASK)
|
|
#define LCDIF_CTRL_CLR_BYPASS_COUNT_MASK (0x80000U)
|
|
#define LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT (19U)
|
|
#define LCDIF_CTRL_CLR_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_CLR_BYPASS_COUNT_MASK)
|
|
#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK (0x3E00000U)
|
|
#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT (21U)
|
|
#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK)
|
|
#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK (0x4000000U)
|
|
#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT (26U)
|
|
/*! DATA_SHIFT_DIR
|
|
* 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
|
|
* 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
|
|
*/
|
|
#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK)
|
|
#define LCDIF_CTRL_CLR_CLKGATE_MASK (0x40000000U)
|
|
#define LCDIF_CTRL_CLR_CLKGATE_SHIFT (30U)
|
|
#define LCDIF_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CLKGATE_SHIFT)) & LCDIF_CTRL_CLR_CLKGATE_MASK)
|
|
#define LCDIF_CTRL_CLR_SFTRST_MASK (0x80000000U)
|
|
#define LCDIF_CTRL_CLR_SFTRST_SHIFT (31U)
|
|
#define LCDIF_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SFTRST_SHIFT)) & LCDIF_CTRL_CLR_SFTRST_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CTRL_TOG - LCDIF General Control Register */
|
|
/*! @{ */
|
|
#define LCDIF_CTRL_TOG_RUN_MASK (0x1U)
|
|
#define LCDIF_CTRL_TOG_RUN_SHIFT (0U)
|
|
#define LCDIF_CTRL_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RUN_SHIFT)) & LCDIF_CTRL_TOG_RUN_MASK)
|
|
#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK (0x2U)
|
|
#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT (1U)
|
|
/*! DATA_FORMAT_24_BIT
|
|
* 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
|
|
* 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped.
|
|
*/
|
|
#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK)
|
|
#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK (0x4U)
|
|
#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT (2U)
|
|
/*! DATA_FORMAT_18_BIT
|
|
* 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data.
|
|
* 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.
|
|
*/
|
|
#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK)
|
|
#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK (0x8U)
|
|
#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT (3U)
|
|
#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK)
|
|
#define LCDIF_CTRL_TOG_RSRVD0_MASK (0x10U)
|
|
#define LCDIF_CTRL_TOG_RSRVD0_SHIFT (4U)
|
|
#define LCDIF_CTRL_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL_TOG_RSRVD0_MASK)
|
|
#define LCDIF_CTRL_TOG_MASTER_MASK (0x20U)
|
|
#define LCDIF_CTRL_TOG_MASTER_SHIFT (5U)
|
|
#define LCDIF_CTRL_TOG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_MASTER_SHIFT)) & LCDIF_CTRL_TOG_MASTER_MASK)
|
|
#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
|
|
#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
|
|
#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK)
|
|
#define LCDIF_CTRL_TOG_WORD_LENGTH_MASK (0x300U)
|
|
#define LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT (8U)
|
|
/*! WORD_LENGTH
|
|
* 0b00..Input data is 16 bits per pixel.
|
|
* 0b01..Input data is 8 bits wide.
|
|
* 0b10..Input data is 18 bits per pixel.
|
|
* 0b11..Input data is 24 bits per pixel.
|
|
*/
|
|
#define LCDIF_CTRL_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK)
|
|
#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK (0xC00U)
|
|
#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT (10U)
|
|
/*! LCD_DATABUS_WIDTH
|
|
* 0b00..16-bit data bus mode.
|
|
* 0b01..8-bit data bus mode.
|
|
* 0b10..18-bit data bus mode.
|
|
* 0b11..24-bit data bus mode.
|
|
*/
|
|
#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK)
|
|
#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK (0x3000U)
|
|
#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT (12U)
|
|
/*! CSC_DATA_SWIZZLE
|
|
* 0b00..No byte swapping.(Little endian)
|
|
* 0b00..Little Endian byte ordering (same as NO_SWAP).
|
|
* 0b01..Big Endian swap (swap bytes 0,3 and 1,2).
|
|
* 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
|
|
* 0b10..Swap half-words.
|
|
* 0b11..Swap bytes within each half-word.
|
|
*/
|
|
#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK)
|
|
#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK (0xC000U)
|
|
#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT (14U)
|
|
/*! INPUT_DATA_SWIZZLE
|
|
* 0b00..No byte swapping.(Little endian)
|
|
* 0b00..Little Endian byte ordering (same as NO_SWAP).
|
|
* 0b01..Big Endian swap (swap bytes 0,3 and 1,2).
|
|
* 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
|
|
* 0b10..Swap half-words.
|
|
* 0b11..Swap bytes within each half-word.
|
|
*/
|
|
#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK)
|
|
#define LCDIF_CTRL_TOG_DOTCLK_MODE_MASK (0x20000U)
|
|
#define LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT (17U)
|
|
#define LCDIF_CTRL_TOG_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_TOG_DOTCLK_MODE_MASK)
|
|
#define LCDIF_CTRL_TOG_BYPASS_COUNT_MASK (0x80000U)
|
|
#define LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT (19U)
|
|
#define LCDIF_CTRL_TOG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_TOG_BYPASS_COUNT_MASK)
|
|
#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK (0x3E00000U)
|
|
#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT (21U)
|
|
#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK)
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#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK (0x4000000U)
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#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT (26U)
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/*! DATA_SHIFT_DIR
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* 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
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* 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
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*/
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#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK)
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#define LCDIF_CTRL_TOG_CLKGATE_MASK (0x40000000U)
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#define LCDIF_CTRL_TOG_CLKGATE_SHIFT (30U)
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#define LCDIF_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CLKGATE_SHIFT)) & LCDIF_CTRL_TOG_CLKGATE_MASK)
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#define LCDIF_CTRL_TOG_SFTRST_MASK (0x80000000U)
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#define LCDIF_CTRL_TOG_SFTRST_SHIFT (31U)
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#define LCDIF_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SFTRST_SHIFT)) & LCDIF_CTRL_TOG_SFTRST_MASK)
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/*! @} */
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/*! @name CTRL1 - LCDIF General Control1 Register */
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/*! @{ */
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#define LCDIF_CTRL1_RSRVD0_MASK (0xF8U)
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#define LCDIF_CTRL1_RSRVD0_SHIFT (3U)
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#define LCDIF_CTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD0_SHIFT)) & LCDIF_CTRL1_RSRVD0_MASK)
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#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK (0x100U)
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#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT (8U)
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/*! VSYNC_EDGE_IRQ
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* 0b0..No Interrupt Request Pending.
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* 0b1..Interrupt Request Pending.
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*/
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#define LCDIF_CTRL1_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK)
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#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK (0x200U)
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#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT (9U)
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/*! CUR_FRAME_DONE_IRQ
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* 0b0..No Interrupt Request Pending.
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* 0b1..Interrupt Request Pending.
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*/
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#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK)
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#define LCDIF_CTRL1_UNDERFLOW_IRQ_MASK (0x400U)
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#define LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT (10U)
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/*! UNDERFLOW_IRQ
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* 0b0..No Interrupt Request Pending.
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* 0b1..Interrupt Request Pending.
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*/
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#define LCDIF_CTRL1_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK)
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#define LCDIF_CTRL1_OVERFLOW_IRQ_MASK (0x800U)
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#define LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT (11U)
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/*! OVERFLOW_IRQ
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* 0b0..No Interrupt Request Pending.
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* 0b1..Interrupt Request Pending.
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*/
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#define LCDIF_CTRL1_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK)
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#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)
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#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT (12U)
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#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK)
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#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
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#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
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#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK)
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#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK (0x4000U)
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#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT (14U)
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#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK)
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#define LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK (0x8000U)
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#define LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT (15U)
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#define LCDIF_CTRL1_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK)
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#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xF0000U)
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#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT (16U)
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#define LCDIF_CTRL1_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK)
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#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
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#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
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#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK)
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#define LCDIF_CTRL1_FIFO_CLEAR_MASK (0x200000U)
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#define LCDIF_CTRL1_FIFO_CLEAR_SHIFT (21U)
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#define LCDIF_CTRL1_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_FIFO_CLEAR_MASK)
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#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
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#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
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#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK)
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#define LCDIF_CTRL1_INTERLACE_FIELDS_MASK (0x800000U)
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#define LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT (23U)
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#define LCDIF_CTRL1_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_INTERLACE_FIELDS_MASK)
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#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
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#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT (24U)
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#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK)
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#define LCDIF_CTRL1_BM_ERROR_IRQ_MASK (0x2000000U)
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#define LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT (25U)
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/*! BM_ERROR_IRQ
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* 0b0..No Interrupt Request Pending.
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* 0b1..Interrupt Request Pending.
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*/
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#define LCDIF_CTRL1_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK)
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#define LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK (0x4000000U)
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#define LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT (26U)
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#define LCDIF_CTRL1_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK)
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#define LCDIF_CTRL1_CS_OUT_SELECT_MASK (0x40000000U)
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#define LCDIF_CTRL1_CS_OUT_SELECT_SHIFT (30U)
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#define LCDIF_CTRL1_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CS_OUT_SELECT_MASK)
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#define LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK (0x80000000U)
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#define LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT (31U)
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#define LCDIF_CTRL1_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK)
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/*! @} */
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/*! @name CTRL1_SET - LCDIF General Control1 Register */
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/*! @{ */
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#define LCDIF_CTRL1_SET_RSRVD0_MASK (0xF8U)
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#define LCDIF_CTRL1_SET_RSRVD0_SHIFT (3U)
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#define LCDIF_CTRL1_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD0_SHIFT)) & LCDIF_CTRL1_SET_RSRVD0_MASK)
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#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK (0x100U)
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#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT (8U)
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/*! VSYNC_EDGE_IRQ
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* 0b0..No Interrupt Request Pending.
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* 0b1..Interrupt Request Pending.
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*/
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#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK)
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#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK (0x200U)
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#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT (9U)
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/*! CUR_FRAME_DONE_IRQ
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* 0b0..No Interrupt Request Pending.
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* 0b1..Interrupt Request Pending.
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*/
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#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK)
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#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK (0x400U)
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#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT (10U)
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/*! UNDERFLOW_IRQ
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* 0b0..No Interrupt Request Pending.
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* 0b1..Interrupt Request Pending.
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*/
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#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK)
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#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK (0x800U)
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#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT (11U)
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/*! OVERFLOW_IRQ
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* 0b0..No Interrupt Request Pending.
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* 0b1..Interrupt Request Pending.
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*/
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#define LCDIF_CTRL1_SET_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK)
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#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)
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#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT (12U)
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#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK)
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#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
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#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
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#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK)
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#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK (0x4000U)
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#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT (14U)
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#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK)
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#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK (0x8000U)
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#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT (15U)
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#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK)
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#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK (0xF0000U)
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#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT (16U)
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#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK)
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#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
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#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
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#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK)
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#define LCDIF_CTRL1_SET_FIFO_CLEAR_MASK (0x200000U)
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#define LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT (21U)
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#define LCDIF_CTRL1_SET_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_SET_FIFO_CLEAR_MASK)
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#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
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#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
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#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK)
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#define LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK (0x800000U)
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#define LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT (23U)
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#define LCDIF_CTRL1_SET_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK)
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#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
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#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT (24U)
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#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK)
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#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK (0x2000000U)
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#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT (25U)
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/*! BM_ERROR_IRQ
|
|
* 0b0..No Interrupt Request Pending.
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* 0b1..Interrupt Request Pending.
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|
*/
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#define LCDIF_CTRL1_SET_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK)
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#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK (0x4000000U)
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#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT (26U)
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#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK)
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#define LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK (0x40000000U)
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#define LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT (30U)
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#define LCDIF_CTRL1_SET_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK)
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#define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK (0x80000000U)
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#define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT (31U)
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|
#define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK)
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/*! @} */
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|
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/*! @name CTRL1_CLR - LCDIF General Control1 Register */
|
|
/*! @{ */
|
|
#define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U)
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|
#define LCDIF_CTRL1_CLR_RSRVD0_SHIFT (3U)
|
|
#define LCDIF_CTRL1_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)
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#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK (0x100U)
|
|
#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT (8U)
|
|
/*! VSYNC_EDGE_IRQ
|
|
* 0b0..No Interrupt Request Pending.
|
|
* 0b1..Interrupt Request Pending.
|
|
*/
|
|
#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK)
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|
#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK (0x200U)
|
|
#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT (9U)
|
|
/*! CUR_FRAME_DONE_IRQ
|
|
* 0b0..No Interrupt Request Pending.
|
|
* 0b1..Interrupt Request Pending.
|
|
*/
|
|
#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK)
|
|
#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK (0x400U)
|
|
#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT (10U)
|
|
/*! UNDERFLOW_IRQ
|
|
* 0b0..No Interrupt Request Pending.
|
|
* 0b1..Interrupt Request Pending.
|
|
*/
|
|
#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK)
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|
#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK (0x800U)
|
|
#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT (11U)
|
|
/*! OVERFLOW_IRQ
|
|
* 0b0..No Interrupt Request Pending.
|
|
* 0b1..Interrupt Request Pending.
|
|
*/
|
|
#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK)
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#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)
|
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#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT (12U)
|
|
#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK)
|
|
#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
|
|
#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
|
|
#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK)
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#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK (0x4000U)
|
|
#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT (14U)
|
|
#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK)
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#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK (0x8000U)
|
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#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT (15U)
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#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK)
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#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK (0xF0000U)
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#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT (16U)
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#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK)
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#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
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#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
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#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK)
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#define LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK (0x200000U)
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#define LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT (21U)
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#define LCDIF_CTRL1_CLR_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK)
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#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
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#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
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#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK)
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#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK (0x800000U)
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#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT (23U)
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#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK)
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#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
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#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT (24U)
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#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK)
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#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK (0x2000000U)
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#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT (25U)
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/*! BM_ERROR_IRQ
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* 0b0..No Interrupt Request Pending.
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* 0b1..Interrupt Request Pending.
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*/
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#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK)
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#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK (0x4000000U)
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#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT (26U)
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#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK)
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#define LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK (0x40000000U)
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#define LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT (30U)
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#define LCDIF_CTRL1_CLR_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK)
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#define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK (0x80000000U)
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#define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT (31U)
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#define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK)
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/*! @} */
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/*! @name CTRL1_TOG - LCDIF General Control1 Register */
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/*! @{ */
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#define LCDIF_CTRL1_TOG_RSRVD0_MASK (0xF8U)
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#define LCDIF_CTRL1_TOG_RSRVD0_SHIFT (3U)
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#define LCDIF_CTRL1_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD0_MASK)
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#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK (0x100U)
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#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT (8U)
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/*! VSYNC_EDGE_IRQ
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* 0b0..No Interrupt Request Pending.
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* 0b1..Interrupt Request Pending.
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*/
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#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK)
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#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK (0x200U)
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#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT (9U)
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/*! CUR_FRAME_DONE_IRQ
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* 0b0..No Interrupt Request Pending.
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* 0b1..Interrupt Request Pending.
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*/
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#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK)
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#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK (0x400U)
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#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT (10U)
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/*! UNDERFLOW_IRQ
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* 0b0..No Interrupt Request Pending.
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* 0b1..Interrupt Request Pending.
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*/
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#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK)
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#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK (0x800U)
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#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT (11U)
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/*! OVERFLOW_IRQ
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* 0b0..No Interrupt Request Pending.
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* 0b1..Interrupt Request Pending.
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*/
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#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK)
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#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)
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#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT (12U)
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#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK)
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#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
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#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
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#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK)
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#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK (0x4000U)
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#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT (14U)
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#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK)
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#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK (0x8000U)
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#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT (15U)
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#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK)
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#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK (0xF0000U)
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#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT (16U)
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#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK)
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#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
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#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
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#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK)
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#define LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK (0x200000U)
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#define LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT (21U)
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#define LCDIF_CTRL1_TOG_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK)
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#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
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#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
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#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK)
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#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK (0x800000U)
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#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT (23U)
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#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK)
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#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
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#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT (24U)
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#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK)
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#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK (0x2000000U)
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#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT (25U)
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/*! BM_ERROR_IRQ
|
|
* 0b0..No Interrupt Request Pending.
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* 0b1..Interrupt Request Pending.
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*/
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#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK)
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#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK (0x4000000U)
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#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT (26U)
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#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK)
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#define LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK (0x40000000U)
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#define LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT (30U)
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#define LCDIF_CTRL1_TOG_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK)
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#define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK (0x80000000U)
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#define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT (31U)
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#define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK)
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/*! @} */
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/*! @name CTRL2 - LCDIF General Control2 Register */
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|
/*! @{ */
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|
#define LCDIF_CTRL2_RSRVD0_MASK (0xFFFU)
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#define LCDIF_CTRL2_RSRVD0_SHIFT (0U)
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#define LCDIF_CTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD0_SHIFT)) & LCDIF_CTRL2_RSRVD0_MASK)
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#define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7000U)
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|
#define LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT (12U)
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|
/*! EVEN_LINE_PATTERN
|
|
* 0b000..RGB
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|
* 0b001..RBG
|
|
* 0b010..GBR
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|
* 0b011..GRB
|
|
* 0b100..BRG
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|
* 0b101..BGR
|
|
*/
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#define LCDIF_CTRL2_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK)
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#define LCDIF_CTRL2_RSRVD3_MASK (0x8000U)
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#define LCDIF_CTRL2_RSRVD3_SHIFT (15U)
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#define LCDIF_CTRL2_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD3_SHIFT)) & LCDIF_CTRL2_RSRVD3_MASK)
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#define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x70000U)
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#define LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT (16U)
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/*! ODD_LINE_PATTERN
|
|
* 0b000..RGB
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|
* 0b001..RBG
|
|
* 0b010..GBR
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|
* 0b011..GRB
|
|
* 0b100..BRG
|
|
* 0b101..BGR
|
|
*/
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#define LCDIF_CTRL2_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK)
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#define LCDIF_CTRL2_RSRVD4_MASK (0x80000U)
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#define LCDIF_CTRL2_RSRVD4_SHIFT (19U)
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#define LCDIF_CTRL2_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD4_SHIFT)) & LCDIF_CTRL2_RSRVD4_MASK)
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#define LCDIF_CTRL2_BURST_LEN_8_MASK (0x100000U)
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#define LCDIF_CTRL2_BURST_LEN_8_SHIFT (20U)
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#define LCDIF_CTRL2_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_BURST_LEN_8_MASK)
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#define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0xE00000U)
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|
#define LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT (21U)
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/*! OUTSTANDING_REQS
|
|
* 0b000..REQ_1
|
|
* 0b001..REQ_2
|
|
* 0b010..REQ_4
|
|
* 0b011..REQ_8
|
|
* 0b100..REQ_16
|
|
*/
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|
#define LCDIF_CTRL2_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK)
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#define LCDIF_CTRL2_RSRVD5_MASK (0xFF000000U)
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|
#define LCDIF_CTRL2_RSRVD5_SHIFT (24U)
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|
#define LCDIF_CTRL2_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD5_SHIFT)) & LCDIF_CTRL2_RSRVD5_MASK)
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/*! @} */
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/*! @name CTRL2_SET - LCDIF General Control2 Register */
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|
/*! @{ */
|
|
#define LCDIF_CTRL2_SET_RSRVD0_MASK (0xFFFU)
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|
#define LCDIF_CTRL2_SET_RSRVD0_SHIFT (0U)
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|
#define LCDIF_CTRL2_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD0_SHIFT)) & LCDIF_CTRL2_SET_RSRVD0_MASK)
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|
#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK (0x7000U)
|
|
#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT (12U)
|
|
/*! EVEN_LINE_PATTERN
|
|
* 0b000..RGB
|
|
* 0b001..RBG
|
|
* 0b010..GBR
|
|
* 0b011..GRB
|
|
* 0b100..BRG
|
|
* 0b101..BGR
|
|
*/
|
|
#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK)
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|
#define LCDIF_CTRL2_SET_RSRVD3_MASK (0x8000U)
|
|
#define LCDIF_CTRL2_SET_RSRVD3_SHIFT (15U)
|
|
#define LCDIF_CTRL2_SET_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD3_SHIFT)) & LCDIF_CTRL2_SET_RSRVD3_MASK)
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|
#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK (0x70000U)
|
|
#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT (16U)
|
|
/*! ODD_LINE_PATTERN
|
|
* 0b000..RGB
|
|
* 0b001..RBG
|
|
* 0b010..GBR
|
|
* 0b011..GRB
|
|
* 0b100..BRG
|
|
* 0b101..BGR
|
|
*/
|
|
#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK)
|
|
#define LCDIF_CTRL2_SET_RSRVD4_MASK (0x80000U)
|
|
#define LCDIF_CTRL2_SET_RSRVD4_SHIFT (19U)
|
|
#define LCDIF_CTRL2_SET_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD4_SHIFT)) & LCDIF_CTRL2_SET_RSRVD4_MASK)
|
|
#define LCDIF_CTRL2_SET_BURST_LEN_8_MASK (0x100000U)
|
|
#define LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT (20U)
|
|
#define LCDIF_CTRL2_SET_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_SET_BURST_LEN_8_MASK)
|
|
#define LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK (0xE00000U)
|
|
#define LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT (21U)
|
|
/*! OUTSTANDING_REQS
|
|
* 0b000..REQ_1
|
|
* 0b001..REQ_2
|
|
* 0b010..REQ_4
|
|
* 0b011..REQ_8
|
|
* 0b100..REQ_16
|
|
*/
|
|
#define LCDIF_CTRL2_SET_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK)
|
|
#define LCDIF_CTRL2_SET_RSRVD5_MASK (0xFF000000U)
|
|
#define LCDIF_CTRL2_SET_RSRVD5_SHIFT (24U)
|
|
#define LCDIF_CTRL2_SET_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD5_SHIFT)) & LCDIF_CTRL2_SET_RSRVD5_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CTRL2_CLR - LCDIF General Control2 Register */
|
|
/*! @{ */
|
|
#define LCDIF_CTRL2_CLR_RSRVD0_MASK (0xFFFU)
|
|
#define LCDIF_CTRL2_CLR_RSRVD0_SHIFT (0U)
|
|
#define LCDIF_CTRL2_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD0_MASK)
|
|
#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK (0x7000U)
|
|
#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT (12U)
|
|
/*! EVEN_LINE_PATTERN
|
|
* 0b000..RGB
|
|
* 0b001..RBG
|
|
* 0b010..GBR
|
|
* 0b011..GRB
|
|
* 0b100..BRG
|
|
* 0b101..BGR
|
|
*/
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#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK)
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#define LCDIF_CTRL2_CLR_RSRVD3_MASK (0x8000U)
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#define LCDIF_CTRL2_CLR_RSRVD3_SHIFT (15U)
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#define LCDIF_CTRL2_CLR_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD3_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD3_MASK)
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#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK (0x70000U)
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#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT (16U)
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/*! ODD_LINE_PATTERN
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* 0b000..RGB
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* 0b001..RBG
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* 0b010..GBR
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* 0b011..GRB
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* 0b100..BRG
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* 0b101..BGR
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*/
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#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK)
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#define LCDIF_CTRL2_CLR_RSRVD4_MASK (0x80000U)
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#define LCDIF_CTRL2_CLR_RSRVD4_SHIFT (19U)
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#define LCDIF_CTRL2_CLR_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD4_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD4_MASK)
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#define LCDIF_CTRL2_CLR_BURST_LEN_8_MASK (0x100000U)
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#define LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT (20U)
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#define LCDIF_CTRL2_CLR_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_CLR_BURST_LEN_8_MASK)
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#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK (0xE00000U)
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#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT (21U)
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/*! OUTSTANDING_REQS
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* 0b000..REQ_1
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* 0b001..REQ_2
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* 0b010..REQ_4
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* 0b011..REQ_8
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* 0b100..REQ_16
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*/
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#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK)
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#define LCDIF_CTRL2_CLR_RSRVD5_MASK (0xFF000000U)
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#define LCDIF_CTRL2_CLR_RSRVD5_SHIFT (24U)
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#define LCDIF_CTRL2_CLR_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD5_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD5_MASK)
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/*! @} */
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/*! @name CTRL2_TOG - LCDIF General Control2 Register */
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/*! @{ */
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#define LCDIF_CTRL2_TOG_RSRVD0_MASK (0xFFFU)
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#define LCDIF_CTRL2_TOG_RSRVD0_SHIFT (0U)
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#define LCDIF_CTRL2_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD0_MASK)
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#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK (0x7000U)
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#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT (12U)
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/*! EVEN_LINE_PATTERN
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* 0b000..RGB
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* 0b001..RBG
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* 0b010..GBR
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* 0b011..GRB
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* 0b100..BRG
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* 0b101..BGR
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*/
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#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK)
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#define LCDIF_CTRL2_TOG_RSRVD3_MASK (0x8000U)
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#define LCDIF_CTRL2_TOG_RSRVD3_SHIFT (15U)
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#define LCDIF_CTRL2_TOG_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD3_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD3_MASK)
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#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK (0x70000U)
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#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT (16U)
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/*! ODD_LINE_PATTERN
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* 0b000..RGB
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* 0b001..RBG
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* 0b010..GBR
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* 0b011..GRB
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* 0b100..BRG
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* 0b101..BGR
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*/
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#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK)
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#define LCDIF_CTRL2_TOG_RSRVD4_MASK (0x80000U)
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#define LCDIF_CTRL2_TOG_RSRVD4_SHIFT (19U)
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#define LCDIF_CTRL2_TOG_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD4_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD4_MASK)
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#define LCDIF_CTRL2_TOG_BURST_LEN_8_MASK (0x100000U)
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#define LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT (20U)
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#define LCDIF_CTRL2_TOG_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_TOG_BURST_LEN_8_MASK)
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#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK (0xE00000U)
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#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT (21U)
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/*! OUTSTANDING_REQS
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* 0b000..REQ_1
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* 0b001..REQ_2
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* 0b010..REQ_4
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* 0b011..REQ_8
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* 0b100..REQ_16
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*/
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#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK)
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#define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U)
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#define LCDIF_CTRL2_TOG_RSRVD5_SHIFT (24U)
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#define LCDIF_CTRL2_TOG_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)
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/*! @} */
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/*! @name TRANSFER_COUNT - LCDIF Horizontal and Vertical Valid Data Count Register */
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/*! @{ */
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#define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xFFFFU)
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#define LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT (0U)
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#define LCDIF_TRANSFER_COUNT_H_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_H_COUNT_MASK)
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#define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xFFFF0000U)
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#define LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT (16U)
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#define LCDIF_TRANSFER_COUNT_V_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_V_COUNT_MASK)
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/*! @} */
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/*! @name CUR_BUF - LCD Interface Current Buffer Address Register */
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/*! @{ */
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#define LCDIF_CUR_BUF_ADDR_MASK (0xFFFFFFFFU)
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#define LCDIF_CUR_BUF_ADDR_SHIFT (0U)
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#define LCDIF_CUR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CUR_BUF_ADDR_SHIFT)) & LCDIF_CUR_BUF_ADDR_MASK)
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/*! @} */
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/*! @name NEXT_BUF - LCD Interface Next Buffer Address Register */
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/*! @{ */
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#define LCDIF_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU)
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#define LCDIF_NEXT_BUF_ADDR_SHIFT (0U)
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#define LCDIF_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_NEXT_BUF_ADDR_SHIFT)) & LCDIF_NEXT_BUF_ADDR_MASK)
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/*! @} */
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/*! @name VDCTRL0 - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */
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/*! @{ */
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#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
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#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT (0U)
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#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK)
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#define LCDIF_VDCTRL0_HALF_LINE_MODE_MASK (0x40000U)
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#define LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT (18U)
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#define LCDIF_VDCTRL0_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MODE_MASK)
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#define LCDIF_VDCTRL0_HALF_LINE_MASK (0x80000U)
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#define LCDIF_VDCTRL0_HALF_LINE_SHIFT (19U)
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#define LCDIF_VDCTRL0_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MASK)
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#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
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#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
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#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK)
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#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK (0x200000U)
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#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT (21U)
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#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK)
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#define LCDIF_VDCTRL0_RSRVD1_MASK (0xC00000U)
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#define LCDIF_VDCTRL0_RSRVD1_SHIFT (22U)
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#define LCDIF_VDCTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_RSRVD1_MASK)
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#define LCDIF_VDCTRL0_ENABLE_POL_MASK (0x1000000U)
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#define LCDIF_VDCTRL0_ENABLE_POL_SHIFT (24U)
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#define LCDIF_VDCTRL0_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_ENABLE_POL_MASK)
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#define LCDIF_VDCTRL0_DOTCLK_POL_MASK (0x2000000U)
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#define LCDIF_VDCTRL0_DOTCLK_POL_SHIFT (25U)
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#define LCDIF_VDCTRL0_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_DOTCLK_POL_MASK)
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#define LCDIF_VDCTRL0_HSYNC_POL_MASK (0x4000000U)
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#define LCDIF_VDCTRL0_HSYNC_POL_SHIFT (26U)
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#define LCDIF_VDCTRL0_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_HSYNC_POL_MASK)
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#define LCDIF_VDCTRL0_VSYNC_POL_MASK (0x8000000U)
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#define LCDIF_VDCTRL0_VSYNC_POL_SHIFT (27U)
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#define LCDIF_VDCTRL0_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_VSYNC_POL_MASK)
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#define LCDIF_VDCTRL0_ENABLE_PRESENT_MASK (0x10000000U)
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#define LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT (28U)
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#define LCDIF_VDCTRL0_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_ENABLE_PRESENT_MASK)
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#define LCDIF_VDCTRL0_RSRVD2_MASK (0xE0000000U)
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#define LCDIF_VDCTRL0_RSRVD2_SHIFT (29U)
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#define LCDIF_VDCTRL0_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_RSRVD2_MASK)
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/*! @} */
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/*! @name VDCTRL0_SET - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */
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/*! @{ */
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#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
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#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT (0U)
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#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK)
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#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK (0x40000U)
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#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT (18U)
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#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK)
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#define LCDIF_VDCTRL0_SET_HALF_LINE_MASK (0x80000U)
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#define LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT (19U)
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#define LCDIF_VDCTRL0_SET_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MASK)
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#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
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#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
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#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK)
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#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK (0x200000U)
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#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT (21U)
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#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK)
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#define LCDIF_VDCTRL0_SET_RSRVD1_MASK (0xC00000U)
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#define LCDIF_VDCTRL0_SET_RSRVD1_SHIFT (22U)
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#define LCDIF_VDCTRL0_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD1_MASK)
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#define LCDIF_VDCTRL0_SET_ENABLE_POL_MASK (0x1000000U)
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#define LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT (24U)
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#define LCDIF_VDCTRL0_SET_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_POL_MASK)
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#define LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK (0x2000000U)
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#define LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT (25U)
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#define LCDIF_VDCTRL0_SET_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK)
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#define LCDIF_VDCTRL0_SET_HSYNC_POL_MASK (0x4000000U)
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#define LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT (26U)
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#define LCDIF_VDCTRL0_SET_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_HSYNC_POL_MASK)
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#define LCDIF_VDCTRL0_SET_VSYNC_POL_MASK (0x8000000U)
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#define LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT (27U)
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#define LCDIF_VDCTRL0_SET_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_POL_MASK)
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#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK (0x10000000U)
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#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT (28U)
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#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK)
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#define LCDIF_VDCTRL0_SET_RSRVD2_MASK (0xE0000000U)
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#define LCDIF_VDCTRL0_SET_RSRVD2_SHIFT (29U)
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#define LCDIF_VDCTRL0_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD2_MASK)
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/*! @} */
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/*! @name VDCTRL0_CLR - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */
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/*! @{ */
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#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
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#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT (0U)
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#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK)
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#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK (0x40000U)
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#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT (18U)
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#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK)
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#define LCDIF_VDCTRL0_CLR_HALF_LINE_MASK (0x80000U)
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#define LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT (19U)
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#define LCDIF_VDCTRL0_CLR_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MASK)
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#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
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#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
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#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK)
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#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK (0x200000U)
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#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT (21U)
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#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK)
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#define LCDIF_VDCTRL0_CLR_RSRVD1_MASK (0xC00000U)
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#define LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT (22U)
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#define LCDIF_VDCTRL0_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD1_MASK)
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#define LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK (0x1000000U)
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#define LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT (24U)
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#define LCDIF_VDCTRL0_CLR_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK)
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#define LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK (0x2000000U)
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#define LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT (25U)
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#define LCDIF_VDCTRL0_CLR_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK)
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#define LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK (0x4000000U)
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#define LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT (26U)
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#define LCDIF_VDCTRL0_CLR_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK)
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#define LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK (0x8000000U)
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#define LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT (27U)
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#define LCDIF_VDCTRL0_CLR_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK)
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#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK (0x10000000U)
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#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT (28U)
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#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK)
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#define LCDIF_VDCTRL0_CLR_RSRVD2_MASK (0xE0000000U)
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#define LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT (29U)
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#define LCDIF_VDCTRL0_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD2_MASK)
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/*! @} */
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/*! @name VDCTRL0_TOG - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */
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/*! @{ */
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#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
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#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT (0U)
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#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK)
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#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK (0x40000U)
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#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT (18U)
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#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK)
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#define LCDIF_VDCTRL0_TOG_HALF_LINE_MASK (0x80000U)
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#define LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT (19U)
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#define LCDIF_VDCTRL0_TOG_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MASK)
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#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
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#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
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#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK)
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#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK (0x200000U)
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#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT (21U)
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#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK)
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#define LCDIF_VDCTRL0_TOG_RSRVD1_MASK (0xC00000U)
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#define LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT (22U)
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#define LCDIF_VDCTRL0_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD1_MASK)
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#define LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK (0x1000000U)
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#define LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT (24U)
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#define LCDIF_VDCTRL0_TOG_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK)
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#define LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK (0x2000000U)
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#define LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT (25U)
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#define LCDIF_VDCTRL0_TOG_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK)
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#define LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK (0x4000000U)
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#define LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT (26U)
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#define LCDIF_VDCTRL0_TOG_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK)
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#define LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK (0x8000000U)
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#define LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT (27U)
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#define LCDIF_VDCTRL0_TOG_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK)
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#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK (0x10000000U)
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#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT (28U)
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#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK)
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#define LCDIF_VDCTRL0_TOG_RSRVD2_MASK (0xE0000000U)
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#define LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT (29U)
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#define LCDIF_VDCTRL0_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD2_MASK)
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/*! @} */
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/*! @name VDCTRL1 - LCDIF VSYNC Mode and Dotclk Mode Control Register1 */
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/*! @{ */
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#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK (0xFFFFFFFFU)
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#define LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT (0U)
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#define LCDIF_VDCTRL1_VSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL1_VSYNC_PERIOD_MASK)
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/*! @} */
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/*! @name VDCTRL2 - LCDIF VSYNC Mode and Dotclk Mode Control Register2 */
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/*! @{ */
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#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK (0x3FFFFU)
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#define LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT (0U)
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#define LCDIF_VDCTRL2_HSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PERIOD_MASK)
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#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xFFFC0000U)
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#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT (18U)
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#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK)
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/*! @} */
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/*! @name VDCTRL3 - LCDIF VSYNC Mode and Dotclk Mode Control Register3 */
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/*! @{ */
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#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xFFFFU)
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#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT (0U)
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#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK)
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#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xFFF0000U)
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#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT (16U)
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#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK)
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#define LCDIF_VDCTRL3_VSYNC_ONLY_MASK (0x10000000U)
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#define LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT (28U)
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#define LCDIF_VDCTRL3_VSYNC_ONLY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT)) & LCDIF_VDCTRL3_VSYNC_ONLY_MASK)
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#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK (0x20000000U)
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#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT (29U)
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#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT)) & LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK)
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#define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U)
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#define LCDIF_VDCTRL3_RSRVD0_SHIFT (30U)
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#define LCDIF_VDCTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)
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/*! @} */
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/*! @name VDCTRL4 - LCDIF VSYNC Mode and Dotclk Mode Control Register4 */
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/*! @{ */
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#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK (0x3FFFFU)
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#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT (0U)
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#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK)
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#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK (0x40000U)
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#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT (18U)
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#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT)) & LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK)
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#define LCDIF_VDCTRL4_RSRVD0_MASK (0x1FF80000U)
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#define LCDIF_VDCTRL4_RSRVD0_SHIFT (19U)
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#define LCDIF_VDCTRL4_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_RSRVD0_SHIFT)) & LCDIF_VDCTRL4_RSRVD0_MASK)
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#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0xE0000000U)
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#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT (29U)
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#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK)
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/*! @} */
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/*! @name BM_ERROR_STAT - Bus Master Error Status Register */
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/*! @{ */
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#define LCDIF_BM_ERROR_STAT_ADDR_MASK (0xFFFFFFFFU)
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#define LCDIF_BM_ERROR_STAT_ADDR_SHIFT (0U)
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#define LCDIF_BM_ERROR_STAT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_BM_ERROR_STAT_ADDR_SHIFT)) & LCDIF_BM_ERROR_STAT_ADDR_MASK)
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/*! @} */
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/*! @name CRC_STAT - CRC Status Register */
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/*! @{ */
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#define LCDIF_CRC_STAT_CRC_VALUE_MASK (0xFFFFFFFFU)
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#define LCDIF_CRC_STAT_CRC_VALUE_SHIFT (0U)
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#define LCDIF_CRC_STAT_CRC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CRC_STAT_CRC_VALUE_SHIFT)) & LCDIF_CRC_STAT_CRC_VALUE_MASK)
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/*! @} */
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/*! @name STAT - LCD Interface Status Register */
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/*! @{ */
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#define LCDIF_STAT_LFIFO_COUNT_MASK (0x1FFU)
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#define LCDIF_STAT_LFIFO_COUNT_SHIFT (0U)
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#define LCDIF_STAT_LFIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_COUNT_SHIFT)) & LCDIF_STAT_LFIFO_COUNT_MASK)
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#define LCDIF_STAT_RSRVD0_MASK (0x1FFFE00U)
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#define LCDIF_STAT_RSRVD0_SHIFT (9U)
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#define LCDIF_STAT_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_RSRVD0_SHIFT)) & LCDIF_STAT_RSRVD0_MASK)
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#define LCDIF_STAT_TXFIFO_EMPTY_MASK (0x4000000U)
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#define LCDIF_STAT_TXFIFO_EMPTY_SHIFT (26U)
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#define LCDIF_STAT_TXFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_EMPTY_SHIFT)) & LCDIF_STAT_TXFIFO_EMPTY_MASK)
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#define LCDIF_STAT_TXFIFO_FULL_MASK (0x8000000U)
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#define LCDIF_STAT_TXFIFO_FULL_SHIFT (27U)
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#define LCDIF_STAT_TXFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_FULL_SHIFT)) & LCDIF_STAT_TXFIFO_FULL_MASK)
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#define LCDIF_STAT_LFIFO_EMPTY_MASK (0x10000000U)
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#define LCDIF_STAT_LFIFO_EMPTY_SHIFT (28U)
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#define LCDIF_STAT_LFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_EMPTY_SHIFT)) & LCDIF_STAT_LFIFO_EMPTY_MASK)
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#define LCDIF_STAT_LFIFO_FULL_MASK (0x20000000U)
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#define LCDIF_STAT_LFIFO_FULL_SHIFT (29U)
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#define LCDIF_STAT_LFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_FULL_SHIFT)) & LCDIF_STAT_LFIFO_FULL_MASK)
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#define LCDIF_STAT_DMA_REQ_MASK (0x40000000U)
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#define LCDIF_STAT_DMA_REQ_SHIFT (30U)
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#define LCDIF_STAT_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_DMA_REQ_SHIFT)) & LCDIF_STAT_DMA_REQ_MASK)
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#define LCDIF_STAT_PRESENT_MASK (0x80000000U)
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#define LCDIF_STAT_PRESENT_SHIFT (31U)
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#define LCDIF_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_PRESENT_SHIFT)) & LCDIF_STAT_PRESENT_MASK)
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/*! @} */
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/*! @name THRES - LCDIF Threshold Register */
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/*! @{ */
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#define LCDIF_THRES_PANIC_MASK (0x1FFU)
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#define LCDIF_THRES_PANIC_SHIFT (0U)
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#define LCDIF_THRES_PANIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_PANIC_SHIFT)) & LCDIF_THRES_PANIC_MASK)
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#define LCDIF_THRES_RSRVD1_MASK (0xFE00U)
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#define LCDIF_THRES_RSRVD1_SHIFT (9U)
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#define LCDIF_THRES_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD1_SHIFT)) & LCDIF_THRES_RSRVD1_MASK)
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#define LCDIF_THRES_FASTCLOCK_MASK (0x1FF0000U)
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#define LCDIF_THRES_FASTCLOCK_SHIFT (16U)
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#define LCDIF_THRES_FASTCLOCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_FASTCLOCK_SHIFT)) & LCDIF_THRES_FASTCLOCK_MASK)
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#define LCDIF_THRES_RSRVD2_MASK (0xFE000000U)
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#define LCDIF_THRES_RSRVD2_SHIFT (25U)
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#define LCDIF_THRES_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD2_SHIFT)) & LCDIF_THRES_RSRVD2_MASK)
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/*! @} */
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/*! @name PIGEONCTRL0 - LCDIF Pigeon Mode Control0 Register */
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/*! @{ */
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#define LCDIF_PIGEONCTRL0_FD_PERIOD_MASK (0xFFFU)
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#define LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT (0U)
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#define LCDIF_PIGEONCTRL0_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_FD_PERIOD_MASK)
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#define LCDIF_PIGEONCTRL0_LD_PERIOD_MASK (0xFFF0000U)
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#define LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT (16U)
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#define LCDIF_PIGEONCTRL0_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_LD_PERIOD_MASK)
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/*! @} */
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/*! @name PIGEONCTRL0_SET - LCDIF Pigeon Mode Control0 Register */
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/*! @{ */
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#define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK (0xFFFU)
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#define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT (0U)
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#define LCDIF_PIGEONCTRL0_SET_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK)
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#define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK (0xFFF0000U)
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#define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT (16U)
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#define LCDIF_PIGEONCTRL0_SET_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK)
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/*! @} */
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/*! @name PIGEONCTRL0_CLR - LCDIF Pigeon Mode Control0 Register */
|
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/*! @{ */
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#define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK (0xFFFU)
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#define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT (0U)
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#define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK)
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#define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK (0xFFF0000U)
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#define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT (16U)
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#define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK)
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/*! @} */
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/*! @name PIGEONCTRL0_TOG - LCDIF Pigeon Mode Control0 Register */
|
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/*! @{ */
|
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#define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK (0xFFFU)
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#define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT (0U)
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#define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK)
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#define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK (0xFFF0000U)
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#define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT (16U)
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#define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK)
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/*! @} */
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/*! @name PIGEONCTRL1 - LCDIF Pigeon Mode Control1 Register */
|
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/*! @{ */
|
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#define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK (0xFFFU)
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#define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT (0U)
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#define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK)
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#define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
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#define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT (16U)
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#define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK)
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/*! @} */
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/*! @name PIGEONCTRL1_SET - LCDIF Pigeon Mode Control1 Register */
|
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/*! @{ */
|
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#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK (0xFFFU)
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#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT (0U)
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#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK)
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#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
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#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT (16U)
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#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK)
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/*! @} */
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/*! @name PIGEONCTRL1_CLR - LCDIF Pigeon Mode Control1 Register */
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/*! @{ */
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#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK (0xFFFU)
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#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT (0U)
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#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK)
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#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
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#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT (16U)
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#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK)
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/*! @} */
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/*! @name PIGEONCTRL1_TOG - LCDIF Pigeon Mode Control1 Register */
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/*! @{ */
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#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK (0xFFFU)
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#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT (0U)
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#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK)
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#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
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#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT (16U)
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#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK)
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/*! @} */
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/*! @name PIGEONCTRL2 - LCDIF Pigeon Mode Control2 Register */
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/*! @{ */
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#define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK (0x1U)
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#define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT (0U)
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#define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK)
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#define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK (0x2U)
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#define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT (1U)
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#define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK)
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/*! @} */
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/*! @name PIGEONCTRL2_SET - LCDIF Pigeon Mode Control2 Register */
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/*! @{ */
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#define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK (0x1U)
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#define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT (0U)
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#define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK)
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#define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK (0x2U)
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#define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT (1U)
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#define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK)
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/*! @} */
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/*! @name PIGEONCTRL2_CLR - LCDIF Pigeon Mode Control2 Register */
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/*! @{ */
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#define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK (0x1U)
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#define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT (0U)
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#define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK)
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#define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK (0x2U)
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#define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT (1U)
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#define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK)
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/*! @} */
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/*! @name PIGEONCTRL2_TOG - LCDIF Pigeon Mode Control2 Register */
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/*! @{ */
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#define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK (0x1U)
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#define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT (0U)
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#define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK)
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#define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK (0x2U)
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#define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT (1U)
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#define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK)
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/*! @} */
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/*! @name PIGEON_0 - Panel Interface Signal Generator Register */
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/*! @{ */
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#define LCDIF_PIGEON_0_EN_MASK (0x1U)
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#define LCDIF_PIGEON_0_EN_SHIFT (0U)
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#define LCDIF_PIGEON_0_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_EN_SHIFT)) & LCDIF_PIGEON_0_EN_MASK)
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#define LCDIF_PIGEON_0_POL_MASK (0x2U)
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#define LCDIF_PIGEON_0_POL_SHIFT (1U)
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/*! POL
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* 0b0..Normal Signal (Active high)
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* 0b1..Inverted signal (Active low)
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*/
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#define LCDIF_PIGEON_0_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_POL_SHIFT)) & LCDIF_PIGEON_0_POL_MASK)
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#define LCDIF_PIGEON_0_INC_SEL_MASK (0xCU)
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#define LCDIF_PIGEON_0_INC_SEL_SHIFT (2U)
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/*! INC_SEL
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* 0b00..pclk
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* 0b01..Line start pulse
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* 0b10..Frame start pulse
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* 0b11..Use another signal as tick event
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*/
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#define LCDIF_PIGEON_0_INC_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_INC_SEL_SHIFT)) & LCDIF_PIGEON_0_INC_SEL_MASK)
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#define LCDIF_PIGEON_0_OFFSET_MASK (0xF0U)
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#define LCDIF_PIGEON_0_OFFSET_SHIFT (4U)
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#define LCDIF_PIGEON_0_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_OFFSET_SHIFT)) & LCDIF_PIGEON_0_OFFSET_MASK)
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#define LCDIF_PIGEON_0_MASK_CNT_SEL_MASK (0xF00U)
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#define LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT (8U)
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/*! MASK_CNT_SEL
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* 0b0000..pclk counter within one hscan state
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* 0b0001..pclk cycle within one hscan state
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* 0b0010..line counter within one vscan state
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* 0b0011..line cycle within one vscan state
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* 0b0100..frame counter
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* 0b0101..frame cycle
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* 0b0110..horizontal counter (pclk counter within one line )
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* 0b0111..vertical counter (line counter within one frame)
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*/
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#define LCDIF_PIGEON_0_MASK_CNT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_SEL_MASK)
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#define LCDIF_PIGEON_0_MASK_CNT_MASK (0xFFF000U)
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#define LCDIF_PIGEON_0_MASK_CNT_SHIFT (12U)
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#define LCDIF_PIGEON_0_MASK_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_MASK)
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#define LCDIF_PIGEON_0_STATE_MASK_MASK (0xFF000000U)
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#define LCDIF_PIGEON_0_STATE_MASK_SHIFT (24U)
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/*! STATE_MASK
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* 0b00000001..FRAME SYNC
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* 0b00000010..FRAME BEGIN
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* 0b00000100..FRAME DATA
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* 0b00001000..FRAME END
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* 0b00010000..LINE SYNC
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* 0b00100000..LINE BEGIN
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* 0b01000000..LINE DATA
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* 0b10000000..LINE END
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*/
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#define LCDIF_PIGEON_0_STATE_MASK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_STATE_MASK_SHIFT)) & LCDIF_PIGEON_0_STATE_MASK_MASK)
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/*! @} */
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/* The count of LCDIF_PIGEON_0 */
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#define LCDIF_PIGEON_0_COUNT (12U)
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/*! @name PIGEON_1 - Panel Interface Signal Generator Register */
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/*! @{ */
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#define LCDIF_PIGEON_1_SET_CNT_MASK (0xFFFFU)
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#define LCDIF_PIGEON_1_SET_CNT_SHIFT (0U)
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/*! SET_CNT
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* 0b0000000000000000..Start as active
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*/
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#define LCDIF_PIGEON_1_SET_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_SET_CNT_SHIFT)) & LCDIF_PIGEON_1_SET_CNT_MASK)
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#define LCDIF_PIGEON_1_CLR_CNT_MASK (0xFFFF0000U)
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#define LCDIF_PIGEON_1_CLR_CNT_SHIFT (16U)
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/*! CLR_CNT
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* 0b0000000000000000..Keep active until mask off
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*/
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#define LCDIF_PIGEON_1_CLR_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_CLR_CNT_SHIFT)) & LCDIF_PIGEON_1_CLR_CNT_MASK)
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/*! @} */
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/* The count of LCDIF_PIGEON_1 */
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#define LCDIF_PIGEON_1_COUNT (12U)
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/*! @name PIGEON_2 - Panel Interface Signal Generator Register */
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/*! @{ */
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#define LCDIF_PIGEON_2_SIG_LOGIC_MASK (0xFU)
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#define LCDIF_PIGEON_2_SIG_LOGIC_SHIFT (0U)
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/*! SIG_LOGIC
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* 0b0000..No logic operation
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* 0b0001..sigout = sig_another AND this_sig
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* 0b0010..sigout = sig_another OR this_sig
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* 0b0011..mask = sig_another AND other_masks
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*/
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#define LCDIF_PIGEON_2_SIG_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_LOGIC_SHIFT)) & LCDIF_PIGEON_2_SIG_LOGIC_MASK)
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#define LCDIF_PIGEON_2_SIG_ANOTHER_MASK (0x1F0U)
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#define LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT (4U)
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/*! SIG_ANOTHER
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* 0b00000..Keep active until mask off
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*/
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#define LCDIF_PIGEON_2_SIG_ANOTHER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT)) & LCDIF_PIGEON_2_SIG_ANOTHER_MASK)
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#define LCDIF_PIGEON_2_RSVD_MASK (0xFFFFFE00U)
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#define LCDIF_PIGEON_2_RSVD_SHIFT (9U)
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#define LCDIF_PIGEON_2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_RSVD_SHIFT)) & LCDIF_PIGEON_2_RSVD_MASK)
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/*! @} */
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/* The count of LCDIF_PIGEON_2 */
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#define LCDIF_PIGEON_2_COUNT (12U)
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/*! @name LUT_CTRL - Lookup Table Data Register. */
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/*! @{ */
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#define LCDIF_LUT_CTRL_LUT_BYPASS_MASK (0x1U)
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#define LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT (0U)
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#define LCDIF_LUT_CTRL_LUT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT)) & LCDIF_LUT_CTRL_LUT_BYPASS_MASK)
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/*! @} */
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/*! @name LUT0_ADDR - Lookup Table Control Register. */
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/*! @{ */
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#define LCDIF_LUT0_ADDR_ADDR_MASK (0xFFU)
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#define LCDIF_LUT0_ADDR_ADDR_SHIFT (0U)
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#define LCDIF_LUT0_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_ADDR_ADDR_SHIFT)) & LCDIF_LUT0_ADDR_ADDR_MASK)
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/*! @} */
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/*! @name LUT0_DATA - Lookup Table Data Register. */
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/*! @{ */
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#define LCDIF_LUT0_DATA_DATA_MASK (0xFFFFFFFFU)
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#define LCDIF_LUT0_DATA_DATA_SHIFT (0U)
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#define LCDIF_LUT0_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_DATA_DATA_SHIFT)) & LCDIF_LUT0_DATA_DATA_MASK)
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/*! @} */
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/*! @name LUT1_ADDR - Lookup Table Control Register. */
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/*! @{ */
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#define LCDIF_LUT1_ADDR_ADDR_MASK (0xFFU)
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#define LCDIF_LUT1_ADDR_ADDR_SHIFT (0U)
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#define LCDIF_LUT1_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_ADDR_ADDR_SHIFT)) & LCDIF_LUT1_ADDR_ADDR_MASK)
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/*! @} */
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/*! @name LUT1_DATA - Lookup Table Data Register. */
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/*! @{ */
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#define LCDIF_LUT1_DATA_DATA_MASK (0xFFFFFFFFU)
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#define LCDIF_LUT1_DATA_DATA_SHIFT (0U)
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#define LCDIF_LUT1_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_DATA_DATA_SHIFT)) & LCDIF_LUT1_DATA_DATA_MASK)
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/*! @} */
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/*!
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* @}
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*/ /* end of group LCDIF_Register_Masks */
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/* LCDIF - Peripheral instance base addresses */
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/** Peripheral LCDIF base address */
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#define LCDIF_BASE (0x402B8000u)
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/** Peripheral LCDIF base pointer */
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#define LCDIF ((LCDIF_Type *)LCDIF_BASE)
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/** Array initializer of LCDIF peripheral base addresses */
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#define LCDIF_BASE_ADDRS { LCDIF_BASE }
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/** Array initializer of LCDIF peripheral base pointers */
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#define LCDIF_BASE_PTRS { LCDIF }
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/** Interrupt vectors for the LCDIF peripheral type */
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#define LCDIF_IRQ0_IRQS { LCDIF_IRQn }
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/*!
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* @}
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*/ /* end of group LCDIF_Peripheral_Access_Layer */
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/* ----------------------------------------------------------------------------
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-- LPI2C Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer
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* @{
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*/
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/** LPI2C - Register Layout Typedef */
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typedef struct {
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__I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
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__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
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uint8_t RESERVED_0[8];
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__IO uint32_t MCR; /**< Master Control Register, offset: 0x10 */
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__IO uint32_t MSR; /**< Master Status Register, offset: 0x14 */
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__IO uint32_t MIER; /**< Master Interrupt Enable Register, offset: 0x18 */
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__IO uint32_t MDER; /**< Master DMA Enable Register, offset: 0x1C */
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__IO uint32_t MCFGR0; /**< Master Configuration Register 0, offset: 0x20 */
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__IO uint32_t MCFGR1; /**< Master Configuration Register 1, offset: 0x24 */
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__IO uint32_t MCFGR2; /**< Master Configuration Register 2, offset: 0x28 */
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__IO uint32_t MCFGR3; /**< Master Configuration Register 3, offset: 0x2C */
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uint8_t RESERVED_1[16];
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__IO uint32_t MDMR; /**< Master Data Match Register, offset: 0x40 */
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uint8_t RESERVED_2[4];
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__IO uint32_t MCCR0; /**< Master Clock Configuration Register 0, offset: 0x48 */
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uint8_t RESERVED_3[4];
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__IO uint32_t MCCR1; /**< Master Clock Configuration Register 1, offset: 0x50 */
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uint8_t RESERVED_4[4];
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__IO uint32_t MFCR; /**< Master FIFO Control Register, offset: 0x58 */
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|
__I uint32_t MFSR; /**< Master FIFO Status Register, offset: 0x5C */
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|
__O uint32_t MTDR; /**< Master Transmit Data Register, offset: 0x60 */
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|
uint8_t RESERVED_5[12];
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__I uint32_t MRDR; /**< Master Receive Data Register, offset: 0x70 */
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|
uint8_t RESERVED_6[156];
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__IO uint32_t SCR; /**< Slave Control Register, offset: 0x110 */
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|
__IO uint32_t SSR; /**< Slave Status Register, offset: 0x114 */
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|
__IO uint32_t SIER; /**< Slave Interrupt Enable Register, offset: 0x118 */
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|
__IO uint32_t SDER; /**< Slave DMA Enable Register, offset: 0x11C */
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|
uint8_t RESERVED_7[4];
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|
__IO uint32_t SCFGR1; /**< Slave Configuration Register 1, offset: 0x124 */
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|
__IO uint32_t SCFGR2; /**< Slave Configuration Register 2, offset: 0x128 */
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|
uint8_t RESERVED_8[20];
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|
__IO uint32_t SAMR; /**< Slave Address Match Register, offset: 0x140 */
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|
uint8_t RESERVED_9[12];
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|
__I uint32_t SASR; /**< Slave Address Status Register, offset: 0x150 */
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|
__IO uint32_t STAR; /**< Slave Transmit ACK Register, offset: 0x154 */
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|
uint8_t RESERVED_10[8];
|
|
__O uint32_t STDR; /**< Slave Transmit Data Register, offset: 0x160 */
|
|
uint8_t RESERVED_11[12];
|
|
__I uint32_t SRDR; /**< Slave Receive Data Register, offset: 0x170 */
|
|
} LPI2C_Type;
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|
|
/* ----------------------------------------------------------------------------
|
|
-- LPI2C Register Masks
|
|
---------------------------------------------------------------------------- */
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|
|
/*!
|
|
* @addtogroup LPI2C_Register_Masks LPI2C Register Masks
|
|
* @{
|
|
*/
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|
|
|
/*! @name VERID - Version ID Register */
|
|
/*! @{ */
|
|
#define LPI2C_VERID_FEATURE_MASK (0xFFFFU)
|
|
#define LPI2C_VERID_FEATURE_SHIFT (0U)
|
|
/*! FEATURE - Feature Specification Number
|
|
* 0b0000000000000010..Master only, with standard feature set
|
|
* 0b0000000000000011..Master and slave, with standard feature set
|
|
*/
|
|
#define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)
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|
#define LPI2C_VERID_MINOR_MASK (0xFF0000U)
|
|
#define LPI2C_VERID_MINOR_SHIFT (16U)
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|
#define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)
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|
#define LPI2C_VERID_MAJOR_MASK (0xFF000000U)
|
|
#define LPI2C_VERID_MAJOR_SHIFT (24U)
|
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#define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PARAM - Parameter Register */
|
|
/*! @{ */
|
|
#define LPI2C_PARAM_MTXFIFO_MASK (0xFU)
|
|
#define LPI2C_PARAM_MTXFIFO_SHIFT (0U)
|
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#define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)
|
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#define LPI2C_PARAM_MRXFIFO_MASK (0xF00U)
|
|
#define LPI2C_PARAM_MRXFIFO_SHIFT (8U)
|
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#define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MCR - Master Control Register */
|
|
/*! @{ */
|
|
#define LPI2C_MCR_MEN_MASK (0x1U)
|
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#define LPI2C_MCR_MEN_SHIFT (0U)
|
|
/*! MEN - Master Enable
|
|
* 0b0..Master logic is disabled
|
|
* 0b1..Master logic is enabled
|
|
*/
|
|
#define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)
|
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#define LPI2C_MCR_RST_MASK (0x2U)
|
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#define LPI2C_MCR_RST_SHIFT (1U)
|
|
/*! RST - Software Reset
|
|
* 0b0..Master logic is not reset
|
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* 0b1..Master logic is reset
|
|
*/
|
|
#define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)
|
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#define LPI2C_MCR_DOZEN_MASK (0x4U)
|
|
#define LPI2C_MCR_DOZEN_SHIFT (2U)
|
|
/*! DOZEN - Doze mode enable
|
|
* 0b0..Master is enabled in Doze mode
|
|
* 0b1..Master is disabled in Doze mode
|
|
*/
|
|
#define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)
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#define LPI2C_MCR_DBGEN_MASK (0x8U)
|
|
#define LPI2C_MCR_DBGEN_SHIFT (3U)
|
|
/*! DBGEN - Debug Enable
|
|
* 0b0..Master is disabled in debug mode
|
|
* 0b1..Master is enabled in debug mode
|
|
*/
|
|
#define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)
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#define LPI2C_MCR_RTF_MASK (0x100U)
|
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#define LPI2C_MCR_RTF_SHIFT (8U)
|
|
/*! RTF - Reset Transmit FIFO
|
|
* 0b0..No effect
|
|
* 0b1..Transmit FIFO is reset
|
|
*/
|
|
#define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)
|
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#define LPI2C_MCR_RRF_MASK (0x200U)
|
|
#define LPI2C_MCR_RRF_SHIFT (9U)
|
|
/*! RRF - Reset Receive FIFO
|
|
* 0b0..No effect
|
|
* 0b1..Receive FIFO is reset
|
|
*/
|
|
#define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MSR - Master Status Register */
|
|
/*! @{ */
|
|
#define LPI2C_MSR_TDF_MASK (0x1U)
|
|
#define LPI2C_MSR_TDF_SHIFT (0U)
|
|
/*! TDF - Transmit Data Flag
|
|
* 0b0..Transmit data is not requested
|
|
* 0b1..Transmit data is requested
|
|
*/
|
|
#define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)
|
|
#define LPI2C_MSR_RDF_MASK (0x2U)
|
|
#define LPI2C_MSR_RDF_SHIFT (1U)
|
|
/*! RDF - Receive Data Flag
|
|
* 0b0..Receive Data is not ready
|
|
* 0b1..Receive data is ready
|
|
*/
|
|
#define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)
|
|
#define LPI2C_MSR_EPF_MASK (0x100U)
|
|
#define LPI2C_MSR_EPF_SHIFT (8U)
|
|
/*! EPF - End Packet Flag
|
|
* 0b0..Master has not generated a STOP or Repeated START condition
|
|
* 0b1..Master has generated a STOP or Repeated START condition
|
|
*/
|
|
#define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)
|
|
#define LPI2C_MSR_SDF_MASK (0x200U)
|
|
#define LPI2C_MSR_SDF_SHIFT (9U)
|
|
/*! SDF - STOP Detect Flag
|
|
* 0b0..Master has not generated a STOP condition
|
|
* 0b1..Master has generated a STOP condition
|
|
*/
|
|
#define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)
|
|
#define LPI2C_MSR_NDF_MASK (0x400U)
|
|
#define LPI2C_MSR_NDF_SHIFT (10U)
|
|
/*! NDF - NACK Detect Flag
|
|
* 0b0..Unexpected NACK was not detected
|
|
* 0b1..Unexpected NACK was detected
|
|
*/
|
|
#define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)
|
|
#define LPI2C_MSR_ALF_MASK (0x800U)
|
|
#define LPI2C_MSR_ALF_SHIFT (11U)
|
|
/*! ALF - Arbitration Lost Flag
|
|
* 0b0..Master has not lost arbitration
|
|
* 0b1..Master has lost arbitration
|
|
*/
|
|
#define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)
|
|
#define LPI2C_MSR_FEF_MASK (0x1000U)
|
|
#define LPI2C_MSR_FEF_SHIFT (12U)
|
|
/*! FEF - FIFO Error Flag
|
|
* 0b0..No error
|
|
* 0b1..Master sending or receiving data without a START condition
|
|
*/
|
|
#define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)
|
|
#define LPI2C_MSR_PLTF_MASK (0x2000U)
|
|
#define LPI2C_MSR_PLTF_SHIFT (13U)
|
|
/*! PLTF - Pin Low Timeout Flag
|
|
* 0b0..Pin low timeout has not occurred or is disabled
|
|
* 0b1..Pin low timeout has occurred
|
|
*/
|
|
#define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)
|
|
#define LPI2C_MSR_DMF_MASK (0x4000U)
|
|
#define LPI2C_MSR_DMF_SHIFT (14U)
|
|
/*! DMF - Data Match Flag
|
|
* 0b0..Have not received matching data
|
|
* 0b1..Have received matching data
|
|
*/
|
|
#define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)
|
|
#define LPI2C_MSR_MBF_MASK (0x1000000U)
|
|
#define LPI2C_MSR_MBF_SHIFT (24U)
|
|
/*! MBF - Master Busy Flag
|
|
* 0b0..I2C Master is idle
|
|
* 0b1..I2C Master is busy
|
|
*/
|
|
#define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)
|
|
#define LPI2C_MSR_BBF_MASK (0x2000000U)
|
|
#define LPI2C_MSR_BBF_SHIFT (25U)
|
|
/*! BBF - Bus Busy Flag
|
|
* 0b0..I2C Bus is idle
|
|
* 0b1..I2C Bus is busy
|
|
*/
|
|
#define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MIER - Master Interrupt Enable Register */
|
|
/*! @{ */
|
|
#define LPI2C_MIER_TDIE_MASK (0x1U)
|
|
#define LPI2C_MIER_TDIE_SHIFT (0U)
|
|
/*! TDIE - Transmit Data Interrupt Enable
|
|
* 0b0..Disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)
|
|
#define LPI2C_MIER_RDIE_MASK (0x2U)
|
|
#define LPI2C_MIER_RDIE_SHIFT (1U)
|
|
/*! RDIE - Receive Data Interrupt Enable
|
|
* 0b0..Disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)
|
|
#define LPI2C_MIER_EPIE_MASK (0x100U)
|
|
#define LPI2C_MIER_EPIE_SHIFT (8U)
|
|
/*! EPIE - End Packet Interrupt Enable
|
|
* 0b0..Disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)
|
|
#define LPI2C_MIER_SDIE_MASK (0x200U)
|
|
#define LPI2C_MIER_SDIE_SHIFT (9U)
|
|
/*! SDIE - STOP Detect Interrupt Enable
|
|
* 0b0..Disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)
|
|
#define LPI2C_MIER_NDIE_MASK (0x400U)
|
|
#define LPI2C_MIER_NDIE_SHIFT (10U)
|
|
/*! NDIE - NACK Detect Interrupt Enable
|
|
* 0b0..Disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)
|
|
#define LPI2C_MIER_ALIE_MASK (0x800U)
|
|
#define LPI2C_MIER_ALIE_SHIFT (11U)
|
|
/*! ALIE - Arbitration Lost Interrupt Enable
|
|
* 0b0..Disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)
|
|
#define LPI2C_MIER_FEIE_MASK (0x1000U)
|
|
#define LPI2C_MIER_FEIE_SHIFT (12U)
|
|
/*! FEIE - FIFO Error Interrupt Enable
|
|
* 0b0..Enabled
|
|
* 0b1..Disabled
|
|
*/
|
|
#define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)
|
|
#define LPI2C_MIER_PLTIE_MASK (0x2000U)
|
|
#define LPI2C_MIER_PLTIE_SHIFT (13U)
|
|
/*! PLTIE - Pin Low Timeout Interrupt Enable
|
|
* 0b0..Disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)
|
|
#define LPI2C_MIER_DMIE_MASK (0x4000U)
|
|
#define LPI2C_MIER_DMIE_SHIFT (14U)
|
|
/*! DMIE - Data Match Interrupt Enable
|
|
* 0b0..Disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MDER - Master DMA Enable Register */
|
|
/*! @{ */
|
|
#define LPI2C_MDER_TDDE_MASK (0x1U)
|
|
#define LPI2C_MDER_TDDE_SHIFT (0U)
|
|
/*! TDDE - Transmit Data DMA Enable
|
|
* 0b0..DMA request is disabled
|
|
* 0b1..DMA request is enabled
|
|
*/
|
|
#define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)
|
|
#define LPI2C_MDER_RDDE_MASK (0x2U)
|
|
#define LPI2C_MDER_RDDE_SHIFT (1U)
|
|
/*! RDDE - Receive Data DMA Enable
|
|
* 0b0..DMA request is disabled
|
|
* 0b1..DMA request is enabled
|
|
*/
|
|
#define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MCFGR0 - Master Configuration Register 0 */
|
|
/*! @{ */
|
|
#define LPI2C_MCFGR0_HREN_MASK (0x1U)
|
|
#define LPI2C_MCFGR0_HREN_SHIFT (0U)
|
|
/*! HREN - Host Request Enable
|
|
* 0b0..Host request input is disabled
|
|
* 0b1..Host request input is enabled
|
|
*/
|
|
#define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)
|
|
#define LPI2C_MCFGR0_HRPOL_MASK (0x2U)
|
|
#define LPI2C_MCFGR0_HRPOL_SHIFT (1U)
|
|
/*! HRPOL - Host Request Polarity
|
|
* 0b0..Active low
|
|
* 0b1..Active high
|
|
*/
|
|
#define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)
|
|
#define LPI2C_MCFGR0_HRSEL_MASK (0x4U)
|
|
#define LPI2C_MCFGR0_HRSEL_SHIFT (2U)
|
|
/*! HRSEL - Host Request Select
|
|
* 0b0..Host request input is pin HREQ
|
|
* 0b1..Host request input is input trigger
|
|
*/
|
|
#define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)
|
|
#define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U)
|
|
#define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U)
|
|
/*! CIRFIFO - Circular FIFO Enable
|
|
* 0b0..Circular FIFO is disabled
|
|
* 0b1..Circular FIFO is enabled
|
|
*/
|
|
#define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)
|
|
#define LPI2C_MCFGR0_RDMO_MASK (0x200U)
|
|
#define LPI2C_MCFGR0_RDMO_SHIFT (9U)
|
|
/*! RDMO - Receive Data Match Only
|
|
* 0b0..Received data is stored in the receive FIFO
|
|
* 0b1..Received data is discarded unless the the Data Match Flag (MSR[DMF]) is set
|
|
*/
|
|
#define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MCFGR1 - Master Configuration Register 1 */
|
|
/*! @{ */
|
|
#define LPI2C_MCFGR1_PRESCALE_MASK (0x7U)
|
|
#define LPI2C_MCFGR1_PRESCALE_SHIFT (0U)
|
|
/*! PRESCALE - Prescaler
|
|
* 0b000..Divide by 1
|
|
* 0b001..Divide by 2
|
|
* 0b010..Divide by 4
|
|
* 0b011..Divide by 8
|
|
* 0b100..Divide by 16
|
|
* 0b101..Divide by 32
|
|
* 0b110..Divide by 64
|
|
* 0b111..Divide by 128
|
|
*/
|
|
#define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)
|
|
#define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U)
|
|
#define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U)
|
|
/*! AUTOSTOP - Automatic STOP Generation
|
|
* 0b0..No effect
|
|
* 0b1..STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy
|
|
*/
|
|
#define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)
|
|
#define LPI2C_MCFGR1_IGNACK_MASK (0x200U)
|
|
#define LPI2C_MCFGR1_IGNACK_SHIFT (9U)
|
|
/*! IGNACK - IGNACK
|
|
* 0b0..LPI2C Master will receive ACK and NACK normally
|
|
* 0b1..LPI2C Master will treat a received NACK as if it (NACK) was an ACK
|
|
*/
|
|
#define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)
|
|
#define LPI2C_MCFGR1_TIMECFG_MASK (0x400U)
|
|
#define LPI2C_MCFGR1_TIMECFG_SHIFT (10U)
|
|
/*! TIMECFG - Timeout Configuration
|
|
* 0b0..Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout
|
|
* 0b1..Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout
|
|
*/
|
|
#define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)
|
|
#define LPI2C_MCFGR1_MATCFG_MASK (0x70000U)
|
|
#define LPI2C_MCFGR1_MATCFG_SHIFT (16U)
|
|
/*! MATCFG - Match Configuration
|
|
* 0b000..Match is disabled
|
|
* 0b001..Reserved
|
|
* 0b010..Match is enabled (1st data word equals MATCH0 OR MATCH1)
|
|
* 0b011..Match is enabled (any data word equals MATCH0 OR MATCH1)
|
|
* 0b100..Match is enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1)
|
|
* 0b101..Match is enabled (any data word equals MATCH0 AND next data word equals MATCH1)
|
|
* 0b110..Match is enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1)
|
|
* 0b111..Match is enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1)
|
|
*/
|
|
#define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)
|
|
#define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U)
|
|
#define LPI2C_MCFGR1_PINCFG_SHIFT (24U)
|
|
/*! PINCFG - Pin Configuration
|
|
* 0b000..2-pin open drain mode
|
|
* 0b001..2-pin output only mode (ultra-fast mode)
|
|
* 0b010..2-pin push-pull mode
|
|
* 0b011..4-pin push-pull mode
|
|
* 0b100..2-pin open drain mode with separate LPI2C slave
|
|
* 0b101..2-pin output only mode (ultra-fast mode) with separate LPI2C slave
|
|
* 0b110..2-pin push-pull mode with separate LPI2C slave
|
|
* 0b111..4-pin push-pull mode (inverted outputs)
|
|
*/
|
|
#define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MCFGR2 - Master Configuration Register 2 */
|
|
/*! @{ */
|
|
#define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU)
|
|
#define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U)
|
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#define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)
|
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#define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U)
|
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#define LPI2C_MCFGR2_FILTSCL_SHIFT (16U)
|
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#define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)
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#define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U)
|
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#define LPI2C_MCFGR2_FILTSDA_SHIFT (24U)
|
|
#define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MCFGR3 - Master Configuration Register 3 */
|
|
/*! @{ */
|
|
#define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U)
|
|
#define LPI2C_MCFGR3_PINLOW_SHIFT (8U)
|
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#define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MDMR - Master Data Match Register */
|
|
/*! @{ */
|
|
#define LPI2C_MDMR_MATCH0_MASK (0xFFU)
|
|
#define LPI2C_MDMR_MATCH0_SHIFT (0U)
|
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#define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)
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#define LPI2C_MDMR_MATCH1_MASK (0xFF0000U)
|
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#define LPI2C_MDMR_MATCH1_SHIFT (16U)
|
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#define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MCCR0 - Master Clock Configuration Register 0 */
|
|
/*! @{ */
|
|
#define LPI2C_MCCR0_CLKLO_MASK (0x3FU)
|
|
#define LPI2C_MCCR0_CLKLO_SHIFT (0U)
|
|
#define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)
|
|
#define LPI2C_MCCR0_CLKHI_MASK (0x3F00U)
|
|
#define LPI2C_MCCR0_CLKHI_SHIFT (8U)
|
|
#define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)
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|
#define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U)
|
|
#define LPI2C_MCCR0_SETHOLD_SHIFT (16U)
|
|
#define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)
|
|
#define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U)
|
|
#define LPI2C_MCCR0_DATAVD_SHIFT (24U)
|
|
#define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MCCR1 - Master Clock Configuration Register 1 */
|
|
/*! @{ */
|
|
#define LPI2C_MCCR1_CLKLO_MASK (0x3FU)
|
|
#define LPI2C_MCCR1_CLKLO_SHIFT (0U)
|
|
#define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)
|
|
#define LPI2C_MCCR1_CLKHI_MASK (0x3F00U)
|
|
#define LPI2C_MCCR1_CLKHI_SHIFT (8U)
|
|
#define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)
|
|
#define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U)
|
|
#define LPI2C_MCCR1_SETHOLD_SHIFT (16U)
|
|
#define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)
|
|
#define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U)
|
|
#define LPI2C_MCCR1_DATAVD_SHIFT (24U)
|
|
#define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MFCR - Master FIFO Control Register */
|
|
/*! @{ */
|
|
#define LPI2C_MFCR_TXWATER_MASK (0x3U)
|
|
#define LPI2C_MFCR_TXWATER_SHIFT (0U)
|
|
#define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)
|
|
#define LPI2C_MFCR_RXWATER_MASK (0x30000U)
|
|
#define LPI2C_MFCR_RXWATER_SHIFT (16U)
|
|
#define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MFSR - Master FIFO Status Register */
|
|
/*! @{ */
|
|
#define LPI2C_MFSR_TXCOUNT_MASK (0x7U)
|
|
#define LPI2C_MFSR_TXCOUNT_SHIFT (0U)
|
|
#define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)
|
|
#define LPI2C_MFSR_RXCOUNT_MASK (0x70000U)
|
|
#define LPI2C_MFSR_RXCOUNT_SHIFT (16U)
|
|
#define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MTDR - Master Transmit Data Register */
|
|
/*! @{ */
|
|
#define LPI2C_MTDR_DATA_MASK (0xFFU)
|
|
#define LPI2C_MTDR_DATA_SHIFT (0U)
|
|
#define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)
|
|
#define LPI2C_MTDR_CMD_MASK (0x700U)
|
|
#define LPI2C_MTDR_CMD_SHIFT (8U)
|
|
/*! CMD - Command Data
|
|
* 0b000..Transmit DATA[7:0]
|
|
* 0b001..Receive (DATA[7:0] + 1) bytes
|
|
* 0b010..Generate STOP condition
|
|
* 0b011..Receive and discard (DATA[7:0] + 1) bytes
|
|
* 0b100..Generate (repeated) START and transmit address in DATA[7:0]
|
|
* 0b101..Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned.
|
|
* 0b110..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode
|
|
* 0b111..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned.
|
|
*/
|
|
#define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MRDR - Master Receive Data Register */
|
|
/*! @{ */
|
|
#define LPI2C_MRDR_DATA_MASK (0xFFU)
|
|
#define LPI2C_MRDR_DATA_SHIFT (0U)
|
|
#define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)
|
|
#define LPI2C_MRDR_RXEMPTY_MASK (0x4000U)
|
|
#define LPI2C_MRDR_RXEMPTY_SHIFT (14U)
|
|
/*! RXEMPTY - RX Empty
|
|
* 0b0..Receive FIFO is not empty
|
|
* 0b1..Receive FIFO is empty
|
|
*/
|
|
#define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SCR - Slave Control Register */
|
|
/*! @{ */
|
|
#define LPI2C_SCR_SEN_MASK (0x1U)
|
|
#define LPI2C_SCR_SEN_SHIFT (0U)
|
|
/*! SEN - Slave Enable
|
|
* 0b0..I2C Slave mode is disabled
|
|
* 0b1..I2C Slave mode is enabled
|
|
*/
|
|
#define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)
|
|
#define LPI2C_SCR_RST_MASK (0x2U)
|
|
#define LPI2C_SCR_RST_SHIFT (1U)
|
|
/*! RST - Software Reset
|
|
* 0b0..Slave mode logic is not reset
|
|
* 0b1..Slave mode logic is reset
|
|
*/
|
|
#define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)
|
|
#define LPI2C_SCR_FILTEN_MASK (0x10U)
|
|
#define LPI2C_SCR_FILTEN_SHIFT (4U)
|
|
/*! FILTEN - Filter Enable
|
|
* 0b0..Disable digital filter and output delay counter for slave mode
|
|
* 0b1..Enable digital filter and output delay counter for slave mode
|
|
*/
|
|
#define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)
|
|
#define LPI2C_SCR_FILTDZ_MASK (0x20U)
|
|
#define LPI2C_SCR_FILTDZ_SHIFT (5U)
|
|
/*! FILTDZ - Filter Doze Enable
|
|
* 0b0..Filter remains enabled in Doze mode
|
|
* 0b1..Filter is disabled in Doze mode
|
|
*/
|
|
#define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)
|
|
#define LPI2C_SCR_RTF_MASK (0x100U)
|
|
#define LPI2C_SCR_RTF_SHIFT (8U)
|
|
/*! RTF - Reset Transmit FIFO
|
|
* 0b0..No effect
|
|
* 0b1..Transmit Data Register is now empty
|
|
*/
|
|
#define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)
|
|
#define LPI2C_SCR_RRF_MASK (0x200U)
|
|
#define LPI2C_SCR_RRF_SHIFT (9U)
|
|
/*! RRF - Reset Receive FIFO
|
|
* 0b0..No effect
|
|
* 0b1..Receive Data Register is now empty
|
|
*/
|
|
#define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SSR - Slave Status Register */
|
|
/*! @{ */
|
|
#define LPI2C_SSR_TDF_MASK (0x1U)
|
|
#define LPI2C_SSR_TDF_SHIFT (0U)
|
|
/*! TDF - Transmit Data Flag
|
|
* 0b0..Transmit data not requested
|
|
* 0b1..Transmit data is requested
|
|
*/
|
|
#define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)
|
|
#define LPI2C_SSR_RDF_MASK (0x2U)
|
|
#define LPI2C_SSR_RDF_SHIFT (1U)
|
|
/*! RDF - Receive Data Flag
|
|
* 0b0..Receive data is not ready
|
|
* 0b1..Receive data is ready
|
|
*/
|
|
#define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)
|
|
#define LPI2C_SSR_AVF_MASK (0x4U)
|
|
#define LPI2C_SSR_AVF_SHIFT (2U)
|
|
/*! AVF - Address Valid Flag
|
|
* 0b0..Address Status Register is not valid
|
|
* 0b1..Address Status Register is valid
|
|
*/
|
|
#define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)
|
|
#define LPI2C_SSR_TAF_MASK (0x8U)
|
|
#define LPI2C_SSR_TAF_SHIFT (3U)
|
|
/*! TAF - Transmit ACK Flag
|
|
* 0b0..Transmit ACK/NACK is not required
|
|
* 0b1..Transmit ACK/NACK is required
|
|
*/
|
|
#define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)
|
|
#define LPI2C_SSR_RSF_MASK (0x100U)
|
|
#define LPI2C_SSR_RSF_SHIFT (8U)
|
|
/*! RSF - Repeated Start Flag
|
|
* 0b0..Slave has not detected a Repeated START condition
|
|
* 0b1..Slave has detected a Repeated START condition
|
|
*/
|
|
#define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)
|
|
#define LPI2C_SSR_SDF_MASK (0x200U)
|
|
#define LPI2C_SSR_SDF_SHIFT (9U)
|
|
/*! SDF - STOP Detect Flag
|
|
* 0b0..Slave has not detected a STOP condition
|
|
* 0b1..Slave has detected a STOP condition
|
|
*/
|
|
#define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)
|
|
#define LPI2C_SSR_BEF_MASK (0x400U)
|
|
#define LPI2C_SSR_BEF_SHIFT (10U)
|
|
/*! BEF - Bit Error Flag
|
|
* 0b0..Slave has not detected a bit error
|
|
* 0b1..Slave has detected a bit error
|
|
*/
|
|
#define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)
|
|
#define LPI2C_SSR_FEF_MASK (0x800U)
|
|
#define LPI2C_SSR_FEF_SHIFT (11U)
|
|
/*! FEF - FIFO Error Flag
|
|
* 0b0..FIFO underflow or overflow was not detected
|
|
* 0b1..FIFO underflow or overflow was detected
|
|
*/
|
|
#define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)
|
|
#define LPI2C_SSR_AM0F_MASK (0x1000U)
|
|
#define LPI2C_SSR_AM0F_SHIFT (12U)
|
|
/*! AM0F - Address Match 0 Flag
|
|
* 0b0..Have not received an ADDR0 matching address
|
|
* 0b1..Have received an ADDR0 matching address
|
|
*/
|
|
#define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)
|
|
#define LPI2C_SSR_AM1F_MASK (0x2000U)
|
|
#define LPI2C_SSR_AM1F_SHIFT (13U)
|
|
/*! AM1F - Address Match 1 Flag
|
|
* 0b0..Have not received an ADDR1 or ADDR0/ADDR1 range matching address
|
|
* 0b1..Have received an ADDR1 or ADDR0/ADDR1 range matching address
|
|
*/
|
|
#define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)
|
|
#define LPI2C_SSR_GCF_MASK (0x4000U)
|
|
#define LPI2C_SSR_GCF_SHIFT (14U)
|
|
/*! GCF - General Call Flag
|
|
* 0b0..Slave has not detected the General Call Address or the General Call Address is disabled
|
|
* 0b1..Slave has detected the General Call Address
|
|
*/
|
|
#define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)
|
|
#define LPI2C_SSR_SARF_MASK (0x8000U)
|
|
#define LPI2C_SSR_SARF_SHIFT (15U)
|
|
/*! SARF - SMBus Alert Response Flag
|
|
* 0b0..SMBus Alert Response is disabled or not detected
|
|
* 0b1..SMBus Alert Response is enabled and detected
|
|
*/
|
|
#define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)
|
|
#define LPI2C_SSR_SBF_MASK (0x1000000U)
|
|
#define LPI2C_SSR_SBF_SHIFT (24U)
|
|
/*! SBF - Slave Busy Flag
|
|
* 0b0..I2C Slave is idle
|
|
* 0b1..I2C Slave is busy
|
|
*/
|
|
#define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)
|
|
#define LPI2C_SSR_BBF_MASK (0x2000000U)
|
|
#define LPI2C_SSR_BBF_SHIFT (25U)
|
|
/*! BBF - Bus Busy Flag
|
|
* 0b0..I2C Bus is idle
|
|
* 0b1..I2C Bus is busy
|
|
*/
|
|
#define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SIER - Slave Interrupt Enable Register */
|
|
/*! @{ */
|
|
#define LPI2C_SIER_TDIE_MASK (0x1U)
|
|
#define LPI2C_SIER_TDIE_SHIFT (0U)
|
|
/*! TDIE - Transmit Data Interrupt Enable
|
|
* 0b0..Disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)
|
|
#define LPI2C_SIER_RDIE_MASK (0x2U)
|
|
#define LPI2C_SIER_RDIE_SHIFT (1U)
|
|
/*! RDIE - Receive Data Interrupt Enable
|
|
* 0b0..Disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)
|
|
#define LPI2C_SIER_AVIE_MASK (0x4U)
|
|
#define LPI2C_SIER_AVIE_SHIFT (2U)
|
|
/*! AVIE - Address Valid Interrupt Enable
|
|
* 0b0..Disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)
|
|
#define LPI2C_SIER_TAIE_MASK (0x8U)
|
|
#define LPI2C_SIER_TAIE_SHIFT (3U)
|
|
/*! TAIE - Transmit ACK Interrupt Enable
|
|
* 0b0..Disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)
|
|
#define LPI2C_SIER_RSIE_MASK (0x100U)
|
|
#define LPI2C_SIER_RSIE_SHIFT (8U)
|
|
/*! RSIE - Repeated Start Interrupt Enable
|
|
* 0b0..Disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)
|
|
#define LPI2C_SIER_SDIE_MASK (0x200U)
|
|
#define LPI2C_SIER_SDIE_SHIFT (9U)
|
|
/*! SDIE - STOP Detect Interrupt Enable
|
|
* 0b0..Disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)
|
|
#define LPI2C_SIER_BEIE_MASK (0x400U)
|
|
#define LPI2C_SIER_BEIE_SHIFT (10U)
|
|
/*! BEIE - Bit Error Interrupt Enable
|
|
* 0b0..Disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)
|
|
#define LPI2C_SIER_FEIE_MASK (0x800U)
|
|
#define LPI2C_SIER_FEIE_SHIFT (11U)
|
|
/*! FEIE - FIFO Error Interrupt Enable
|
|
* 0b0..Disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)
|
|
#define LPI2C_SIER_AM0IE_MASK (0x1000U)
|
|
#define LPI2C_SIER_AM0IE_SHIFT (12U)
|
|
/*! AM0IE - Address Match 0 Interrupt Enable
|
|
* 0b0..Enabled
|
|
* 0b1..Disabled
|
|
*/
|
|
#define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)
|
|
#define LPI2C_SIER_AM1F_MASK (0x2000U)
|
|
#define LPI2C_SIER_AM1F_SHIFT (13U)
|
|
/*! AM1F - Address Match 1 Interrupt Enable
|
|
* 0b0..Disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK)
|
|
#define LPI2C_SIER_GCIE_MASK (0x4000U)
|
|
#define LPI2C_SIER_GCIE_SHIFT (14U)
|
|
/*! GCIE - General Call Interrupt Enable
|
|
* 0b0..Disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)
|
|
#define LPI2C_SIER_SARIE_MASK (0x8000U)
|
|
#define LPI2C_SIER_SARIE_SHIFT (15U)
|
|
/*! SARIE - SMBus Alert Response Interrupt Enable
|
|
* 0b0..Disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SDER - Slave DMA Enable Register */
|
|
/*! @{ */
|
|
#define LPI2C_SDER_TDDE_MASK (0x1U)
|
|
#define LPI2C_SDER_TDDE_SHIFT (0U)
|
|
/*! TDDE - Transmit Data DMA Enable
|
|
* 0b0..DMA request is disabled
|
|
* 0b1..DMA request is enabled
|
|
*/
|
|
#define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)
|
|
#define LPI2C_SDER_RDDE_MASK (0x2U)
|
|
#define LPI2C_SDER_RDDE_SHIFT (1U)
|
|
/*! RDDE - Receive Data DMA Enable
|
|
* 0b0..DMA request is disabled
|
|
* 0b1..DMA request is enabled
|
|
*/
|
|
#define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)
|
|
#define LPI2C_SDER_AVDE_MASK (0x4U)
|
|
#define LPI2C_SDER_AVDE_SHIFT (2U)
|
|
/*! AVDE - Address Valid DMA Enable
|
|
* 0b0..DMA request is disabled
|
|
* 0b1..DMA request is enabled
|
|
*/
|
|
#define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SCFGR1 - Slave Configuration Register 1 */
|
|
/*! @{ */
|
|
#define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U)
|
|
#define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U)
|
|
/*! ADRSTALL - Address SCL Stall
|
|
* 0b0..Clock stretching is disabled
|
|
* 0b1..Clock stretching is enabled
|
|
*/
|
|
#define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)
|
|
#define LPI2C_SCFGR1_RXSTALL_MASK (0x2U)
|
|
#define LPI2C_SCFGR1_RXSTALL_SHIFT (1U)
|
|
/*! RXSTALL - RX SCL Stall
|
|
* 0b0..Clock stretching is disabled
|
|
* 0b1..Clock stretching is enabled
|
|
*/
|
|
#define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)
|
|
#define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U)
|
|
#define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U)
|
|
/*! TXDSTALL - TX Data SCL Stall
|
|
* 0b0..Clock stretching is disabled
|
|
* 0b1..Clock stretching is enabled
|
|
*/
|
|
#define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)
|
|
#define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U)
|
|
#define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U)
|
|
/*! ACKSTALL - ACK SCL Stall
|
|
* 0b0..Clock stretching is disabled
|
|
* 0b1..Clock stretching is enabled
|
|
*/
|
|
#define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)
|
|
#define LPI2C_SCFGR1_GCEN_MASK (0x100U)
|
|
#define LPI2C_SCFGR1_GCEN_SHIFT (8U)
|
|
/*! GCEN - General Call Enable
|
|
* 0b0..General Call address is disabled
|
|
* 0b1..General Call address is enabled
|
|
*/
|
|
#define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)
|
|
#define LPI2C_SCFGR1_SAEN_MASK (0x200U)
|
|
#define LPI2C_SCFGR1_SAEN_SHIFT (9U)
|
|
/*! SAEN - SMBus Alert Enable
|
|
* 0b0..Disables match on SMBus Alert
|
|
* 0b1..Enables match on SMBus Alert
|
|
*/
|
|
#define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)
|
|
#define LPI2C_SCFGR1_TXCFG_MASK (0x400U)
|
|
#define LPI2C_SCFGR1_TXCFG_SHIFT (10U)
|
|
/*! TXCFG - Transmit Flag Configuration
|
|
* 0b0..Transmit Data Flag will only assert during a slave-transmit transfer when the Transmit Data register is empty
|
|
* 0b1..Transmit Data Flag will assert whenever the Transmit Data register is empty
|
|
*/
|
|
#define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)
|
|
#define LPI2C_SCFGR1_RXCFG_MASK (0x800U)
|
|
#define LPI2C_SCFGR1_RXCFG_SHIFT (11U)
|
|
/*! RXCFG - Receive Data Configuration
|
|
* 0b0..Reading the Receive Data register will return received data and clear the Receive Data flag (MSR[RDF]).
|
|
* 0b1..Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, will return the Address Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid flag is clear, will return received data and clear the Receive Data flag (MSR[RDF]).
|
|
*/
|
|
#define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)
|
|
#define LPI2C_SCFGR1_IGNACK_MASK (0x1000U)
|
|
#define LPI2C_SCFGR1_IGNACK_SHIFT (12U)
|
|
/*! IGNACK - Ignore NACK
|
|
* 0b0..Slave will end transfer when NACK is detected
|
|
* 0b1..Slave will not end transfer when NACK detected
|
|
*/
|
|
#define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)
|
|
#define LPI2C_SCFGR1_HSMEN_MASK (0x2000U)
|
|
#define LPI2C_SCFGR1_HSMEN_SHIFT (13U)
|
|
/*! HSMEN - High Speed Mode Enable
|
|
* 0b0..Disables detection of HS-mode master code
|
|
* 0b1..Enables detection of HS-mode master code
|
|
*/
|
|
#define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)
|
|
#define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U)
|
|
#define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U)
|
|
/*! ADDRCFG - Address Configuration
|
|
* 0b000..Address match 0 (7-bit)
|
|
* 0b001..Address match 0 (10-bit)
|
|
* 0b010..Address match 0 (7-bit) or Address match 1 (7-bit)
|
|
* 0b011..Address match 0 (10-bit) or Address match 1 (10-bit)
|
|
* 0b100..Address match 0 (7-bit) or Address match 1 (10-bit)
|
|
* 0b101..Address match 0 (10-bit) or Address match 1 (7-bit)
|
|
* 0b110..From Address match 0 (7-bit) to Address match 1 (7-bit)
|
|
* 0b111..From Address match 0 (10-bit) to Address match 1 (10-bit)
|
|
*/
|
|
#define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SCFGR2 - Slave Configuration Register 2 */
|
|
/*! @{ */
|
|
#define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU)
|
|
#define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U)
|
|
#define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)
|
|
#define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U)
|
|
#define LPI2C_SCFGR2_DATAVD_SHIFT (8U)
|
|
#define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)
|
|
#define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U)
|
|
#define LPI2C_SCFGR2_FILTSCL_SHIFT (16U)
|
|
#define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)
|
|
#define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U)
|
|
#define LPI2C_SCFGR2_FILTSDA_SHIFT (24U)
|
|
#define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SAMR - Slave Address Match Register */
|
|
/*! @{ */
|
|
#define LPI2C_SAMR_ADDR0_MASK (0x7FEU)
|
|
#define LPI2C_SAMR_ADDR0_SHIFT (1U)
|
|
#define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)
|
|
#define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U)
|
|
#define LPI2C_SAMR_ADDR1_SHIFT (17U)
|
|
#define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SASR - Slave Address Status Register */
|
|
/*! @{ */
|
|
#define LPI2C_SASR_RADDR_MASK (0x7FFU)
|
|
#define LPI2C_SASR_RADDR_SHIFT (0U)
|
|
#define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)
|
|
#define LPI2C_SASR_ANV_MASK (0x4000U)
|
|
#define LPI2C_SASR_ANV_SHIFT (14U)
|
|
/*! ANV - Address Not Valid
|
|
* 0b0..Received Address (RADDR) is valid
|
|
* 0b1..Received Address (RADDR) is not valid
|
|
*/
|
|
#define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name STAR - Slave Transmit ACK Register */
|
|
/*! @{ */
|
|
#define LPI2C_STAR_TXNACK_MASK (0x1U)
|
|
#define LPI2C_STAR_TXNACK_SHIFT (0U)
|
|
/*! TXNACK - Transmit NACK
|
|
* 0b0..Write a Transmit ACK for each received word
|
|
* 0b1..Write a Transmit NACK for each received word
|
|
*/
|
|
#define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name STDR - Slave Transmit Data Register */
|
|
/*! @{ */
|
|
#define LPI2C_STDR_DATA_MASK (0xFFU)
|
|
#define LPI2C_STDR_DATA_SHIFT (0U)
|
|
#define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SRDR - Slave Receive Data Register */
|
|
/*! @{ */
|
|
#define LPI2C_SRDR_DATA_MASK (0xFFU)
|
|
#define LPI2C_SRDR_DATA_SHIFT (0U)
|
|
#define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)
|
|
#define LPI2C_SRDR_RXEMPTY_MASK (0x4000U)
|
|
#define LPI2C_SRDR_RXEMPTY_SHIFT (14U)
|
|
/*! RXEMPTY - RX Empty
|
|
* 0b0..The Receive Data Register is not empty
|
|
* 0b1..The Receive Data Register is empty
|
|
*/
|
|
#define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)
|
|
#define LPI2C_SRDR_SOF_MASK (0x8000U)
|
|
#define LPI2C_SRDR_SOF_SHIFT (15U)
|
|
/*! SOF - Start Of Frame
|
|
* 0b0..Indicates this is not the first data word since a (repeated) START or STOP condition
|
|
* 0b1..Indicates this is the first data word since a (repeated) START or STOP condition
|
|
*/
|
|
#define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group LPI2C_Register_Masks */
|
|
|
|
|
|
/* LPI2C - Peripheral instance base addresses */
|
|
/** Peripheral LPI2C1 base address */
|
|
#define LPI2C1_BASE (0x403F0000u)
|
|
/** Peripheral LPI2C1 base pointer */
|
|
#define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE)
|
|
/** Peripheral LPI2C2 base address */
|
|
#define LPI2C2_BASE (0x403F4000u)
|
|
/** Peripheral LPI2C2 base pointer */
|
|
#define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE)
|
|
/** Peripheral LPI2C3 base address */
|
|
#define LPI2C3_BASE (0x403F8000u)
|
|
/** Peripheral LPI2C3 base pointer */
|
|
#define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE)
|
|
/** Peripheral LPI2C4 base address */
|
|
#define LPI2C4_BASE (0x403FC000u)
|
|
/** Peripheral LPI2C4 base pointer */
|
|
#define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE)
|
|
/** Array initializer of LPI2C peripheral base addresses */
|
|
#define LPI2C_BASE_ADDRS { 0u, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE }
|
|
/** Array initializer of LPI2C peripheral base pointers */
|
|
#define LPI2C_BASE_PTRS { (LPI2C_Type *)0u, LPI2C1, LPI2C2, LPI2C3, LPI2C4 }
|
|
/** Interrupt vectors for the LPI2C peripheral type */
|
|
#define LPI2C_IRQS { NotAvail_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn, LPI2C4_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group LPI2C_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- LPSPI Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** LPSPI - Register Layout Typedef */
|
|
typedef struct {
|
|
__I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
|
|
__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
|
|
uint8_t RESERVED_0[8];
|
|
__IO uint32_t CR; /**< Control Register, offset: 0x10 */
|
|
__IO uint32_t SR; /**< Status Register, offset: 0x14 */
|
|
__IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x18 */
|
|
__IO uint32_t DER; /**< DMA Enable Register, offset: 0x1C */
|
|
__IO uint32_t CFGR0; /**< Configuration Register 0, offset: 0x20 */
|
|
__IO uint32_t CFGR1; /**< Configuration Register 1, offset: 0x24 */
|
|
uint8_t RESERVED_1[8];
|
|
__IO uint32_t DMR0; /**< Data Match Register 0, offset: 0x30 */
|
|
__IO uint32_t DMR1; /**< Data Match Register 1, offset: 0x34 */
|
|
uint8_t RESERVED_2[8];
|
|
__IO uint32_t CCR; /**< Clock Configuration Register, offset: 0x40 */
|
|
uint8_t RESERVED_3[20];
|
|
__IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */
|
|
__I uint32_t FSR; /**< FIFO Status Register, offset: 0x5C */
|
|
__IO uint32_t TCR; /**< Transmit Command Register, offset: 0x60 */
|
|
__O uint32_t TDR; /**< Transmit Data Register, offset: 0x64 */
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uint8_t RESERVED_4[8];
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__I uint32_t RSR; /**< Receive Status Register, offset: 0x70 */
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__I uint32_t RDR; /**< Receive Data Register, offset: 0x74 */
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} LPSPI_Type;
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|
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/* ----------------------------------------------------------------------------
|
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-- LPSPI Register Masks
|
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---------------------------------------------------------------------------- */
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/*!
|
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* @addtogroup LPSPI_Register_Masks LPSPI Register Masks
|
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* @{
|
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*/
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/*! @name VERID - Version ID Register */
|
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/*! @{ */
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#define LPSPI_VERID_FEATURE_MASK (0xFFFFU)
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#define LPSPI_VERID_FEATURE_SHIFT (0U)
|
|
/*! FEATURE - Module Identification Number
|
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* 0b0000000000000100..Standard feature set supporting a 32-bit shift register.
|
|
*/
|
|
#define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)
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#define LPSPI_VERID_MINOR_MASK (0xFF0000U)
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#define LPSPI_VERID_MINOR_SHIFT (16U)
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#define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)
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#define LPSPI_VERID_MAJOR_MASK (0xFF000000U)
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#define LPSPI_VERID_MAJOR_SHIFT (24U)
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#define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)
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/*! @} */
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|
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/*! @name PARAM - Parameter Register */
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|
/*! @{ */
|
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#define LPSPI_PARAM_TXFIFO_MASK (0xFFU)
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#define LPSPI_PARAM_TXFIFO_SHIFT (0U)
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#define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)
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#define LPSPI_PARAM_RXFIFO_MASK (0xFF00U)
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#define LPSPI_PARAM_RXFIFO_SHIFT (8U)
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#define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)
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#define LPSPI_PARAM_PCSNUM_MASK (0xFF0000U)
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#define LPSPI_PARAM_PCSNUM_SHIFT (16U)
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#define LPSPI_PARAM_PCSNUM(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK)
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/*! @} */
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|
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/*! @name CR - Control Register */
|
|
/*! @{ */
|
|
#define LPSPI_CR_MEN_MASK (0x1U)
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#define LPSPI_CR_MEN_SHIFT (0U)
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/*! MEN - Module Enable
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* 0b0..Module is disabled
|
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* 0b1..Module is enabled
|
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*/
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#define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)
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#define LPSPI_CR_RST_MASK (0x2U)
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#define LPSPI_CR_RST_SHIFT (1U)
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|
/*! RST - Software Reset
|
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* 0b0..Module is not reset
|
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* 0b1..Module is reset
|
|
*/
|
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#define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)
|
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#define LPSPI_CR_DOZEN_MASK (0x4U)
|
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#define LPSPI_CR_DOZEN_SHIFT (2U)
|
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/*! DOZEN - Doze mode enable
|
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* 0b0..Module is enabled in Doze mode
|
|
* 0b1..Module is disabled in Doze mode
|
|
*/
|
|
#define LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK)
|
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#define LPSPI_CR_DBGEN_MASK (0x8U)
|
|
#define LPSPI_CR_DBGEN_SHIFT (3U)
|
|
/*! DBGEN - Debug Enable
|
|
* 0b0..Module is disabled in debug mode
|
|
* 0b1..Module is enabled in debug mode
|
|
*/
|
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#define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)
|
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#define LPSPI_CR_RTF_MASK (0x100U)
|
|
#define LPSPI_CR_RTF_SHIFT (8U)
|
|
/*! RTF - Reset Transmit FIFO
|
|
* 0b0..No effect
|
|
* 0b1..Transmit FIFO is reset
|
|
*/
|
|
#define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)
|
|
#define LPSPI_CR_RRF_MASK (0x200U)
|
|
#define LPSPI_CR_RRF_SHIFT (9U)
|
|
/*! RRF - Reset Receive FIFO
|
|
* 0b0..No effect
|
|
* 0b1..Receive FIFO is reset
|
|
*/
|
|
#define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SR - Status Register */
|
|
/*! @{ */
|
|
#define LPSPI_SR_TDF_MASK (0x1U)
|
|
#define LPSPI_SR_TDF_SHIFT (0U)
|
|
/*! TDF - Transmit Data Flag
|
|
* 0b0..Transmit data not requested
|
|
* 0b1..Transmit data is requested
|
|
*/
|
|
#define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK)
|
|
#define LPSPI_SR_RDF_MASK (0x2U)
|
|
#define LPSPI_SR_RDF_SHIFT (1U)
|
|
/*! RDF - Receive Data Flag
|
|
* 0b0..Receive Data is not ready
|
|
* 0b1..Receive data is ready
|
|
*/
|
|
#define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK)
|
|
#define LPSPI_SR_WCF_MASK (0x100U)
|
|
#define LPSPI_SR_WCF_SHIFT (8U)
|
|
/*! WCF - Word Complete Flag
|
|
* 0b0..Transfer of a received word has not yet completed
|
|
* 0b1..Transfer of a received word has completed
|
|
*/
|
|
#define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK)
|
|
#define LPSPI_SR_FCF_MASK (0x200U)
|
|
#define LPSPI_SR_FCF_SHIFT (9U)
|
|
/*! FCF - Frame Complete Flag
|
|
* 0b0..Frame transfer has not completed
|
|
* 0b1..Frame transfer has completed
|
|
*/
|
|
#define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK)
|
|
#define LPSPI_SR_TCF_MASK (0x400U)
|
|
#define LPSPI_SR_TCF_SHIFT (10U)
|
|
/*! TCF - Transfer Complete Flag
|
|
* 0b0..All transfers have not completed
|
|
* 0b1..All transfers have completed
|
|
*/
|
|
#define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK)
|
|
#define LPSPI_SR_TEF_MASK (0x800U)
|
|
#define LPSPI_SR_TEF_SHIFT (11U)
|
|
/*! TEF - Transmit Error Flag
|
|
* 0b0..Transmit FIFO underrun has not occurred
|
|
* 0b1..Transmit FIFO underrun has occurred
|
|
*/
|
|
#define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK)
|
|
#define LPSPI_SR_REF_MASK (0x1000U)
|
|
#define LPSPI_SR_REF_SHIFT (12U)
|
|
/*! REF - Receive Error Flag
|
|
* 0b0..Receive FIFO has not overflowed
|
|
* 0b1..Receive FIFO has overflowed
|
|
*/
|
|
#define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK)
|
|
#define LPSPI_SR_DMF_MASK (0x2000U)
|
|
#define LPSPI_SR_DMF_SHIFT (13U)
|
|
/*! DMF - Data Match Flag
|
|
* 0b0..Have not received matching data
|
|
* 0b1..Have received matching data
|
|
*/
|
|
#define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK)
|
|
#define LPSPI_SR_MBF_MASK (0x1000000U)
|
|
#define LPSPI_SR_MBF_SHIFT (24U)
|
|
/*! MBF - Module Busy Flag
|
|
* 0b0..LPSPI is idle
|
|
* 0b1..LPSPI is busy
|
|
*/
|
|
#define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name IER - Interrupt Enable Register */
|
|
/*! @{ */
|
|
#define LPSPI_IER_TDIE_MASK (0x1U)
|
|
#define LPSPI_IER_TDIE_SHIFT (0U)
|
|
/*! TDIE - Transmit Data Interrupt Enable
|
|
* 0b0..Disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK)
|
|
#define LPSPI_IER_RDIE_MASK (0x2U)
|
|
#define LPSPI_IER_RDIE_SHIFT (1U)
|
|
/*! RDIE - Receive Data Interrupt Enable
|
|
* 0b0..Disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK)
|
|
#define LPSPI_IER_WCIE_MASK (0x100U)
|
|
#define LPSPI_IER_WCIE_SHIFT (8U)
|
|
/*! WCIE - Word Complete Interrupt Enable
|
|
* 0b0..Disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK)
|
|
#define LPSPI_IER_FCIE_MASK (0x200U)
|
|
#define LPSPI_IER_FCIE_SHIFT (9U)
|
|
/*! FCIE - Frame Complete Interrupt Enable
|
|
* 0b0..Disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK)
|
|
#define LPSPI_IER_TCIE_MASK (0x400U)
|
|
#define LPSPI_IER_TCIE_SHIFT (10U)
|
|
/*! TCIE - Transfer Complete Interrupt Enable
|
|
* 0b0..Disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK)
|
|
#define LPSPI_IER_TEIE_MASK (0x800U)
|
|
#define LPSPI_IER_TEIE_SHIFT (11U)
|
|
/*! TEIE - Transmit Error Interrupt Enable
|
|
* 0b0..Disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK)
|
|
#define LPSPI_IER_REIE_MASK (0x1000U)
|
|
#define LPSPI_IER_REIE_SHIFT (12U)
|
|
/*! REIE - Receive Error Interrupt Enable
|
|
* 0b0..Disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK)
|
|
#define LPSPI_IER_DMIE_MASK (0x2000U)
|
|
#define LPSPI_IER_DMIE_SHIFT (13U)
|
|
/*! DMIE - Data Match Interrupt Enable
|
|
* 0b0..Disabled
|
|
* 0b1..Enabled
|
|
*/
|
|
#define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DER - DMA Enable Register */
|
|
/*! @{ */
|
|
#define LPSPI_DER_TDDE_MASK (0x1U)
|
|
#define LPSPI_DER_TDDE_SHIFT (0U)
|
|
/*! TDDE - Transmit Data DMA Enable
|
|
* 0b0..DMA request is disabled
|
|
* 0b1..DMA request is enabled
|
|
*/
|
|
#define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK)
|
|
#define LPSPI_DER_RDDE_MASK (0x2U)
|
|
#define LPSPI_DER_RDDE_SHIFT (1U)
|
|
/*! RDDE - Receive Data DMA Enable
|
|
* 0b0..DMA request is disabled
|
|
* 0b1..DMA request is enabled
|
|
*/
|
|
#define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CFGR0 - Configuration Register 0 */
|
|
/*! @{ */
|
|
#define LPSPI_CFGR0_HREN_MASK (0x1U)
|
|
#define LPSPI_CFGR0_HREN_SHIFT (0U)
|
|
/*! HREN - Host Request Enable
|
|
* 0b0..Host request is disabled
|
|
* 0b1..Host request is enabled
|
|
*/
|
|
#define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK)
|
|
#define LPSPI_CFGR0_HRPOL_MASK (0x2U)
|
|
#define LPSPI_CFGR0_HRPOL_SHIFT (1U)
|
|
/*! HRPOL - Host Request Polarity
|
|
* 0b0..Active low
|
|
* 0b1..Active high
|
|
*/
|
|
#define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
|
|
#define LPSPI_CFGR0_HRSEL_MASK (0x4U)
|
|
#define LPSPI_CFGR0_HRSEL_SHIFT (2U)
|
|
/*! HRSEL - Host Request Select
|
|
* 0b0..Host request input is the LPSPI_HREQ pin
|
|
* 0b1..Host request input is the input trigger
|
|
*/
|
|
#define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK)
|
|
#define LPSPI_CFGR0_CIRFIFO_MASK (0x100U)
|
|
#define LPSPI_CFGR0_CIRFIFO_SHIFT (8U)
|
|
/*! CIRFIFO - Circular FIFO Enable
|
|
* 0b0..Circular FIFO is disabled
|
|
* 0b1..Circular FIFO is enabled
|
|
*/
|
|
#define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK)
|
|
#define LPSPI_CFGR0_RDMO_MASK (0x200U)
|
|
#define LPSPI_CFGR0_RDMO_SHIFT (9U)
|
|
/*! RDMO - Receive Data Match Only
|
|
* 0b0..Received data is stored in the receive FIFO as in normal operations
|
|
* 0b1..Received data is discarded unless the Data Match Flag (DMF) is set
|
|
*/
|
|
#define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CFGR1 - Configuration Register 1 */
|
|
/*! @{ */
|
|
#define LPSPI_CFGR1_MASTER_MASK (0x1U)
|
|
#define LPSPI_CFGR1_MASTER_SHIFT (0U)
|
|
/*! MASTER - Master Mode
|
|
* 0b0..Slave mode
|
|
* 0b1..Master mode
|
|
*/
|
|
#define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
|
|
#define LPSPI_CFGR1_SAMPLE_MASK (0x2U)
|
|
#define LPSPI_CFGR1_SAMPLE_SHIFT (1U)
|
|
/*! SAMPLE - Sample Point
|
|
* 0b0..Input data is sampled on SCK edge
|
|
* 0b1..Input data is sampled on delayed SCK edge
|
|
*/
|
|
#define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK)
|
|
#define LPSPI_CFGR1_AUTOPCS_MASK (0x4U)
|
|
#define LPSPI_CFGR1_AUTOPCS_SHIFT (2U)
|
|
/*! AUTOPCS - Automatic PCS
|
|
* 0b0..Automatic PCS generation is disabled
|
|
* 0b1..Automatic PCS generation is enabled
|
|
*/
|
|
#define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK)
|
|
#define LPSPI_CFGR1_NOSTALL_MASK (0x8U)
|
|
#define LPSPI_CFGR1_NOSTALL_SHIFT (3U)
|
|
/*! NOSTALL - No Stall
|
|
* 0b0..Transfers will stall when the transmit FIFO is empty or the receive FIFO is full
|
|
* 0b1..Transfers will not stall, allowing transmit FIFO underruns or receive FIFO overruns to occur
|
|
*/
|
|
#define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK)
|
|
#define LPSPI_CFGR1_PCSPOL_MASK (0xF00U)
|
|
#define LPSPI_CFGR1_PCSPOL_SHIFT (8U)
|
|
/*! PCSPOL - Peripheral Chip Select Polarity
|
|
* 0b0000..The Peripheral Chip Select pin PCSx is active low
|
|
* 0b0001..The Peripheral Chip Select pin PCSx is active high
|
|
*/
|
|
#define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
|
|
#define LPSPI_CFGR1_MATCFG_MASK (0x70000U)
|
|
#define LPSPI_CFGR1_MATCFG_SHIFT (16U)
|
|
/*! MATCFG - Match Configuration
|
|
* 0b000..Match is disabled
|
|
* 0b001..Reserved
|
|
* 0b010..010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1)
|
|
* 0b011..011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1)
|
|
* 0b100..100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st data word = MATCH0) * (2nd data word = MATCH1)]
|
|
* 0b101..101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., [(any data word = MATCH0) * (next data word = MATCH1)]
|
|
* 0b110..110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * MATCH1) = (MATCH0 * MATCH1)]
|
|
* 0b111..111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)]
|
|
*/
|
|
#define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
|
|
#define LPSPI_CFGR1_PINCFG_MASK (0x3000000U)
|
|
#define LPSPI_CFGR1_PINCFG_SHIFT (24U)
|
|
/*! PINCFG - Pin Configuration
|
|
* 0b00..SIN is used for input data and SOUT is used for output data
|
|
* 0b01..SIN is used for both input and output data
|
|
* 0b10..SOUT is used for both input and output data
|
|
* 0b11..SOUT is used for input data and SIN is used for output data
|
|
*/
|
|
#define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK)
|
|
#define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U)
|
|
#define LPSPI_CFGR1_OUTCFG_SHIFT (26U)
|
|
/*! OUTCFG - Output Config
|
|
* 0b0..Output data retains last value when chip select is negated
|
|
* 0b1..Output data is tristated when chip select is negated
|
|
*/
|
|
#define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK)
|
|
#define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U)
|
|
#define LPSPI_CFGR1_PCSCFG_SHIFT (27U)
|
|
/*! PCSCFG - Peripheral Chip Select Configuration
|
|
* 0b0..PCS[3:2] are enabled
|
|
* 0b1..PCS[3:2] are disabled
|
|
*/
|
|
#define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DMR0 - Data Match Register 0 */
|
|
/*! @{ */
|
|
#define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU)
|
|
#define LPSPI_DMR0_MATCH0_SHIFT (0U)
|
|
#define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DMR1 - Data Match Register 1 */
|
|
/*! @{ */
|
|
#define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU)
|
|
#define LPSPI_DMR1_MATCH1_SHIFT (0U)
|
|
#define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CCR - Clock Configuration Register */
|
|
/*! @{ */
|
|
#define LPSPI_CCR_SCKDIV_MASK (0xFFU)
|
|
#define LPSPI_CCR_SCKDIV_SHIFT (0U)
|
|
#define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK)
|
|
#define LPSPI_CCR_DBT_MASK (0xFF00U)
|
|
#define LPSPI_CCR_DBT_SHIFT (8U)
|
|
#define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK)
|
|
#define LPSPI_CCR_PCSSCK_MASK (0xFF0000U)
|
|
#define LPSPI_CCR_PCSSCK_SHIFT (16U)
|
|
#define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK)
|
|
#define LPSPI_CCR_SCKPCS_MASK (0xFF000000U)
|
|
#define LPSPI_CCR_SCKPCS_SHIFT (24U)
|
|
#define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FCR - FIFO Control Register */
|
|
/*! @{ */
|
|
#define LPSPI_FCR_TXWATER_MASK (0xFU)
|
|
#define LPSPI_FCR_TXWATER_SHIFT (0U)
|
|
#define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK)
|
|
#define LPSPI_FCR_RXWATER_MASK (0xF0000U)
|
|
#define LPSPI_FCR_RXWATER_SHIFT (16U)
|
|
#define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FSR - FIFO Status Register */
|
|
/*! @{ */
|
|
#define LPSPI_FSR_TXCOUNT_MASK (0x1FU)
|
|
#define LPSPI_FSR_TXCOUNT_SHIFT (0U)
|
|
#define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK)
|
|
#define LPSPI_FSR_RXCOUNT_MASK (0x1F0000U)
|
|
#define LPSPI_FSR_RXCOUNT_SHIFT (16U)
|
|
#define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TCR - Transmit Command Register */
|
|
/*! @{ */
|
|
#define LPSPI_TCR_FRAMESZ_MASK (0xFFFU)
|
|
#define LPSPI_TCR_FRAMESZ_SHIFT (0U)
|
|
#define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK)
|
|
#define LPSPI_TCR_WIDTH_MASK (0x30000U)
|
|
#define LPSPI_TCR_WIDTH_SHIFT (16U)
|
|
/*! WIDTH - Transfer Width
|
|
* 0b00..1 bit transfer
|
|
* 0b01..2 bit transfer
|
|
* 0b10..4 bit transfer
|
|
* 0b11..Reserved
|
|
*/
|
|
#define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK)
|
|
#define LPSPI_TCR_TXMSK_MASK (0x40000U)
|
|
#define LPSPI_TCR_TXMSK_SHIFT (18U)
|
|
/*! TXMSK - Transmit Data Mask
|
|
* 0b0..Normal transfer
|
|
* 0b1..Mask transmit data
|
|
*/
|
|
#define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK)
|
|
#define LPSPI_TCR_RXMSK_MASK (0x80000U)
|
|
#define LPSPI_TCR_RXMSK_SHIFT (19U)
|
|
/*! RXMSK - Receive Data Mask
|
|
* 0b0..Normal transfer
|
|
* 0b1..Receive data is masked
|
|
*/
|
|
#define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK)
|
|
#define LPSPI_TCR_CONTC_MASK (0x100000U)
|
|
#define LPSPI_TCR_CONTC_SHIFT (20U)
|
|
/*! CONTC - Continuing Command
|
|
* 0b0..Command word for start of new transfer
|
|
* 0b1..Command word for continuing transfer
|
|
*/
|
|
#define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK)
|
|
#define LPSPI_TCR_CONT_MASK (0x200000U)
|
|
#define LPSPI_TCR_CONT_SHIFT (21U)
|
|
/*! CONT - Continuous Transfer
|
|
* 0b0..Continuous transfer is disabled
|
|
* 0b1..Continuous transfer is enabled
|
|
*/
|
|
#define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK)
|
|
#define LPSPI_TCR_BYSW_MASK (0x400000U)
|
|
#define LPSPI_TCR_BYSW_SHIFT (22U)
|
|
/*! BYSW - Byte Swap
|
|
* 0b0..Byte swap is disabled
|
|
* 0b1..Byte swap is enabled
|
|
*/
|
|
#define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK)
|
|
#define LPSPI_TCR_LSBF_MASK (0x800000U)
|
|
#define LPSPI_TCR_LSBF_SHIFT (23U)
|
|
/*! LSBF - LSB First
|
|
* 0b0..Data is transferred MSB first
|
|
* 0b1..Data is transferred LSB first
|
|
*/
|
|
#define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK)
|
|
#define LPSPI_TCR_PCS_MASK (0x3000000U)
|
|
#define LPSPI_TCR_PCS_SHIFT (24U)
|
|
/*! PCS - Peripheral Chip Select
|
|
* 0b00..Transfer using LPSPI_PCS[0]
|
|
* 0b01..Transfer using LPSPI_PCS[1]
|
|
* 0b10..Transfer using LPSPI_PCS[2]
|
|
* 0b11..Transfer using LPSPI_PCS[3]
|
|
*/
|
|
#define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK)
|
|
#define LPSPI_TCR_PRESCALE_MASK (0x38000000U)
|
|
#define LPSPI_TCR_PRESCALE_SHIFT (27U)
|
|
/*! PRESCALE - Prescaler Value
|
|
* 0b000..Divide by 1
|
|
* 0b001..Divide by 2
|
|
* 0b010..Divide by 4
|
|
* 0b011..Divide by 8
|
|
* 0b100..Divide by 16
|
|
* 0b101..Divide by 32
|
|
* 0b110..Divide by 64
|
|
* 0b111..Divide by 128
|
|
*/
|
|
#define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK)
|
|
#define LPSPI_TCR_CPHA_MASK (0x40000000U)
|
|
#define LPSPI_TCR_CPHA_SHIFT (30U)
|
|
/*! CPHA - Clock Phase
|
|
* 0b0..Data is captured on the leading edge of SCK and changed on the following edge of SCK
|
|
* 0b1..Data is changed on the leading edge of SCK and captured on the following edge of SCK
|
|
*/
|
|
#define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK)
|
|
#define LPSPI_TCR_CPOL_MASK (0x80000000U)
|
|
#define LPSPI_TCR_CPOL_SHIFT (31U)
|
|
/*! CPOL - Clock Polarity
|
|
* 0b0..The inactive state value of SCK is low
|
|
* 0b1..The inactive state value of SCK is high
|
|
*/
|
|
#define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TDR - Transmit Data Register */
|
|
/*! @{ */
|
|
#define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU)
|
|
#define LPSPI_TDR_DATA_SHIFT (0U)
|
|
#define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RSR - Receive Status Register */
|
|
/*! @{ */
|
|
#define LPSPI_RSR_SOF_MASK (0x1U)
|
|
#define LPSPI_RSR_SOF_SHIFT (0U)
|
|
/*! SOF - Start Of Frame
|
|
* 0b0..Subsequent data word received after LPSPI_PCS assertion
|
|
* 0b1..First data word received after LPSPI_PCS assertion
|
|
*/
|
|
#define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK)
|
|
#define LPSPI_RSR_RXEMPTY_MASK (0x2U)
|
|
#define LPSPI_RSR_RXEMPTY_SHIFT (1U)
|
|
/*! RXEMPTY - RX FIFO Empty
|
|
* 0b0..RX FIFO is not empty
|
|
* 0b1..RX FIFO is empty
|
|
*/
|
|
#define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name RDR - Receive Data Register */
|
|
/*! @{ */
|
|
#define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU)
|
|
#define LPSPI_RDR_DATA_SHIFT (0U)
|
|
#define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group LPSPI_Register_Masks */
|
|
|
|
|
|
/* LPSPI - Peripheral instance base addresses */
|
|
/** Peripheral LPSPI1 base address */
|
|
#define LPSPI1_BASE (0x40394000u)
|
|
/** Peripheral LPSPI1 base pointer */
|
|
#define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE)
|
|
/** Peripheral LPSPI2 base address */
|
|
#define LPSPI2_BASE (0x40398000u)
|
|
/** Peripheral LPSPI2 base pointer */
|
|
#define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE)
|
|
/** Peripheral LPSPI3 base address */
|
|
#define LPSPI3_BASE (0x4039C000u)
|
|
/** Peripheral LPSPI3 base pointer */
|
|
#define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE)
|
|
/** Peripheral LPSPI4 base address */
|
|
#define LPSPI4_BASE (0x403A0000u)
|
|
/** Peripheral LPSPI4 base pointer */
|
|
#define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE)
|
|
/** Array initializer of LPSPI peripheral base addresses */
|
|
#define LPSPI_BASE_ADDRS { 0u, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE }
|
|
/** Array initializer of LPSPI peripheral base pointers */
|
|
#define LPSPI_BASE_PTRS { (LPSPI_Type *)0u, LPSPI1, LPSPI2, LPSPI3, LPSPI4 }
|
|
/** Interrupt vectors for the LPSPI peripheral type */
|
|
#define LPSPI_IRQS { NotAvail_IRQn, LPSPI1_IRQn, LPSPI2_IRQn, LPSPI3_IRQn, LPSPI4_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group LPSPI_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- LPUART Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** LPUART - Register Layout Typedef */
|
|
typedef struct {
|
|
__I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
|
|
__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
|
|
__IO uint32_t GLOBAL; /**< LPUART Global Register, offset: 0x8 */
|
|
__IO uint32_t PINCFG; /**< LPUART Pin Configuration Register, offset: 0xC */
|
|
__IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x10 */
|
|
__IO uint32_t STAT; /**< LPUART Status Register, offset: 0x14 */
|
|
__IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x18 */
|
|
__IO uint32_t DATA; /**< LPUART Data Register, offset: 0x1C */
|
|
__IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x20 */
|
|
__IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x24 */
|
|
__IO uint32_t FIFO; /**< LPUART FIFO Register, offset: 0x28 */
|
|
__IO uint32_t WATER; /**< LPUART Watermark Register, offset: 0x2C */
|
|
} LPUART_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- LPUART Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup LPUART_Register_Masks LPUART Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name VERID - Version ID Register */
|
|
/*! @{ */
|
|
#define LPUART_VERID_FEATURE_MASK (0xFFFFU)
|
|
#define LPUART_VERID_FEATURE_SHIFT (0U)
|
|
/*! FEATURE - Feature Identification Number
|
|
* 0b0000000000000001..Standard feature set.
|
|
* 0b0000000000000011..Standard feature set with MODEM/IrDA support.
|
|
*/
|
|
#define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)
|
|
#define LPUART_VERID_MINOR_MASK (0xFF0000U)
|
|
#define LPUART_VERID_MINOR_SHIFT (16U)
|
|
#define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)
|
|
#define LPUART_VERID_MAJOR_MASK (0xFF000000U)
|
|
#define LPUART_VERID_MAJOR_SHIFT (24U)
|
|
#define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PARAM - Parameter Register */
|
|
/*! @{ */
|
|
#define LPUART_PARAM_TXFIFO_MASK (0xFFU)
|
|
#define LPUART_PARAM_TXFIFO_SHIFT (0U)
|
|
#define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)
|
|
#define LPUART_PARAM_RXFIFO_MASK (0xFF00U)
|
|
#define LPUART_PARAM_RXFIFO_SHIFT (8U)
|
|
#define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GLOBAL - LPUART Global Register */
|
|
/*! @{ */
|
|
#define LPUART_GLOBAL_RST_MASK (0x2U)
|
|
#define LPUART_GLOBAL_RST_SHIFT (1U)
|
|
/*! RST - Software Reset
|
|
* 0b0..Module is not reset.
|
|
* 0b1..Module is reset.
|
|
*/
|
|
#define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PINCFG - LPUART Pin Configuration Register */
|
|
/*! @{ */
|
|
#define LPUART_PINCFG_TRGSEL_MASK (0x3U)
|
|
#define LPUART_PINCFG_TRGSEL_SHIFT (0U)
|
|
/*! TRGSEL - Trigger Select
|
|
* 0b00..Input trigger is disabled.
|
|
* 0b01..Input trigger is used instead of RXD pin input.
|
|
* 0b10..Input trigger is used instead of CTS_B pin input.
|
|
* 0b11..Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger.
|
|
*/
|
|
#define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name BAUD - LPUART Baud Rate Register */
|
|
/*! @{ */
|
|
#define LPUART_BAUD_SBR_MASK (0x1FFFU)
|
|
#define LPUART_BAUD_SBR_SHIFT (0U)
|
|
#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
|
|
#define LPUART_BAUD_SBNS_MASK (0x2000U)
|
|
#define LPUART_BAUD_SBNS_SHIFT (13U)
|
|
/*! SBNS - Stop Bit Number Select
|
|
* 0b0..One stop bit.
|
|
* 0b1..Two stop bits.
|
|
*/
|
|
#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
|
|
#define LPUART_BAUD_RXEDGIE_MASK (0x4000U)
|
|
#define LPUART_BAUD_RXEDGIE_SHIFT (14U)
|
|
/*! RXEDGIE - RX Input Active Edge Interrupt Enable
|
|
* 0b0..Hardware interrupts from STAT[RXEDGIF] are disabled.
|
|
* 0b1..Hardware interrupt is requested when STAT[RXEDGIF] flag is 1.
|
|
*/
|
|
#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
|
|
#define LPUART_BAUD_LBKDIE_MASK (0x8000U)
|
|
#define LPUART_BAUD_LBKDIE_SHIFT (15U)
|
|
/*! LBKDIE - LIN Break Detect Interrupt Enable
|
|
* 0b0..Hardware interrupts from STAT[LBKDIF] flag are disabled (use polling).
|
|
* 0b1..Hardware interrupt requested when STAT[LBKDIF] flag is 1.
|
|
*/
|
|
#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
|
|
#define LPUART_BAUD_RESYNCDIS_MASK (0x10000U)
|
|
#define LPUART_BAUD_RESYNCDIS_SHIFT (16U)
|
|
/*! RESYNCDIS - Resynchronization Disable
|
|
* 0b0..Resynchronization during received data word is supported
|
|
* 0b1..Resynchronization during received data word is disabled
|
|
*/
|
|
#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
|
|
#define LPUART_BAUD_BOTHEDGE_MASK (0x20000U)
|
|
#define LPUART_BAUD_BOTHEDGE_SHIFT (17U)
|
|
/*! BOTHEDGE - Both Edge Sampling
|
|
* 0b0..Receiver samples input data using the rising edge of the baud rate clock.
|
|
* 0b1..Receiver samples input data using the rising and falling edge of the baud rate clock.
|
|
*/
|
|
#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
|
|
#define LPUART_BAUD_MATCFG_MASK (0xC0000U)
|
|
#define LPUART_BAUD_MATCFG_SHIFT (18U)
|
|
/*! MATCFG - Match Configuration
|
|
* 0b00..Address Match Wakeup
|
|
* 0b01..Idle Match Wakeup
|
|
* 0b10..Match On and Match Off
|
|
* 0b11..Enables RWU on Data Match and Match On/Off for transmitter CTS input
|
|
*/
|
|
#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
|
|
#define LPUART_BAUD_RIDMAE_MASK (0x100000U)
|
|
#define LPUART_BAUD_RIDMAE_SHIFT (20U)
|
|
/*! RIDMAE - Receiver Idle DMA Enable
|
|
* 0b0..DMA request disabled.
|
|
* 0b1..DMA request enabled.
|
|
*/
|
|
#define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK)
|
|
#define LPUART_BAUD_RDMAE_MASK (0x200000U)
|
|
#define LPUART_BAUD_RDMAE_SHIFT (21U)
|
|
/*! RDMAE - Receiver Full DMA Enable
|
|
* 0b0..DMA request disabled.
|
|
* 0b1..DMA request enabled.
|
|
*/
|
|
#define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
|
|
#define LPUART_BAUD_TDMAE_MASK (0x800000U)
|
|
#define LPUART_BAUD_TDMAE_SHIFT (23U)
|
|
/*! TDMAE - Transmitter DMA Enable
|
|
* 0b0..DMA request disabled.
|
|
* 0b1..DMA request enabled.
|
|
*/
|
|
#define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
|
|
#define LPUART_BAUD_OSR_MASK (0x1F000000U)
|
|
#define LPUART_BAUD_OSR_SHIFT (24U)
|
|
/*! OSR - Oversampling Ratio
|
|
* 0b00000..Writing 0 to this field will result in an oversampling ratio of 16
|
|
* 0b00001..Reserved
|
|
* 0b00010..Reserved
|
|
* 0b00011..Oversampling ratio of 4, requires BOTHEDGE to be set.
|
|
* 0b00100..Oversampling ratio of 5, requires BOTHEDGE to be set.
|
|
* 0b00101..Oversampling ratio of 6, requires BOTHEDGE to be set.
|
|
* 0b00110..Oversampling ratio of 7, requires BOTHEDGE to be set.
|
|
* 0b00111..Oversampling ratio of 8.
|
|
* 0b01000..Oversampling ratio of 9.
|
|
* 0b01001..Oversampling ratio of 10.
|
|
* 0b01010..Oversampling ratio of 11.
|
|
* 0b01011..Oversampling ratio of 12.
|
|
* 0b01100..Oversampling ratio of 13.
|
|
* 0b01101..Oversampling ratio of 14.
|
|
* 0b01110..Oversampling ratio of 15.
|
|
* 0b01111..Oversampling ratio of 16.
|
|
* 0b10000..Oversampling ratio of 17.
|
|
* 0b10001..Oversampling ratio of 18.
|
|
* 0b10010..Oversampling ratio of 19.
|
|
* 0b10011..Oversampling ratio of 20.
|
|
* 0b10100..Oversampling ratio of 21.
|
|
* 0b10101..Oversampling ratio of 22.
|
|
* 0b10110..Oversampling ratio of 23.
|
|
* 0b10111..Oversampling ratio of 24.
|
|
* 0b11000..Oversampling ratio of 25.
|
|
* 0b11001..Oversampling ratio of 26.
|
|
* 0b11010..Oversampling ratio of 27.
|
|
* 0b11011..Oversampling ratio of 28.
|
|
* 0b11100..Oversampling ratio of 29.
|
|
* 0b11101..Oversampling ratio of 30.
|
|
* 0b11110..Oversampling ratio of 31.
|
|
* 0b11111..Oversampling ratio of 32.
|
|
*/
|
|
#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
|
|
#define LPUART_BAUD_M10_MASK (0x20000000U)
|
|
#define LPUART_BAUD_M10_SHIFT (29U)
|
|
/*! M10 - 10-bit Mode select
|
|
* 0b0..Receiver and transmitter use 7-bit to 9-bit data characters.
|
|
* 0b1..Receiver and transmitter use 10-bit data characters.
|
|
*/
|
|
#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
|
|
#define LPUART_BAUD_MAEN2_MASK (0x40000000U)
|
|
#define LPUART_BAUD_MAEN2_SHIFT (30U)
|
|
/*! MAEN2 - Match Address Mode Enable 2
|
|
* 0b0..Normal operation.
|
|
* 0b1..Enables automatic address matching or data matching mode for MATCH[MA2].
|
|
*/
|
|
#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
|
|
#define LPUART_BAUD_MAEN1_MASK (0x80000000U)
|
|
#define LPUART_BAUD_MAEN1_SHIFT (31U)
|
|
/*! MAEN1 - Match Address Mode Enable 1
|
|
* 0b0..Normal operation.
|
|
* 0b1..Enables automatic address matching or data matching mode for MATCH[MA1].
|
|
*/
|
|
#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name STAT - LPUART Status Register */
|
|
/*! @{ */
|
|
#define LPUART_STAT_MA2F_MASK (0x4000U)
|
|
#define LPUART_STAT_MA2F_SHIFT (14U)
|
|
/*! MA2F - Match 2 Flag
|
|
* 0b0..Received data is not equal to MA2
|
|
* 0b1..Received data is equal to MA2
|
|
*/
|
|
#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
|
|
#define LPUART_STAT_MA1F_MASK (0x8000U)
|
|
#define LPUART_STAT_MA1F_SHIFT (15U)
|
|
/*! MA1F - Match 1 Flag
|
|
* 0b0..Received data is not equal to MA1
|
|
* 0b1..Received data is equal to MA1
|
|
*/
|
|
#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
|
|
#define LPUART_STAT_PF_MASK (0x10000U)
|
|
#define LPUART_STAT_PF_SHIFT (16U)
|
|
/*! PF - Parity Error Flag
|
|
* 0b0..No parity error.
|
|
* 0b1..Parity error.
|
|
*/
|
|
#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
|
|
#define LPUART_STAT_FE_MASK (0x20000U)
|
|
#define LPUART_STAT_FE_SHIFT (17U)
|
|
/*! FE - Framing Error Flag
|
|
* 0b0..No framing error detected. This does not guarantee the framing is correct.
|
|
* 0b1..Framing error.
|
|
*/
|
|
#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
|
|
#define LPUART_STAT_NF_MASK (0x40000U)
|
|
#define LPUART_STAT_NF_SHIFT (18U)
|
|
/*! NF - Noise Flag
|
|
* 0b0..No noise detected.
|
|
* 0b1..Noise detected in the received character in the DATA register.
|
|
*/
|
|
#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
|
|
#define LPUART_STAT_OR_MASK (0x80000U)
|
|
#define LPUART_STAT_OR_SHIFT (19U)
|
|
/*! OR - Receiver Overrun Flag
|
|
* 0b0..No overrun.
|
|
* 0b1..Receive overrun (new LPUART data lost).
|
|
*/
|
|
#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
|
|
#define LPUART_STAT_IDLE_MASK (0x100000U)
|
|
#define LPUART_STAT_IDLE_SHIFT (20U)
|
|
/*! IDLE - Idle Line Flag
|
|
* 0b0..No idle line detected.
|
|
* 0b1..Idle line was detected.
|
|
*/
|
|
#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
|
|
#define LPUART_STAT_RDRF_MASK (0x200000U)
|
|
#define LPUART_STAT_RDRF_SHIFT (21U)
|
|
/*! RDRF - Receive Data Register Full Flag
|
|
* 0b0..Receive data buffer empty.
|
|
* 0b1..Receive data buffer full.
|
|
*/
|
|
#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
|
|
#define LPUART_STAT_TC_MASK (0x400000U)
|
|
#define LPUART_STAT_TC_SHIFT (22U)
|
|
/*! TC - Transmission Complete Flag
|
|
* 0b0..Transmitter active (sending data, a preamble, or a break).
|
|
* 0b1..Transmitter idle (transmission activity complete).
|
|
*/
|
|
#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
|
|
#define LPUART_STAT_TDRE_MASK (0x800000U)
|
|
#define LPUART_STAT_TDRE_SHIFT (23U)
|
|
/*! TDRE - Transmit Data Register Empty Flag
|
|
* 0b0..Transmit data buffer full.
|
|
* 0b1..Transmit data buffer empty.
|
|
*/
|
|
#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
|
|
#define LPUART_STAT_RAF_MASK (0x1000000U)
|
|
#define LPUART_STAT_RAF_SHIFT (24U)
|
|
/*! RAF - Receiver Active Flag
|
|
* 0b0..LPUART receiver idle waiting for a start bit.
|
|
* 0b1..LPUART receiver active (RXD input not idle).
|
|
*/
|
|
#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
|
|
#define LPUART_STAT_LBKDE_MASK (0x2000000U)
|
|
#define LPUART_STAT_LBKDE_SHIFT (25U)
|
|
/*! LBKDE - LIN Break Detection Enable
|
|
* 0b0..LIN break detect is disabled, normal break character can be detected.
|
|
* 0b1..LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1).
|
|
*/
|
|
#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
|
|
#define LPUART_STAT_BRK13_MASK (0x4000000U)
|
|
#define LPUART_STAT_BRK13_SHIFT (26U)
|
|
/*! BRK13 - Break Character Generation Length
|
|
* 0b0..Break character is transmitted with length of 9 to 13 bit times.
|
|
* 0b1..Break character is transmitted with length of 12 to 15 bit times.
|
|
*/
|
|
#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
|
|
#define LPUART_STAT_RWUID_MASK (0x8000000U)
|
|
#define LPUART_STAT_RWUID_SHIFT (27U)
|
|
/*! RWUID - Receive Wake Up Idle Detect
|
|
* 0b0..During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not set when an address does not match.
|
|
* 0b1..During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does set when an address does not match.
|
|
*/
|
|
#define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
|
|
#define LPUART_STAT_RXINV_MASK (0x10000000U)
|
|
#define LPUART_STAT_RXINV_SHIFT (28U)
|
|
/*! RXINV - Receive Data Inversion
|
|
* 0b0..Receive data not inverted.
|
|
* 0b1..Receive data inverted.
|
|
*/
|
|
#define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
|
|
#define LPUART_STAT_MSBF_MASK (0x20000000U)
|
|
#define LPUART_STAT_MSBF_SHIFT (29U)
|
|
/*! MSBF - MSB First
|
|
* 0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.
|
|
* 0b1..MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE].
|
|
*/
|
|
#define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
|
|
#define LPUART_STAT_RXEDGIF_MASK (0x40000000U)
|
|
#define LPUART_STAT_RXEDGIF_SHIFT (30U)
|
|
/*! RXEDGIF - RXD Pin Active Edge Interrupt Flag
|
|
* 0b0..No active edge on the receive pin has occurred.
|
|
* 0b1..An active edge on the receive pin has occurred.
|
|
*/
|
|
#define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
|
|
#define LPUART_STAT_LBKDIF_MASK (0x80000000U)
|
|
#define LPUART_STAT_LBKDIF_SHIFT (31U)
|
|
/*! LBKDIF - LIN Break Detect Interrupt Flag
|
|
* 0b0..No LIN break character has been detected.
|
|
* 0b1..LIN break character has been detected.
|
|
*/
|
|
#define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CTRL - LPUART Control Register */
|
|
/*! @{ */
|
|
#define LPUART_CTRL_PT_MASK (0x1U)
|
|
#define LPUART_CTRL_PT_SHIFT (0U)
|
|
/*! PT - Parity Type
|
|
* 0b0..Even parity.
|
|
* 0b1..Odd parity.
|
|
*/
|
|
#define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
|
|
#define LPUART_CTRL_PE_MASK (0x2U)
|
|
#define LPUART_CTRL_PE_SHIFT (1U)
|
|
/*! PE - Parity Enable
|
|
* 0b0..No hardware parity generation or checking.
|
|
* 0b1..Parity enabled.
|
|
*/
|
|
#define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
|
|
#define LPUART_CTRL_ILT_MASK (0x4U)
|
|
#define LPUART_CTRL_ILT_SHIFT (2U)
|
|
/*! ILT - Idle Line Type Select
|
|
* 0b0..Idle character bit count starts after start bit.
|
|
* 0b1..Idle character bit count starts after stop bit.
|
|
*/
|
|
#define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
|
|
#define LPUART_CTRL_WAKE_MASK (0x8U)
|
|
#define LPUART_CTRL_WAKE_SHIFT (3U)
|
|
/*! WAKE - Receiver Wakeup Method Select
|
|
* 0b0..Configures RWU for idle-line wakeup.
|
|
* 0b1..Configures RWU with address-mark wakeup.
|
|
*/
|
|
#define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
|
|
#define LPUART_CTRL_M_MASK (0x10U)
|
|
#define LPUART_CTRL_M_SHIFT (4U)
|
|
/*! M - 9-Bit or 8-Bit Mode Select
|
|
* 0b0..Receiver and transmitter use 8-bit data characters.
|
|
* 0b1..Receiver and transmitter use 9-bit data characters.
|
|
*/
|
|
#define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
|
|
#define LPUART_CTRL_RSRC_MASK (0x20U)
|
|
#define LPUART_CTRL_RSRC_SHIFT (5U)
|
|
/*! RSRC - Receiver Source Select
|
|
* 0b0..Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin.
|
|
* 0b1..Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input.
|
|
*/
|
|
#define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
|
|
#define LPUART_CTRL_DOZEEN_MASK (0x40U)
|
|
#define LPUART_CTRL_DOZEEN_SHIFT (6U)
|
|
/*! DOZEEN - Doze Enable
|
|
* 0b0..LPUART is enabled in Doze mode.
|
|
* 0b1..LPUART is disabled in Doze mode.
|
|
*/
|
|
#define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
|
|
#define LPUART_CTRL_LOOPS_MASK (0x80U)
|
|
#define LPUART_CTRL_LOOPS_SHIFT (7U)
|
|
/*! LOOPS - Loop Mode Select
|
|
* 0b0..Normal operation - RXD and TXD use separate pins.
|
|
* 0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit).
|
|
*/
|
|
#define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
|
|
#define LPUART_CTRL_IDLECFG_MASK (0x700U)
|
|
#define LPUART_CTRL_IDLECFG_SHIFT (8U)
|
|
/*! IDLECFG - Idle Configuration
|
|
* 0b000..1 idle character
|
|
* 0b001..2 idle characters
|
|
* 0b010..4 idle characters
|
|
* 0b011..8 idle characters
|
|
* 0b100..16 idle characters
|
|
* 0b101..32 idle characters
|
|
* 0b110..64 idle characters
|
|
* 0b111..128 idle characters
|
|
*/
|
|
#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
|
|
#define LPUART_CTRL_M7_MASK (0x800U)
|
|
#define LPUART_CTRL_M7_SHIFT (11U)
|
|
/*! M7 - 7-Bit Mode Select
|
|
* 0b0..Receiver and transmitter use 8-bit to 10-bit data characters.
|
|
* 0b1..Receiver and transmitter use 7-bit data characters.
|
|
*/
|
|
#define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK)
|
|
#define LPUART_CTRL_MA2IE_MASK (0x4000U)
|
|
#define LPUART_CTRL_MA2IE_SHIFT (14U)
|
|
/*! MA2IE - Match 2 Interrupt Enable
|
|
* 0b0..MA2F interrupt disabled
|
|
* 0b1..MA2F interrupt enabled
|
|
*/
|
|
#define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
|
|
#define LPUART_CTRL_MA1IE_MASK (0x8000U)
|
|
#define LPUART_CTRL_MA1IE_SHIFT (15U)
|
|
/*! MA1IE - Match 1 Interrupt Enable
|
|
* 0b0..MA1F interrupt disabled
|
|
* 0b1..MA1F interrupt enabled
|
|
*/
|
|
#define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
|
|
#define LPUART_CTRL_SBK_MASK (0x10000U)
|
|
#define LPUART_CTRL_SBK_SHIFT (16U)
|
|
/*! SBK - Send Break
|
|
* 0b0..Normal transmitter operation.
|
|
* 0b1..Queue break character(s) to be sent.
|
|
*/
|
|
#define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
|
|
#define LPUART_CTRL_RWU_MASK (0x20000U)
|
|
#define LPUART_CTRL_RWU_SHIFT (17U)
|
|
/*! RWU - Receiver Wakeup Control
|
|
* 0b0..Normal receiver operation.
|
|
* 0b1..LPUART receiver in standby waiting for wakeup condition.
|
|
*/
|
|
#define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
|
|
#define LPUART_CTRL_RE_MASK (0x40000U)
|
|
#define LPUART_CTRL_RE_SHIFT (18U)
|
|
/*! RE - Receiver Enable
|
|
* 0b0..Receiver disabled.
|
|
* 0b1..Receiver enabled.
|
|
*/
|
|
#define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
|
|
#define LPUART_CTRL_TE_MASK (0x80000U)
|
|
#define LPUART_CTRL_TE_SHIFT (19U)
|
|
/*! TE - Transmitter Enable
|
|
* 0b0..Transmitter disabled.
|
|
* 0b1..Transmitter enabled.
|
|
*/
|
|
#define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
|
|
#define LPUART_CTRL_ILIE_MASK (0x100000U)
|
|
#define LPUART_CTRL_ILIE_SHIFT (20U)
|
|
/*! ILIE - Idle Line Interrupt Enable
|
|
* 0b0..Hardware interrupts from IDLE disabled; use polling.
|
|
* 0b1..Hardware interrupt requested when IDLE flag is 1.
|
|
*/
|
|
#define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
|
|
#define LPUART_CTRL_RIE_MASK (0x200000U)
|
|
#define LPUART_CTRL_RIE_SHIFT (21U)
|
|
/*! RIE - Receiver Interrupt Enable
|
|
* 0b0..Hardware interrupts from RDRF disabled; use polling.
|
|
* 0b1..Hardware interrupt requested when RDRF flag is 1.
|
|
*/
|
|
#define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
|
|
#define LPUART_CTRL_TCIE_MASK (0x400000U)
|
|
#define LPUART_CTRL_TCIE_SHIFT (22U)
|
|
/*! TCIE - Transmission Complete Interrupt Enable for
|
|
* 0b0..Hardware interrupts from TC disabled; use polling.
|
|
* 0b1..Hardware interrupt requested when TC flag is 1.
|
|
*/
|
|
#define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
|
|
#define LPUART_CTRL_TIE_MASK (0x800000U)
|
|
#define LPUART_CTRL_TIE_SHIFT (23U)
|
|
/*! TIE - Transmit Interrupt Enable
|
|
* 0b0..Hardware interrupts from TDRE disabled; use polling.
|
|
* 0b1..Hardware interrupt requested when TDRE flag is 1.
|
|
*/
|
|
#define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
|
|
#define LPUART_CTRL_PEIE_MASK (0x1000000U)
|
|
#define LPUART_CTRL_PEIE_SHIFT (24U)
|
|
/*! PEIE - Parity Error Interrupt Enable
|
|
* 0b0..PF interrupts disabled; use polling).
|
|
* 0b1..Hardware interrupt requested when PF is set.
|
|
*/
|
|
#define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
|
|
#define LPUART_CTRL_FEIE_MASK (0x2000000U)
|
|
#define LPUART_CTRL_FEIE_SHIFT (25U)
|
|
/*! FEIE - Framing Error Interrupt Enable
|
|
* 0b0..FE interrupts disabled; use polling.
|
|
* 0b1..Hardware interrupt requested when FE is set.
|
|
*/
|
|
#define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
|
|
#define LPUART_CTRL_NEIE_MASK (0x4000000U)
|
|
#define LPUART_CTRL_NEIE_SHIFT (26U)
|
|
/*! NEIE - Noise Error Interrupt Enable
|
|
* 0b0..NF interrupts disabled; use polling.
|
|
* 0b1..Hardware interrupt requested when NF is set.
|
|
*/
|
|
#define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
|
|
#define LPUART_CTRL_ORIE_MASK (0x8000000U)
|
|
#define LPUART_CTRL_ORIE_SHIFT (27U)
|
|
/*! ORIE - Overrun Interrupt Enable
|
|
* 0b0..OR interrupts disabled; use polling.
|
|
* 0b1..Hardware interrupt requested when OR is set.
|
|
*/
|
|
#define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
|
|
#define LPUART_CTRL_TXINV_MASK (0x10000000U)
|
|
#define LPUART_CTRL_TXINV_SHIFT (28U)
|
|
/*! TXINV - Transmit Data Inversion
|
|
* 0b0..Transmit data not inverted.
|
|
* 0b1..Transmit data inverted.
|
|
*/
|
|
#define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
|
|
#define LPUART_CTRL_TXDIR_MASK (0x20000000U)
|
|
#define LPUART_CTRL_TXDIR_SHIFT (29U)
|
|
/*! TXDIR - TXD Pin Direction in Single-Wire Mode
|
|
* 0b0..TXD pin is an input in single-wire mode.
|
|
* 0b1..TXD pin is an output in single-wire mode.
|
|
*/
|
|
#define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
|
|
#define LPUART_CTRL_R9T8_MASK (0x40000000U)
|
|
#define LPUART_CTRL_R9T8_SHIFT (30U)
|
|
#define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
|
|
#define LPUART_CTRL_R8T9_MASK (0x80000000U)
|
|
#define LPUART_CTRL_R8T9_SHIFT (31U)
|
|
#define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DATA - LPUART Data Register */
|
|
/*! @{ */
|
|
#define LPUART_DATA_R0T0_MASK (0x1U)
|
|
#define LPUART_DATA_R0T0_SHIFT (0U)
|
|
#define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
|
|
#define LPUART_DATA_R1T1_MASK (0x2U)
|
|
#define LPUART_DATA_R1T1_SHIFT (1U)
|
|
#define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
|
|
#define LPUART_DATA_R2T2_MASK (0x4U)
|
|
#define LPUART_DATA_R2T2_SHIFT (2U)
|
|
#define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
|
|
#define LPUART_DATA_R3T3_MASK (0x8U)
|
|
#define LPUART_DATA_R3T3_SHIFT (3U)
|
|
#define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
|
|
#define LPUART_DATA_R4T4_MASK (0x10U)
|
|
#define LPUART_DATA_R4T4_SHIFT (4U)
|
|
#define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
|
|
#define LPUART_DATA_R5T5_MASK (0x20U)
|
|
#define LPUART_DATA_R5T5_SHIFT (5U)
|
|
#define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
|
|
#define LPUART_DATA_R6T6_MASK (0x40U)
|
|
#define LPUART_DATA_R6T6_SHIFT (6U)
|
|
#define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
|
|
#define LPUART_DATA_R7T7_MASK (0x80U)
|
|
#define LPUART_DATA_R7T7_SHIFT (7U)
|
|
#define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
|
|
#define LPUART_DATA_R8T8_MASK (0x100U)
|
|
#define LPUART_DATA_R8T8_SHIFT (8U)
|
|
#define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
|
|
#define LPUART_DATA_R9T9_MASK (0x200U)
|
|
#define LPUART_DATA_R9T9_SHIFT (9U)
|
|
#define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
|
|
#define LPUART_DATA_IDLINE_MASK (0x800U)
|
|
#define LPUART_DATA_IDLINE_SHIFT (11U)
|
|
/*! IDLINE - Idle Line
|
|
* 0b0..Receiver was not idle before receiving this character.
|
|
* 0b1..Receiver was idle before receiving this character.
|
|
*/
|
|
#define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
|
|
#define LPUART_DATA_RXEMPT_MASK (0x1000U)
|
|
#define LPUART_DATA_RXEMPT_SHIFT (12U)
|
|
/*! RXEMPT - Receive Buffer Empty
|
|
* 0b0..Receive buffer contains valid data.
|
|
* 0b1..Receive buffer is empty, data returned on read is not valid.
|
|
*/
|
|
#define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
|
|
#define LPUART_DATA_FRETSC_MASK (0x2000U)
|
|
#define LPUART_DATA_FRETSC_SHIFT (13U)
|
|
/*! FRETSC - Frame Error / Transmit Special Character
|
|
* 0b0..The dataword was received without a frame error on read, or transmit a normal character on write.
|
|
* 0b1..The dataword was received with a frame error, or transmit an idle or break character on transmit.
|
|
*/
|
|
#define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
|
|
#define LPUART_DATA_PARITYE_MASK (0x4000U)
|
|
#define LPUART_DATA_PARITYE_SHIFT (14U)
|
|
/*! PARITYE - PARITYE
|
|
* 0b0..The dataword was received without a parity error.
|
|
* 0b1..The dataword was received with a parity error.
|
|
*/
|
|
#define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
|
|
#define LPUART_DATA_NOISY_MASK (0x8000U)
|
|
#define LPUART_DATA_NOISY_SHIFT (15U)
|
|
/*! NOISY - NOISY
|
|
* 0b0..The dataword was received without noise.
|
|
* 0b1..The data was received with noise.
|
|
*/
|
|
#define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MATCH - LPUART Match Address Register */
|
|
/*! @{ */
|
|
#define LPUART_MATCH_MA1_MASK (0x3FFU)
|
|
#define LPUART_MATCH_MA1_SHIFT (0U)
|
|
#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
|
|
#define LPUART_MATCH_MA2_MASK (0x3FF0000U)
|
|
#define LPUART_MATCH_MA2_SHIFT (16U)
|
|
#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MODIR - LPUART Modem IrDA Register */
|
|
/*! @{ */
|
|
#define LPUART_MODIR_TXCTSE_MASK (0x1U)
|
|
#define LPUART_MODIR_TXCTSE_SHIFT (0U)
|
|
/*! TXCTSE - Transmitter clear-to-send enable
|
|
* 0b0..CTS has no effect on the transmitter.
|
|
* 0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.
|
|
*/
|
|
#define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
|
|
#define LPUART_MODIR_TXRTSE_MASK (0x2U)
|
|
#define LPUART_MODIR_TXRTSE_SHIFT (1U)
|
|
/*! TXRTSE - Transmitter request-to-send enable
|
|
* 0b0..The transmitter has no effect on RTS.
|
|
* 0b1..When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit.
|
|
*/
|
|
#define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
|
|
#define LPUART_MODIR_TXRTSPOL_MASK (0x4U)
|
|
#define LPUART_MODIR_TXRTSPOL_SHIFT (2U)
|
|
/*! TXRTSPOL - Transmitter request-to-send polarity
|
|
* 0b0..Transmitter RTS is active low.
|
|
* 0b1..Transmitter RTS is active high.
|
|
*/
|
|
#define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
|
|
#define LPUART_MODIR_RXRTSE_MASK (0x8U)
|
|
#define LPUART_MODIR_RXRTSE_SHIFT (3U)
|
|
/*! RXRTSE - Receiver request-to-send enable
|
|
* 0b0..The receiver has no effect on RTS.
|
|
* 0b1..RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause the receiver data register to become full. RTS is asserted if the receiver data register is not full and has not detected a start bit that would cause the receiver data register to become full.
|
|
*/
|
|
#define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
|
|
#define LPUART_MODIR_TXCTSC_MASK (0x10U)
|
|
#define LPUART_MODIR_TXCTSC_SHIFT (4U)
|
|
/*! TXCTSC - Transmit CTS Configuration
|
|
* 0b0..CTS input is sampled at the start of each character.
|
|
* 0b1..CTS input is sampled when the transmitter is idle.
|
|
*/
|
|
#define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
|
|
#define LPUART_MODIR_TXCTSSRC_MASK (0x20U)
|
|
#define LPUART_MODIR_TXCTSSRC_SHIFT (5U)
|
|
/*! TXCTSSRC - Transmit CTS Source
|
|
* 0b0..CTS input is the CTS_B pin.
|
|
* 0b1..CTS input is the inverted Receiver Match result.
|
|
*/
|
|
#define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
|
|
#define LPUART_MODIR_RTSWATER_MASK (0x300U)
|
|
#define LPUART_MODIR_RTSWATER_SHIFT (8U)
|
|
#define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)
|
|
#define LPUART_MODIR_TNP_MASK (0x30000U)
|
|
#define LPUART_MODIR_TNP_SHIFT (16U)
|
|
/*! TNP - Transmitter narrow pulse
|
|
* 0b00..1/OSR.
|
|
* 0b01..2/OSR.
|
|
* 0b10..3/OSR.
|
|
* 0b11..4/OSR.
|
|
*/
|
|
#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
|
|
#define LPUART_MODIR_IREN_MASK (0x40000U)
|
|
#define LPUART_MODIR_IREN_SHIFT (18U)
|
|
/*! IREN - Infrared enable
|
|
* 0b0..IR disabled.
|
|
* 0b1..IR enabled.
|
|
*/
|
|
#define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FIFO - LPUART FIFO Register */
|
|
/*! @{ */
|
|
#define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U)
|
|
#define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U)
|
|
/*! RXFIFOSIZE - Receive FIFO Buffer Depth
|
|
* 0b000..Receive FIFO/Buffer depth = 1 dataword.
|
|
* 0b001..Receive FIFO/Buffer depth = 4 datawords.
|
|
* 0b010..Receive FIFO/Buffer depth = 8 datawords.
|
|
* 0b011..Receive FIFO/Buffer depth = 16 datawords.
|
|
* 0b100..Receive FIFO/Buffer depth = 32 datawords.
|
|
* 0b101..Receive FIFO/Buffer depth = 64 datawords.
|
|
* 0b110..Receive FIFO/Buffer depth = 128 datawords.
|
|
* 0b111..Receive FIFO/Buffer depth = 256 datawords.
|
|
*/
|
|
#define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)
|
|
#define LPUART_FIFO_RXFE_MASK (0x8U)
|
|
#define LPUART_FIFO_RXFE_SHIFT (3U)
|
|
/*! RXFE - Receive FIFO Enable
|
|
* 0b0..Receive FIFO is not enabled. Buffer is depth 1.
|
|
* 0b1..Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
|
|
*/
|
|
#define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)
|
|
#define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U)
|
|
#define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U)
|
|
/*! TXFIFOSIZE - Transmit FIFO Buffer Depth
|
|
* 0b000..Transmit FIFO/Buffer depth = 1 dataword.
|
|
* 0b001..Transmit FIFO/Buffer depth = 4 datawords.
|
|
* 0b010..Transmit FIFO/Buffer depth = 8 datawords.
|
|
* 0b011..Transmit FIFO/Buffer depth = 16 datawords.
|
|
* 0b100..Transmit FIFO/Buffer depth = 32 datawords.
|
|
* 0b101..Transmit FIFO/Buffer depth = 64 datawords.
|
|
* 0b110..Transmit FIFO/Buffer depth = 128 datawords.
|
|
* 0b111..Transmit FIFO/Buffer depth = 256 datawords
|
|
*/
|
|
#define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)
|
|
#define LPUART_FIFO_TXFE_MASK (0x80U)
|
|
#define LPUART_FIFO_TXFE_SHIFT (7U)
|
|
/*! TXFE - Transmit FIFO Enable
|
|
* 0b0..Transmit FIFO is not enabled. Buffer is depth 1.
|
|
* 0b1..Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
|
|
*/
|
|
#define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)
|
|
#define LPUART_FIFO_RXUFE_MASK (0x100U)
|
|
#define LPUART_FIFO_RXUFE_SHIFT (8U)
|
|
/*! RXUFE - Receive FIFO Underflow Interrupt Enable
|
|
* 0b0..RXUF flag does not generate an interrupt to the host.
|
|
* 0b1..RXUF flag generates an interrupt to the host.
|
|
*/
|
|
#define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)
|
|
#define LPUART_FIFO_TXOFE_MASK (0x200U)
|
|
#define LPUART_FIFO_TXOFE_SHIFT (9U)
|
|
/*! TXOFE - Transmit FIFO Overflow Interrupt Enable
|
|
* 0b0..TXOF flag does not generate an interrupt to the host.
|
|
* 0b1..TXOF flag generates an interrupt to the host.
|
|
*/
|
|
#define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)
|
|
#define LPUART_FIFO_RXIDEN_MASK (0x1C00U)
|
|
#define LPUART_FIFO_RXIDEN_SHIFT (10U)
|
|
/*! RXIDEN - Receiver Idle Empty Enable
|
|
* 0b000..Disable RDRF assertion due to partially filled FIFO when receiver is idle.
|
|
* 0b001..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character.
|
|
* 0b010..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters.
|
|
* 0b011..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters.
|
|
* 0b100..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters.
|
|
* 0b101..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters.
|
|
* 0b110..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters.
|
|
* 0b111..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters.
|
|
*/
|
|
#define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)
|
|
#define LPUART_FIFO_RXFLUSH_MASK (0x4000U)
|
|
#define LPUART_FIFO_RXFLUSH_SHIFT (14U)
|
|
/*! RXFLUSH - Receive FIFO/Buffer Flush
|
|
* 0b0..No flush operation occurs.
|
|
* 0b1..All data in the receive FIFO/buffer is cleared out.
|
|
*/
|
|
#define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)
|
|
#define LPUART_FIFO_TXFLUSH_MASK (0x8000U)
|
|
#define LPUART_FIFO_TXFLUSH_SHIFT (15U)
|
|
/*! TXFLUSH - Transmit FIFO/Buffer Flush
|
|
* 0b0..No flush operation occurs.
|
|
* 0b1..All data in the transmit FIFO/Buffer is cleared out.
|
|
*/
|
|
#define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)
|
|
#define LPUART_FIFO_RXUF_MASK (0x10000U)
|
|
#define LPUART_FIFO_RXUF_SHIFT (16U)
|
|
/*! RXUF - Receiver Buffer Underflow Flag
|
|
* 0b0..No receive buffer underflow has occurred since the last time the flag was cleared.
|
|
* 0b1..At least one receive buffer underflow has occurred since the last time the flag was cleared.
|
|
*/
|
|
#define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)
|
|
#define LPUART_FIFO_TXOF_MASK (0x20000U)
|
|
#define LPUART_FIFO_TXOF_SHIFT (17U)
|
|
/*! TXOF - Transmitter Buffer Overflow Flag
|
|
* 0b0..No transmit buffer overflow has occurred since the last time the flag was cleared.
|
|
* 0b1..At least one transmit buffer overflow has occurred since the last time the flag was cleared.
|
|
*/
|
|
#define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)
|
|
#define LPUART_FIFO_RXEMPT_MASK (0x400000U)
|
|
#define LPUART_FIFO_RXEMPT_SHIFT (22U)
|
|
/*! RXEMPT - Receive Buffer/FIFO Empty
|
|
* 0b0..Receive buffer is not empty.
|
|
* 0b1..Receive buffer is empty.
|
|
*/
|
|
#define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)
|
|
#define LPUART_FIFO_TXEMPT_MASK (0x800000U)
|
|
#define LPUART_FIFO_TXEMPT_SHIFT (23U)
|
|
/*! TXEMPT - Transmit Buffer/FIFO Empty
|
|
* 0b0..Transmit buffer is not empty.
|
|
* 0b1..Transmit buffer is empty.
|
|
*/
|
|
#define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name WATER - LPUART Watermark Register */
|
|
/*! @{ */
|
|
#define LPUART_WATER_TXWATER_MASK (0x3U)
|
|
#define LPUART_WATER_TXWATER_SHIFT (0U)
|
|
#define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)
|
|
#define LPUART_WATER_TXCOUNT_MASK (0x700U)
|
|
#define LPUART_WATER_TXCOUNT_SHIFT (8U)
|
|
#define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)
|
|
#define LPUART_WATER_RXWATER_MASK (0x30000U)
|
|
#define LPUART_WATER_RXWATER_SHIFT (16U)
|
|
#define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)
|
|
#define LPUART_WATER_RXCOUNT_MASK (0x7000000U)
|
|
#define LPUART_WATER_RXCOUNT_SHIFT (24U)
|
|
#define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group LPUART_Register_Masks */
|
|
|
|
|
|
/* LPUART - Peripheral instance base addresses */
|
|
/** Peripheral LPUART1 base address */
|
|
#define LPUART1_BASE (0x40184000u)
|
|
/** Peripheral LPUART1 base pointer */
|
|
#define LPUART1 ((LPUART_Type *)LPUART1_BASE)
|
|
/** Peripheral LPUART2 base address */
|
|
#define LPUART2_BASE (0x40188000u)
|
|
/** Peripheral LPUART2 base pointer */
|
|
#define LPUART2 ((LPUART_Type *)LPUART2_BASE)
|
|
/** Peripheral LPUART3 base address */
|
|
#define LPUART3_BASE (0x4018C000u)
|
|
/** Peripheral LPUART3 base pointer */
|
|
#define LPUART3 ((LPUART_Type *)LPUART3_BASE)
|
|
/** Peripheral LPUART4 base address */
|
|
#define LPUART4_BASE (0x40190000u)
|
|
/** Peripheral LPUART4 base pointer */
|
|
#define LPUART4 ((LPUART_Type *)LPUART4_BASE)
|
|
/** Peripheral LPUART5 base address */
|
|
#define LPUART5_BASE (0x40194000u)
|
|
/** Peripheral LPUART5 base pointer */
|
|
#define LPUART5 ((LPUART_Type *)LPUART5_BASE)
|
|
/** Peripheral LPUART6 base address */
|
|
#define LPUART6_BASE (0x40198000u)
|
|
/** Peripheral LPUART6 base pointer */
|
|
#define LPUART6 ((LPUART_Type *)LPUART6_BASE)
|
|
/** Peripheral LPUART7 base address */
|
|
#define LPUART7_BASE (0x4019C000u)
|
|
/** Peripheral LPUART7 base pointer */
|
|
#define LPUART7 ((LPUART_Type *)LPUART7_BASE)
|
|
/** Peripheral LPUART8 base address */
|
|
#define LPUART8_BASE (0x401A0000u)
|
|
/** Peripheral LPUART8 base pointer */
|
|
#define LPUART8 ((LPUART_Type *)LPUART8_BASE)
|
|
/** Array initializer of LPUART peripheral base addresses */
|
|
#define LPUART_BASE_ADDRS { 0u, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE }
|
|
/** Array initializer of LPUART peripheral base pointers */
|
|
#define LPUART_BASE_PTRS { (LPUART_Type *)0u, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 }
|
|
/** Interrupt vectors for the LPUART peripheral type */
|
|
#define LPUART_RX_TX_IRQS { NotAvail_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn, LPUART6_IRQn, LPUART7_IRQn, LPUART8_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group LPUART_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- OCOTP Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup OCOTP_Peripheral_Access_Layer OCOTP Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** OCOTP - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t CTRL; /**< OTP Controller Control Register, offset: 0x0 */
|
|
__IO uint32_t CTRL_SET; /**< OTP Controller Control Register, offset: 0x4 */
|
|
__IO uint32_t CTRL_CLR; /**< OTP Controller Control Register, offset: 0x8 */
|
|
__IO uint32_t CTRL_TOG; /**< OTP Controller Control Register, offset: 0xC */
|
|
__IO uint32_t TIMING; /**< OTP Controller Timing Register, offset: 0x10 */
|
|
uint8_t RESERVED_0[12];
|
|
__IO uint32_t DATA; /**< OTP Controller Write Data Register, offset: 0x20 */
|
|
uint8_t RESERVED_1[12];
|
|
__IO uint32_t READ_CTRL; /**< OTP Controller Write Data Register, offset: 0x30 */
|
|
uint8_t RESERVED_2[12];
|
|
__IO uint32_t READ_FUSE_DATA; /**< OTP Controller Read Data Register, offset: 0x40 */
|
|
uint8_t RESERVED_3[12];
|
|
__IO uint32_t SW_STICKY; /**< Sticky bit Register, offset: 0x50 */
|
|
uint8_t RESERVED_4[12];
|
|
__IO uint32_t SCS; /**< Software Controllable Signals Register, offset: 0x60 */
|
|
__IO uint32_t SCS_SET; /**< Software Controllable Signals Register, offset: 0x64 */
|
|
__IO uint32_t SCS_CLR; /**< Software Controllable Signals Register, offset: 0x68 */
|
|
__IO uint32_t SCS_TOG; /**< Software Controllable Signals Register, offset: 0x6C */
|
|
uint8_t RESERVED_5[32];
|
|
__I uint32_t VERSION; /**< OTP Controller Version Register, offset: 0x90 */
|
|
uint8_t RESERVED_6[108];
|
|
__IO uint32_t TIMING2; /**< OTP Controller Timing Register 2, offset: 0x100 */
|
|
uint8_t RESERVED_7[764];
|
|
__IO uint32_t LOCK; /**< Value of OTP Bank0 Word0 (Lock controls), offset: 0x400 */
|
|
uint8_t RESERVED_8[12];
|
|
__IO uint32_t CFG0; /**< Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.), offset: 0x410 */
|
|
uint8_t RESERVED_9[12];
|
|
__IO uint32_t CFG1; /**< Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.), offset: 0x420 */
|
|
uint8_t RESERVED_10[12];
|
|
__IO uint32_t CFG2; /**< Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.), offset: 0x430 */
|
|
uint8_t RESERVED_11[12];
|
|
__IO uint32_t CFG3; /**< Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.), offset: 0x440 */
|
|
uint8_t RESERVED_12[12];
|
|
__IO uint32_t CFG4; /**< Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.), offset: 0x450 */
|
|
uint8_t RESERVED_13[12];
|
|
__IO uint32_t CFG5; /**< Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.), offset: 0x460 */
|
|
uint8_t RESERVED_14[12];
|
|
__IO uint32_t CFG6; /**< Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.), offset: 0x470 */
|
|
uint8_t RESERVED_15[12];
|
|
__IO uint32_t MEM0; /**< Value of OTP Bank1 Word0 (Memory Related Info.), offset: 0x480 */
|
|
uint8_t RESERVED_16[12];
|
|
__IO uint32_t MEM1; /**< Value of OTP Bank1 Word1 (Memory Related Info.), offset: 0x490 */
|
|
uint8_t RESERVED_17[12];
|
|
__IO uint32_t MEM2; /**< Value of OTP Bank1 Word2 (Memory Related Info.), offset: 0x4A0 */
|
|
uint8_t RESERVED_18[12];
|
|
__IO uint32_t MEM3; /**< Value of OTP Bank1 Word3 (Memory Related Info.), offset: 0x4B0 */
|
|
uint8_t RESERVED_19[12];
|
|
__IO uint32_t MEM4; /**< Value of OTP Bank1 Word4 (Memory Related Info.), offset: 0x4C0 */
|
|
uint8_t RESERVED_20[12];
|
|
__IO uint32_t ANA0; /**< Value of OTP Bank1 Word5 (Analog Info.), offset: 0x4D0 */
|
|
uint8_t RESERVED_21[12];
|
|
__IO uint32_t ANA1; /**< Value of OTP Bank1 Word6 (Analog Info.), offset: 0x4E0 */
|
|
uint8_t RESERVED_22[12];
|
|
__IO uint32_t ANA2; /**< Value of OTP Bank1 Word7 (Analog Info.), offset: 0x4F0 */
|
|
uint8_t RESERVED_23[140];
|
|
__IO uint32_t SRK0; /**< Shadow Register for OTP Bank3 Word0 (SRK Hash), offset: 0x580 */
|
|
uint8_t RESERVED_24[12];
|
|
__IO uint32_t SRK1; /**< Shadow Register for OTP Bank3 Word1 (SRK Hash), offset: 0x590 */
|
|
uint8_t RESERVED_25[12];
|
|
__IO uint32_t SRK2; /**< Shadow Register for OTP Bank3 Word2 (SRK Hash), offset: 0x5A0 */
|
|
uint8_t RESERVED_26[12];
|
|
__IO uint32_t SRK3; /**< Shadow Register for OTP Bank3 Word3 (SRK Hash), offset: 0x5B0 */
|
|
uint8_t RESERVED_27[12];
|
|
__IO uint32_t SRK4; /**< Shadow Register for OTP Bank3 Word4 (SRK Hash), offset: 0x5C0 */
|
|
uint8_t RESERVED_28[12];
|
|
__IO uint32_t SRK5; /**< Shadow Register for OTP Bank3 Word5 (SRK Hash), offset: 0x5D0 */
|
|
uint8_t RESERVED_29[12];
|
|
__IO uint32_t SRK6; /**< Shadow Register for OTP Bank3 Word6 (SRK Hash), offset: 0x5E0 */
|
|
uint8_t RESERVED_30[12];
|
|
__IO uint32_t SRK7; /**< Shadow Register for OTP Bank3 Word7 (SRK Hash), offset: 0x5F0 */
|
|
uint8_t RESERVED_31[12];
|
|
__IO uint32_t SJC_RESP0; /**< Value of OTP Bank4 Word0 (Secure JTAG Response Field), offset: 0x600 */
|
|
uint8_t RESERVED_32[12];
|
|
__IO uint32_t SJC_RESP1; /**< Value of OTP Bank4 Word1 (Secure JTAG Response Field), offset: 0x610 */
|
|
uint8_t RESERVED_33[12];
|
|
__IO uint32_t MAC0; /**< Value of OTP Bank4 Word2 (MAC Address), offset: 0x620 */
|
|
uint8_t RESERVED_34[12];
|
|
__IO uint32_t MAC1; /**< Value of OTP Bank4 Word3 (MAC Address), offset: 0x630 */
|
|
uint8_t RESERVED_35[12];
|
|
__IO uint32_t GP3; /**< Value of OTP Bank4 Word4 (MAC Address), offset: 0x640 */
|
|
uint8_t RESERVED_36[28];
|
|
__IO uint32_t GP1; /**< Value of OTP Bank4 Word6 (General Purpose Customer Defined Info), offset: 0x660 */
|
|
uint8_t RESERVED_37[12];
|
|
__IO uint32_t GP2; /**< Value of OTP Bank4 Word7 (General Purpose Customer Defined Info), offset: 0x670 */
|
|
uint8_t RESERVED_38[12];
|
|
__IO uint32_t SW_GP1; /**< Value of OTP Bank5 Word0 (SW GP1), offset: 0x680 */
|
|
uint8_t RESERVED_39[12];
|
|
__IO uint32_t SW_GP20; /**< Value of OTP Bank5 Word1 (SW GP2), offset: 0x690 */
|
|
uint8_t RESERVED_40[12];
|
|
__IO uint32_t SW_GP21; /**< Value of OTP Bank5 Word2 (SW GP2), offset: 0x6A0 */
|
|
uint8_t RESERVED_41[12];
|
|
__IO uint32_t SW_GP22; /**< Value of OTP Bank5 Word3 (SW GP2), offset: 0x6B0 */
|
|
uint8_t RESERVED_42[12];
|
|
__IO uint32_t SW_GP23; /**< Value of OTP Bank5 Word4 (SW GP2), offset: 0x6C0 */
|
|
uint8_t RESERVED_43[12];
|
|
__IO uint32_t MISC_CONF0; /**< Value of OTP Bank5 Word5 (Misc Conf), offset: 0x6D0 */
|
|
uint8_t RESERVED_44[12];
|
|
__IO uint32_t MISC_CONF1; /**< Value of OTP Bank5 Word6 (Misc Conf), offset: 0x6E0 */
|
|
uint8_t RESERVED_45[12];
|
|
__IO uint32_t SRK_REVOKE; /**< Value of OTP Bank5 Word7 (SRK Revoke), offset: 0x6F0 */
|
|
} OCOTP_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- OCOTP Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup OCOTP_Register_Masks OCOTP Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name CTRL - OTP Controller Control Register */
|
|
/*! @{ */
|
|
#define OCOTP_CTRL_ADDR_MASK (0x3FU)
|
|
#define OCOTP_CTRL_ADDR_SHIFT (0U)
|
|
#define OCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_CTRL_ADDR_MASK)
|
|
#define OCOTP_CTRL_BUSY_MASK (0x100U)
|
|
#define OCOTP_CTRL_BUSY_SHIFT (8U)
|
|
#define OCOTP_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_BUSY_SHIFT)) & OCOTP_CTRL_BUSY_MASK)
|
|
#define OCOTP_CTRL_ERROR_MASK (0x200U)
|
|
#define OCOTP_CTRL_ERROR_SHIFT (9U)
|
|
#define OCOTP_CTRL_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ERROR_SHIFT)) & OCOTP_CTRL_ERROR_MASK)
|
|
#define OCOTP_CTRL_RELOAD_SHADOWS_MASK (0x400U)
|
|
#define OCOTP_CTRL_RELOAD_SHADOWS_SHIFT (10U)
|
|
#define OCOTP_CTRL_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_RELOAD_SHADOWS_MASK)
|
|
#define OCOTP_CTRL_WR_UNLOCK_MASK (0xFFFF0000U)
|
|
#define OCOTP_CTRL_WR_UNLOCK_SHIFT (16U)
|
|
#define OCOTP_CTRL_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_WR_UNLOCK_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CTRL_SET - OTP Controller Control Register */
|
|
/*! @{ */
|
|
#define OCOTP_CTRL_SET_ADDR_MASK (0x3FU)
|
|
#define OCOTP_CTRL_SET_ADDR_SHIFT (0U)
|
|
#define OCOTP_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_CTRL_SET_ADDR_MASK)
|
|
#define OCOTP_CTRL_SET_BUSY_MASK (0x100U)
|
|
#define OCOTP_CTRL_SET_BUSY_SHIFT (8U)
|
|
#define OCOTP_CTRL_SET_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_BUSY_SHIFT)) & OCOTP_CTRL_SET_BUSY_MASK)
|
|
#define OCOTP_CTRL_SET_ERROR_MASK (0x200U)
|
|
#define OCOTP_CTRL_SET_ERROR_SHIFT (9U)
|
|
#define OCOTP_CTRL_SET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ERROR_SHIFT)) & OCOTP_CTRL_SET_ERROR_MASK)
|
|
#define OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK (0x400U)
|
|
#define OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT (10U)
|
|
#define OCOTP_CTRL_SET_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK)
|
|
#define OCOTP_CTRL_SET_WR_UNLOCK_MASK (0xFFFF0000U)
|
|
#define OCOTP_CTRL_SET_WR_UNLOCK_SHIFT (16U)
|
|
#define OCOTP_CTRL_SET_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_SET_WR_UNLOCK_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CTRL_CLR - OTP Controller Control Register */
|
|
/*! @{ */
|
|
#define OCOTP_CTRL_CLR_ADDR_MASK (0x3FU)
|
|
#define OCOTP_CTRL_CLR_ADDR_SHIFT (0U)
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#define OCOTP_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_CTRL_CLR_ADDR_MASK)
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#define OCOTP_CTRL_CLR_BUSY_MASK (0x100U)
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#define OCOTP_CTRL_CLR_BUSY_SHIFT (8U)
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#define OCOTP_CTRL_CLR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_BUSY_SHIFT)) & OCOTP_CTRL_CLR_BUSY_MASK)
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#define OCOTP_CTRL_CLR_ERROR_MASK (0x200U)
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#define OCOTP_CTRL_CLR_ERROR_SHIFT (9U)
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#define OCOTP_CTRL_CLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ERROR_SHIFT)) & OCOTP_CTRL_CLR_ERROR_MASK)
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#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK (0x400U)
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#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT (10U)
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#define OCOTP_CTRL_CLR_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK)
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#define OCOTP_CTRL_CLR_WR_UNLOCK_MASK (0xFFFF0000U)
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#define OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT (16U)
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#define OCOTP_CTRL_CLR_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_CLR_WR_UNLOCK_MASK)
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/*! @} */
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/*! @name CTRL_TOG - OTP Controller Control Register */
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/*! @{ */
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#define OCOTP_CTRL_TOG_ADDR_MASK (0x3FU)
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#define OCOTP_CTRL_TOG_ADDR_SHIFT (0U)
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#define OCOTP_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_CTRL_TOG_ADDR_MASK)
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#define OCOTP_CTRL_TOG_BUSY_MASK (0x100U)
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#define OCOTP_CTRL_TOG_BUSY_SHIFT (8U)
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#define OCOTP_CTRL_TOG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_BUSY_SHIFT)) & OCOTP_CTRL_TOG_BUSY_MASK)
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#define OCOTP_CTRL_TOG_ERROR_MASK (0x200U)
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#define OCOTP_CTRL_TOG_ERROR_SHIFT (9U)
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#define OCOTP_CTRL_TOG_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ERROR_SHIFT)) & OCOTP_CTRL_TOG_ERROR_MASK)
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#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK (0x400U)
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#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT (10U)
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#define OCOTP_CTRL_TOG_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK)
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#define OCOTP_CTRL_TOG_WR_UNLOCK_MASK (0xFFFF0000U)
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#define OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT (16U)
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#define OCOTP_CTRL_TOG_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_TOG_WR_UNLOCK_MASK)
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/*! @} */
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/*! @name TIMING - OTP Controller Timing Register */
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/*! @{ */
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#define OCOTP_TIMING_STROBE_PROG_MASK (0xFFFU)
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#define OCOTP_TIMING_STROBE_PROG_SHIFT (0U)
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#define OCOTP_TIMING_STROBE_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_PROG_SHIFT)) & OCOTP_TIMING_STROBE_PROG_MASK)
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#define OCOTP_TIMING_RELAX_MASK (0xF000U)
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#define OCOTP_TIMING_RELAX_SHIFT (12U)
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#define OCOTP_TIMING_RELAX(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_RELAX_SHIFT)) & OCOTP_TIMING_RELAX_MASK)
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#define OCOTP_TIMING_STROBE_READ_MASK (0x3F0000U)
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#define OCOTP_TIMING_STROBE_READ_SHIFT (16U)
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#define OCOTP_TIMING_STROBE_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_READ_SHIFT)) & OCOTP_TIMING_STROBE_READ_MASK)
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#define OCOTP_TIMING_WAIT_MASK (0xFC00000U)
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#define OCOTP_TIMING_WAIT_SHIFT (22U)
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#define OCOTP_TIMING_WAIT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_WAIT_SHIFT)) & OCOTP_TIMING_WAIT_MASK)
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/*! @} */
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/*! @name DATA - OTP Controller Write Data Register */
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/*! @{ */
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#define OCOTP_DATA_DATA_MASK (0xFFFFFFFFU)
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#define OCOTP_DATA_DATA_SHIFT (0U)
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#define OCOTP_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_DATA_DATA_SHIFT)) & OCOTP_DATA_DATA_MASK)
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/*! @} */
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/*! @name READ_CTRL - OTP Controller Write Data Register */
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/*! @{ */
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#define OCOTP_READ_CTRL_READ_FUSE_MASK (0x1U)
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#define OCOTP_READ_CTRL_READ_FUSE_SHIFT (0U)
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#define OCOTP_READ_CTRL_READ_FUSE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_MASK)
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/*! @} */
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/*! @name READ_FUSE_DATA - OTP Controller Read Data Register */
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/*! @{ */
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#define OCOTP_READ_FUSE_DATA_DATA_MASK (0xFFFFFFFFU)
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#define OCOTP_READ_FUSE_DATA_DATA_SHIFT (0U)
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#define OCOTP_READ_FUSE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_READ_FUSE_DATA_DATA_MASK)
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/*! @} */
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/*! @name SW_STICKY - Sticky bit Register */
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/*! @{ */
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#define OCOTP_SW_STICKY_BLOCK_DTCP_KEY_MASK (0x1U)
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#define OCOTP_SW_STICKY_BLOCK_DTCP_KEY_SHIFT (0U)
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#define OCOTP_SW_STICKY_BLOCK_DTCP_KEY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_BLOCK_DTCP_KEY_SHIFT)) & OCOTP_SW_STICKY_BLOCK_DTCP_KEY_MASK)
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#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK (0x2U)
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#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT (1U)
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#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT)) & OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK)
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#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK (0x4U)
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#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT (2U)
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#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT)) & OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK)
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#define OCOTP_SW_STICKY_BLOCK_ROM_PART_MASK (0x8U)
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#define OCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT (3U)
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#define OCOTP_SW_STICKY_BLOCK_ROM_PART(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT)) & OCOTP_SW_STICKY_BLOCK_ROM_PART_MASK)
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#define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK (0x10U)
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#define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT (4U)
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#define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT)) & OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK)
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/*! @} */
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/*! @name SCS - Software Controllable Signals Register */
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/*! @{ */
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#define OCOTP_SCS_HAB_JDE_MASK (0x1U)
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#define OCOTP_SCS_HAB_JDE_SHIFT (0U)
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#define OCOTP_SCS_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_HAB_JDE_SHIFT)) & OCOTP_SCS_HAB_JDE_MASK)
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#define OCOTP_SCS_SPARE_MASK (0x7FFFFFFEU)
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#define OCOTP_SCS_SPARE_SHIFT (1U)
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#define OCOTP_SCS_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SPARE_SHIFT)) & OCOTP_SCS_SPARE_MASK)
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#define OCOTP_SCS_LOCK_MASK (0x80000000U)
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#define OCOTP_SCS_LOCK_SHIFT (31U)
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#define OCOTP_SCS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_LOCK_SHIFT)) & OCOTP_SCS_LOCK_MASK)
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/*! @} */
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/*! @name SCS_SET - Software Controllable Signals Register */
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/*! @{ */
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#define OCOTP_SCS_SET_HAB_JDE_MASK (0x1U)
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#define OCOTP_SCS_SET_HAB_JDE_SHIFT (0U)
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#define OCOTP_SCS_SET_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_HAB_JDE_SHIFT)) & OCOTP_SCS_SET_HAB_JDE_MASK)
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#define OCOTP_SCS_SET_SPARE_MASK (0x7FFFFFFEU)
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#define OCOTP_SCS_SET_SPARE_SHIFT (1U)
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#define OCOTP_SCS_SET_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_SPARE_SHIFT)) & OCOTP_SCS_SET_SPARE_MASK)
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#define OCOTP_SCS_SET_LOCK_MASK (0x80000000U)
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#define OCOTP_SCS_SET_LOCK_SHIFT (31U)
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#define OCOTP_SCS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_LOCK_SHIFT)) & OCOTP_SCS_SET_LOCK_MASK)
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/*! @} */
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/*! @name SCS_CLR - Software Controllable Signals Register */
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/*! @{ */
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#define OCOTP_SCS_CLR_HAB_JDE_MASK (0x1U)
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#define OCOTP_SCS_CLR_HAB_JDE_SHIFT (0U)
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#define OCOTP_SCS_CLR_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_HAB_JDE_SHIFT)) & OCOTP_SCS_CLR_HAB_JDE_MASK)
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#define OCOTP_SCS_CLR_SPARE_MASK (0x7FFFFFFEU)
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#define OCOTP_SCS_CLR_SPARE_SHIFT (1U)
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#define OCOTP_SCS_CLR_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_SPARE_SHIFT)) & OCOTP_SCS_CLR_SPARE_MASK)
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#define OCOTP_SCS_CLR_LOCK_MASK (0x80000000U)
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#define OCOTP_SCS_CLR_LOCK_SHIFT (31U)
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#define OCOTP_SCS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_LOCK_SHIFT)) & OCOTP_SCS_CLR_LOCK_MASK)
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/*! @} */
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/*! @name SCS_TOG - Software Controllable Signals Register */
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/*! @{ */
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#define OCOTP_SCS_TOG_HAB_JDE_MASK (0x1U)
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#define OCOTP_SCS_TOG_HAB_JDE_SHIFT (0U)
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#define OCOTP_SCS_TOG_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_HAB_JDE_SHIFT)) & OCOTP_SCS_TOG_HAB_JDE_MASK)
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#define OCOTP_SCS_TOG_SPARE_MASK (0x7FFFFFFEU)
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#define OCOTP_SCS_TOG_SPARE_SHIFT (1U)
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#define OCOTP_SCS_TOG_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_SPARE_SHIFT)) & OCOTP_SCS_TOG_SPARE_MASK)
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#define OCOTP_SCS_TOG_LOCK_MASK (0x80000000U)
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#define OCOTP_SCS_TOG_LOCK_SHIFT (31U)
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#define OCOTP_SCS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_LOCK_SHIFT)) & OCOTP_SCS_TOG_LOCK_MASK)
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/*! @} */
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/*! @name VERSION - OTP Controller Version Register */
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/*! @{ */
|
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#define OCOTP_VERSION_STEP_MASK (0xFFFFU)
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#define OCOTP_VERSION_STEP_SHIFT (0U)
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#define OCOTP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_STEP_SHIFT)) & OCOTP_VERSION_STEP_MASK)
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#define OCOTP_VERSION_MINOR_MASK (0xFF0000U)
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#define OCOTP_VERSION_MINOR_SHIFT (16U)
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#define OCOTP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MINOR_SHIFT)) & OCOTP_VERSION_MINOR_MASK)
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#define OCOTP_VERSION_MAJOR_MASK (0xFF000000U)
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#define OCOTP_VERSION_MAJOR_SHIFT (24U)
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#define OCOTP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_VERSION_MAJOR_MASK)
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/*! @} */
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/*! @name TIMING2 - OTP Controller Timing Register 2 */
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/*! @{ */
|
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#define OCOTP_TIMING2_RELAX_PROG_MASK (0xFFFU)
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#define OCOTP_TIMING2_RELAX_PROG_SHIFT (0U)
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#define OCOTP_TIMING2_RELAX_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_PROG_SHIFT)) & OCOTP_TIMING2_RELAX_PROG_MASK)
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#define OCOTP_TIMING2_RELAX_READ_MASK (0x3F0000U)
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#define OCOTP_TIMING2_RELAX_READ_SHIFT (16U)
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#define OCOTP_TIMING2_RELAX_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_READ_SHIFT)) & OCOTP_TIMING2_RELAX_READ_MASK)
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#define OCOTP_TIMING2_RELAX1_MASK (0x1FC00000U)
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#define OCOTP_TIMING2_RELAX1_SHIFT (22U)
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#define OCOTP_TIMING2_RELAX1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX1_SHIFT)) & OCOTP_TIMING2_RELAX1_MASK)
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/*! @} */
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/*! @name LOCK - Value of OTP Bank0 Word0 (Lock controls) */
|
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/*! @{ */
|
|
#define OCOTP_LOCK_TESTER_MASK (0x3U)
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#define OCOTP_LOCK_TESTER_SHIFT (0U)
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#define OCOTP_LOCK_TESTER(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_TESTER_SHIFT)) & OCOTP_LOCK_TESTER_MASK)
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#define OCOTP_LOCK_BOOT_CFG_MASK (0xCU)
|
|
#define OCOTP_LOCK_BOOT_CFG_SHIFT (2U)
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#define OCOTP_LOCK_BOOT_CFG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_BOOT_CFG_SHIFT)) & OCOTP_LOCK_BOOT_CFG_MASK)
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|
#define OCOTP_LOCK_MEM_TRIM_MASK (0x30U)
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|
#define OCOTP_LOCK_MEM_TRIM_SHIFT (4U)
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#define OCOTP_LOCK_MEM_TRIM(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MEM_TRIM_SHIFT)) & OCOTP_LOCK_MEM_TRIM_MASK)
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#define OCOTP_LOCK_SJC_RESP_MASK (0x40U)
|
|
#define OCOTP_LOCK_SJC_RESP_SHIFT (6U)
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|
#define OCOTP_LOCK_SJC_RESP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SJC_RESP_SHIFT)) & OCOTP_LOCK_SJC_RESP_MASK)
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#define OCOTP_LOCK_MAC_ADDR_MASK (0x300U)
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#define OCOTP_LOCK_MAC_ADDR_SHIFT (8U)
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#define OCOTP_LOCK_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MAC_ADDR_SHIFT)) & OCOTP_LOCK_MAC_ADDR_MASK)
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#define OCOTP_LOCK_GP1_MASK (0xC00U)
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|
#define OCOTP_LOCK_GP1_SHIFT (10U)
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|
#define OCOTP_LOCK_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP1_SHIFT)) & OCOTP_LOCK_GP1_MASK)
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|
#define OCOTP_LOCK_GP2_MASK (0x3000U)
|
|
#define OCOTP_LOCK_GP2_SHIFT (12U)
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|
#define OCOTP_LOCK_GP2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP2_SHIFT)) & OCOTP_LOCK_GP2_MASK)
|
|
#define OCOTP_LOCK_OTPMK_MSB_MASK (0x8000U)
|
|
#define OCOTP_LOCK_OTPMK_MSB_SHIFT (15U)
|
|
#define OCOTP_LOCK_OTPMK_MSB(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_MSB_SHIFT)) & OCOTP_LOCK_OTPMK_MSB_MASK)
|
|
#define OCOTP_LOCK_SW_GP1_MASK (0x10000U)
|
|
#define OCOTP_LOCK_SW_GP1_SHIFT (16U)
|
|
#define OCOTP_LOCK_SW_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP1_SHIFT)) & OCOTP_LOCK_SW_GP1_MASK)
|
|
#define OCOTP_LOCK_OTPMK_LSB_MASK (0x20000U)
|
|
#define OCOTP_LOCK_OTPMK_LSB_SHIFT (17U)
|
|
#define OCOTP_LOCK_OTPMK_LSB(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_LSB_SHIFT)) & OCOTP_LOCK_OTPMK_LSB_MASK)
|
|
#define OCOTP_LOCK_ANALOG_MASK (0xC0000U)
|
|
#define OCOTP_LOCK_ANALOG_SHIFT (18U)
|
|
#define OCOTP_LOCK_ANALOG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_ANALOG_SHIFT)) & OCOTP_LOCK_ANALOG_MASK)
|
|
#define OCOTP_LOCK_OTPMK_CRC_MASK (0x100000U)
|
|
#define OCOTP_LOCK_OTPMK_CRC_SHIFT (20U)
|
|
#define OCOTP_LOCK_OTPMK_CRC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_CRC_SHIFT)) & OCOTP_LOCK_OTPMK_CRC_MASK)
|
|
#define OCOTP_LOCK_SW_GP2_LOCK_MASK (0x200000U)
|
|
#define OCOTP_LOCK_SW_GP2_LOCK_SHIFT (21U)
|
|
#define OCOTP_LOCK_SW_GP2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP2_LOCK_SHIFT)) & OCOTP_LOCK_SW_GP2_LOCK_MASK)
|
|
#define OCOTP_LOCK_MISC_CONF_MASK (0x400000U)
|
|
#define OCOTP_LOCK_MISC_CONF_SHIFT (22U)
|
|
#define OCOTP_LOCK_MISC_CONF(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MISC_CONF_SHIFT)) & OCOTP_LOCK_MISC_CONF_MASK)
|
|
#define OCOTP_LOCK_SW_GP2_RLOCK_MASK (0x800000U)
|
|
#define OCOTP_LOCK_SW_GP2_RLOCK_SHIFT (23U)
|
|
#define OCOTP_LOCK_SW_GP2_RLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP2_RLOCK_SHIFT)) & OCOTP_LOCK_SW_GP2_RLOCK_MASK)
|
|
#define OCOTP_LOCK_GP3_MASK (0xC000000U)
|
|
#define OCOTP_LOCK_GP3_SHIFT (26U)
|
|
#define OCOTP_LOCK_GP3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP3_SHIFT)) & OCOTP_LOCK_GP3_MASK)
|
|
#define OCOTP_LOCK_FIELD_RETURN_MASK (0xF0000000U)
|
|
#define OCOTP_LOCK_FIELD_RETURN_SHIFT (28U)
|
|
#define OCOTP_LOCK_FIELD_RETURN(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_FIELD_RETURN_SHIFT)) & OCOTP_LOCK_FIELD_RETURN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CFG0 - Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.) */
|
|
/*! @{ */
|
|
#define OCOTP_CFG0_BITS_MASK (0xFFFFFFFFU)
|
|
#define OCOTP_CFG0_BITS_SHIFT (0U)
|
|
#define OCOTP_CFG0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG0_BITS_SHIFT)) & OCOTP_CFG0_BITS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CFG1 - Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.) */
|
|
/*! @{ */
|
|
#define OCOTP_CFG1_BITS_MASK (0xFFFFFFFFU)
|
|
#define OCOTP_CFG1_BITS_SHIFT (0U)
|
|
#define OCOTP_CFG1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG1_BITS_SHIFT)) & OCOTP_CFG1_BITS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CFG2 - Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.) */
|
|
/*! @{ */
|
|
#define OCOTP_CFG2_BITS_MASK (0xFFFFFFFFU)
|
|
#define OCOTP_CFG2_BITS_SHIFT (0U)
|
|
#define OCOTP_CFG2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG2_BITS_SHIFT)) & OCOTP_CFG2_BITS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CFG3 - Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.) */
|
|
/*! @{ */
|
|
#define OCOTP_CFG3_BITS_MASK (0xFFFFFFFFU)
|
|
#define OCOTP_CFG3_BITS_SHIFT (0U)
|
|
#define OCOTP_CFG3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG3_BITS_SHIFT)) & OCOTP_CFG3_BITS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CFG4 - Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.) */
|
|
/*! @{ */
|
|
#define OCOTP_CFG4_BITS_MASK (0xFFFFFFFFU)
|
|
#define OCOTP_CFG4_BITS_SHIFT (0U)
|
|
#define OCOTP_CFG4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG4_BITS_SHIFT)) & OCOTP_CFG4_BITS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CFG5 - Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.) */
|
|
/*! @{ */
|
|
#define OCOTP_CFG5_BITS_MASK (0xFFFFFFFFU)
|
|
#define OCOTP_CFG5_BITS_SHIFT (0U)
|
|
#define OCOTP_CFG5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG5_BITS_SHIFT)) & OCOTP_CFG5_BITS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CFG6 - Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.) */
|
|
/*! @{ */
|
|
#define OCOTP_CFG6_BITS_MASK (0xFFFFFFFFU)
|
|
#define OCOTP_CFG6_BITS_SHIFT (0U)
|
|
#define OCOTP_CFG6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG6_BITS_SHIFT)) & OCOTP_CFG6_BITS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MEM0 - Value of OTP Bank1 Word0 (Memory Related Info.) */
|
|
/*! @{ */
|
|
#define OCOTP_MEM0_BITS_MASK (0xFFFFFFFFU)
|
|
#define OCOTP_MEM0_BITS_SHIFT (0U)
|
|
#define OCOTP_MEM0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM0_BITS_SHIFT)) & OCOTP_MEM0_BITS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MEM1 - Value of OTP Bank1 Word1 (Memory Related Info.) */
|
|
/*! @{ */
|
|
#define OCOTP_MEM1_BITS_MASK (0xFFFFFFFFU)
|
|
#define OCOTP_MEM1_BITS_SHIFT (0U)
|
|
#define OCOTP_MEM1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM1_BITS_SHIFT)) & OCOTP_MEM1_BITS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MEM2 - Value of OTP Bank1 Word2 (Memory Related Info.) */
|
|
/*! @{ */
|
|
#define OCOTP_MEM2_BITS_MASK (0xFFFFFFFFU)
|
|
#define OCOTP_MEM2_BITS_SHIFT (0U)
|
|
#define OCOTP_MEM2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM2_BITS_SHIFT)) & OCOTP_MEM2_BITS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MEM3 - Value of OTP Bank1 Word3 (Memory Related Info.) */
|
|
/*! @{ */
|
|
#define OCOTP_MEM3_BITS_MASK (0xFFFFFFFFU)
|
|
#define OCOTP_MEM3_BITS_SHIFT (0U)
|
|
#define OCOTP_MEM3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM3_BITS_SHIFT)) & OCOTP_MEM3_BITS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MEM4 - Value of OTP Bank1 Word4 (Memory Related Info.) */
|
|
/*! @{ */
|
|
#define OCOTP_MEM4_BITS_MASK (0xFFFFFFFFU)
|
|
#define OCOTP_MEM4_BITS_SHIFT (0U)
|
|
#define OCOTP_MEM4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM4_BITS_SHIFT)) & OCOTP_MEM4_BITS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ANA0 - Value of OTP Bank1 Word5 (Analog Info.) */
|
|
/*! @{ */
|
|
#define OCOTP_ANA0_BITS_MASK (0xFFFFFFFFU)
|
|
#define OCOTP_ANA0_BITS_SHIFT (0U)
|
|
#define OCOTP_ANA0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA0_BITS_SHIFT)) & OCOTP_ANA0_BITS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ANA1 - Value of OTP Bank1 Word6 (Analog Info.) */
|
|
/*! @{ */
|
|
#define OCOTP_ANA1_BITS_MASK (0xFFFFFFFFU)
|
|
#define OCOTP_ANA1_BITS_SHIFT (0U)
|
|
#define OCOTP_ANA1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA1_BITS_SHIFT)) & OCOTP_ANA1_BITS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ANA2 - Value of OTP Bank1 Word7 (Analog Info.) */
|
|
/*! @{ */
|
|
#define OCOTP_ANA2_BITS_MASK (0xFFFFFFFFU)
|
|
#define OCOTP_ANA2_BITS_SHIFT (0U)
|
|
#define OCOTP_ANA2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA2_BITS_SHIFT)) & OCOTP_ANA2_BITS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SRK0 - Shadow Register for OTP Bank3 Word0 (SRK Hash) */
|
|
/*! @{ */
|
|
#define OCOTP_SRK0_BITS_MASK (0xFFFFFFFFU)
|
|
#define OCOTP_SRK0_BITS_SHIFT (0U)
|
|
#define OCOTP_SRK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK0_BITS_SHIFT)) & OCOTP_SRK0_BITS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SRK1 - Shadow Register for OTP Bank3 Word1 (SRK Hash) */
|
|
/*! @{ */
|
|
#define OCOTP_SRK1_BITS_MASK (0xFFFFFFFFU)
|
|
#define OCOTP_SRK1_BITS_SHIFT (0U)
|
|
#define OCOTP_SRK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK1_BITS_SHIFT)) & OCOTP_SRK1_BITS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SRK2 - Shadow Register for OTP Bank3 Word2 (SRK Hash) */
|
|
/*! @{ */
|
|
#define OCOTP_SRK2_BITS_MASK (0xFFFFFFFFU)
|
|
#define OCOTP_SRK2_BITS_SHIFT (0U)
|
|
#define OCOTP_SRK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK2_BITS_SHIFT)) & OCOTP_SRK2_BITS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SRK3 - Shadow Register for OTP Bank3 Word3 (SRK Hash) */
|
|
/*! @{ */
|
|
#define OCOTP_SRK3_BITS_MASK (0xFFFFFFFFU)
|
|
#define OCOTP_SRK3_BITS_SHIFT (0U)
|
|
#define OCOTP_SRK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK3_BITS_SHIFT)) & OCOTP_SRK3_BITS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SRK4 - Shadow Register for OTP Bank3 Word4 (SRK Hash) */
|
|
/*! @{ */
|
|
#define OCOTP_SRK4_BITS_MASK (0xFFFFFFFFU)
|
|
#define OCOTP_SRK4_BITS_SHIFT (0U)
|
|
#define OCOTP_SRK4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK4_BITS_SHIFT)) & OCOTP_SRK4_BITS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SRK5 - Shadow Register for OTP Bank3 Word5 (SRK Hash) */
|
|
/*! @{ */
|
|
#define OCOTP_SRK5_BITS_MASK (0xFFFFFFFFU)
|
|
#define OCOTP_SRK5_BITS_SHIFT (0U)
|
|
#define OCOTP_SRK5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK5_BITS_SHIFT)) & OCOTP_SRK5_BITS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SRK6 - Shadow Register for OTP Bank3 Word6 (SRK Hash) */
|
|
/*! @{ */
|
|
#define OCOTP_SRK6_BITS_MASK (0xFFFFFFFFU)
|
|
#define OCOTP_SRK6_BITS_SHIFT (0U)
|
|
#define OCOTP_SRK6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK6_BITS_SHIFT)) & OCOTP_SRK6_BITS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SRK7 - Shadow Register for OTP Bank3 Word7 (SRK Hash) */
|
|
/*! @{ */
|
|
#define OCOTP_SRK7_BITS_MASK (0xFFFFFFFFU)
|
|
#define OCOTP_SRK7_BITS_SHIFT (0U)
|
|
#define OCOTP_SRK7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK7_BITS_SHIFT)) & OCOTP_SRK7_BITS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SJC_RESP0 - Value of OTP Bank4 Word0 (Secure JTAG Response Field) */
|
|
/*! @{ */
|
|
#define OCOTP_SJC_RESP0_BITS_MASK (0xFFFFFFFFU)
|
|
#define OCOTP_SJC_RESP0_BITS_SHIFT (0U)
|
|
#define OCOTP_SJC_RESP0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP0_BITS_SHIFT)) & OCOTP_SJC_RESP0_BITS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SJC_RESP1 - Value of OTP Bank4 Word1 (Secure JTAG Response Field) */
|
|
/*! @{ */
|
|
#define OCOTP_SJC_RESP1_BITS_MASK (0xFFFFFFFFU)
|
|
#define OCOTP_SJC_RESP1_BITS_SHIFT (0U)
|
|
#define OCOTP_SJC_RESP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP1_BITS_SHIFT)) & OCOTP_SJC_RESP1_BITS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MAC0 - Value of OTP Bank4 Word2 (MAC Address) */
|
|
/*! @{ */
|
|
#define OCOTP_MAC0_BITS_MASK (0xFFFFFFFFU)
|
|
#define OCOTP_MAC0_BITS_SHIFT (0U)
|
|
#define OCOTP_MAC0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC0_BITS_SHIFT)) & OCOTP_MAC0_BITS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MAC1 - Value of OTP Bank4 Word3 (MAC Address) */
|
|
/*! @{ */
|
|
#define OCOTP_MAC1_BITS_MASK (0xFFFFFFFFU)
|
|
#define OCOTP_MAC1_BITS_SHIFT (0U)
|
|
#define OCOTP_MAC1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC1_BITS_SHIFT)) & OCOTP_MAC1_BITS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GP3 - Value of OTP Bank4 Word4 (MAC Address) */
|
|
/*! @{ */
|
|
#define OCOTP_GP3_BITS_MASK (0xFFFFFFFFU)
|
|
#define OCOTP_GP3_BITS_SHIFT (0U)
|
|
#define OCOTP_GP3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP3_BITS_SHIFT)) & OCOTP_GP3_BITS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GP1 - Value of OTP Bank4 Word6 (General Purpose Customer Defined Info) */
|
|
/*! @{ */
|
|
#define OCOTP_GP1_BITS_MASK (0xFFFFFFFFU)
|
|
#define OCOTP_GP1_BITS_SHIFT (0U)
|
|
#define OCOTP_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP1_BITS_SHIFT)) & OCOTP_GP1_BITS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GP2 - Value of OTP Bank4 Word7 (General Purpose Customer Defined Info) */
|
|
/*! @{ */
|
|
#define OCOTP_GP2_BITS_MASK (0xFFFFFFFFU)
|
|
#define OCOTP_GP2_BITS_SHIFT (0U)
|
|
#define OCOTP_GP2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP2_BITS_SHIFT)) & OCOTP_GP2_BITS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SW_GP1 - Value of OTP Bank5 Word0 (SW GP1) */
|
|
/*! @{ */
|
|
#define OCOTP_SW_GP1_BITS_MASK (0xFFFFFFFFU)
|
|
#define OCOTP_SW_GP1_BITS_SHIFT (0U)
|
|
#define OCOTP_SW_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP1_BITS_SHIFT)) & OCOTP_SW_GP1_BITS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SW_GP20 - Value of OTP Bank5 Word1 (SW GP2) */
|
|
/*! @{ */
|
|
#define OCOTP_SW_GP20_BITS_MASK (0xFFFFFFFFU)
|
|
#define OCOTP_SW_GP20_BITS_SHIFT (0U)
|
|
#define OCOTP_SW_GP20_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP20_BITS_SHIFT)) & OCOTP_SW_GP20_BITS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SW_GP21 - Value of OTP Bank5 Word2 (SW GP2) */
|
|
/*! @{ */
|
|
#define OCOTP_SW_GP21_BITS_MASK (0xFFFFFFFFU)
|
|
#define OCOTP_SW_GP21_BITS_SHIFT (0U)
|
|
#define OCOTP_SW_GP21_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP21_BITS_SHIFT)) & OCOTP_SW_GP21_BITS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SW_GP22 - Value of OTP Bank5 Word3 (SW GP2) */
|
|
/*! @{ */
|
|
#define OCOTP_SW_GP22_BITS_MASK (0xFFFFFFFFU)
|
|
#define OCOTP_SW_GP22_BITS_SHIFT (0U)
|
|
#define OCOTP_SW_GP22_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP22_BITS_SHIFT)) & OCOTP_SW_GP22_BITS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SW_GP23 - Value of OTP Bank5 Word4 (SW GP2) */
|
|
/*! @{ */
|
|
#define OCOTP_SW_GP23_BITS_MASK (0xFFFFFFFFU)
|
|
#define OCOTP_SW_GP23_BITS_SHIFT (0U)
|
|
#define OCOTP_SW_GP23_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP23_BITS_SHIFT)) & OCOTP_SW_GP23_BITS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MISC_CONF0 - Value of OTP Bank5 Word5 (Misc Conf) */
|
|
/*! @{ */
|
|
#define OCOTP_MISC_CONF0_BITS_MASK (0xFFFFFFFFU)
|
|
#define OCOTP_MISC_CONF0_BITS_SHIFT (0U)
|
|
#define OCOTP_MISC_CONF0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF0_BITS_SHIFT)) & OCOTP_MISC_CONF0_BITS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MISC_CONF1 - Value of OTP Bank5 Word6 (Misc Conf) */
|
|
/*! @{ */
|
|
#define OCOTP_MISC_CONF1_BITS_MASK (0xFFFFFFFFU)
|
|
#define OCOTP_MISC_CONF1_BITS_SHIFT (0U)
|
|
#define OCOTP_MISC_CONF1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF1_BITS_SHIFT)) & OCOTP_MISC_CONF1_BITS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SRK_REVOKE - Value of OTP Bank5 Word7 (SRK Revoke) */
|
|
/*! @{ */
|
|
#define OCOTP_SRK_REVOKE_BITS_MASK (0xFFFFFFFFU)
|
|
#define OCOTP_SRK_REVOKE_BITS_SHIFT (0U)
|
|
#define OCOTP_SRK_REVOKE_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK_REVOKE_BITS_SHIFT)) & OCOTP_SRK_REVOKE_BITS_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group OCOTP_Register_Masks */
|
|
|
|
|
|
/* OCOTP - Peripheral instance base addresses */
|
|
/** Peripheral OCOTP base address */
|
|
#define OCOTP_BASE (0x401F4000u)
|
|
/** Peripheral OCOTP base pointer */
|
|
#define OCOTP ((OCOTP_Type *)OCOTP_BASE)
|
|
/** Array initializer of OCOTP peripheral base addresses */
|
|
#define OCOTP_BASE_ADDRS { OCOTP_BASE }
|
|
/** Array initializer of OCOTP peripheral base pointers */
|
|
#define OCOTP_BASE_PTRS { OCOTP }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group OCOTP_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- PGC Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup PGC_Peripheral_Access_Layer PGC Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** PGC - Register Layout Typedef */
|
|
typedef struct {
|
|
uint8_t RESERVED_0[544];
|
|
__IO uint32_t MEGA_CTRL; /**< PGC Mega Control Register, offset: 0x220 */
|
|
__IO uint32_t MEGA_PUPSCR; /**< PGC Mega Power Up Sequence Control Register, offset: 0x224 */
|
|
__IO uint32_t MEGA_PDNSCR; /**< PGC Mega Pull Down Sequence Control Register, offset: 0x228 */
|
|
__IO uint32_t MEGA_SR; /**< PGC Mega Power Gating Controller Status Register, offset: 0x22C */
|
|
uint8_t RESERVED_1[112];
|
|
__IO uint32_t CPU_CTRL; /**< PGC CPU Control Register, offset: 0x2A0 */
|
|
__IO uint32_t CPU_PUPSCR; /**< PGC CPU Power Up Sequence Control Register, offset: 0x2A4 */
|
|
__IO uint32_t CPU_PDNSCR; /**< PGC CPU Pull Down Sequence Control Register, offset: 0x2A8 */
|
|
__IO uint32_t CPU_SR; /**< PGC CPU Power Gating Controller Status Register, offset: 0x2AC */
|
|
} PGC_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- PGC Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup PGC_Register_Masks PGC Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name MEGA_CTRL - PGC Mega Control Register */
|
|
/*! @{ */
|
|
#define PGC_MEGA_CTRL_PCR_MASK (0x1U)
|
|
#define PGC_MEGA_CTRL_PCR_SHIFT (0U)
|
|
/*! PCR
|
|
* 0b0..Do not switch off power even if pdn_req is asserted.
|
|
* 0b1..Switch off power when pdn_req is asserted.
|
|
*/
|
|
#define PGC_MEGA_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_CTRL_PCR_SHIFT)) & PGC_MEGA_CTRL_PCR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MEGA_PUPSCR - PGC Mega Power Up Sequence Control Register */
|
|
/*! @{ */
|
|
#define PGC_MEGA_PUPSCR_SW_MASK (0x3FU)
|
|
#define PGC_MEGA_PUPSCR_SW_SHIFT (0U)
|
|
#define PGC_MEGA_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW_SHIFT)) & PGC_MEGA_PUPSCR_SW_MASK)
|
|
#define PGC_MEGA_PUPSCR_SW2ISO_MASK (0x3F00U)
|
|
#define PGC_MEGA_PUPSCR_SW2ISO_SHIFT (8U)
|
|
#define PGC_MEGA_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW2ISO_SHIFT)) & PGC_MEGA_PUPSCR_SW2ISO_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MEGA_PDNSCR - PGC Mega Pull Down Sequence Control Register */
|
|
/*! @{ */
|
|
#define PGC_MEGA_PDNSCR_ISO_MASK (0x3FU)
|
|
#define PGC_MEGA_PDNSCR_ISO_SHIFT (0U)
|
|
#define PGC_MEGA_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO_SHIFT)) & PGC_MEGA_PDNSCR_ISO_MASK)
|
|
#define PGC_MEGA_PDNSCR_ISO2SW_MASK (0x3F00U)
|
|
#define PGC_MEGA_PDNSCR_ISO2SW_SHIFT (8U)
|
|
#define PGC_MEGA_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO2SW_SHIFT)) & PGC_MEGA_PDNSCR_ISO2SW_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MEGA_SR - PGC Mega Power Gating Controller Status Register */
|
|
/*! @{ */
|
|
#define PGC_MEGA_SR_PSR_MASK (0x1U)
|
|
#define PGC_MEGA_SR_PSR_SHIFT (0U)
|
|
/*! PSR
|
|
* 0b0..The target subsystem was not powered down for the previous power-down request.
|
|
* 0b1..The target subsystem was powered down for the previous power-down request.
|
|
*/
|
|
#define PGC_MEGA_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_SR_PSR_SHIFT)) & PGC_MEGA_SR_PSR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CPU_CTRL - PGC CPU Control Register */
|
|
/*! @{ */
|
|
#define PGC_CPU_CTRL_PCR_MASK (0x1U)
|
|
#define PGC_CPU_CTRL_PCR_SHIFT (0U)
|
|
/*! PCR
|
|
* 0b0..Do not switch off power even if pdn_req is asserted.
|
|
* 0b1..Switch off power when pdn_req is asserted.
|
|
*/
|
|
#define PGC_CPU_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_CTRL_PCR_SHIFT)) & PGC_CPU_CTRL_PCR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CPU_PUPSCR - PGC CPU Power Up Sequence Control Register */
|
|
/*! @{ */
|
|
#define PGC_CPU_PUPSCR_SW_MASK (0x3FU)
|
|
#define PGC_CPU_PUPSCR_SW_SHIFT (0U)
|
|
#define PGC_CPU_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW_SHIFT)) & PGC_CPU_PUPSCR_SW_MASK)
|
|
#define PGC_CPU_PUPSCR_SW2ISO_MASK (0x3F00U)
|
|
#define PGC_CPU_PUPSCR_SW2ISO_SHIFT (8U)
|
|
#define PGC_CPU_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW2ISO_SHIFT)) & PGC_CPU_PUPSCR_SW2ISO_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CPU_PDNSCR - PGC CPU Pull Down Sequence Control Register */
|
|
/*! @{ */
|
|
#define PGC_CPU_PDNSCR_ISO_MASK (0x3FU)
|
|
#define PGC_CPU_PDNSCR_ISO_SHIFT (0U)
|
|
#define PGC_CPU_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO_SHIFT)) & PGC_CPU_PDNSCR_ISO_MASK)
|
|
#define PGC_CPU_PDNSCR_ISO2SW_MASK (0x3F00U)
|
|
#define PGC_CPU_PDNSCR_ISO2SW_SHIFT (8U)
|
|
#define PGC_CPU_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO2SW_SHIFT)) & PGC_CPU_PDNSCR_ISO2SW_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CPU_SR - PGC CPU Power Gating Controller Status Register */
|
|
/*! @{ */
|
|
#define PGC_CPU_SR_PSR_MASK (0x1U)
|
|
#define PGC_CPU_SR_PSR_SHIFT (0U)
|
|
/*! PSR
|
|
* 0b0..The target subsystem was not powered down for the previous power-down request.
|
|
* 0b1..The target subsystem was powered down for the previous power-down request.
|
|
*/
|
|
#define PGC_CPU_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_SR_PSR_SHIFT)) & PGC_CPU_SR_PSR_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group PGC_Register_Masks */
|
|
|
|
|
|
/* PGC - Peripheral instance base addresses */
|
|
/** Peripheral PGC base address */
|
|
#define PGC_BASE (0x400F4000u)
|
|
/** Peripheral PGC base pointer */
|
|
#define PGC ((PGC_Type *)PGC_BASE)
|
|
/** Array initializer of PGC peripheral base addresses */
|
|
#define PGC_BASE_ADDRS { PGC_BASE }
|
|
/** Array initializer of PGC peripheral base pointers */
|
|
#define PGC_BASE_PTRS { PGC }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group PGC_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- PIT Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** PIT - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
|
|
uint8_t RESERVED_0[220];
|
|
__I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
|
|
__I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
|
|
uint8_t RESERVED_1[24];
|
|
struct { /* offset: 0x100, array step: 0x10 */
|
|
__IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
|
|
__I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
|
|
__IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
|
|
__IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
|
|
} CHANNEL[4];
|
|
} PIT_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- PIT Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup PIT_Register_Masks PIT Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name MCR - PIT Module Control Register */
|
|
/*! @{ */
|
|
#define PIT_MCR_FRZ_MASK (0x1U)
|
|
#define PIT_MCR_FRZ_SHIFT (0U)
|
|
/*! FRZ - Freeze
|
|
* 0b0..Timers continue to run in Debug mode.
|
|
* 0b1..Timers are stopped in Debug mode.
|
|
*/
|
|
#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
|
|
#define PIT_MCR_MDIS_MASK (0x2U)
|
|
#define PIT_MCR_MDIS_SHIFT (1U)
|
|
/*! MDIS - Module Disable - (PIT section)
|
|
* 0b0..Clock for standard PIT timers is enabled.
|
|
* 0b1..Clock for standard PIT timers is disabled.
|
|
*/
|
|
#define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name LTMR64H - PIT Upper Lifetime Timer Register */
|
|
/*! @{ */
|
|
#define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU)
|
|
#define PIT_LTMR64H_LTH_SHIFT (0U)
|
|
#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name LTMR64L - PIT Lower Lifetime Timer Register */
|
|
/*! @{ */
|
|
#define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU)
|
|
#define PIT_LTMR64L_LTL_SHIFT (0U)
|
|
#define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name LDVAL - Timer Load Value Register */
|
|
/*! @{ */
|
|
#define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)
|
|
#define PIT_LDVAL_TSV_SHIFT (0U)
|
|
#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PIT_LDVAL */
|
|
#define PIT_LDVAL_COUNT (4U)
|
|
|
|
/*! @name CVAL - Current Timer Value Register */
|
|
/*! @{ */
|
|
#define PIT_CVAL_TVL_MASK (0xFFFFFFFFU)
|
|
#define PIT_CVAL_TVL_SHIFT (0U)
|
|
#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PIT_CVAL */
|
|
#define PIT_CVAL_COUNT (4U)
|
|
|
|
/*! @name TCTRL - Timer Control Register */
|
|
/*! @{ */
|
|
#define PIT_TCTRL_TEN_MASK (0x1U)
|
|
#define PIT_TCTRL_TEN_SHIFT (0U)
|
|
/*! TEN - Timer Enable
|
|
* 0b0..Timer n is disabled.
|
|
* 0b1..Timer n is enabled.
|
|
*/
|
|
#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
|
|
#define PIT_TCTRL_TIE_MASK (0x2U)
|
|
#define PIT_TCTRL_TIE_SHIFT (1U)
|
|
/*! TIE - Timer Interrupt Enable
|
|
* 0b0..Interrupt requests from Timer n are disabled.
|
|
* 0b1..Interrupt will be requested whenever TIF is set.
|
|
*/
|
|
#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
|
|
#define PIT_TCTRL_CHN_MASK (0x4U)
|
|
#define PIT_TCTRL_CHN_SHIFT (2U)
|
|
/*! CHN - Chain Mode
|
|
* 0b0..Timer is not chained.
|
|
* 0b1..Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.
|
|
*/
|
|
#define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PIT_TCTRL */
|
|
#define PIT_TCTRL_COUNT (4U)
|
|
|
|
/*! @name TFLG - Timer Flag Register */
|
|
/*! @{ */
|
|
#define PIT_TFLG_TIF_MASK (0x1U)
|
|
#define PIT_TFLG_TIF_SHIFT (0U)
|
|
/*! TIF - Timer Interrupt Flag
|
|
* 0b0..Timeout has not yet occurred.
|
|
* 0b1..Timeout has occurred.
|
|
*/
|
|
#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PIT_TFLG */
|
|
#define PIT_TFLG_COUNT (4U)
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group PIT_Register_Masks */
|
|
|
|
|
|
/* PIT - Peripheral instance base addresses */
|
|
/** Peripheral PIT base address */
|
|
#define PIT_BASE (0x40084000u)
|
|
/** Peripheral PIT base pointer */
|
|
#define PIT ((PIT_Type *)PIT_BASE)
|
|
/** Array initializer of PIT peripheral base addresses */
|
|
#define PIT_BASE_ADDRS { PIT_BASE }
|
|
/** Array initializer of PIT peripheral base pointers */
|
|
#define PIT_BASE_PTRS { PIT }
|
|
/** Interrupt vectors for the PIT peripheral type */
|
|
#define PIT_IRQS { { PIT_IRQn, PIT_IRQn, PIT_IRQn, PIT_IRQn } }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group PIT_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- PMU Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup PMU_Peripheral_Access_Layer PMU Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** PMU - Register Layout Typedef */
|
|
typedef struct {
|
|
uint8_t RESERVED_0[272];
|
|
__IO uint32_t REG_1P1; /**< Regulator 1P1 Register, offset: 0x110 */
|
|
__IO uint32_t REG_1P1_SET; /**< Regulator 1P1 Register, offset: 0x114 */
|
|
__IO uint32_t REG_1P1_CLR; /**< Regulator 1P1 Register, offset: 0x118 */
|
|
__IO uint32_t REG_1P1_TOG; /**< Regulator 1P1 Register, offset: 0x11C */
|
|
__IO uint32_t REG_3P0; /**< Regulator 3P0 Register, offset: 0x120 */
|
|
__IO uint32_t REG_3P0_SET; /**< Regulator 3P0 Register, offset: 0x124 */
|
|
__IO uint32_t REG_3P0_CLR; /**< Regulator 3P0 Register, offset: 0x128 */
|
|
__IO uint32_t REG_3P0_TOG; /**< Regulator 3P0 Register, offset: 0x12C */
|
|
__IO uint32_t REG_2P5; /**< Regulator 2P5 Register, offset: 0x130 */
|
|
__IO uint32_t REG_2P5_SET; /**< Regulator 2P5 Register, offset: 0x134 */
|
|
__IO uint32_t REG_2P5_CLR; /**< Regulator 2P5 Register, offset: 0x138 */
|
|
__IO uint32_t REG_2P5_TOG; /**< Regulator 2P5 Register, offset: 0x13C */
|
|
__IO uint32_t REG_CORE; /**< Digital Regulator Core Register, offset: 0x140 */
|
|
__IO uint32_t REG_CORE_SET; /**< Digital Regulator Core Register, offset: 0x144 */
|
|
__IO uint32_t REG_CORE_CLR; /**< Digital Regulator Core Register, offset: 0x148 */
|
|
__IO uint32_t REG_CORE_TOG; /**< Digital Regulator Core Register, offset: 0x14C */
|
|
__IO uint32_t MISC0; /**< Miscellaneous Register 0, offset: 0x150 */
|
|
__IO uint32_t MISC0_SET; /**< Miscellaneous Register 0, offset: 0x154 */
|
|
__IO uint32_t MISC0_CLR; /**< Miscellaneous Register 0, offset: 0x158 */
|
|
__IO uint32_t MISC0_TOG; /**< Miscellaneous Register 0, offset: 0x15C */
|
|
__IO uint32_t MISC1; /**< Miscellaneous Register 1, offset: 0x160 */
|
|
__IO uint32_t MISC1_SET; /**< Miscellaneous Register 1, offset: 0x164 */
|
|
__IO uint32_t MISC1_CLR; /**< Miscellaneous Register 1, offset: 0x168 */
|
|
__IO uint32_t MISC1_TOG; /**< Miscellaneous Register 1, offset: 0x16C */
|
|
__IO uint32_t MISC2; /**< Miscellaneous Control Register, offset: 0x170 */
|
|
__IO uint32_t MISC2_SET; /**< Miscellaneous Control Register, offset: 0x174 */
|
|
__IO uint32_t MISC2_CLR; /**< Miscellaneous Control Register, offset: 0x178 */
|
|
__IO uint32_t MISC2_TOG; /**< Miscellaneous Control Register, offset: 0x17C */
|
|
} PMU_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- PMU Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup PMU_Register_Masks PMU Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name REG_1P1 - Regulator 1P1 Register */
|
|
/*! @{ */
|
|
#define PMU_REG_1P1_ENABLE_LINREG_MASK (0x1U)
|
|
#define PMU_REG_1P1_ENABLE_LINREG_SHIFT (0U)
|
|
#define PMU_REG_1P1_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_LINREG_MASK)
|
|
#define PMU_REG_1P1_ENABLE_BO_MASK (0x2U)
|
|
#define PMU_REG_1P1_ENABLE_BO_SHIFT (1U)
|
|
#define PMU_REG_1P1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_BO_SHIFT)) & PMU_REG_1P1_ENABLE_BO_MASK)
|
|
#define PMU_REG_1P1_ENABLE_ILIMIT_MASK (0x4U)
|
|
#define PMU_REG_1P1_ENABLE_ILIMIT_SHIFT (2U)
|
|
#define PMU_REG_1P1_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_ENABLE_ILIMIT_MASK)
|
|
#define PMU_REG_1P1_ENABLE_PULLDOWN_MASK (0x8U)
|
|
#define PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT (3U)
|
|
#define PMU_REG_1P1_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_ENABLE_PULLDOWN_MASK)
|
|
#define PMU_REG_1P1_BO_OFFSET_MASK (0x70U)
|
|
#define PMU_REG_1P1_BO_OFFSET_SHIFT (4U)
|
|
#define PMU_REG_1P1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_OFFSET_SHIFT)) & PMU_REG_1P1_BO_OFFSET_MASK)
|
|
#define PMU_REG_1P1_OUTPUT_TRG_MASK (0x1F00U)
|
|
#define PMU_REG_1P1_OUTPUT_TRG_SHIFT (8U)
|
|
/*! OUTPUT_TRG
|
|
* 0b00100..0.8V
|
|
* 0b10000..1.1V
|
|
* 0b000x1..1.375V
|
|
*/
|
|
#define PMU_REG_1P1_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_OUTPUT_TRG_MASK)
|
|
#define PMU_REG_1P1_BO_VDD1P1_MASK (0x10000U)
|
|
#define PMU_REG_1P1_BO_VDD1P1_SHIFT (16U)
|
|
#define PMU_REG_1P1_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_BO_VDD1P1_MASK)
|
|
#define PMU_REG_1P1_OK_VDD1P1_MASK (0x20000U)
|
|
#define PMU_REG_1P1_OK_VDD1P1_SHIFT (17U)
|
|
#define PMU_REG_1P1_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_OK_VDD1P1_MASK)
|
|
#define PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK (0x40000U)
|
|
#define PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT (18U)
|
|
#define PMU_REG_1P1_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK)
|
|
#define PMU_REG_1P1_SELREF_WEAK_LINREG_MASK (0x80000U)
|
|
#define PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT (19U)
|
|
/*! SELREF_WEAK_LINREG
|
|
* 0b0..Weak-linreg output tracks low-power-bandgap voltage
|
|
* 0b1..Weak-linreg output tracks VDD_SOC_IN voltage
|
|
*/
|
|
#define PMU_REG_1P1_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SELREF_WEAK_LINREG_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name REG_1P1_SET - Regulator 1P1 Register */
|
|
/*! @{ */
|
|
#define PMU_REG_1P1_SET_ENABLE_LINREG_MASK (0x1U)
|
|
#define PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT (0U)
|
|
#define PMU_REG_1P1_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_LINREG_MASK)
|
|
#define PMU_REG_1P1_SET_ENABLE_BO_MASK (0x2U)
|
|
#define PMU_REG_1P1_SET_ENABLE_BO_SHIFT (1U)
|
|
#define PMU_REG_1P1_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_BO_SHIFT)) & PMU_REG_1P1_SET_ENABLE_BO_MASK)
|
|
#define PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK (0x4U)
|
|
#define PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT (2U)
|
|
#define PMU_REG_1P1_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK)
|
|
#define PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK (0x8U)
|
|
#define PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT (3U)
|
|
#define PMU_REG_1P1_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK)
|
|
#define PMU_REG_1P1_SET_BO_OFFSET_MASK (0x70U)
|
|
#define PMU_REG_1P1_SET_BO_OFFSET_SHIFT (4U)
|
|
#define PMU_REG_1P1_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_OFFSET_SHIFT)) & PMU_REG_1P1_SET_BO_OFFSET_MASK)
|
|
#define PMU_REG_1P1_SET_OUTPUT_TRG_MASK (0x1F00U)
|
|
#define PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT (8U)
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/*! OUTPUT_TRG
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* 0b00100..0.8V
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* 0b10000..1.1V
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* 0b000x1..1.375V
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*/
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#define PMU_REG_1P1_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_SET_OUTPUT_TRG_MASK)
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#define PMU_REG_1P1_SET_BO_VDD1P1_MASK (0x10000U)
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#define PMU_REG_1P1_SET_BO_VDD1P1_SHIFT (16U)
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#define PMU_REG_1P1_SET_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_BO_VDD1P1_MASK)
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#define PMU_REG_1P1_SET_OK_VDD1P1_MASK (0x20000U)
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#define PMU_REG_1P1_SET_OK_VDD1P1_SHIFT (17U)
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#define PMU_REG_1P1_SET_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_OK_VDD1P1_MASK)
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#define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK (0x40000U)
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#define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT (18U)
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#define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK)
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#define PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK (0x80000U)
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#define PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT (19U)
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/*! SELREF_WEAK_LINREG
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* 0b0..Weak-linreg output tracks low-power-bandgap voltage
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* 0b1..Weak-linreg output tracks VDD_SOC_IN voltage
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*/
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#define PMU_REG_1P1_SET_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK)
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/*! @} */
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/*! @name REG_1P1_CLR - Regulator 1P1 Register */
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/*! @{ */
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#define PMU_REG_1P1_CLR_ENABLE_LINREG_MASK (0x1U)
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#define PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT (0U)
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#define PMU_REG_1P1_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_LINREG_MASK)
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#define PMU_REG_1P1_CLR_ENABLE_BO_MASK (0x2U)
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#define PMU_REG_1P1_CLR_ENABLE_BO_SHIFT (1U)
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#define PMU_REG_1P1_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_BO_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_BO_MASK)
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#define PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK (0x4U)
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#define PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT (2U)
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#define PMU_REG_1P1_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK)
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#define PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK (0x8U)
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#define PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT (3U)
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#define PMU_REG_1P1_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK)
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#define PMU_REG_1P1_CLR_BO_OFFSET_MASK (0x70U)
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#define PMU_REG_1P1_CLR_BO_OFFSET_SHIFT (4U)
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#define PMU_REG_1P1_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_OFFSET_SHIFT)) & PMU_REG_1P1_CLR_BO_OFFSET_MASK)
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#define PMU_REG_1P1_CLR_OUTPUT_TRG_MASK (0x1F00U)
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#define PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT (8U)
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/*! OUTPUT_TRG
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* 0b00100..0.8V
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* 0b10000..1.1V
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* 0b000x1..1.375V
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*/
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#define PMU_REG_1P1_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_CLR_OUTPUT_TRG_MASK)
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#define PMU_REG_1P1_CLR_BO_VDD1P1_MASK (0x10000U)
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#define PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT (16U)
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#define PMU_REG_1P1_CLR_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_BO_VDD1P1_MASK)
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#define PMU_REG_1P1_CLR_OK_VDD1P1_MASK (0x20000U)
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#define PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT (17U)
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#define PMU_REG_1P1_CLR_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_OK_VDD1P1_MASK)
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#define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U)
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#define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT (18U)
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#define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK)
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#define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK (0x80000U)
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#define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT (19U)
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/*! SELREF_WEAK_LINREG
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* 0b0..Weak-linreg output tracks low-power-bandgap voltage
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* 0b1..Weak-linreg output tracks VDD_SOC_IN voltage
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*/
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#define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK)
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/*! @} */
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/*! @name REG_1P1_TOG - Regulator 1P1 Register */
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/*! @{ */
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#define PMU_REG_1P1_TOG_ENABLE_LINREG_MASK (0x1U)
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#define PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT (0U)
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#define PMU_REG_1P1_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_LINREG_MASK)
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#define PMU_REG_1P1_TOG_ENABLE_BO_MASK (0x2U)
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#define PMU_REG_1P1_TOG_ENABLE_BO_SHIFT (1U)
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#define PMU_REG_1P1_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_BO_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_BO_MASK)
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#define PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK (0x4U)
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#define PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT (2U)
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#define PMU_REG_1P1_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK)
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#define PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK (0x8U)
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#define PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT (3U)
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#define PMU_REG_1P1_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK)
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#define PMU_REG_1P1_TOG_BO_OFFSET_MASK (0x70U)
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#define PMU_REG_1P1_TOG_BO_OFFSET_SHIFT (4U)
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#define PMU_REG_1P1_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_OFFSET_SHIFT)) & PMU_REG_1P1_TOG_BO_OFFSET_MASK)
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#define PMU_REG_1P1_TOG_OUTPUT_TRG_MASK (0x1F00U)
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#define PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT (8U)
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/*! OUTPUT_TRG
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* 0b00100..0.8V
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* 0b10000..1.1V
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* 0b000x1..1.375V
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*/
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#define PMU_REG_1P1_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_TOG_OUTPUT_TRG_MASK)
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#define PMU_REG_1P1_TOG_BO_VDD1P1_MASK (0x10000U)
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#define PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT (16U)
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#define PMU_REG_1P1_TOG_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_BO_VDD1P1_MASK)
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#define PMU_REG_1P1_TOG_OK_VDD1P1_MASK (0x20000U)
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#define PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT (17U)
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#define PMU_REG_1P1_TOG_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_OK_VDD1P1_MASK)
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#define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U)
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#define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT (18U)
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#define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK)
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#define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK (0x80000U)
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#define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT (19U)
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/*! SELREF_WEAK_LINREG
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* 0b0..Weak-linreg output tracks low-power-bandgap voltage
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* 0b1..Weak-linreg output tracks VDD_SOC_IN voltage
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*/
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#define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK)
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/*! @} */
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/*! @name REG_3P0 - Regulator 3P0 Register */
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/*! @{ */
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#define PMU_REG_3P0_ENABLE_LINREG_MASK (0x1U)
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#define PMU_REG_3P0_ENABLE_LINREG_SHIFT (0U)
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#define PMU_REG_3P0_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK)
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#define PMU_REG_3P0_ENABLE_BO_MASK (0x2U)
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#define PMU_REG_3P0_ENABLE_BO_SHIFT (1U)
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#define PMU_REG_3P0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_BO_SHIFT)) & PMU_REG_3P0_ENABLE_BO_MASK)
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#define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U)
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#define PMU_REG_3P0_ENABLE_ILIMIT_SHIFT (2U)
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#define PMU_REG_3P0_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_ENABLE_ILIMIT_MASK)
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#define PMU_REG_3P0_BO_OFFSET_MASK (0x70U)
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#define PMU_REG_3P0_BO_OFFSET_SHIFT (4U)
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#define PMU_REG_3P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_OFFSET_SHIFT)) & PMU_REG_3P0_BO_OFFSET_MASK)
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#define PMU_REG_3P0_VBUS_SEL_MASK (0x80U)
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#define PMU_REG_3P0_VBUS_SEL_SHIFT (7U)
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/*! VBUS_SEL
|
|
* 0b1..Utilize VBUS OTG1 power
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* 0b0..Utilize VBUS OTG2 power
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|
*/
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#define PMU_REG_3P0_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_VBUS_SEL_SHIFT)) & PMU_REG_3P0_VBUS_SEL_MASK)
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#define PMU_REG_3P0_OUTPUT_TRG_MASK (0x1F00U)
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#define PMU_REG_3P0_OUTPUT_TRG_SHIFT (8U)
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/*! OUTPUT_TRG
|
|
* 0b00000..2.625V
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|
* 0b01111..3.000V
|
|
* 0b11111..3.400V
|
|
*/
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#define PMU_REG_3P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_OUTPUT_TRG_MASK)
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#define PMU_REG_3P0_BO_VDD3P0_MASK (0x10000U)
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#define PMU_REG_3P0_BO_VDD3P0_SHIFT (16U)
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#define PMU_REG_3P0_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_BO_VDD3P0_MASK)
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#define PMU_REG_3P0_OK_VDD3P0_MASK (0x20000U)
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#define PMU_REG_3P0_OK_VDD3P0_SHIFT (17U)
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#define PMU_REG_3P0_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_OK_VDD3P0_MASK)
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/*! @} */
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/*! @name REG_3P0_SET - Regulator 3P0 Register */
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/*! @{ */
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#define PMU_REG_3P0_SET_ENABLE_LINREG_MASK (0x1U)
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#define PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT (0U)
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#define PMU_REG_3P0_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_SET_ENABLE_LINREG_MASK)
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#define PMU_REG_3P0_SET_ENABLE_BO_MASK (0x2U)
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#define PMU_REG_3P0_SET_ENABLE_BO_SHIFT (1U)
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#define PMU_REG_3P0_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_BO_SHIFT)) & PMU_REG_3P0_SET_ENABLE_BO_MASK)
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#define PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK (0x4U)
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#define PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT (2U)
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#define PMU_REG_3P0_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK)
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#define PMU_REG_3P0_SET_BO_OFFSET_MASK (0x70U)
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#define PMU_REG_3P0_SET_BO_OFFSET_SHIFT (4U)
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#define PMU_REG_3P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_OFFSET_SHIFT)) & PMU_REG_3P0_SET_BO_OFFSET_MASK)
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#define PMU_REG_3P0_SET_VBUS_SEL_MASK (0x80U)
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#define PMU_REG_3P0_SET_VBUS_SEL_SHIFT (7U)
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/*! VBUS_SEL
|
|
* 0b1..Utilize VBUS OTG1 power
|
|
* 0b0..Utilize VBUS OTG2 power
|
|
*/
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#define PMU_REG_3P0_SET_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_VBUS_SEL_SHIFT)) & PMU_REG_3P0_SET_VBUS_SEL_MASK)
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#define PMU_REG_3P0_SET_OUTPUT_TRG_MASK (0x1F00U)
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#define PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT (8U)
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/*! OUTPUT_TRG
|
|
* 0b00000..2.625V
|
|
* 0b01111..3.000V
|
|
* 0b11111..3.400V
|
|
*/
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#define PMU_REG_3P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_SET_OUTPUT_TRG_MASK)
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#define PMU_REG_3P0_SET_BO_VDD3P0_MASK (0x10000U)
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#define PMU_REG_3P0_SET_BO_VDD3P0_SHIFT (16U)
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#define PMU_REG_3P0_SET_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_BO_VDD3P0_MASK)
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#define PMU_REG_3P0_SET_OK_VDD3P0_MASK (0x20000U)
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#define PMU_REG_3P0_SET_OK_VDD3P0_SHIFT (17U)
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#define PMU_REG_3P0_SET_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_OK_VDD3P0_MASK)
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/*! @} */
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/*! @name REG_3P0_CLR - Regulator 3P0 Register */
|
|
/*! @{ */
|
|
#define PMU_REG_3P0_CLR_ENABLE_LINREG_MASK (0x1U)
|
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#define PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT (0U)
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#define PMU_REG_3P0_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_LINREG_MASK)
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#define PMU_REG_3P0_CLR_ENABLE_BO_MASK (0x2U)
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#define PMU_REG_3P0_CLR_ENABLE_BO_SHIFT (1U)
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#define PMU_REG_3P0_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_BO_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_BO_MASK)
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#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK (0x4U)
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#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT (2U)
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#define PMU_REG_3P0_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK)
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#define PMU_REG_3P0_CLR_BO_OFFSET_MASK (0x70U)
|
|
#define PMU_REG_3P0_CLR_BO_OFFSET_SHIFT (4U)
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|
#define PMU_REG_3P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_OFFSET_SHIFT)) & PMU_REG_3P0_CLR_BO_OFFSET_MASK)
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#define PMU_REG_3P0_CLR_VBUS_SEL_MASK (0x80U)
|
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#define PMU_REG_3P0_CLR_VBUS_SEL_SHIFT (7U)
|
|
/*! VBUS_SEL
|
|
* 0b1..Utilize VBUS OTG1 power
|
|
* 0b0..Utilize VBUS OTG2 power
|
|
*/
|
|
#define PMU_REG_3P0_CLR_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_VBUS_SEL_SHIFT)) & PMU_REG_3P0_CLR_VBUS_SEL_MASK)
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#define PMU_REG_3P0_CLR_OUTPUT_TRG_MASK (0x1F00U)
|
|
#define PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT (8U)
|
|
/*! OUTPUT_TRG
|
|
* 0b00000..2.625V
|
|
* 0b01111..3.000V
|
|
* 0b11111..3.400V
|
|
*/
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#define PMU_REG_3P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_CLR_OUTPUT_TRG_MASK)
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#define PMU_REG_3P0_CLR_BO_VDD3P0_MASK (0x10000U)
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#define PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT (16U)
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#define PMU_REG_3P0_CLR_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_BO_VDD3P0_MASK)
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#define PMU_REG_3P0_CLR_OK_VDD3P0_MASK (0x20000U)
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#define PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT (17U)
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#define PMU_REG_3P0_CLR_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_OK_VDD3P0_MASK)
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/*! @} */
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/*! @name REG_3P0_TOG - Regulator 3P0 Register */
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/*! @{ */
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#define PMU_REG_3P0_TOG_ENABLE_LINREG_MASK (0x1U)
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#define PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT (0U)
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#define PMU_REG_3P0_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_LINREG_MASK)
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#define PMU_REG_3P0_TOG_ENABLE_BO_MASK (0x2U)
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#define PMU_REG_3P0_TOG_ENABLE_BO_SHIFT (1U)
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#define PMU_REG_3P0_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_BO_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_BO_MASK)
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#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK (0x4U)
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#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT (2U)
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#define PMU_REG_3P0_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK)
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#define PMU_REG_3P0_TOG_BO_OFFSET_MASK (0x70U)
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#define PMU_REG_3P0_TOG_BO_OFFSET_SHIFT (4U)
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#define PMU_REG_3P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_OFFSET_SHIFT)) & PMU_REG_3P0_TOG_BO_OFFSET_MASK)
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#define PMU_REG_3P0_TOG_VBUS_SEL_MASK (0x80U)
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#define PMU_REG_3P0_TOG_VBUS_SEL_SHIFT (7U)
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/*! VBUS_SEL
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* 0b1..Utilize VBUS OTG1 power
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* 0b0..Utilize VBUS OTG2 power
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*/
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#define PMU_REG_3P0_TOG_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_VBUS_SEL_SHIFT)) & PMU_REG_3P0_TOG_VBUS_SEL_MASK)
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#define PMU_REG_3P0_TOG_OUTPUT_TRG_MASK (0x1F00U)
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#define PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT (8U)
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/*! OUTPUT_TRG
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* 0b00000..2.625V
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* 0b01111..3.000V
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* 0b11111..3.400V
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*/
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#define PMU_REG_3P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_TOG_OUTPUT_TRG_MASK)
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#define PMU_REG_3P0_TOG_BO_VDD3P0_MASK (0x10000U)
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#define PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT (16U)
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#define PMU_REG_3P0_TOG_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_BO_VDD3P0_MASK)
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#define PMU_REG_3P0_TOG_OK_VDD3P0_MASK (0x20000U)
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#define PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT (17U)
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#define PMU_REG_3P0_TOG_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_OK_VDD3P0_MASK)
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/*! @} */
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/*! @name REG_2P5 - Regulator 2P5 Register */
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/*! @{ */
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#define PMU_REG_2P5_ENABLE_LINREG_MASK (0x1U)
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#define PMU_REG_2P5_ENABLE_LINREG_SHIFT (0U)
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#define PMU_REG_2P5_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_LINREG_MASK)
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#define PMU_REG_2P5_ENABLE_BO_MASK (0x2U)
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#define PMU_REG_2P5_ENABLE_BO_SHIFT (1U)
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#define PMU_REG_2P5_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_BO_SHIFT)) & PMU_REG_2P5_ENABLE_BO_MASK)
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#define PMU_REG_2P5_ENABLE_ILIMIT_MASK (0x4U)
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#define PMU_REG_2P5_ENABLE_ILIMIT_SHIFT (2U)
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#define PMU_REG_2P5_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_ENABLE_ILIMIT_MASK)
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#define PMU_REG_2P5_ENABLE_PULLDOWN_MASK (0x8U)
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#define PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT (3U)
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#define PMU_REG_2P5_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_ENABLE_PULLDOWN_MASK)
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#define PMU_REG_2P5_BO_OFFSET_MASK (0x70U)
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#define PMU_REG_2P5_BO_OFFSET_SHIFT (4U)
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#define PMU_REG_2P5_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_OFFSET_SHIFT)) & PMU_REG_2P5_BO_OFFSET_MASK)
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#define PMU_REG_2P5_OUTPUT_TRG_MASK (0x1F00U)
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#define PMU_REG_2P5_OUTPUT_TRG_SHIFT (8U)
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/*! OUTPUT_TRG
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* 0b00000..2.10V
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* 0b10000..2.50V
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* 0b11111..2.875V
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*/
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#define PMU_REG_2P5_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK)
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#define PMU_REG_2P5_BO_VDD2P5_MASK (0x10000U)
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#define PMU_REG_2P5_BO_VDD2P5_SHIFT (16U)
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#define PMU_REG_2P5_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_BO_VDD2P5_MASK)
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#define PMU_REG_2P5_OK_VDD2P5_MASK (0x20000U)
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#define PMU_REG_2P5_OK_VDD2P5_SHIFT (17U)
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#define PMU_REG_2P5_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_OK_VDD2P5_MASK)
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#define PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK (0x40000U)
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#define PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT (18U)
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#define PMU_REG_2P5_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK)
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/*! @} */
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/*! @name REG_2P5_SET - Regulator 2P5 Register */
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/*! @{ */
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#define PMU_REG_2P5_SET_ENABLE_LINREG_MASK (0x1U)
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#define PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT (0U)
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#define PMU_REG_2P5_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_LINREG_MASK)
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#define PMU_REG_2P5_SET_ENABLE_BO_MASK (0x2U)
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#define PMU_REG_2P5_SET_ENABLE_BO_SHIFT (1U)
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#define PMU_REG_2P5_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_BO_SHIFT)) & PMU_REG_2P5_SET_ENABLE_BO_MASK)
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#define PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK (0x4U)
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#define PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT (2U)
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#define PMU_REG_2P5_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK)
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#define PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK (0x8U)
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#define PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT (3U)
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#define PMU_REG_2P5_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK)
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#define PMU_REG_2P5_SET_BO_OFFSET_MASK (0x70U)
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#define PMU_REG_2P5_SET_BO_OFFSET_SHIFT (4U)
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#define PMU_REG_2P5_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_OFFSET_SHIFT)) & PMU_REG_2P5_SET_BO_OFFSET_MASK)
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#define PMU_REG_2P5_SET_OUTPUT_TRG_MASK (0x1F00U)
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#define PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT (8U)
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/*! OUTPUT_TRG
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* 0b00000..2.10V
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* 0b10000..2.50V
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* 0b11111..2.875V
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|
*/
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#define PMU_REG_2P5_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_SET_OUTPUT_TRG_MASK)
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#define PMU_REG_2P5_SET_BO_VDD2P5_MASK (0x10000U)
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#define PMU_REG_2P5_SET_BO_VDD2P5_SHIFT (16U)
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#define PMU_REG_2P5_SET_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_BO_VDD2P5_MASK)
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#define PMU_REG_2P5_SET_OK_VDD2P5_MASK (0x20000U)
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#define PMU_REG_2P5_SET_OK_VDD2P5_SHIFT (17U)
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#define PMU_REG_2P5_SET_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_OK_VDD2P5_MASK)
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#define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK (0x40000U)
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#define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT (18U)
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#define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK)
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/*! @} */
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/*! @name REG_2P5_CLR - Regulator 2P5 Register */
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/*! @{ */
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#define PMU_REG_2P5_CLR_ENABLE_LINREG_MASK (0x1U)
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#define PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT (0U)
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#define PMU_REG_2P5_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_LINREG_MASK)
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#define PMU_REG_2P5_CLR_ENABLE_BO_MASK (0x2U)
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#define PMU_REG_2P5_CLR_ENABLE_BO_SHIFT (1U)
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#define PMU_REG_2P5_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_BO_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_BO_MASK)
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#define PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK (0x4U)
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#define PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT (2U)
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#define PMU_REG_2P5_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK)
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#define PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK (0x8U)
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#define PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT (3U)
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#define PMU_REG_2P5_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK)
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#define PMU_REG_2P5_CLR_BO_OFFSET_MASK (0x70U)
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#define PMU_REG_2P5_CLR_BO_OFFSET_SHIFT (4U)
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#define PMU_REG_2P5_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_OFFSET_SHIFT)) & PMU_REG_2P5_CLR_BO_OFFSET_MASK)
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#define PMU_REG_2P5_CLR_OUTPUT_TRG_MASK (0x1F00U)
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#define PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT (8U)
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/*! OUTPUT_TRG
|
|
* 0b00000..2.10V
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* 0b10000..2.50V
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* 0b11111..2.875V
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|
*/
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#define PMU_REG_2P5_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_CLR_OUTPUT_TRG_MASK)
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#define PMU_REG_2P5_CLR_BO_VDD2P5_MASK (0x10000U)
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#define PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT (16U)
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#define PMU_REG_2P5_CLR_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_BO_VDD2P5_MASK)
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#define PMU_REG_2P5_CLR_OK_VDD2P5_MASK (0x20000U)
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#define PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT (17U)
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#define PMU_REG_2P5_CLR_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_OK_VDD2P5_MASK)
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#define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U)
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#define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT (18U)
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#define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK)
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/*! @} */
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/*! @name REG_2P5_TOG - Regulator 2P5 Register */
|
|
/*! @{ */
|
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#define PMU_REG_2P5_TOG_ENABLE_LINREG_MASK (0x1U)
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#define PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT (0U)
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#define PMU_REG_2P5_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_LINREG_MASK)
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#define PMU_REG_2P5_TOG_ENABLE_BO_MASK (0x2U)
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#define PMU_REG_2P5_TOG_ENABLE_BO_SHIFT (1U)
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#define PMU_REG_2P5_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_BO_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_BO_MASK)
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#define PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK (0x4U)
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#define PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT (2U)
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#define PMU_REG_2P5_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK)
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#define PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK (0x8U)
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#define PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT (3U)
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#define PMU_REG_2P5_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK)
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#define PMU_REG_2P5_TOG_BO_OFFSET_MASK (0x70U)
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#define PMU_REG_2P5_TOG_BO_OFFSET_SHIFT (4U)
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|
#define PMU_REG_2P5_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_OFFSET_SHIFT)) & PMU_REG_2P5_TOG_BO_OFFSET_MASK)
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#define PMU_REG_2P5_TOG_OUTPUT_TRG_MASK (0x1F00U)
|
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#define PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT (8U)
|
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/*! OUTPUT_TRG
|
|
* 0b00000..2.10V
|
|
* 0b10000..2.50V
|
|
* 0b11111..2.875V
|
|
*/
|
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#define PMU_REG_2P5_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_TOG_OUTPUT_TRG_MASK)
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|
#define PMU_REG_2P5_TOG_BO_VDD2P5_MASK (0x10000U)
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#define PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT (16U)
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#define PMU_REG_2P5_TOG_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_BO_VDD2P5_MASK)
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#define PMU_REG_2P5_TOG_OK_VDD2P5_MASK (0x20000U)
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#define PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT (17U)
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#define PMU_REG_2P5_TOG_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_OK_VDD2P5_MASK)
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#define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U)
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#define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT (18U)
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#define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK)
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/*! @} */
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|
|
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/*! @name REG_CORE - Digital Regulator Core Register */
|
|
/*! @{ */
|
|
#define PMU_REG_CORE_REG0_TARG_MASK (0x1FU)
|
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#define PMU_REG_CORE_REG0_TARG_SHIFT (0U)
|
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/*! REG0_TARG
|
|
* 0b00000..Power gated off
|
|
* 0b00001..Target core voltage = 0.725V
|
|
* 0b00010..Target core voltage = 0.750V
|
|
* 0b00011..Target core voltage = 0.775V
|
|
* 0b10000..Target core voltage = 1.100V
|
|
* 0b11110..Target core voltage = 1.450V
|
|
* 0b11111..Power FET switched full on. No regulation.
|
|
*/
|
|
#define PMU_REG_CORE_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_TARG_SHIFT)) & PMU_REG_CORE_REG0_TARG_MASK)
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#define PMU_REG_CORE_REG0_ADJ_MASK (0x1E0U)
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#define PMU_REG_CORE_REG0_ADJ_SHIFT (5U)
|
|
/*! REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.
|
|
* 0b0000..No adjustment
|
|
* 0b0001..+ 0.25%
|
|
* 0b0010..+ 0.50%
|
|
* 0b0011..+ 0.75%
|
|
* 0b0100..+ 1.00%
|
|
* 0b0101..+ 1.25%
|
|
* 0b0110..+ 1.50%
|
|
* 0b0111..+ 1.75%
|
|
* 0b1000..- 0.25%
|
|
* 0b1001..- 0.50%
|
|
* 0b1010..- 0.75%
|
|
* 0b1011..- 1.00%
|
|
* 0b1100..- 1.25%
|
|
* 0b1101..- 1.50%
|
|
* 0b1110..- 1.75%
|
|
* 0b1111..- 2.00%
|
|
*/
|
|
#define PMU_REG_CORE_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_ADJ_SHIFT)) & PMU_REG_CORE_REG0_ADJ_MASK)
|
|
#define PMU_REG_CORE_REG1_TARG_MASK (0x3E00U)
|
|
#define PMU_REG_CORE_REG1_TARG_SHIFT (9U)
|
|
/*! REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation.
|
|
* 0b00000..Power gated off
|
|
* 0b00001..Target core voltage = 0.725V
|
|
* 0b00010..Target core voltage = 0.750V
|
|
* 0b00011..Target core voltage = 0.775V
|
|
* 0b10000..Target core voltage = 1.100V
|
|
* 0b11110..Target core voltage = 1.450V
|
|
* 0b11111..Power FET switched full on. No regulation.
|
|
*/
|
|
#define PMU_REG_CORE_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_TARG_SHIFT)) & PMU_REG_CORE_REG1_TARG_MASK)
|
|
#define PMU_REG_CORE_REG1_ADJ_MASK (0x3C000U)
|
|
#define PMU_REG_CORE_REG1_ADJ_SHIFT (14U)
|
|
/*! REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.
|
|
* 0b0000..No adjustment
|
|
* 0b0001..+ 0.25%
|
|
* 0b0010..+ 0.50%
|
|
* 0b0011..+ 0.75%
|
|
* 0b0100..+ 1.00%
|
|
* 0b0101..+ 1.25%
|
|
* 0b0110..+ 1.50%
|
|
* 0b0111..+ 1.75%
|
|
* 0b1000..- 0.25%
|
|
* 0b1001..- 0.50%
|
|
* 0b1010..- 0.75%
|
|
* 0b1011..- 1.00%
|
|
* 0b1100..- 1.25%
|
|
* 0b1101..- 1.50%
|
|
* 0b1110..- 1.75%
|
|
* 0b1111..- 2.00%
|
|
*/
|
|
#define PMU_REG_CORE_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_ADJ_SHIFT)) & PMU_REG_CORE_REG1_ADJ_MASK)
|
|
#define PMU_REG_CORE_REG2_TARG_MASK (0x7C0000U)
|
|
#define PMU_REG_CORE_REG2_TARG_SHIFT (18U)
|
|
/*! REG2_TARG
|
|
* 0b00000..Power gated off
|
|
* 0b00001..Target core voltage = 0.725V
|
|
* 0b00010..Target core voltage = 0.750V
|
|
* 0b00011..Target core voltage = 0.775V
|
|
* 0b10000..Target core voltage = 1.100V
|
|
* 0b11110..Target core voltage = 1.450V
|
|
* 0b11111..Power FET switched full on. No regulation.
|
|
*/
|
|
#define PMU_REG_CORE_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_TARG_SHIFT)) & PMU_REG_CORE_REG2_TARG_MASK)
|
|
#define PMU_REG_CORE_REG2_ADJ_MASK (0x7800000U)
|
|
#define PMU_REG_CORE_REG2_ADJ_SHIFT (23U)
|
|
/*! REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.
|
|
* 0b0000..No adjustment
|
|
* 0b0001..+ 0.25%
|
|
* 0b0010..+ 0.50%
|
|
* 0b0011..+ 0.75%
|
|
* 0b0100..+ 1.00%
|
|
* 0b0101..+ 1.25%
|
|
* 0b0110..+ 1.50%
|
|
* 0b0111..+ 1.75%
|
|
* 0b1000..- 0.25%
|
|
* 0b1001..- 0.50%
|
|
* 0b1010..- 0.75%
|
|
* 0b1011..- 1.00%
|
|
* 0b1100..- 1.25%
|
|
* 0b1101..- 1.50%
|
|
* 0b1110..- 1.75%
|
|
* 0b1111..- 2.00%
|
|
*/
|
|
#define PMU_REG_CORE_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_ADJ_SHIFT)) & PMU_REG_CORE_REG2_ADJ_MASK)
|
|
#define PMU_REG_CORE_RAMP_RATE_MASK (0x18000000U)
|
|
#define PMU_REG_CORE_RAMP_RATE_SHIFT (27U)
|
|
/*! RAMP_RATE
|
|
* 0b00..Fast
|
|
* 0b01..Medium Fast
|
|
* 0b10..Medium Slow
|
|
* 0b11..Slow
|
|
*/
|
|
#define PMU_REG_CORE_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_RAMP_RATE_SHIFT)) & PMU_REG_CORE_RAMP_RATE_MASK)
|
|
#define PMU_REG_CORE_FET_ODRIVE_MASK (0x20000000U)
|
|
#define PMU_REG_CORE_FET_ODRIVE_SHIFT (29U)
|
|
#define PMU_REG_CORE_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_FET_ODRIVE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name REG_CORE_SET - Digital Regulator Core Register */
|
|
/*! @{ */
|
|
#define PMU_REG_CORE_SET_REG0_TARG_MASK (0x1FU)
|
|
#define PMU_REG_CORE_SET_REG0_TARG_SHIFT (0U)
|
|
/*! REG0_TARG
|
|
* 0b00000..Power gated off
|
|
* 0b00001..Target core voltage = 0.725V
|
|
* 0b00010..Target core voltage = 0.750V
|
|
* 0b00011..Target core voltage = 0.775V
|
|
* 0b10000..Target core voltage = 1.100V
|
|
* 0b11110..Target core voltage = 1.450V
|
|
* 0b11111..Power FET switched full on. No regulation.
|
|
*/
|
|
#define PMU_REG_CORE_SET_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_TARG_SHIFT)) & PMU_REG_CORE_SET_REG0_TARG_MASK)
|
|
#define PMU_REG_CORE_SET_REG0_ADJ_MASK (0x1E0U)
|
|
#define PMU_REG_CORE_SET_REG0_ADJ_SHIFT (5U)
|
|
/*! REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.
|
|
* 0b0000..No adjustment
|
|
* 0b0001..+ 0.25%
|
|
* 0b0010..+ 0.50%
|
|
* 0b0011..+ 0.75%
|
|
* 0b0100..+ 1.00%
|
|
* 0b0101..+ 1.25%
|
|
* 0b0110..+ 1.50%
|
|
* 0b0111..+ 1.75%
|
|
* 0b1000..- 0.25%
|
|
* 0b1001..- 0.50%
|
|
* 0b1010..- 0.75%
|
|
* 0b1011..- 1.00%
|
|
* 0b1100..- 1.25%
|
|
* 0b1101..- 1.50%
|
|
* 0b1110..- 1.75%
|
|
* 0b1111..- 2.00%
|
|
*/
|
|
#define PMU_REG_CORE_SET_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG0_ADJ_MASK)
|
|
#define PMU_REG_CORE_SET_REG1_TARG_MASK (0x3E00U)
|
|
#define PMU_REG_CORE_SET_REG1_TARG_SHIFT (9U)
|
|
/*! REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation.
|
|
* 0b00000..Power gated off
|
|
* 0b00001..Target core voltage = 0.725V
|
|
* 0b00010..Target core voltage = 0.750V
|
|
* 0b00011..Target core voltage = 0.775V
|
|
* 0b10000..Target core voltage = 1.100V
|
|
* 0b11110..Target core voltage = 1.450V
|
|
* 0b11111..Power FET switched full on. No regulation.
|
|
*/
|
|
#define PMU_REG_CORE_SET_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_TARG_SHIFT)) & PMU_REG_CORE_SET_REG1_TARG_MASK)
|
|
#define PMU_REG_CORE_SET_REG1_ADJ_MASK (0x3C000U)
|
|
#define PMU_REG_CORE_SET_REG1_ADJ_SHIFT (14U)
|
|
/*! REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.
|
|
* 0b0000..No adjustment
|
|
* 0b0001..+ 0.25%
|
|
* 0b0010..+ 0.50%
|
|
* 0b0011..+ 0.75%
|
|
* 0b0100..+ 1.00%
|
|
* 0b0101..+ 1.25%
|
|
* 0b0110..+ 1.50%
|
|
* 0b0111..+ 1.75%
|
|
* 0b1000..- 0.25%
|
|
* 0b1001..- 0.50%
|
|
* 0b1010..- 0.75%
|
|
* 0b1011..- 1.00%
|
|
* 0b1100..- 1.25%
|
|
* 0b1101..- 1.50%
|
|
* 0b1110..- 1.75%
|
|
* 0b1111..- 2.00%
|
|
*/
|
|
#define PMU_REG_CORE_SET_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG1_ADJ_MASK)
|
|
#define PMU_REG_CORE_SET_REG2_TARG_MASK (0x7C0000U)
|
|
#define PMU_REG_CORE_SET_REG2_TARG_SHIFT (18U)
|
|
/*! REG2_TARG
|
|
* 0b00000..Power gated off
|
|
* 0b00001..Target core voltage = 0.725V
|
|
* 0b00010..Target core voltage = 0.750V
|
|
* 0b00011..Target core voltage = 0.775V
|
|
* 0b10000..Target core voltage = 1.100V
|
|
* 0b11110..Target core voltage = 1.450V
|
|
* 0b11111..Power FET switched full on. No regulation.
|
|
*/
|
|
#define PMU_REG_CORE_SET_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_TARG_SHIFT)) & PMU_REG_CORE_SET_REG2_TARG_MASK)
|
|
#define PMU_REG_CORE_SET_REG2_ADJ_MASK (0x7800000U)
|
|
#define PMU_REG_CORE_SET_REG2_ADJ_SHIFT (23U)
|
|
/*! REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.
|
|
* 0b0000..No adjustment
|
|
* 0b0001..+ 0.25%
|
|
* 0b0010..+ 0.50%
|
|
* 0b0011..+ 0.75%
|
|
* 0b0100..+ 1.00%
|
|
* 0b0101..+ 1.25%
|
|
* 0b0110..+ 1.50%
|
|
* 0b0111..+ 1.75%
|
|
* 0b1000..- 0.25%
|
|
* 0b1001..- 0.50%
|
|
* 0b1010..- 0.75%
|
|
* 0b1011..- 1.00%
|
|
* 0b1100..- 1.25%
|
|
* 0b1101..- 1.50%
|
|
* 0b1110..- 1.75%
|
|
* 0b1111..- 2.00%
|
|
*/
|
|
#define PMU_REG_CORE_SET_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG2_ADJ_MASK)
|
|
#define PMU_REG_CORE_SET_RAMP_RATE_MASK (0x18000000U)
|
|
#define PMU_REG_CORE_SET_RAMP_RATE_SHIFT (27U)
|
|
/*! RAMP_RATE
|
|
* 0b00..Fast
|
|
* 0b01..Medium Fast
|
|
* 0b10..Medium Slow
|
|
* 0b11..Slow
|
|
*/
|
|
#define PMU_REG_CORE_SET_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_RAMP_RATE_SHIFT)) & PMU_REG_CORE_SET_RAMP_RATE_MASK)
|
|
#define PMU_REG_CORE_SET_FET_ODRIVE_MASK (0x20000000U)
|
|
#define PMU_REG_CORE_SET_FET_ODRIVE_SHIFT (29U)
|
|
#define PMU_REG_CORE_SET_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_SET_FET_ODRIVE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name REG_CORE_CLR - Digital Regulator Core Register */
|
|
/*! @{ */
|
|
#define PMU_REG_CORE_CLR_REG0_TARG_MASK (0x1FU)
|
|
#define PMU_REG_CORE_CLR_REG0_TARG_SHIFT (0U)
|
|
/*! REG0_TARG
|
|
* 0b00000..Power gated off
|
|
* 0b00001..Target core voltage = 0.725V
|
|
* 0b00010..Target core voltage = 0.750V
|
|
* 0b00011..Target core voltage = 0.775V
|
|
* 0b10000..Target core voltage = 1.100V
|
|
* 0b11110..Target core voltage = 1.450V
|
|
* 0b11111..Power FET switched full on. No regulation.
|
|
*/
|
|
#define PMU_REG_CORE_CLR_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG0_TARG_MASK)
|
|
#define PMU_REG_CORE_CLR_REG0_ADJ_MASK (0x1E0U)
|
|
#define PMU_REG_CORE_CLR_REG0_ADJ_SHIFT (5U)
|
|
/*! REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.
|
|
* 0b0000..No adjustment
|
|
* 0b0001..+ 0.25%
|
|
* 0b0010..+ 0.50%
|
|
* 0b0011..+ 0.75%
|
|
* 0b0100..+ 1.00%
|
|
* 0b0101..+ 1.25%
|
|
* 0b0110..+ 1.50%
|
|
* 0b0111..+ 1.75%
|
|
* 0b1000..- 0.25%
|
|
* 0b1001..- 0.50%
|
|
* 0b1010..- 0.75%
|
|
* 0b1011..- 1.00%
|
|
* 0b1100..- 1.25%
|
|
* 0b1101..- 1.50%
|
|
* 0b1110..- 1.75%
|
|
* 0b1111..- 2.00%
|
|
*/
|
|
#define PMU_REG_CORE_CLR_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG0_ADJ_MASK)
|
|
#define PMU_REG_CORE_CLR_REG1_TARG_MASK (0x3E00U)
|
|
#define PMU_REG_CORE_CLR_REG1_TARG_SHIFT (9U)
|
|
/*! REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation.
|
|
* 0b00000..Power gated off
|
|
* 0b00001..Target core voltage = 0.725V
|
|
* 0b00010..Target core voltage = 0.750V
|
|
* 0b00011..Target core voltage = 0.775V
|
|
* 0b10000..Target core voltage = 1.100V
|
|
* 0b11110..Target core voltage = 1.450V
|
|
* 0b11111..Power FET switched full on. No regulation.
|
|
*/
|
|
#define PMU_REG_CORE_CLR_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG1_TARG_MASK)
|
|
#define PMU_REG_CORE_CLR_REG1_ADJ_MASK (0x3C000U)
|
|
#define PMU_REG_CORE_CLR_REG1_ADJ_SHIFT (14U)
|
|
/*! REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.
|
|
* 0b0000..No adjustment
|
|
* 0b0001..+ 0.25%
|
|
* 0b0010..+ 0.50%
|
|
* 0b0011..+ 0.75%
|
|
* 0b0100..+ 1.00%
|
|
* 0b0101..+ 1.25%
|
|
* 0b0110..+ 1.50%
|
|
* 0b0111..+ 1.75%
|
|
* 0b1000..- 0.25%
|
|
* 0b1001..- 0.50%
|
|
* 0b1010..- 0.75%
|
|
* 0b1011..- 1.00%
|
|
* 0b1100..- 1.25%
|
|
* 0b1101..- 1.50%
|
|
* 0b1110..- 1.75%
|
|
* 0b1111..- 2.00%
|
|
*/
|
|
#define PMU_REG_CORE_CLR_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG1_ADJ_MASK)
|
|
#define PMU_REG_CORE_CLR_REG2_TARG_MASK (0x7C0000U)
|
|
#define PMU_REG_CORE_CLR_REG2_TARG_SHIFT (18U)
|
|
/*! REG2_TARG
|
|
* 0b00000..Power gated off
|
|
* 0b00001..Target core voltage = 0.725V
|
|
* 0b00010..Target core voltage = 0.750V
|
|
* 0b00011..Target core voltage = 0.775V
|
|
* 0b10000..Target core voltage = 1.100V
|
|
* 0b11110..Target core voltage = 1.450V
|
|
* 0b11111..Power FET switched full on. No regulation.
|
|
*/
|
|
#define PMU_REG_CORE_CLR_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG2_TARG_MASK)
|
|
#define PMU_REG_CORE_CLR_REG2_ADJ_MASK (0x7800000U)
|
|
#define PMU_REG_CORE_CLR_REG2_ADJ_SHIFT (23U)
|
|
/*! REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.
|
|
* 0b0000..No adjustment
|
|
* 0b0001..+ 0.25%
|
|
* 0b0010..+ 0.50%
|
|
* 0b0011..+ 0.75%
|
|
* 0b0100..+ 1.00%
|
|
* 0b0101..+ 1.25%
|
|
* 0b0110..+ 1.50%
|
|
* 0b0111..+ 1.75%
|
|
* 0b1000..- 0.25%
|
|
* 0b1001..- 0.50%
|
|
* 0b1010..- 0.75%
|
|
* 0b1011..- 1.00%
|
|
* 0b1100..- 1.25%
|
|
* 0b1101..- 1.50%
|
|
* 0b1110..- 1.75%
|
|
* 0b1111..- 2.00%
|
|
*/
|
|
#define PMU_REG_CORE_CLR_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG2_ADJ_MASK)
|
|
#define PMU_REG_CORE_CLR_RAMP_RATE_MASK (0x18000000U)
|
|
#define PMU_REG_CORE_CLR_RAMP_RATE_SHIFT (27U)
|
|
/*! RAMP_RATE
|
|
* 0b00..Fast
|
|
* 0b01..Medium Fast
|
|
* 0b10..Medium Slow
|
|
* 0b11..Slow
|
|
*/
|
|
#define PMU_REG_CORE_CLR_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_RAMP_RATE_SHIFT)) & PMU_REG_CORE_CLR_RAMP_RATE_MASK)
|
|
#define PMU_REG_CORE_CLR_FET_ODRIVE_MASK (0x20000000U)
|
|
#define PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT (29U)
|
|
#define PMU_REG_CORE_CLR_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_CLR_FET_ODRIVE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name REG_CORE_TOG - Digital Regulator Core Register */
|
|
/*! @{ */
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#define PMU_REG_CORE_TOG_REG0_TARG_MASK (0x1FU)
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#define PMU_REG_CORE_TOG_REG0_TARG_SHIFT (0U)
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/*! REG0_TARG
|
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* 0b00000..Power gated off
|
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* 0b00001..Target core voltage = 0.725V
|
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* 0b00010..Target core voltage = 0.750V
|
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* 0b00011..Target core voltage = 0.775V
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* 0b10000..Target core voltage = 1.100V
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* 0b11110..Target core voltage = 1.450V
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* 0b11111..Power FET switched full on. No regulation.
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*/
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#define PMU_REG_CORE_TOG_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG0_TARG_MASK)
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#define PMU_REG_CORE_TOG_REG0_ADJ_MASK (0x1E0U)
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#define PMU_REG_CORE_TOG_REG0_ADJ_SHIFT (5U)
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/*! REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.
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* 0b0000..No adjustment
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* 0b0001..+ 0.25%
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* 0b0010..+ 0.50%
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* 0b0011..+ 0.75%
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* 0b0100..+ 1.00%
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* 0b0101..+ 1.25%
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* 0b0110..+ 1.50%
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* 0b0111..+ 1.75%
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* 0b1000..- 0.25%
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* 0b1001..- 0.50%
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* 0b1010..- 0.75%
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* 0b1011..- 1.00%
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* 0b1100..- 1.25%
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* 0b1101..- 1.50%
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* 0b1110..- 1.75%
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* 0b1111..- 2.00%
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*/
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#define PMU_REG_CORE_TOG_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG0_ADJ_MASK)
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#define PMU_REG_CORE_TOG_REG1_TARG_MASK (0x3E00U)
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#define PMU_REG_CORE_TOG_REG1_TARG_SHIFT (9U)
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/*! REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation.
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* 0b00000..Power gated off
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* 0b00001..Target core voltage = 0.725V
|
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* 0b00010..Target core voltage = 0.750V
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* 0b00011..Target core voltage = 0.775V
|
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* 0b10000..Target core voltage = 1.100V
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* 0b11110..Target core voltage = 1.450V
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* 0b11111..Power FET switched full on. No regulation.
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*/
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#define PMU_REG_CORE_TOG_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG1_TARG_MASK)
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#define PMU_REG_CORE_TOG_REG1_ADJ_MASK (0x3C000U)
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#define PMU_REG_CORE_TOG_REG1_ADJ_SHIFT (14U)
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/*! REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.
|
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* 0b0000..No adjustment
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* 0b0001..+ 0.25%
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* 0b0010..+ 0.50%
|
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* 0b0011..+ 0.75%
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* 0b0100..+ 1.00%
|
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* 0b0101..+ 1.25%
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* 0b0110..+ 1.50%
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* 0b0111..+ 1.75%
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* 0b1000..- 0.25%
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* 0b1001..- 0.50%
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* 0b1010..- 0.75%
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* 0b1011..- 1.00%
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* 0b1100..- 1.25%
|
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* 0b1101..- 1.50%
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* 0b1110..- 1.75%
|
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* 0b1111..- 2.00%
|
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*/
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#define PMU_REG_CORE_TOG_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG1_ADJ_MASK)
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#define PMU_REG_CORE_TOG_REG2_TARG_MASK (0x7C0000U)
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#define PMU_REG_CORE_TOG_REG2_TARG_SHIFT (18U)
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/*! REG2_TARG
|
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* 0b00000..Power gated off
|
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* 0b00001..Target core voltage = 0.725V
|
|
* 0b00010..Target core voltage = 0.750V
|
|
* 0b00011..Target core voltage = 0.775V
|
|
* 0b10000..Target core voltage = 1.100V
|
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* 0b11110..Target core voltage = 1.450V
|
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* 0b11111..Power FET switched full on. No regulation.
|
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*/
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#define PMU_REG_CORE_TOG_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG2_TARG_MASK)
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#define PMU_REG_CORE_TOG_REG2_ADJ_MASK (0x7800000U)
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#define PMU_REG_CORE_TOG_REG2_ADJ_SHIFT (23U)
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/*! REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.
|
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* 0b0000..No adjustment
|
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* 0b0001..+ 0.25%
|
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* 0b0010..+ 0.50%
|
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* 0b0011..+ 0.75%
|
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* 0b0100..+ 1.00%
|
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* 0b0101..+ 1.25%
|
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* 0b0110..+ 1.50%
|
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* 0b0111..+ 1.75%
|
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* 0b1000..- 0.25%
|
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* 0b1001..- 0.50%
|
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* 0b1010..- 0.75%
|
|
* 0b1011..- 1.00%
|
|
* 0b1100..- 1.25%
|
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* 0b1101..- 1.50%
|
|
* 0b1110..- 1.75%
|
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* 0b1111..- 2.00%
|
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*/
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#define PMU_REG_CORE_TOG_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG2_ADJ_MASK)
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#define PMU_REG_CORE_TOG_RAMP_RATE_MASK (0x18000000U)
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#define PMU_REG_CORE_TOG_RAMP_RATE_SHIFT (27U)
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/*! RAMP_RATE
|
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* 0b00..Fast
|
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* 0b01..Medium Fast
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* 0b10..Medium Slow
|
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* 0b11..Slow
|
|
*/
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#define PMU_REG_CORE_TOG_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_RAMP_RATE_SHIFT)) & PMU_REG_CORE_TOG_RAMP_RATE_MASK)
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#define PMU_REG_CORE_TOG_FET_ODRIVE_MASK (0x20000000U)
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#define PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT (29U)
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#define PMU_REG_CORE_TOG_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_TOG_FET_ODRIVE_MASK)
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/*! @} */
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|
|
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/*! @name MISC0 - Miscellaneous Register 0 */
|
|
/*! @{ */
|
|
#define PMU_MISC0_REFTOP_PWD_MASK (0x1U)
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#define PMU_MISC0_REFTOP_PWD_SHIFT (0U)
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#define PMU_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_PWD_SHIFT)) & PMU_MISC0_REFTOP_PWD_MASK)
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#define PMU_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)
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#define PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)
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/*! REFTOP_SELFBIASOFF
|
|
* 0b0..Uses coarse bias currents for startup
|
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* 0b1..Uses bandgap-based bias currents for best performance.
|
|
*/
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|
#define PMU_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_REFTOP_SELFBIASOFF_MASK)
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#define PMU_MISC0_REFTOP_VBGADJ_MASK (0x70U)
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#define PMU_MISC0_REFTOP_VBGADJ_SHIFT (4U)
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|
/*! REFTOP_VBGADJ
|
|
* 0b000..Nominal VBG
|
|
* 0b001..VBG+0.78%
|
|
* 0b010..VBG+1.56%
|
|
* 0b011..VBG+2.34%
|
|
* 0b100..VBG-0.78%
|
|
* 0b101..VBG-1.56%
|
|
* 0b110..VBG-2.34%
|
|
* 0b111..VBG-3.12%
|
|
*/
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#define PMU_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_REFTOP_VBGADJ_MASK)
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#define PMU_MISC0_REFTOP_VBGUP_MASK (0x80U)
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#define PMU_MISC0_REFTOP_VBGUP_SHIFT (7U)
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#define PMU_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_REFTOP_VBGUP_MASK)
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#define PMU_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)
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#define PMU_MISC0_STOP_MODE_CONFIG_SHIFT (10U)
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/*! STOP_MODE_CONFIG
|
|
* 0b00..SUSPEND (DSM)
|
|
* 0b01..Analog regulators are ON.
|
|
* 0b10..STOP (lower power)
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|
* 0b11..STOP (very lower power)
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|
*/
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#define PMU_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_STOP_MODE_CONFIG_MASK)
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#define PMU_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)
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#define PMU_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)
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/*! DISCON_HIGH_SNVS
|
|
* 0b0..Turn on the switch
|
|
* 0b1..Turn off the switch
|
|
*/
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#define PMU_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_DISCON_HIGH_SNVS_MASK)
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#define PMU_MISC0_OSC_I_MASK (0x6000U)
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#define PMU_MISC0_OSC_I_SHIFT (13U)
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/*! OSC_I
|
|
* 0b00..Nominal
|
|
* 0b01..Decrease current by 12.5%
|
|
* 0b10..Decrease current by 25.0%
|
|
* 0b11..Decrease current by 37.5%
|
|
*/
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#define PMU_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_I_SHIFT)) & PMU_MISC0_OSC_I_MASK)
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#define PMU_MISC0_OSC_XTALOK_MASK (0x8000U)
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#define PMU_MISC0_OSC_XTALOK_SHIFT (15U)
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#define PMU_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_SHIFT)) & PMU_MISC0_OSC_XTALOK_MASK)
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#define PMU_MISC0_OSC_XTALOK_EN_MASK (0x10000U)
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#define PMU_MISC0_OSC_XTALOK_EN_SHIFT (16U)
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#define PMU_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_OSC_XTALOK_EN_MASK)
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#define PMU_MISC0_CLKGATE_CTRL_MASK (0x2000000U)
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#define PMU_MISC0_CLKGATE_CTRL_SHIFT (25U)
|
|
/*! CLKGATE_CTRL
|
|
* 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
|
|
* 0b1..Prevent the logic from ever gating off the clock.
|
|
*/
|
|
#define PMU_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLKGATE_CTRL_MASK)
|
|
#define PMU_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)
|
|
#define PMU_MISC0_CLKGATE_DELAY_SHIFT (26U)
|
|
/*! CLKGATE_DELAY
|
|
* 0b000..0.5ms
|
|
* 0b001..1.0ms
|
|
* 0b010..2.0ms
|
|
* 0b011..3.0ms
|
|
* 0b100..4.0ms
|
|
* 0b101..5.0ms
|
|
* 0b110..6.0ms
|
|
* 0b111..7.0ms
|
|
*/
|
|
#define PMU_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLKGATE_DELAY_MASK)
|
|
#define PMU_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)
|
|
#define PMU_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)
|
|
/*! RTC_XTAL_SOURCE
|
|
* 0b0..Internal ring oscillator
|
|
* 0b1..RTC_XTAL
|
|
*/
|
|
#define PMU_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_RTC_XTAL_SOURCE_MASK)
|
|
#define PMU_MISC0_XTAL_24M_PWD_MASK (0x40000000U)
|
|
#define PMU_MISC0_XTAL_24M_PWD_SHIFT (30U)
|
|
#define PMU_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_XTAL_24M_PWD_MASK)
|
|
#define PMU_MISC0_VID_PLL_PREDIV_MASK (0x80000000U)
|
|
#define PMU_MISC0_VID_PLL_PREDIV_SHIFT (31U)
|
|
/*! VID_PLL_PREDIV
|
|
* 0b0..Divide by 1
|
|
* 0b1..Divide by 2
|
|
*/
|
|
#define PMU_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_VID_PLL_PREDIV_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MISC0_SET - Miscellaneous Register 0 */
|
|
/*! @{ */
|
|
#define PMU_MISC0_SET_REFTOP_PWD_MASK (0x1U)
|
|
#define PMU_MISC0_SET_REFTOP_PWD_SHIFT (0U)
|
|
#define PMU_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_PWD_SHIFT)) & PMU_MISC0_SET_REFTOP_PWD_MASK)
|
|
#define PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)
|
|
#define PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)
|
|
/*! REFTOP_SELFBIASOFF
|
|
* 0b0..Uses coarse bias currents for startup
|
|
* 0b1..Uses bandgap-based bias currents for best performance.
|
|
*/
|
|
#define PMU_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK)
|
|
#define PMU_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)
|
|
#define PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)
|
|
/*! REFTOP_VBGADJ
|
|
* 0b000..Nominal VBG
|
|
* 0b001..VBG+0.78%
|
|
* 0b010..VBG+1.56%
|
|
* 0b011..VBG+2.34%
|
|
* 0b100..VBG-0.78%
|
|
* 0b101..VBG-1.56%
|
|
* 0b110..VBG-2.34%
|
|
* 0b111..VBG-3.12%
|
|
*/
|
|
#define PMU_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGADJ_MASK)
|
|
#define PMU_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)
|
|
#define PMU_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)
|
|
#define PMU_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGUP_MASK)
|
|
#define PMU_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)
|
|
#define PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)
|
|
/*! STOP_MODE_CONFIG
|
|
* 0b00..SUSPEND (DSM)
|
|
* 0b01..Analog regulators are ON.
|
|
* 0b10..STOP (lower power)
|
|
* 0b11..STOP (very lower power)
|
|
*/
|
|
#define PMU_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_SET_STOP_MODE_CONFIG_MASK)
|
|
#define PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)
|
|
#define PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)
|
|
/*! DISCON_HIGH_SNVS
|
|
* 0b0..Turn on the switch
|
|
* 0b1..Turn off the switch
|
|
*/
|
|
#define PMU_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK)
|
|
#define PMU_MISC0_SET_OSC_I_MASK (0x6000U)
|
|
#define PMU_MISC0_SET_OSC_I_SHIFT (13U)
|
|
/*! OSC_I
|
|
* 0b00..Nominal
|
|
* 0b01..Decrease current by 12.5%
|
|
* 0b10..Decrease current by 25.0%
|
|
* 0b11..Decrease current by 37.5%
|
|
*/
|
|
#define PMU_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_I_SHIFT)) & PMU_MISC0_SET_OSC_I_MASK)
|
|
#define PMU_MISC0_SET_OSC_XTALOK_MASK (0x8000U)
|
|
#define PMU_MISC0_SET_OSC_XTALOK_SHIFT (15U)
|
|
#define PMU_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_MASK)
|
|
#define PMU_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)
|
|
#define PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)
|
|
#define PMU_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_EN_MASK)
|
|
#define PMU_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)
|
|
#define PMU_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)
|
|
/*! CLKGATE_CTRL
|
|
* 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
|
|
* 0b1..Prevent the logic from ever gating off the clock.
|
|
*/
|
|
#define PMU_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_SET_CLKGATE_CTRL_MASK)
|
|
#define PMU_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)
|
|
#define PMU_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)
|
|
/*! CLKGATE_DELAY
|
|
* 0b000..0.5ms
|
|
* 0b001..1.0ms
|
|
* 0b010..2.0ms
|
|
* 0b011..3.0ms
|
|
* 0b100..4.0ms
|
|
* 0b101..5.0ms
|
|
* 0b110..6.0ms
|
|
* 0b111..7.0ms
|
|
*/
|
|
#define PMU_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_SET_CLKGATE_DELAY_MASK)
|
|
#define PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)
|
|
#define PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)
|
|
/*! RTC_XTAL_SOURCE
|
|
* 0b0..Internal ring oscillator
|
|
* 0b1..RTC_XTAL
|
|
*/
|
|
#define PMU_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK)
|
|
#define PMU_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)
|
|
#define PMU_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)
|
|
#define PMU_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_SET_XTAL_24M_PWD_MASK)
|
|
#define PMU_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U)
|
|
#define PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U)
|
|
/*! VID_PLL_PREDIV
|
|
* 0b0..Divide by 1
|
|
* 0b1..Divide by 2
|
|
*/
|
|
#define PMU_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_SET_VID_PLL_PREDIV_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MISC0_CLR - Miscellaneous Register 0 */
|
|
/*! @{ */
|
|
#define PMU_MISC0_CLR_REFTOP_PWD_MASK (0x1U)
|
|
#define PMU_MISC0_CLR_REFTOP_PWD_SHIFT (0U)
|
|
#define PMU_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_PWD_SHIFT)) & PMU_MISC0_CLR_REFTOP_PWD_MASK)
|
|
#define PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)
|
|
#define PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)
|
|
/*! REFTOP_SELFBIASOFF
|
|
* 0b0..Uses coarse bias currents for startup
|
|
* 0b1..Uses bandgap-based bias currents for best performance.
|
|
*/
|
|
#define PMU_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)
|
|
#define PMU_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)
|
|
#define PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)
|
|
/*! REFTOP_VBGADJ
|
|
* 0b000..Nominal VBG
|
|
* 0b001..VBG+0.78%
|
|
* 0b010..VBG+1.56%
|
|
* 0b011..VBG+2.34%
|
|
* 0b100..VBG-0.78%
|
|
* 0b101..VBG-1.56%
|
|
* 0b110..VBG-2.34%
|
|
* 0b111..VBG-3.12%
|
|
*/
|
|
#define PMU_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGADJ_MASK)
|
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#define PMU_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)
|
|
#define PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)
|
|
#define PMU_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGUP_MASK)
|
|
#define PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)
|
|
#define PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)
|
|
/*! STOP_MODE_CONFIG
|
|
* 0b00..SUSPEND (DSM)
|
|
* 0b01..Analog regulators are ON.
|
|
* 0b10..STOP (lower power)
|
|
* 0b11..STOP (very lower power)
|
|
*/
|
|
#define PMU_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK)
|
|
#define PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)
|
|
#define PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)
|
|
/*! DISCON_HIGH_SNVS
|
|
* 0b0..Turn on the switch
|
|
* 0b1..Turn off the switch
|
|
*/
|
|
#define PMU_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK)
|
|
#define PMU_MISC0_CLR_OSC_I_MASK (0x6000U)
|
|
#define PMU_MISC0_CLR_OSC_I_SHIFT (13U)
|
|
/*! OSC_I
|
|
* 0b00..Nominal
|
|
* 0b01..Decrease current by 12.5%
|
|
* 0b10..Decrease current by 25.0%
|
|
* 0b11..Decrease current by 37.5%
|
|
*/
|
|
#define PMU_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_I_SHIFT)) & PMU_MISC0_CLR_OSC_I_MASK)
|
|
#define PMU_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)
|
|
#define PMU_MISC0_CLR_OSC_XTALOK_SHIFT (15U)
|
|
#define PMU_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_MASK)
|
|
#define PMU_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)
|
|
#define PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)
|
|
#define PMU_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_EN_MASK)
|
|
#define PMU_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)
|
|
#define PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)
|
|
/*! CLKGATE_CTRL
|
|
* 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
|
|
* 0b1..Prevent the logic from ever gating off the clock.
|
|
*/
|
|
#define PMU_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLR_CLKGATE_CTRL_MASK)
|
|
#define PMU_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)
|
|
#define PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)
|
|
/*! CLKGATE_DELAY
|
|
* 0b000..0.5ms
|
|
* 0b001..1.0ms
|
|
* 0b010..2.0ms
|
|
* 0b011..3.0ms
|
|
* 0b100..4.0ms
|
|
* 0b101..5.0ms
|
|
* 0b110..6.0ms
|
|
* 0b111..7.0ms
|
|
*/
|
|
#define PMU_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLR_CLKGATE_DELAY_MASK)
|
|
#define PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)
|
|
#define PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)
|
|
/*! RTC_XTAL_SOURCE
|
|
* 0b0..Internal ring oscillator
|
|
* 0b1..RTC_XTAL
|
|
*/
|
|
#define PMU_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK)
|
|
#define PMU_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)
|
|
#define PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)
|
|
#define PMU_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_CLR_XTAL_24M_PWD_MASK)
|
|
#define PMU_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U)
|
|
#define PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U)
|
|
/*! VID_PLL_PREDIV
|
|
* 0b0..Divide by 1
|
|
* 0b1..Divide by 2
|
|
*/
|
|
#define PMU_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_CLR_VID_PLL_PREDIV_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MISC0_TOG - Miscellaneous Register 0 */
|
|
/*! @{ */
|
|
#define PMU_MISC0_TOG_REFTOP_PWD_MASK (0x1U)
|
|
#define PMU_MISC0_TOG_REFTOP_PWD_SHIFT (0U)
|
|
#define PMU_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_PWD_SHIFT)) & PMU_MISC0_TOG_REFTOP_PWD_MASK)
|
|
#define PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)
|
|
#define PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)
|
|
/*! REFTOP_SELFBIASOFF
|
|
* 0b0..Uses coarse bias currents for startup
|
|
* 0b1..Uses bandgap-based bias currents for best performance.
|
|
*/
|
|
#define PMU_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)
|
|
#define PMU_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)
|
|
#define PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)
|
|
/*! REFTOP_VBGADJ
|
|
* 0b000..Nominal VBG
|
|
* 0b001..VBG+0.78%
|
|
* 0b010..VBG+1.56%
|
|
* 0b011..VBG+2.34%
|
|
* 0b100..VBG-0.78%
|
|
* 0b101..VBG-1.56%
|
|
* 0b110..VBG-2.34%
|
|
* 0b111..VBG-3.12%
|
|
*/
|
|
#define PMU_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGADJ_MASK)
|
|
#define PMU_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)
|
|
#define PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)
|
|
#define PMU_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGUP_MASK)
|
|
#define PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)
|
|
#define PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)
|
|
/*! STOP_MODE_CONFIG
|
|
* 0b00..SUSPEND (DSM)
|
|
* 0b01..Analog regulators are ON.
|
|
* 0b10..STOP (lower power)
|
|
* 0b11..STOP (very lower power)
|
|
*/
|
|
#define PMU_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK)
|
|
#define PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)
|
|
#define PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)
|
|
/*! DISCON_HIGH_SNVS
|
|
* 0b0..Turn on the switch
|
|
* 0b1..Turn off the switch
|
|
*/
|
|
#define PMU_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK)
|
|
#define PMU_MISC0_TOG_OSC_I_MASK (0x6000U)
|
|
#define PMU_MISC0_TOG_OSC_I_SHIFT (13U)
|
|
/*! OSC_I
|
|
* 0b00..Nominal
|
|
* 0b01..Decrease current by 12.5%
|
|
* 0b10..Decrease current by 25.0%
|
|
* 0b11..Decrease current by 37.5%
|
|
*/
|
|
#define PMU_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_I_SHIFT)) & PMU_MISC0_TOG_OSC_I_MASK)
|
|
#define PMU_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)
|
|
#define PMU_MISC0_TOG_OSC_XTALOK_SHIFT (15U)
|
|
#define PMU_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_MASK)
|
|
#define PMU_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)
|
|
#define PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)
|
|
#define PMU_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_EN_MASK)
|
|
#define PMU_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)
|
|
#define PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)
|
|
/*! CLKGATE_CTRL
|
|
* 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
|
|
* 0b1..Prevent the logic from ever gating off the clock.
|
|
*/
|
|
#define PMU_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_TOG_CLKGATE_CTRL_MASK)
|
|
#define PMU_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)
|
|
#define PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)
|
|
/*! CLKGATE_DELAY
|
|
* 0b000..0.5ms
|
|
* 0b001..1.0ms
|
|
* 0b010..2.0ms
|
|
* 0b011..3.0ms
|
|
* 0b100..4.0ms
|
|
* 0b101..5.0ms
|
|
* 0b110..6.0ms
|
|
* 0b111..7.0ms
|
|
*/
|
|
#define PMU_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_TOG_CLKGATE_DELAY_MASK)
|
|
#define PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)
|
|
#define PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)
|
|
/*! RTC_XTAL_SOURCE
|
|
* 0b0..Internal ring oscillator
|
|
* 0b1..RTC_XTAL
|
|
*/
|
|
#define PMU_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK)
|
|
#define PMU_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)
|
|
#define PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)
|
|
#define PMU_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_TOG_XTAL_24M_PWD_MASK)
|
|
#define PMU_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U)
|
|
#define PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U)
|
|
/*! VID_PLL_PREDIV
|
|
* 0b0..Divide by 1
|
|
* 0b1..Divide by 2
|
|
*/
|
|
#define PMU_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_TOG_VID_PLL_PREDIV_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MISC1 - Miscellaneous Register 1 */
|
|
/*! @{ */
|
|
#define PMU_MISC1_LVDS1_CLK_SEL_MASK (0x1FU)
|
|
#define PMU_MISC1_LVDS1_CLK_SEL_SHIFT (0U)
|
|
/*! LVDS1_CLK_SEL
|
|
* 0b00000..Arm PLL
|
|
* 0b00001..System PLL
|
|
* 0b00010..ref_pfd4_clk == pll2_pfd0_clk
|
|
* 0b00011..ref_pfd5_clk == pll2_pfd1_clk
|
|
* 0b00100..ref_pfd6_clk == pll2_pfd2_clk
|
|
* 0b00101..ref_pfd7_clk == pll2_pfd3_clk
|
|
* 0b00110..Audio PLL
|
|
* 0b00111..Video PLL
|
|
* 0b01001..ethernet ref clock (ENET_PLL)
|
|
* 0b01100..USB1 PLL clock
|
|
* 0b01101..USB2 PLL clock
|
|
* 0b01110..ref_pfd0_clk == pll3_pfd0_clk
|
|
* 0b01111..ref_pfd1_clk == pll3_pfd1_clk
|
|
* 0b10000..ref_pfd2_clk == pll3_pfd2_clk
|
|
* 0b10001..ref_pfd3_clk == pll3_pfd3_clk
|
|
* 0b10010..xtal (24M)
|
|
*/
|
|
#define PMU_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS1_CLK_SEL_MASK)
|
|
#define PMU_MISC1_LVDS2_CLK_SEL_MASK (0x3E0U)
|
|
#define PMU_MISC1_LVDS2_CLK_SEL_SHIFT (5U)
|
|
/*! LVDS2_CLK_SEL
|
|
* 0b00000..Arm PLL
|
|
* 0b00001..System PLL
|
|
* 0b00010..ref_pfd4_clk == pll2_pfd0_clk
|
|
* 0b00011..ref_pfd5_clk == pll2_pfd1_clk
|
|
* 0b00100..ref_pfd6_clk == pll2_pfd2_clk
|
|
* 0b00101..ref_pfd7_clk == pll2_pfd3_clk
|
|
* 0b00110..Audio PLL
|
|
* 0b00111..Video PLL
|
|
* 0b01000..MLB PLL
|
|
* 0b01001..ethernet ref clock (ENET_PLL)
|
|
* 0b01010..PCIe ref clock (125M)
|
|
* 0b01011..SATA ref clock (100M)
|
|
* 0b01100..USB1 PLL clock
|
|
* 0b01101..USB2 PLL clock
|
|
* 0b01110..ref_pfd0_clk == pll3_pfd0_clk
|
|
* 0b01111..ref_pfd1_clk == pll3_pfd1_clk
|
|
* 0b10000..ref_pfd2_clk == pll3_pfd2_clk
|
|
* 0b10001..ref_pfd3_clk == pll3_pfd3_clk
|
|
* 0b10010..xtal (24M)
|
|
* 0b10011..LVDS1 (loopback)
|
|
* 0b10100..LVDS2 (not useful)
|
|
*/
|
|
#define PMU_MISC1_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS2_CLK_SEL_MASK)
|
|
#define PMU_MISC1_LVDSCLK1_OBEN_MASK (0x400U)
|
|
#define PMU_MISC1_LVDSCLK1_OBEN_SHIFT (10U)
|
|
#define PMU_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_OBEN_MASK)
|
|
#define PMU_MISC1_LVDSCLK2_OBEN_MASK (0x800U)
|
|
#define PMU_MISC1_LVDSCLK2_OBEN_SHIFT (11U)
|
|
#define PMU_MISC1_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_OBEN_MASK)
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#define PMU_MISC1_LVDSCLK1_IBEN_MASK (0x1000U)
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#define PMU_MISC1_LVDSCLK1_IBEN_SHIFT (12U)
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#define PMU_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_IBEN_MASK)
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#define PMU_MISC1_LVDSCLK2_IBEN_MASK (0x2000U)
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#define PMU_MISC1_LVDSCLK2_IBEN_SHIFT (13U)
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#define PMU_MISC1_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_IBEN_MASK)
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#define PMU_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U)
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#define PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U)
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#define PMU_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_480_AUTOGATE_EN_MASK)
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#define PMU_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U)
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#define PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U)
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#define PMU_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_528_AUTOGATE_EN_MASK)
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#define PMU_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U)
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#define PMU_MISC1_IRQ_TEMPPANIC_SHIFT (27U)
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#define PMU_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_IRQ_TEMPPANIC_MASK)
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#define PMU_MISC1_IRQ_TEMPLOW_MASK (0x10000000U)
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#define PMU_MISC1_IRQ_TEMPLOW_SHIFT (28U)
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#define PMU_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_IRQ_TEMPLOW_MASK)
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#define PMU_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U)
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#define PMU_MISC1_IRQ_TEMPHIGH_SHIFT (29U)
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#define PMU_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_IRQ_TEMPHIGH_MASK)
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#define PMU_MISC1_IRQ_ANA_BO_MASK (0x40000000U)
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#define PMU_MISC1_IRQ_ANA_BO_SHIFT (30U)
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#define PMU_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_IRQ_ANA_BO_MASK)
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#define PMU_MISC1_IRQ_DIG_BO_MASK (0x80000000U)
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#define PMU_MISC1_IRQ_DIG_BO_SHIFT (31U)
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#define PMU_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_IRQ_DIG_BO_MASK)
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/*! @} */
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/*! @name MISC1_SET - Miscellaneous Register 1 */
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/*! @{ */
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#define PMU_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU)
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#define PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U)
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/*! LVDS1_CLK_SEL
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* 0b00000..Arm PLL
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* 0b00001..System PLL
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* 0b00010..ref_pfd4_clk == pll2_pfd0_clk
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* 0b00011..ref_pfd5_clk == pll2_pfd1_clk
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* 0b00100..ref_pfd6_clk == pll2_pfd2_clk
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* 0b00101..ref_pfd7_clk == pll2_pfd3_clk
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* 0b00110..Audio PLL
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* 0b00111..Video PLL
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* 0b01001..ethernet ref clock (ENET_PLL)
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* 0b01100..USB1 PLL clock
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* 0b01101..USB2 PLL clock
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* 0b01110..ref_pfd0_clk == pll3_pfd0_clk
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* 0b01111..ref_pfd1_clk == pll3_pfd1_clk
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* 0b10000..ref_pfd2_clk == pll3_pfd2_clk
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* 0b10001..ref_pfd3_clk == pll3_pfd3_clk
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* 0b10010..xtal (24M)
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*/
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#define PMU_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS1_CLK_SEL_MASK)
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#define PMU_MISC1_SET_LVDS2_CLK_SEL_MASK (0x3E0U)
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#define PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT (5U)
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/*! LVDS2_CLK_SEL
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* 0b00000..Arm PLL
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* 0b00001..System PLL
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* 0b00010..ref_pfd4_clk == pll2_pfd0_clk
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* 0b00011..ref_pfd5_clk == pll2_pfd1_clk
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* 0b00100..ref_pfd6_clk == pll2_pfd2_clk
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* 0b00101..ref_pfd7_clk == pll2_pfd3_clk
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* 0b00110..Audio PLL
|
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* 0b00111..Video PLL
|
|
* 0b01000..MLB PLL
|
|
* 0b01001..ethernet ref clock (ENET_PLL)
|
|
* 0b01010..PCIe ref clock (125M)
|
|
* 0b01011..SATA ref clock (100M)
|
|
* 0b01100..USB1 PLL clock
|
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* 0b01101..USB2 PLL clock
|
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* 0b01110..ref_pfd0_clk == pll3_pfd0_clk
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* 0b01111..ref_pfd1_clk == pll3_pfd1_clk
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* 0b10000..ref_pfd2_clk == pll3_pfd2_clk
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* 0b10001..ref_pfd3_clk == pll3_pfd3_clk
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* 0b10010..xtal (24M)
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* 0b10011..LVDS1 (loopback)
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* 0b10100..LVDS2 (not useful)
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*/
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#define PMU_MISC1_SET_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS2_CLK_SEL_MASK)
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#define PMU_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U)
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#define PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U)
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#define PMU_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_OBEN_MASK)
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#define PMU_MISC1_SET_LVDSCLK2_OBEN_MASK (0x800U)
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#define PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT (11U)
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#define PMU_MISC1_SET_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_OBEN_MASK)
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#define PMU_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U)
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#define PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U)
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#define PMU_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_IBEN_MASK)
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#define PMU_MISC1_SET_LVDSCLK2_IBEN_MASK (0x2000U)
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#define PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT (13U)
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#define PMU_MISC1_SET_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_IBEN_MASK)
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#define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U)
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#define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U)
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#define PMU_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK)
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#define PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U)
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#define PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U)
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#define PMU_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK)
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#define PMU_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U)
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#define PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U)
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#define PMU_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPPANIC_MASK)
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#define PMU_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U)
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#define PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U)
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#define PMU_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPLOW_MASK)
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#define PMU_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U)
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#define PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U)
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#define PMU_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPHIGH_MASK)
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#define PMU_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U)
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#define PMU_MISC1_SET_IRQ_ANA_BO_SHIFT (30U)
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#define PMU_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_SET_IRQ_ANA_BO_MASK)
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#define PMU_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U)
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#define PMU_MISC1_SET_IRQ_DIG_BO_SHIFT (31U)
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#define PMU_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_SET_IRQ_DIG_BO_MASK)
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/*! @} */
|
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/*! @name MISC1_CLR - Miscellaneous Register 1 */
|
|
/*! @{ */
|
|
#define PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU)
|
|
#define PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U)
|
|
/*! LVDS1_CLK_SEL
|
|
* 0b00000..Arm PLL
|
|
* 0b00001..System PLL
|
|
* 0b00010..ref_pfd4_clk == pll2_pfd0_clk
|
|
* 0b00011..ref_pfd5_clk == pll2_pfd1_clk
|
|
* 0b00100..ref_pfd6_clk == pll2_pfd2_clk
|
|
* 0b00101..ref_pfd7_clk == pll2_pfd3_clk
|
|
* 0b00110..Audio PLL
|
|
* 0b00111..Video PLL
|
|
* 0b01001..ethernet ref clock (ENET_PLL)
|
|
* 0b01100..USB1 PLL clock
|
|
* 0b01101..USB2 PLL clock
|
|
* 0b01110..ref_pfd0_clk == pll3_pfd0_clk
|
|
* 0b01111..ref_pfd1_clk == pll3_pfd1_clk
|
|
* 0b10000..ref_pfd2_clk == pll3_pfd2_clk
|
|
* 0b10001..ref_pfd3_clk == pll3_pfd3_clk
|
|
* 0b10010..xtal (24M)
|
|
*/
|
|
#define PMU_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK)
|
|
#define PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK (0x3E0U)
|
|
#define PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT (5U)
|
|
/*! LVDS2_CLK_SEL
|
|
* 0b00000..Arm PLL
|
|
* 0b00001..System PLL
|
|
* 0b00010..ref_pfd4_clk == pll2_pfd0_clk
|
|
* 0b00011..ref_pfd5_clk == pll2_pfd1_clk
|
|
* 0b00100..ref_pfd6_clk == pll2_pfd2_clk
|
|
* 0b00101..ref_pfd7_clk == pll2_pfd3_clk
|
|
* 0b00110..Audio PLL
|
|
* 0b00111..Video PLL
|
|
* 0b01000..MLB PLL
|
|
* 0b01001..ethernet ref clock (ENET_PLL)
|
|
* 0b01010..PCIe ref clock (125M)
|
|
* 0b01011..SATA ref clock (100M)
|
|
* 0b01100..USB1 PLL clock
|
|
* 0b01101..USB2 PLL clock
|
|
* 0b01110..ref_pfd0_clk == pll3_pfd0_clk
|
|
* 0b01111..ref_pfd1_clk == pll3_pfd1_clk
|
|
* 0b10000..ref_pfd2_clk == pll3_pfd2_clk
|
|
* 0b10001..ref_pfd3_clk == pll3_pfd3_clk
|
|
* 0b10010..xtal (24M)
|
|
* 0b10011..LVDS1 (loopback)
|
|
* 0b10100..LVDS2 (not useful)
|
|
*/
|
|
#define PMU_MISC1_CLR_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK)
|
|
#define PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U)
|
|
#define PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U)
|
|
#define PMU_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK)
|
|
#define PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK (0x800U)
|
|
#define PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT (11U)
|
|
#define PMU_MISC1_CLR_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK)
|
|
#define PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U)
|
|
#define PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U)
|
|
#define PMU_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK)
|
|
#define PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK (0x2000U)
|
|
#define PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT (13U)
|
|
#define PMU_MISC1_CLR_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK)
|
|
#define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U)
|
|
#define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U)
|
|
#define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK)
|
|
#define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U)
|
|
#define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U)
|
|
#define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK)
|
|
#define PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U)
|
|
#define PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U)
|
|
#define PMU_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK)
|
|
#define PMU_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U)
|
|
#define PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U)
|
|
#define PMU_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPLOW_MASK)
|
|
#define PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U)
|
|
#define PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U)
|
|
#define PMU_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK)
|
|
#define PMU_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U)
|
|
#define PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U)
|
|
#define PMU_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_ANA_BO_MASK)
|
|
#define PMU_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U)
|
|
#define PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U)
|
|
#define PMU_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_DIG_BO_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MISC1_TOG - Miscellaneous Register 1 */
|
|
/*! @{ */
|
|
#define PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU)
|
|
#define PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U)
|
|
/*! LVDS1_CLK_SEL
|
|
* 0b00000..Arm PLL
|
|
* 0b00001..System PLL
|
|
* 0b00010..ref_pfd4_clk == pll2_pfd0_clk
|
|
* 0b00011..ref_pfd5_clk == pll2_pfd1_clk
|
|
* 0b00100..ref_pfd6_clk == pll2_pfd2_clk
|
|
* 0b00101..ref_pfd7_clk == pll2_pfd3_clk
|
|
* 0b00110..Audio PLL
|
|
* 0b00111..Video PLL
|
|
* 0b01001..ethernet ref clock (ENET_PLL)
|
|
* 0b01100..USB1 PLL clock
|
|
* 0b01101..USB2 PLL clock
|
|
* 0b01110..ref_pfd0_clk == pll3_pfd0_clk
|
|
* 0b01111..ref_pfd1_clk == pll3_pfd1_clk
|
|
* 0b10000..ref_pfd2_clk == pll3_pfd2_clk
|
|
* 0b10001..ref_pfd3_clk == pll3_pfd3_clk
|
|
* 0b10010..xtal (24M)
|
|
*/
|
|
#define PMU_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK)
|
|
#define PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK (0x3E0U)
|
|
#define PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT (5U)
|
|
/*! LVDS2_CLK_SEL
|
|
* 0b00000..Arm PLL
|
|
* 0b00001..System PLL
|
|
* 0b00010..ref_pfd4_clk == pll2_pfd0_clk
|
|
* 0b00011..ref_pfd5_clk == pll2_pfd1_clk
|
|
* 0b00100..ref_pfd6_clk == pll2_pfd2_clk
|
|
* 0b00101..ref_pfd7_clk == pll2_pfd3_clk
|
|
* 0b00110..Audio PLL
|
|
* 0b00111..Video PLL
|
|
* 0b01000..MLB PLL
|
|
* 0b01001..ethernet ref clock (ENET_PLL)
|
|
* 0b01010..PCIe ref clock (125M)
|
|
* 0b01011..SATA ref clock (100M)
|
|
* 0b01100..USB1 PLL clock
|
|
* 0b01101..USB2 PLL clock
|
|
* 0b01110..ref_pfd0_clk == pll3_pfd0_clk
|
|
* 0b01111..ref_pfd1_clk == pll3_pfd1_clk
|
|
* 0b10000..ref_pfd2_clk == pll3_pfd2_clk
|
|
* 0b10001..ref_pfd3_clk == pll3_pfd3_clk
|
|
* 0b10010..xtal (24M)
|
|
* 0b10011..LVDS1 (loopback)
|
|
* 0b10100..LVDS2 (not useful)
|
|
*/
|
|
#define PMU_MISC1_TOG_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK)
|
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#define PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U)
|
|
#define PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U)
|
|
#define PMU_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK)
|
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#define PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK (0x800U)
|
|
#define PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT (11U)
|
|
#define PMU_MISC1_TOG_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK)
|
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#define PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U)
|
|
#define PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U)
|
|
#define PMU_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK)
|
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#define PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK (0x2000U)
|
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#define PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT (13U)
|
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#define PMU_MISC1_TOG_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK)
|
|
#define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U)
|
|
#define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U)
|
|
#define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK)
|
|
#define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U)
|
|
#define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U)
|
|
#define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK)
|
|
#define PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U)
|
|
#define PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U)
|
|
#define PMU_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK)
|
|
#define PMU_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U)
|
|
#define PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U)
|
|
#define PMU_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPLOW_MASK)
|
|
#define PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U)
|
|
#define PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U)
|
|
#define PMU_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK)
|
|
#define PMU_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U)
|
|
#define PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U)
|
|
#define PMU_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_ANA_BO_MASK)
|
|
#define PMU_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U)
|
|
#define PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U)
|
|
#define PMU_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_DIG_BO_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MISC2 - Miscellaneous Control Register */
|
|
/*! @{ */
|
|
#define PMU_MISC2_REG0_BO_OFFSET_MASK (0x7U)
|
|
#define PMU_MISC2_REG0_BO_OFFSET_SHIFT (0U)
|
|
/*! REG0_BO_OFFSET
|
|
* 0b100..Brownout offset = 0.100V
|
|
* 0b111..Brownout offset = 0.175V
|
|
*/
|
|
#define PMU_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_REG0_BO_OFFSET_MASK)
|
|
#define PMU_MISC2_REG0_BO_STATUS_MASK (0x8U)
|
|
#define PMU_MISC2_REG0_BO_STATUS_SHIFT (3U)
|
|
/*! REG0_BO_STATUS
|
|
* 0b1..Brownout, supply is below target minus brownout offset.
|
|
*/
|
|
#define PMU_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_REG0_BO_STATUS_MASK)
|
|
#define PMU_MISC2_REG0_ENABLE_BO_MASK (0x20U)
|
|
#define PMU_MISC2_REG0_ENABLE_BO_SHIFT (5U)
|
|
#define PMU_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_REG0_ENABLE_BO_MASK)
|
|
#define PMU_MISC2_PLL3_disable_MASK (0x80U)
|
|
#define PMU_MISC2_PLL3_disable_SHIFT (7U)
|
|
#define PMU_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_PLL3_disable_SHIFT)) & PMU_MISC2_PLL3_disable_MASK)
|
|
#define PMU_MISC2_REG1_BO_OFFSET_MASK (0x700U)
|
|
#define PMU_MISC2_REG1_BO_OFFSET_SHIFT (8U)
|
|
/*! REG1_BO_OFFSET
|
|
* 0b100..Brownout offset = 0.100V
|
|
* 0b111..Brownout offset = 0.175V
|
|
*/
|
|
#define PMU_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_REG1_BO_OFFSET_MASK)
|
|
#define PMU_MISC2_REG1_BO_STATUS_MASK (0x800U)
|
|
#define PMU_MISC2_REG1_BO_STATUS_SHIFT (11U)
|
|
/*! REG1_BO_STATUS
|
|
* 0b1..Brownout, supply is below target minus brownout offset.
|
|
*/
|
|
#define PMU_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_REG1_BO_STATUS_MASK)
|
|
#define PMU_MISC2_REG1_ENABLE_BO_MASK (0x2000U)
|
|
#define PMU_MISC2_REG1_ENABLE_BO_SHIFT (13U)
|
|
#define PMU_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_REG1_ENABLE_BO_MASK)
|
|
#define PMU_MISC2_AUDIO_DIV_LSB_MASK (0x8000U)
|
|
#define PMU_MISC2_AUDIO_DIV_LSB_SHIFT (15U)
|
|
/*! AUDIO_DIV_LSB
|
|
* 0b0..divide by 1 (Default)
|
|
* 0b1..divide by 2
|
|
*/
|
|
#define PMU_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_LSB_MASK)
|
|
#define PMU_MISC2_REG2_BO_OFFSET_MASK (0x70000U)
|
|
#define PMU_MISC2_REG2_BO_OFFSET_SHIFT (16U)
|
|
/*! REG2_BO_OFFSET
|
|
* 0b100..Brownout offset = 0.100V
|
|
* 0b111..Brownout offset = 0.175V
|
|
*/
|
|
#define PMU_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_REG2_BO_OFFSET_MASK)
|
|
#define PMU_MISC2_REG2_BO_STATUS_MASK (0x80000U)
|
|
#define PMU_MISC2_REG2_BO_STATUS_SHIFT (19U)
|
|
#define PMU_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_REG2_BO_STATUS_MASK)
|
|
#define PMU_MISC2_REG2_ENABLE_BO_MASK (0x200000U)
|
|
#define PMU_MISC2_REG2_ENABLE_BO_SHIFT (21U)
|
|
#define PMU_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_REG2_ENABLE_BO_MASK)
|
|
#define PMU_MISC2_REG2_OK_MASK (0x400000U)
|
|
#define PMU_MISC2_REG2_OK_SHIFT (22U)
|
|
#define PMU_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_OK_SHIFT)) & PMU_MISC2_REG2_OK_MASK)
|
|
#define PMU_MISC2_AUDIO_DIV_MSB_MASK (0x800000U)
|
|
#define PMU_MISC2_AUDIO_DIV_MSB_SHIFT (23U)
|
|
/*! AUDIO_DIV_MSB
|
|
* 0b0..divide by 1 (Default)
|
|
* 0b1..divide by 2
|
|
*/
|
|
#define PMU_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_MSB_MASK)
|
|
#define PMU_MISC2_REG0_STEP_TIME_MASK (0x3000000U)
|
|
#define PMU_MISC2_REG0_STEP_TIME_SHIFT (24U)
|
|
/*! REG0_STEP_TIME
|
|
* 0b00..64
|
|
* 0b01..128
|
|
* 0b10..256
|
|
* 0b11..512
|
|
*/
|
|
#define PMU_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_REG0_STEP_TIME_MASK)
|
|
#define PMU_MISC2_REG1_STEP_TIME_MASK (0xC000000U)
|
|
#define PMU_MISC2_REG1_STEP_TIME_SHIFT (26U)
|
|
/*! REG1_STEP_TIME
|
|
* 0b00..64
|
|
* 0b01..128
|
|
* 0b10..256
|
|
* 0b11..512
|
|
*/
|
|
#define PMU_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_REG1_STEP_TIME_MASK)
|
|
#define PMU_MISC2_REG2_STEP_TIME_MASK (0x30000000U)
|
|
#define PMU_MISC2_REG2_STEP_TIME_SHIFT (28U)
|
|
/*! REG2_STEP_TIME
|
|
* 0b00..64
|
|
* 0b01..128
|
|
* 0b10..256
|
|
* 0b11..512
|
|
*/
|
|
#define PMU_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_REG2_STEP_TIME_MASK)
|
|
#define PMU_MISC2_VIDEO_DIV_MASK (0xC0000000U)
|
|
#define PMU_MISC2_VIDEO_DIV_SHIFT (30U)
|
|
/*! VIDEO_DIV
|
|
* 0b00..divide by 1 (Default)
|
|
* 0b01..divide by 2
|
|
* 0b10..divide by 1
|
|
* 0b11..divide by 4
|
|
*/
|
|
#define PMU_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_VIDEO_DIV_SHIFT)) & PMU_MISC2_VIDEO_DIV_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MISC2_SET - Miscellaneous Control Register */
|
|
/*! @{ */
|
|
#define PMU_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U)
|
|
#define PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U)
|
|
/*! REG0_BO_OFFSET
|
|
* 0b100..Brownout offset = 0.100V
|
|
* 0b111..Brownout offset = 0.175V
|
|
*/
|
|
#define PMU_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG0_BO_OFFSET_MASK)
|
|
#define PMU_MISC2_SET_REG0_BO_STATUS_MASK (0x8U)
|
|
#define PMU_MISC2_SET_REG0_BO_STATUS_SHIFT (3U)
|
|
/*! REG0_BO_STATUS
|
|
* 0b1..Brownout, supply is below target minus brownout offset.
|
|
*/
|
|
#define PMU_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG0_BO_STATUS_MASK)
|
|
#define PMU_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U)
|
|
#define PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U)
|
|
#define PMU_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG0_ENABLE_BO_MASK)
|
|
#define PMU_MISC2_SET_PLL3_disable_MASK (0x80U)
|
|
#define PMU_MISC2_SET_PLL3_disable_SHIFT (7U)
|
|
#define PMU_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_PLL3_disable_SHIFT)) & PMU_MISC2_SET_PLL3_disable_MASK)
|
|
#define PMU_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U)
|
|
#define PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U)
|
|
/*! REG1_BO_OFFSET
|
|
* 0b100..Brownout offset = 0.100V
|
|
* 0b111..Brownout offset = 0.175V
|
|
*/
|
|
#define PMU_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG1_BO_OFFSET_MASK)
|
|
#define PMU_MISC2_SET_REG1_BO_STATUS_MASK (0x800U)
|
|
#define PMU_MISC2_SET_REG1_BO_STATUS_SHIFT (11U)
|
|
/*! REG1_BO_STATUS
|
|
* 0b1..Brownout, supply is below target minus brownout offset.
|
|
*/
|
|
#define PMU_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG1_BO_STATUS_MASK)
|
|
#define PMU_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U)
|
|
#define PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U)
|
|
#define PMU_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG1_ENABLE_BO_MASK)
|
|
#define PMU_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U)
|
|
#define PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U)
|
|
/*! AUDIO_DIV_LSB
|
|
* 0b0..divide by 1 (Default)
|
|
* 0b1..divide by 2
|
|
*/
|
|
#define PMU_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_LSB_MASK)
|
|
#define PMU_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U)
|
|
#define PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U)
|
|
/*! REG2_BO_OFFSET
|
|
* 0b100..Brownout offset = 0.100V
|
|
* 0b111..Brownout offset = 0.175V
|
|
*/
|
|
#define PMU_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG2_BO_OFFSET_MASK)
|
|
#define PMU_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U)
|
|
#define PMU_MISC2_SET_REG2_BO_STATUS_SHIFT (19U)
|
|
#define PMU_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG2_BO_STATUS_MASK)
|
|
#define PMU_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U)
|
|
#define PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U)
|
|
#define PMU_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG2_ENABLE_BO_MASK)
|
|
#define PMU_MISC2_SET_REG2_OK_MASK (0x400000U)
|
|
#define PMU_MISC2_SET_REG2_OK_SHIFT (22U)
|
|
#define PMU_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_OK_SHIFT)) & PMU_MISC2_SET_REG2_OK_MASK)
|
|
#define PMU_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U)
|
|
#define PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U)
|
|
/*! AUDIO_DIV_MSB
|
|
* 0b0..divide by 1 (Default)
|
|
* 0b1..divide by 2
|
|
*/
|
|
#define PMU_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_MSB_MASK)
|
|
#define PMU_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U)
|
|
#define PMU_MISC2_SET_REG0_STEP_TIME_SHIFT (24U)
|
|
/*! REG0_STEP_TIME
|
|
* 0b00..64
|
|
* 0b01..128
|
|
* 0b10..256
|
|
* 0b11..512
|
|
*/
|
|
#define PMU_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG0_STEP_TIME_MASK)
|
|
#define PMU_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U)
|
|
#define PMU_MISC2_SET_REG1_STEP_TIME_SHIFT (26U)
|
|
/*! REG1_STEP_TIME
|
|
* 0b00..64
|
|
* 0b01..128
|
|
* 0b10..256
|
|
* 0b11..512
|
|
*/
|
|
#define PMU_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG1_STEP_TIME_MASK)
|
|
#define PMU_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U)
|
|
#define PMU_MISC2_SET_REG2_STEP_TIME_SHIFT (28U)
|
|
/*! REG2_STEP_TIME
|
|
* 0b00..64
|
|
* 0b01..128
|
|
* 0b10..256
|
|
* 0b11..512
|
|
*/
|
|
#define PMU_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG2_STEP_TIME_MASK)
|
|
#define PMU_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U)
|
|
#define PMU_MISC2_SET_VIDEO_DIV_SHIFT (30U)
|
|
/*! VIDEO_DIV
|
|
* 0b00..divide by 1 (Default)
|
|
* 0b01..divide by 2
|
|
* 0b10..divide by 1
|
|
* 0b11..divide by 4
|
|
*/
|
|
#define PMU_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_VIDEO_DIV_SHIFT)) & PMU_MISC2_SET_VIDEO_DIV_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MISC2_CLR - Miscellaneous Control Register */
|
|
/*! @{ */
|
|
#define PMU_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U)
|
|
#define PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U)
|
|
/*! REG0_BO_OFFSET
|
|
* 0b100..Brownout offset = 0.100V
|
|
* 0b111..Brownout offset = 0.175V
|
|
*/
|
|
#define PMU_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG0_BO_OFFSET_MASK)
|
|
#define PMU_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U)
|
|
#define PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U)
|
|
/*! REG0_BO_STATUS
|
|
* 0b1..Brownout, supply is below target minus brownout offset.
|
|
*/
|
|
#define PMU_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG0_BO_STATUS_MASK)
|
|
#define PMU_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U)
|
|
#define PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U)
|
|
#define PMU_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG0_ENABLE_BO_MASK)
|
|
#define PMU_MISC2_CLR_PLL3_disable_MASK (0x80U)
|
|
#define PMU_MISC2_CLR_PLL3_disable_SHIFT (7U)
|
|
#define PMU_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_PLL3_disable_SHIFT)) & PMU_MISC2_CLR_PLL3_disable_MASK)
|
|
#define PMU_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U)
|
|
#define PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U)
|
|
/*! REG1_BO_OFFSET
|
|
* 0b100..Brownout offset = 0.100V
|
|
* 0b111..Brownout offset = 0.175V
|
|
*/
|
|
#define PMU_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG1_BO_OFFSET_MASK)
|
|
#define PMU_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U)
|
|
#define PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U)
|
|
/*! REG1_BO_STATUS
|
|
* 0b1..Brownout, supply is below target minus brownout offset.
|
|
*/
|
|
#define PMU_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG1_BO_STATUS_MASK)
|
|
#define PMU_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U)
|
|
#define PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U)
|
|
#define PMU_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG1_ENABLE_BO_MASK)
|
|
#define PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U)
|
|
#define PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U)
|
|
/*! AUDIO_DIV_LSB
|
|
* 0b0..divide by 1 (Default)
|
|
* 0b1..divide by 2
|
|
*/
|
|
#define PMU_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK)
|
|
#define PMU_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U)
|
|
#define PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U)
|
|
/*! REG2_BO_OFFSET
|
|
* 0b100..Brownout offset = 0.100V
|
|
* 0b111..Brownout offset = 0.175V
|
|
*/
|
|
#define PMU_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG2_BO_OFFSET_MASK)
|
|
#define PMU_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U)
|
|
#define PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U)
|
|
#define PMU_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG2_BO_STATUS_MASK)
|
|
#define PMU_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U)
|
|
#define PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U)
|
|
#define PMU_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG2_ENABLE_BO_MASK)
|
|
#define PMU_MISC2_CLR_REG2_OK_MASK (0x400000U)
|
|
#define PMU_MISC2_CLR_REG2_OK_SHIFT (22U)
|
|
#define PMU_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_OK_SHIFT)) & PMU_MISC2_CLR_REG2_OK_MASK)
|
|
#define PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U)
|
|
#define PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U)
|
|
/*! AUDIO_DIV_MSB
|
|
* 0b0..divide by 1 (Default)
|
|
* 0b1..divide by 2
|
|
*/
|
|
#define PMU_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK)
|
|
#define PMU_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U)
|
|
#define PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U)
|
|
/*! REG0_STEP_TIME
|
|
* 0b00..64
|
|
* 0b01..128
|
|
* 0b10..256
|
|
* 0b11..512
|
|
*/
|
|
#define PMU_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG0_STEP_TIME_MASK)
|
|
#define PMU_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U)
|
|
#define PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U)
|
|
/*! REG1_STEP_TIME
|
|
* 0b00..64
|
|
* 0b01..128
|
|
* 0b10..256
|
|
* 0b11..512
|
|
*/
|
|
#define PMU_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG1_STEP_TIME_MASK)
|
|
#define PMU_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U)
|
|
#define PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U)
|
|
/*! REG2_STEP_TIME
|
|
* 0b00..64
|
|
* 0b01..128
|
|
* 0b10..256
|
|
* 0b11..512
|
|
*/
|
|
#define PMU_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG2_STEP_TIME_MASK)
|
|
#define PMU_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U)
|
|
#define PMU_MISC2_CLR_VIDEO_DIV_SHIFT (30U)
|
|
/*! VIDEO_DIV
|
|
* 0b00..divide by 1 (Default)
|
|
* 0b01..divide by 2
|
|
* 0b10..divide by 1
|
|
* 0b11..divide by 4
|
|
*/
|
|
#define PMU_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_VIDEO_DIV_SHIFT)) & PMU_MISC2_CLR_VIDEO_DIV_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MISC2_TOG - Miscellaneous Control Register */
|
|
/*! @{ */
|
|
#define PMU_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U)
|
|
#define PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U)
|
|
/*! REG0_BO_OFFSET
|
|
* 0b100..Brownout offset = 0.100V
|
|
* 0b111..Brownout offset = 0.175V
|
|
*/
|
|
#define PMU_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG0_BO_OFFSET_MASK)
|
|
#define PMU_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U)
|
|
#define PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U)
|
|
/*! REG0_BO_STATUS
|
|
* 0b1..Brownout, supply is below target minus brownout offset.
|
|
*/
|
|
#define PMU_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG0_BO_STATUS_MASK)
|
|
#define PMU_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U)
|
|
#define PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U)
|
|
#define PMU_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG0_ENABLE_BO_MASK)
|
|
#define PMU_MISC2_TOG_PLL3_disable_MASK (0x80U)
|
|
#define PMU_MISC2_TOG_PLL3_disable_SHIFT (7U)
|
|
#define PMU_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_PLL3_disable_SHIFT)) & PMU_MISC2_TOG_PLL3_disable_MASK)
|
|
#define PMU_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U)
|
|
#define PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U)
|
|
/*! REG1_BO_OFFSET
|
|
* 0b100..Brownout offset = 0.100V
|
|
* 0b111..Brownout offset = 0.175V
|
|
*/
|
|
#define PMU_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG1_BO_OFFSET_MASK)
|
|
#define PMU_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U)
|
|
#define PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U)
|
|
/*! REG1_BO_STATUS
|
|
* 0b1..Brownout, supply is below target minus brownout offset.
|
|
*/
|
|
#define PMU_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG1_BO_STATUS_MASK)
|
|
#define PMU_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U)
|
|
#define PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U)
|
|
#define PMU_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG1_ENABLE_BO_MASK)
|
|
#define PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U)
|
|
#define PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U)
|
|
/*! AUDIO_DIV_LSB
|
|
* 0b0..divide by 1 (Default)
|
|
* 0b1..divide by 2
|
|
*/
|
|
#define PMU_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK)
|
|
#define PMU_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U)
|
|
#define PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U)
|
|
/*! REG2_BO_OFFSET
|
|
* 0b100..Brownout offset = 0.100V
|
|
* 0b111..Brownout offset = 0.175V
|
|
*/
|
|
#define PMU_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG2_BO_OFFSET_MASK)
|
|
#define PMU_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U)
|
|
#define PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U)
|
|
#define PMU_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG2_BO_STATUS_MASK)
|
|
#define PMU_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U)
|
|
#define PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U)
|
|
#define PMU_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG2_ENABLE_BO_MASK)
|
|
#define PMU_MISC2_TOG_REG2_OK_MASK (0x400000U)
|
|
#define PMU_MISC2_TOG_REG2_OK_SHIFT (22U)
|
|
#define PMU_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_OK_SHIFT)) & PMU_MISC2_TOG_REG2_OK_MASK)
|
|
#define PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U)
|
|
#define PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U)
|
|
/*! AUDIO_DIV_MSB
|
|
* 0b0..divide by 1 (Default)
|
|
* 0b1..divide by 2
|
|
*/
|
|
#define PMU_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK)
|
|
#define PMU_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U)
|
|
#define PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U)
|
|
/*! REG0_STEP_TIME
|
|
* 0b00..64
|
|
* 0b01..128
|
|
* 0b10..256
|
|
* 0b11..512
|
|
*/
|
|
#define PMU_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG0_STEP_TIME_MASK)
|
|
#define PMU_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U)
|
|
#define PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U)
|
|
/*! REG1_STEP_TIME
|
|
* 0b00..64
|
|
* 0b01..128
|
|
* 0b10..256
|
|
* 0b11..512
|
|
*/
|
|
#define PMU_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG1_STEP_TIME_MASK)
|
|
#define PMU_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U)
|
|
#define PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U)
|
|
/*! REG2_STEP_TIME
|
|
* 0b00..64
|
|
* 0b01..128
|
|
* 0b10..256
|
|
* 0b11..512
|
|
*/
|
|
#define PMU_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG2_STEP_TIME_MASK)
|
|
#define PMU_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U)
|
|
#define PMU_MISC2_TOG_VIDEO_DIV_SHIFT (30U)
|
|
/*! VIDEO_DIV
|
|
* 0b00..divide by 1 (Default)
|
|
* 0b01..divide by 2
|
|
* 0b10..divide by 1
|
|
* 0b11..divide by 4
|
|
*/
|
|
#define PMU_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_VIDEO_DIV_SHIFT)) & PMU_MISC2_TOG_VIDEO_DIV_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group PMU_Register_Masks */
|
|
|
|
|
|
/* PMU - Peripheral instance base addresses */
|
|
/** Peripheral PMU base address */
|
|
#define PMU_BASE (0x400D8000u)
|
|
/** Peripheral PMU base pointer */
|
|
#define PMU ((PMU_Type *)PMU_BASE)
|
|
/** Array initializer of PMU peripheral base addresses */
|
|
#define PMU_BASE_ADDRS { PMU_BASE }
|
|
/** Array initializer of PMU peripheral base pointers */
|
|
#define PMU_BASE_PTRS { PMU }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group PMU_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- PWM Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** PWM - Register Layout Typedef */
|
|
typedef struct {
|
|
struct { /* offset: 0x0, array step: 0x60 */
|
|
__I uint16_t CNT; /**< Counter Register, array offset: 0x0, array step: 0x60 */
|
|
__IO uint16_t INIT; /**< Initial Count Register, array offset: 0x2, array step: 0x60 */
|
|
__IO uint16_t CTRL2; /**< Control 2 Register, array offset: 0x4, array step: 0x60 */
|
|
__IO uint16_t CTRL; /**< Control Register, array offset: 0x6, array step: 0x60 */
|
|
uint8_t RESERVED_0[2];
|
|
__IO uint16_t VAL0; /**< Value Register 0, array offset: 0xA, array step: 0x60 */
|
|
__IO uint16_t FRACVAL1; /**< Fractional Value Register 1, array offset: 0xC, array step: 0x60 */
|
|
__IO uint16_t VAL1; /**< Value Register 1, array offset: 0xE, array step: 0x60 */
|
|
__IO uint16_t FRACVAL2; /**< Fractional Value Register 2, array offset: 0x10, array step: 0x60 */
|
|
__IO uint16_t VAL2; /**< Value Register 2, array offset: 0x12, array step: 0x60 */
|
|
__IO uint16_t FRACVAL3; /**< Fractional Value Register 3, array offset: 0x14, array step: 0x60 */
|
|
__IO uint16_t VAL3; /**< Value Register 3, array offset: 0x16, array step: 0x60 */
|
|
__IO uint16_t FRACVAL4; /**< Fractional Value Register 4, array offset: 0x18, array step: 0x60 */
|
|
__IO uint16_t VAL4; /**< Value Register 4, array offset: 0x1A, array step: 0x60 */
|
|
__IO uint16_t FRACVAL5; /**< Fractional Value Register 5, array offset: 0x1C, array step: 0x60 */
|
|
__IO uint16_t VAL5; /**< Value Register 5, array offset: 0x1E, array step: 0x60 */
|
|
__IO uint16_t FRCTRL; /**< Fractional Control Register, array offset: 0x20, array step: 0x60 */
|
|
__IO uint16_t OCTRL; /**< Output Control Register, array offset: 0x22, array step: 0x60 */
|
|
__IO uint16_t STS; /**< Status Register, array offset: 0x24, array step: 0x60 */
|
|
__IO uint16_t INTEN; /**< Interrupt Enable Register, array offset: 0x26, array step: 0x60 */
|
|
__IO uint16_t DMAEN; /**< DMA Enable Register, array offset: 0x28, array step: 0x60 */
|
|
__IO uint16_t TCTRL; /**< Output Trigger Control Register, array offset: 0x2A, array step: 0x60 */
|
|
__IO uint16_t DISMAP[2]; /**< Fault Disable Mapping Register 0..Fault Disable Mapping Register 1, array offset: 0x2C, array step: index*0x60, index2*0x2 */
|
|
__IO uint16_t DTCNT0; /**< Deadtime Count Register 0, array offset: 0x30, array step: 0x60 */
|
|
__IO uint16_t DTCNT1; /**< Deadtime Count Register 1, array offset: 0x32, array step: 0x60 */
|
|
__IO uint16_t CAPTCTRLA; /**< Capture Control A Register, array offset: 0x34, array step: 0x60 */
|
|
__IO uint16_t CAPTCOMPA; /**< Capture Compare A Register, array offset: 0x36, array step: 0x60 */
|
|
__IO uint16_t CAPTCTRLB; /**< Capture Control B Register, array offset: 0x38, array step: 0x60 */
|
|
__IO uint16_t CAPTCOMPB; /**< Capture Compare B Register, array offset: 0x3A, array step: 0x60 */
|
|
__IO uint16_t CAPTCTRLX; /**< Capture Control X Register, array offset: 0x3C, array step: 0x60 */
|
|
__IO uint16_t CAPTCOMPX; /**< Capture Compare X Register, array offset: 0x3E, array step: 0x60 */
|
|
__I uint16_t CVAL0; /**< Capture Value 0 Register, array offset: 0x40, array step: 0x60 */
|
|
__I uint16_t CVAL0CYC; /**< Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60 */
|
|
__I uint16_t CVAL1; /**< Capture Value 1 Register, array offset: 0x44, array step: 0x60 */
|
|
__I uint16_t CVAL1CYC; /**< Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60 */
|
|
__I uint16_t CVAL2; /**< Capture Value 2 Register, array offset: 0x48, array step: 0x60 */
|
|
__I uint16_t CVAL2CYC; /**< Capture Value 2 Cycle Register, array offset: 0x4A, array step: 0x60 */
|
|
__I uint16_t CVAL3; /**< Capture Value 3 Register, array offset: 0x4C, array step: 0x60 */
|
|
__I uint16_t CVAL3CYC; /**< Capture Value 3 Cycle Register, array offset: 0x4E, array step: 0x60 */
|
|
__I uint16_t CVAL4; /**< Capture Value 4 Register, array offset: 0x50, array step: 0x60 */
|
|
__I uint16_t CVAL4CYC; /**< Capture Value 4 Cycle Register, array offset: 0x52, array step: 0x60 */
|
|
__I uint16_t CVAL5; /**< Capture Value 5 Register, array offset: 0x54, array step: 0x60 */
|
|
__I uint16_t CVAL5CYC; /**< Capture Value 5 Cycle Register, array offset: 0x56, array step: 0x60 */
|
|
uint8_t RESERVED_1[8];
|
|
} SM[4];
|
|
__IO uint16_t OUTEN; /**< Output Enable Register, offset: 0x180 */
|
|
__IO uint16_t MASK; /**< Mask Register, offset: 0x182 */
|
|
__IO uint16_t SWCOUT; /**< Software Controlled Output Register, offset: 0x184 */
|
|
__IO uint16_t DTSRCSEL; /**< PWM Source Select Register, offset: 0x186 */
|
|
__IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */
|
|
__IO uint16_t MCTRL2; /**< Master Control 2 Register, offset: 0x18A */
|
|
__IO uint16_t FCTRL; /**< Fault Control Register, offset: 0x18C */
|
|
__IO uint16_t FSTS; /**< Fault Status Register, offset: 0x18E */
|
|
__IO uint16_t FFILT; /**< Fault Filter Register, offset: 0x190 */
|
|
__IO uint16_t FTST; /**< Fault Test Register, offset: 0x192 */
|
|
__IO uint16_t FCTRL2; /**< Fault Control 2 Register, offset: 0x194 */
|
|
} PWM_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- PWM Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup PWM_Register_Masks PWM Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name CNT - Counter Register */
|
|
/*! @{ */
|
|
#define PWM_CNT_CNT_MASK (0xFFFFU)
|
|
#define PWM_CNT_CNT_SHIFT (0U)
|
|
#define PWM_CNT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_CNT */
|
|
#define PWM_CNT_COUNT (4U)
|
|
|
|
/*! @name INIT - Initial Count Register */
|
|
/*! @{ */
|
|
#define PWM_INIT_INIT_MASK (0xFFFFU)
|
|
#define PWM_INIT_INIT_SHIFT (0U)
|
|
#define PWM_INIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_INIT */
|
|
#define PWM_INIT_COUNT (4U)
|
|
|
|
/*! @name CTRL2 - Control 2 Register */
|
|
/*! @{ */
|
|
#define PWM_CTRL2_CLK_SEL_MASK (0x3U)
|
|
#define PWM_CTRL2_CLK_SEL_SHIFT (0U)
|
|
/*! CLK_SEL - Clock Source Select
|
|
* 0b00..The IPBus clock is used as the clock for the local prescaler and counter.
|
|
* 0b01..EXT_CLK is used as the clock for the local prescaler and counter.
|
|
* 0b10..Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0.
|
|
* 0b11..reserved
|
|
*/
|
|
#define PWM_CTRL2_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK)
|
|
#define PWM_CTRL2_RELOAD_SEL_MASK (0x4U)
|
|
#define PWM_CTRL2_RELOAD_SEL_SHIFT (2U)
|
|
/*! RELOAD_SEL - Reload Source Select
|
|
* 0b0..The local RELOAD signal is used to reload registers.
|
|
* 0b1..The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0.
|
|
*/
|
|
#define PWM_CTRL2_RELOAD_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK)
|
|
#define PWM_CTRL2_FORCE_SEL_MASK (0x38U)
|
|
#define PWM_CTRL2_FORCE_SEL_SHIFT (3U)
|
|
/*! FORCE_SEL - This read/write bit determines the source of the FORCE OUTPUT signal for this submodule.
|
|
* 0b000..The local force signal, CTRL2[FORCE], from this submodule is used to force updates.
|
|
* 0b001..The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0.
|
|
* 0b010..The local reload signal from this submodule is used to force updates without regard to the state of LDOK.
|
|
* 0b011..The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0.
|
|
* 0b100..The local sync signal from this submodule is used to force updates.
|
|
* 0b101..The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0.
|
|
* 0b110..The external force signal, EXT_FORCE, from outside the PWM module causes updates.
|
|
* 0b111..The external sync signal, EXT_SYNC, from outside the PWM module causes updates.
|
|
*/
|
|
#define PWM_CTRL2_FORCE_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK)
|
|
#define PWM_CTRL2_FORCE_MASK (0x40U)
|
|
#define PWM_CTRL2_FORCE_SHIFT (6U)
|
|
#define PWM_CTRL2_FORCE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK)
|
|
#define PWM_CTRL2_FRCEN_MASK (0x80U)
|
|
#define PWM_CTRL2_FRCEN_SHIFT (7U)
|
|
/*! FRCEN - FRCEN
|
|
* 0b0..Initialization from a FORCE_OUT is disabled.
|
|
* 0b1..Initialization from a FORCE_OUT is enabled.
|
|
*/
|
|
#define PWM_CTRL2_FRCEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK)
|
|
#define PWM_CTRL2_INIT_SEL_MASK (0x300U)
|
|
#define PWM_CTRL2_INIT_SEL_SHIFT (8U)
|
|
/*! INIT_SEL - Initialization Control Select
|
|
* 0b00..Local sync (PWM_X) causes initialization.
|
|
* 0b01..Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs.
|
|
* 0b10..Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0.
|
|
* 0b11..EXT_SYNC causes initialization.
|
|
*/
|
|
#define PWM_CTRL2_INIT_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK)
|
|
#define PWM_CTRL2_PWMX_INIT_MASK (0x400U)
|
|
#define PWM_CTRL2_PWMX_INIT_SHIFT (10U)
|
|
#define PWM_CTRL2_PWMX_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK)
|
|
#define PWM_CTRL2_PWM45_INIT_MASK (0x800U)
|
|
#define PWM_CTRL2_PWM45_INIT_SHIFT (11U)
|
|
#define PWM_CTRL2_PWM45_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK)
|
|
#define PWM_CTRL2_PWM23_INIT_MASK (0x1000U)
|
|
#define PWM_CTRL2_PWM23_INIT_SHIFT (12U)
|
|
#define PWM_CTRL2_PWM23_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK)
|
|
#define PWM_CTRL2_INDEP_MASK (0x2000U)
|
|
#define PWM_CTRL2_INDEP_SHIFT (13U)
|
|
/*! INDEP - Independent or Complementary Pair Operation
|
|
* 0b0..PWM_A and PWM_B form a complementary PWM pair.
|
|
* 0b1..PWM_A and PWM_B outputs are independent PWMs.
|
|
*/
|
|
#define PWM_CTRL2_INDEP(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK)
|
|
#define PWM_CTRL2_WAITEN_MASK (0x4000U)
|
|
#define PWM_CTRL2_WAITEN_SHIFT (14U)
|
|
#define PWM_CTRL2_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK)
|
|
#define PWM_CTRL2_DBGEN_MASK (0x8000U)
|
|
#define PWM_CTRL2_DBGEN_SHIFT (15U)
|
|
#define PWM_CTRL2_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_CTRL2 */
|
|
#define PWM_CTRL2_COUNT (4U)
|
|
|
|
/*! @name CTRL - Control Register */
|
|
/*! @{ */
|
|
#define PWM_CTRL_DBLEN_MASK (0x1U)
|
|
#define PWM_CTRL_DBLEN_SHIFT (0U)
|
|
/*! DBLEN - Double Switching Enable
|
|
* 0b0..Double switching disabled.
|
|
* 0b1..Double switching enabled.
|
|
*/
|
|
#define PWM_CTRL_DBLEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK)
|
|
#define PWM_CTRL_DBLX_MASK (0x2U)
|
|
#define PWM_CTRL_DBLX_SHIFT (1U)
|
|
/*! DBLX - PWMX Double Switching Enable
|
|
* 0b0..PWMX double pulse disabled.
|
|
* 0b1..PWMX double pulse enabled.
|
|
*/
|
|
#define PWM_CTRL_DBLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK)
|
|
#define PWM_CTRL_LDMOD_MASK (0x4U)
|
|
#define PWM_CTRL_LDMOD_SHIFT (2U)
|
|
/*! LDMOD - Load Mode Select
|
|
* 0b0..Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set.
|
|
* 0b1..Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF].
|
|
*/
|
|
#define PWM_CTRL_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK)
|
|
#define PWM_CTRL_SPLIT_MASK (0x8U)
|
|
#define PWM_CTRL_SPLIT_SHIFT (3U)
|
|
/*! SPLIT - Split the DBLPWM signal to PWMA and PWMB
|
|
* 0b0..DBLPWM is not split. PWMA and PWMB each have double pulses.
|
|
* 0b1..DBLPWM is split to PWMA and PWMB.
|
|
*/
|
|
#define PWM_CTRL_SPLIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK)
|
|
#define PWM_CTRL_PRSC_MASK (0x70U)
|
|
#define PWM_CTRL_PRSC_SHIFT (4U)
|
|
/*! PRSC - Prescaler
|
|
* 0b000..PWM clock frequency = fclk
|
|
* 0b001..PWM clock frequency = fclk/2
|
|
* 0b010..PWM clock frequency = fclk/4
|
|
* 0b011..PWM clock frequency = fclk/8
|
|
* 0b100..PWM clock frequency = fclk/16
|
|
* 0b101..PWM clock frequency = fclk/32
|
|
* 0b110..PWM clock frequency = fclk/64
|
|
* 0b111..PWM clock frequency = fclk/128
|
|
*/
|
|
#define PWM_CTRL_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK)
|
|
#define PWM_CTRL_COMPMODE_MASK (0x80U)
|
|
#define PWM_CTRL_COMPMODE_SHIFT (7U)
|
|
/*! COMPMODE - Compare Mode
|
|
* 0b0..The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA output that is high at the end of a period will maintain this state until a match with VAL3 clears the output in the following period.
|
|
* 0b1..The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWMA output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value.
|
|
*/
|
|
#define PWM_CTRL_COMPMODE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK)
|
|
#define PWM_CTRL_DT_MASK (0x300U)
|
|
#define PWM_CTRL_DT_SHIFT (8U)
|
|
#define PWM_CTRL_DT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK)
|
|
#define PWM_CTRL_FULL_MASK (0x400U)
|
|
#define PWM_CTRL_FULL_SHIFT (10U)
|
|
/*! FULL - Full Cycle Reload
|
|
* 0b0..Full-cycle reloads disabled.
|
|
* 0b1..Full-cycle reloads enabled.
|
|
*/
|
|
#define PWM_CTRL_FULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK)
|
|
#define PWM_CTRL_HALF_MASK (0x800U)
|
|
#define PWM_CTRL_HALF_SHIFT (11U)
|
|
/*! HALF - Half Cycle Reload
|
|
* 0b0..Half-cycle reloads disabled.
|
|
* 0b1..Half-cycle reloads enabled.
|
|
*/
|
|
#define PWM_CTRL_HALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK)
|
|
#define PWM_CTRL_LDFQ_MASK (0xF000U)
|
|
#define PWM_CTRL_LDFQ_SHIFT (12U)
|
|
/*! LDFQ - Load Frequency
|
|
* 0b0000..Every PWM opportunity
|
|
* 0b0001..Every 2 PWM opportunities
|
|
* 0b0010..Every 3 PWM opportunities
|
|
* 0b0011..Every 4 PWM opportunities
|
|
* 0b0100..Every 5 PWM opportunities
|
|
* 0b0101..Every 6 PWM opportunities
|
|
* 0b0110..Every 7 PWM opportunities
|
|
* 0b0111..Every 8 PWM opportunities
|
|
* 0b1000..Every 9 PWM opportunities
|
|
* 0b1001..Every 10 PWM opportunities
|
|
* 0b1010..Every 11 PWM opportunities
|
|
* 0b1011..Every 12 PWM opportunities
|
|
* 0b1100..Every 13 PWM opportunities
|
|
* 0b1101..Every 14 PWM opportunities
|
|
* 0b1110..Every 15 PWM opportunities
|
|
* 0b1111..Every 16 PWM opportunities
|
|
*/
|
|
#define PWM_CTRL_LDFQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_CTRL */
|
|
#define PWM_CTRL_COUNT (4U)
|
|
|
|
/*! @name VAL0 - Value Register 0 */
|
|
/*! @{ */
|
|
#define PWM_VAL0_VAL0_MASK (0xFFFFU)
|
|
#define PWM_VAL0_VAL0_SHIFT (0U)
|
|
#define PWM_VAL0_VAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_VAL0 */
|
|
#define PWM_VAL0_COUNT (4U)
|
|
|
|
/*! @name FRACVAL1 - Fractional Value Register 1 */
|
|
/*! @{ */
|
|
#define PWM_FRACVAL1_FRACVAL1_MASK (0xF800U)
|
|
#define PWM_FRACVAL1_FRACVAL1_SHIFT (11U)
|
|
#define PWM_FRACVAL1_FRACVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_FRACVAL1 */
|
|
#define PWM_FRACVAL1_COUNT (4U)
|
|
|
|
/*! @name VAL1 - Value Register 1 */
|
|
/*! @{ */
|
|
#define PWM_VAL1_VAL1_MASK (0xFFFFU)
|
|
#define PWM_VAL1_VAL1_SHIFT (0U)
|
|
#define PWM_VAL1_VAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_VAL1 */
|
|
#define PWM_VAL1_COUNT (4U)
|
|
|
|
/*! @name FRACVAL2 - Fractional Value Register 2 */
|
|
/*! @{ */
|
|
#define PWM_FRACVAL2_FRACVAL2_MASK (0xF800U)
|
|
#define PWM_FRACVAL2_FRACVAL2_SHIFT (11U)
|
|
#define PWM_FRACVAL2_FRACVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_FRACVAL2 */
|
|
#define PWM_FRACVAL2_COUNT (4U)
|
|
|
|
/*! @name VAL2 - Value Register 2 */
|
|
/*! @{ */
|
|
#define PWM_VAL2_VAL2_MASK (0xFFFFU)
|
|
#define PWM_VAL2_VAL2_SHIFT (0U)
|
|
#define PWM_VAL2_VAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_VAL2 */
|
|
#define PWM_VAL2_COUNT (4U)
|
|
|
|
/*! @name FRACVAL3 - Fractional Value Register 3 */
|
|
/*! @{ */
|
|
#define PWM_FRACVAL3_FRACVAL3_MASK (0xF800U)
|
|
#define PWM_FRACVAL3_FRACVAL3_SHIFT (11U)
|
|
#define PWM_FRACVAL3_FRACVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_FRACVAL3 */
|
|
#define PWM_FRACVAL3_COUNT (4U)
|
|
|
|
/*! @name VAL3 - Value Register 3 */
|
|
/*! @{ */
|
|
#define PWM_VAL3_VAL3_MASK (0xFFFFU)
|
|
#define PWM_VAL3_VAL3_SHIFT (0U)
|
|
#define PWM_VAL3_VAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_VAL3 */
|
|
#define PWM_VAL3_COUNT (4U)
|
|
|
|
/*! @name FRACVAL4 - Fractional Value Register 4 */
|
|
/*! @{ */
|
|
#define PWM_FRACVAL4_FRACVAL4_MASK (0xF800U)
|
|
#define PWM_FRACVAL4_FRACVAL4_SHIFT (11U)
|
|
#define PWM_FRACVAL4_FRACVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_FRACVAL4 */
|
|
#define PWM_FRACVAL4_COUNT (4U)
|
|
|
|
/*! @name VAL4 - Value Register 4 */
|
|
/*! @{ */
|
|
#define PWM_VAL4_VAL4_MASK (0xFFFFU)
|
|
#define PWM_VAL4_VAL4_SHIFT (0U)
|
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#define PWM_VAL4_VAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_VAL4 */
|
|
#define PWM_VAL4_COUNT (4U)
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|
|
|
/*! @name FRACVAL5 - Fractional Value Register 5 */
|
|
/*! @{ */
|
|
#define PWM_FRACVAL5_FRACVAL5_MASK (0xF800U)
|
|
#define PWM_FRACVAL5_FRACVAL5_SHIFT (11U)
|
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#define PWM_FRACVAL5_FRACVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_FRACVAL5 */
|
|
#define PWM_FRACVAL5_COUNT (4U)
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|
|
|
/*! @name VAL5 - Value Register 5 */
|
|
/*! @{ */
|
|
#define PWM_VAL5_VAL5_MASK (0xFFFFU)
|
|
#define PWM_VAL5_VAL5_SHIFT (0U)
|
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#define PWM_VAL5_VAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_VAL5 */
|
|
#define PWM_VAL5_COUNT (4U)
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|
|
|
/*! @name FRCTRL - Fractional Control Register */
|
|
/*! @{ */
|
|
#define PWM_FRCTRL_FRAC1_EN_MASK (0x2U)
|
|
#define PWM_FRCTRL_FRAC1_EN_SHIFT (1U)
|
|
/*! FRAC1_EN - Fractional Cycle PWM Period Enable
|
|
* 0b0..Disable fractional cycle length for the PWM period.
|
|
* 0b1..Enable fractional cycle length for the PWM period.
|
|
*/
|
|
#define PWM_FRCTRL_FRAC1_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK)
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|
#define PWM_FRCTRL_FRAC23_EN_MASK (0x4U)
|
|
#define PWM_FRCTRL_FRAC23_EN_SHIFT (2U)
|
|
/*! FRAC23_EN - Fractional Cycle Placement Enable for PWM_A
|
|
* 0b0..Disable fractional cycle placement for PWM_A.
|
|
* 0b1..Enable fractional cycle placement for PWM_A.
|
|
*/
|
|
#define PWM_FRCTRL_FRAC23_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK)
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|
#define PWM_FRCTRL_FRAC45_EN_MASK (0x10U)
|
|
#define PWM_FRCTRL_FRAC45_EN_SHIFT (4U)
|
|
/*! FRAC45_EN - Fractional Cycle Placement Enable for PWM_B
|
|
* 0b0..Disable fractional cycle placement for PWM_B.
|
|
* 0b1..Enable fractional cycle placement for PWM_B.
|
|
*/
|
|
#define PWM_FRCTRL_FRAC45_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK)
|
|
#define PWM_FRCTRL_FRAC_PU_MASK (0x100U)
|
|
#define PWM_FRCTRL_FRAC_PU_SHIFT (8U)
|
|
/*! FRAC_PU - Fractional Delay Circuit Power Up
|
|
* 0b0..Turn off fractional delay logic.
|
|
* 0b1..Power up fractional delay logic.
|
|
*/
|
|
#define PWM_FRCTRL_FRAC_PU(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC_PU_SHIFT)) & PWM_FRCTRL_FRAC_PU_MASK)
|
|
#define PWM_FRCTRL_TEST_MASK (0x8000U)
|
|
#define PWM_FRCTRL_TEST_SHIFT (15U)
|
|
#define PWM_FRCTRL_TEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_FRCTRL */
|
|
#define PWM_FRCTRL_COUNT (4U)
|
|
|
|
/*! @name OCTRL - Output Control Register */
|
|
/*! @{ */
|
|
#define PWM_OCTRL_PWMXFS_MASK (0x3U)
|
|
#define PWM_OCTRL_PWMXFS_SHIFT (0U)
|
|
/*! PWMXFS - PWM_X Fault State
|
|
* 0b00..Output is forced to logic 0 state prior to consideration of output polarity control.
|
|
* 0b01..Output is forced to logic 1 state prior to consideration of output polarity control.
|
|
* 0b10..Output is tristated.
|
|
* 0b11..Output is tristated.
|
|
*/
|
|
#define PWM_OCTRL_PWMXFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK)
|
|
#define PWM_OCTRL_PWMBFS_MASK (0xCU)
|
|
#define PWM_OCTRL_PWMBFS_SHIFT (2U)
|
|
/*! PWMBFS - PWM_B Fault State
|
|
* 0b00..Output is forced to logic 0 state prior to consideration of output polarity control.
|
|
* 0b01..Output is forced to logic 1 state prior to consideration of output polarity control.
|
|
* 0b10..Output is tristated.
|
|
* 0b11..Output is tristated.
|
|
*/
|
|
#define PWM_OCTRL_PWMBFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK)
|
|
#define PWM_OCTRL_PWMAFS_MASK (0x30U)
|
|
#define PWM_OCTRL_PWMAFS_SHIFT (4U)
|
|
/*! PWMAFS - PWM_A Fault State
|
|
* 0b00..Output is forced to logic 0 state prior to consideration of output polarity control.
|
|
* 0b01..Output is forced to logic 1 state prior to consideration of output polarity control.
|
|
* 0b10..Output is tristated.
|
|
* 0b11..Output is tristated.
|
|
*/
|
|
#define PWM_OCTRL_PWMAFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK)
|
|
#define PWM_OCTRL_POLX_MASK (0x100U)
|
|
#define PWM_OCTRL_POLX_SHIFT (8U)
|
|
/*! POLX - PWM_X Output Polarity
|
|
* 0b0..PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state.
|
|
* 0b1..PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state.
|
|
*/
|
|
#define PWM_OCTRL_POLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK)
|
|
#define PWM_OCTRL_POLB_MASK (0x200U)
|
|
#define PWM_OCTRL_POLB_SHIFT (9U)
|
|
/*! POLB - PWM_B Output Polarity
|
|
* 0b0..PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state.
|
|
* 0b1..PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state.
|
|
*/
|
|
#define PWM_OCTRL_POLB(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK)
|
|
#define PWM_OCTRL_POLA_MASK (0x400U)
|
|
#define PWM_OCTRL_POLA_SHIFT (10U)
|
|
/*! POLA - PWM_A Output Polarity
|
|
* 0b0..PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state.
|
|
* 0b1..PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state.
|
|
*/
|
|
#define PWM_OCTRL_POLA(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK)
|
|
#define PWM_OCTRL_PWMX_IN_MASK (0x2000U)
|
|
#define PWM_OCTRL_PWMX_IN_SHIFT (13U)
|
|
#define PWM_OCTRL_PWMX_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK)
|
|
#define PWM_OCTRL_PWMB_IN_MASK (0x4000U)
|
|
#define PWM_OCTRL_PWMB_IN_SHIFT (14U)
|
|
#define PWM_OCTRL_PWMB_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK)
|
|
#define PWM_OCTRL_PWMA_IN_MASK (0x8000U)
|
|
#define PWM_OCTRL_PWMA_IN_SHIFT (15U)
|
|
#define PWM_OCTRL_PWMA_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_OCTRL */
|
|
#define PWM_OCTRL_COUNT (4U)
|
|
|
|
/*! @name STS - Status Register */
|
|
/*! @{ */
|
|
#define PWM_STS_CMPF_MASK (0x3FU)
|
|
#define PWM_STS_CMPF_SHIFT (0U)
|
|
/*! CMPF - Compare Flags
|
|
* 0b000000..No compare event has occurred for a particular VALx value.
|
|
* 0b000001..A compare event has occurred for a particular VALx value.
|
|
*/
|
|
#define PWM_STS_CMPF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK)
|
|
#define PWM_STS_CFX0_MASK (0x40U)
|
|
#define PWM_STS_CFX0_SHIFT (6U)
|
|
#define PWM_STS_CFX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK)
|
|
#define PWM_STS_CFX1_MASK (0x80U)
|
|
#define PWM_STS_CFX1_SHIFT (7U)
|
|
#define PWM_STS_CFX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK)
|
|
#define PWM_STS_CFB0_MASK (0x100U)
|
|
#define PWM_STS_CFB0_SHIFT (8U)
|
|
#define PWM_STS_CFB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB0_SHIFT)) & PWM_STS_CFB0_MASK)
|
|
#define PWM_STS_CFB1_MASK (0x200U)
|
|
#define PWM_STS_CFB1_SHIFT (9U)
|
|
#define PWM_STS_CFB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB1_SHIFT)) & PWM_STS_CFB1_MASK)
|
|
#define PWM_STS_CFA0_MASK (0x400U)
|
|
#define PWM_STS_CFA0_SHIFT (10U)
|
|
#define PWM_STS_CFA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA0_SHIFT)) & PWM_STS_CFA0_MASK)
|
|
#define PWM_STS_CFA1_MASK (0x800U)
|
|
#define PWM_STS_CFA1_SHIFT (11U)
|
|
#define PWM_STS_CFA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK)
|
|
#define PWM_STS_RF_MASK (0x1000U)
|
|
#define PWM_STS_RF_SHIFT (12U)
|
|
/*! RF - Reload Flag
|
|
* 0b0..No new reload cycle since last STS[RF] clearing
|
|
* 0b1..New reload cycle since last STS[RF] clearing
|
|
*/
|
|
#define PWM_STS_RF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK)
|
|
#define PWM_STS_REF_MASK (0x2000U)
|
|
#define PWM_STS_REF_SHIFT (13U)
|
|
/*! REF - Reload Error Flag
|
|
* 0b0..No reload error occurred.
|
|
* 0b1..Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0.
|
|
*/
|
|
#define PWM_STS_REF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK)
|
|
#define PWM_STS_RUF_MASK (0x4000U)
|
|
#define PWM_STS_RUF_SHIFT (14U)
|
|
/*! RUF - Registers Updated Flag
|
|
* 0b0..No register update has occurred since last reload.
|
|
* 0b1..At least one of the double buffered registers has been updated since the last reload.
|
|
*/
|
|
#define PWM_STS_RUF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_STS */
|
|
#define PWM_STS_COUNT (4U)
|
|
|
|
/*! @name INTEN - Interrupt Enable Register */
|
|
/*! @{ */
|
|
#define PWM_INTEN_CMPIE_MASK (0x3FU)
|
|
#define PWM_INTEN_CMPIE_SHIFT (0U)
|
|
/*! CMPIE - Compare Interrupt Enables
|
|
* 0b000000..The corresponding STS[CMPF] bit will not cause an interrupt request.
|
|
* 0b000001..The corresponding STS[CMPF] bit will cause an interrupt request.
|
|
*/
|
|
#define PWM_INTEN_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK)
|
|
#define PWM_INTEN_CX0IE_MASK (0x40U)
|
|
#define PWM_INTEN_CX0IE_SHIFT (6U)
|
|
/*! CX0IE - Capture X 0 Interrupt Enable
|
|
* 0b0..Interrupt request disabled for STS[CFX0].
|
|
* 0b1..Interrupt request enabled for STS[CFX0].
|
|
*/
|
|
#define PWM_INTEN_CX0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK)
|
|
#define PWM_INTEN_CX1IE_MASK (0x80U)
|
|
#define PWM_INTEN_CX1IE_SHIFT (7U)
|
|
/*! CX1IE - Capture X 1 Interrupt Enable
|
|
* 0b0..Interrupt request disabled for STS[CFX1].
|
|
* 0b1..Interrupt request enabled for STS[CFX1].
|
|
*/
|
|
#define PWM_INTEN_CX1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK)
|
|
#define PWM_INTEN_CB0IE_MASK (0x100U)
|
|
#define PWM_INTEN_CB0IE_SHIFT (8U)
|
|
/*! CB0IE - Capture B 0 Interrupt Enable
|
|
* 0b0..Interrupt request disabled for STS[CFB0].
|
|
* 0b1..Interrupt request enabled for STS[CFB0].
|
|
*/
|
|
#define PWM_INTEN_CB0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK)
|
|
#define PWM_INTEN_CB1IE_MASK (0x200U)
|
|
#define PWM_INTEN_CB1IE_SHIFT (9U)
|
|
/*! CB1IE - Capture B 1 Interrupt Enable
|
|
* 0b0..Interrupt request disabled for STS[CFB1].
|
|
* 0b1..Interrupt request enabled for STS[CFB1].
|
|
*/
|
|
#define PWM_INTEN_CB1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK)
|
|
#define PWM_INTEN_CA0IE_MASK (0x400U)
|
|
#define PWM_INTEN_CA0IE_SHIFT (10U)
|
|
/*! CA0IE - Capture A 0 Interrupt Enable
|
|
* 0b0..Interrupt request disabled for STS[CFA0].
|
|
* 0b1..Interrupt request enabled for STS[CFA0].
|
|
*/
|
|
#define PWM_INTEN_CA0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK)
|
|
#define PWM_INTEN_CA1IE_MASK (0x800U)
|
|
#define PWM_INTEN_CA1IE_SHIFT (11U)
|
|
/*! CA1IE - Capture A 1 Interrupt Enable
|
|
* 0b0..Interrupt request disabled for STS[CFA1].
|
|
* 0b1..Interrupt request enabled for STS[CFA1].
|
|
*/
|
|
#define PWM_INTEN_CA1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK)
|
|
#define PWM_INTEN_RIE_MASK (0x1000U)
|
|
#define PWM_INTEN_RIE_SHIFT (12U)
|
|
/*! RIE - Reload Interrupt Enable
|
|
* 0b0..STS[RF] CPU interrupt requests disabled
|
|
* 0b1..STS[RF] CPU interrupt requests enabled
|
|
*/
|
|
#define PWM_INTEN_RIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK)
|
|
#define PWM_INTEN_REIE_MASK (0x2000U)
|
|
#define PWM_INTEN_REIE_SHIFT (13U)
|
|
/*! REIE - Reload Error Interrupt Enable
|
|
* 0b0..STS[REF] CPU interrupt requests disabled
|
|
* 0b1..STS[REF] CPU interrupt requests enabled
|
|
*/
|
|
#define PWM_INTEN_REIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_INTEN */
|
|
#define PWM_INTEN_COUNT (4U)
|
|
|
|
/*! @name DMAEN - DMA Enable Register */
|
|
/*! @{ */
|
|
#define PWM_DMAEN_CX0DE_MASK (0x1U)
|
|
#define PWM_DMAEN_CX0DE_SHIFT (0U)
|
|
#define PWM_DMAEN_CX0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK)
|
|
#define PWM_DMAEN_CX1DE_MASK (0x2U)
|
|
#define PWM_DMAEN_CX1DE_SHIFT (1U)
|
|
#define PWM_DMAEN_CX1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK)
|
|
#define PWM_DMAEN_CB0DE_MASK (0x4U)
|
|
#define PWM_DMAEN_CB0DE_SHIFT (2U)
|
|
#define PWM_DMAEN_CB0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB0DE_SHIFT)) & PWM_DMAEN_CB0DE_MASK)
|
|
#define PWM_DMAEN_CB1DE_MASK (0x8U)
|
|
#define PWM_DMAEN_CB1DE_SHIFT (3U)
|
|
#define PWM_DMAEN_CB1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB1DE_SHIFT)) & PWM_DMAEN_CB1DE_MASK)
|
|
#define PWM_DMAEN_CA0DE_MASK (0x10U)
|
|
#define PWM_DMAEN_CA0DE_SHIFT (4U)
|
|
#define PWM_DMAEN_CA0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA0DE_SHIFT)) & PWM_DMAEN_CA0DE_MASK)
|
|
#define PWM_DMAEN_CA1DE_MASK (0x20U)
|
|
#define PWM_DMAEN_CA1DE_SHIFT (5U)
|
|
#define PWM_DMAEN_CA1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK)
|
|
#define PWM_DMAEN_CAPTDE_MASK (0xC0U)
|
|
#define PWM_DMAEN_CAPTDE_SHIFT (6U)
|
|
/*! CAPTDE - Capture DMA Enable Source Select
|
|
* 0b00..Read DMA requests disabled.
|
|
* 0b01..Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive.
|
|
* 0b10..A local sync (VAL1 matches counter) sets the read DMA request.
|
|
* 0b11..A local reload (STS[RF] being set) sets the read DMA request.
|
|
*/
|
|
#define PWM_DMAEN_CAPTDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK)
|
|
#define PWM_DMAEN_FAND_MASK (0x100U)
|
|
#define PWM_DMAEN_FAND_SHIFT (8U)
|
|
/*! FAND - FIFO Watermark AND Control
|
|
* 0b0..Selected FIFO watermarks are OR'ed together.
|
|
* 0b1..Selected FIFO watermarks are AND'ed together.
|
|
*/
|
|
#define PWM_DMAEN_FAND(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK)
|
|
#define PWM_DMAEN_VALDE_MASK (0x200U)
|
|
#define PWM_DMAEN_VALDE_SHIFT (9U)
|
|
/*! VALDE - Value Registers DMA Enable
|
|
* 0b0..DMA write requests disabled
|
|
* 0b1..DMA write requests for the VALx and FRACVALx registers enabled
|
|
*/
|
|
#define PWM_DMAEN_VALDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_DMAEN */
|
|
#define PWM_DMAEN_COUNT (4U)
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|
|
|
/*! @name TCTRL - Output Trigger Control Register */
|
|
/*! @{ */
|
|
#define PWM_TCTRL_OUT_TRIG_EN_MASK (0x3FU)
|
|
#define PWM_TCTRL_OUT_TRIG_EN_SHIFT (0U)
|
|
/*! OUT_TRIG_EN - Output Trigger Enables
|
|
* 0b000000..PWM_OUT_TRIGx will not set when the counter value matches the VALx value.
|
|
* 0b000001..PWM_OUT_TRIGx will set when the counter value matches the VALx value.
|
|
*/
|
|
#define PWM_TCTRL_OUT_TRIG_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK)
|
|
#define PWM_TCTRL_TRGFRQ_MASK (0x1000U)
|
|
#define PWM_TCTRL_TRGFRQ_SHIFT (12U)
|
|
/*! TRGFRQ - Trigger frequency
|
|
* 0b0..Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero.
|
|
* 0b1..Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero.
|
|
*/
|
|
#define PWM_TCTRL_TRGFRQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK)
|
|
#define PWM_TCTRL_PWBOT1_MASK (0x4000U)
|
|
#define PWM_TCTRL_PWBOT1_SHIFT (14U)
|
|
/*! PWBOT1 - Output Trigger 1 Source Select
|
|
* 0b0..Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port.
|
|
* 0b1..Route the PWMB output to the PWM_OUT_TRIG1 port.
|
|
*/
|
|
#define PWM_TCTRL_PWBOT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK)
|
|
#define PWM_TCTRL_PWAOT0_MASK (0x8000U)
|
|
#define PWM_TCTRL_PWAOT0_SHIFT (15U)
|
|
/*! PWAOT0 - Output Trigger 0 Source Select
|
|
* 0b0..Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port.
|
|
* 0b1..Route the PWMA output to the PWM_OUT_TRIG0 port.
|
|
*/
|
|
#define PWM_TCTRL_PWAOT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_TCTRL */
|
|
#define PWM_TCTRL_COUNT (4U)
|
|
|
|
/*! @name DISMAP - Fault Disable Mapping Register 0..Fault Disable Mapping Register 1 */
|
|
/*! @{ */
|
|
#define PWM_DISMAP_DIS0A_MASK (0xFU)
|
|
#define PWM_DISMAP_DIS0A_SHIFT (0U)
|
|
#define PWM_DISMAP_DIS0A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK)
|
|
#define PWM_DISMAP_DIS1A_MASK (0xFU)
|
|
#define PWM_DISMAP_DIS1A_SHIFT (0U)
|
|
#define PWM_DISMAP_DIS1A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1A_SHIFT)) & PWM_DISMAP_DIS1A_MASK)
|
|
#define PWM_DISMAP_DIS0B_MASK (0xF0U)
|
|
#define PWM_DISMAP_DIS0B_SHIFT (4U)
|
|
#define PWM_DISMAP_DIS0B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK)
|
|
#define PWM_DISMAP_DIS1B_MASK (0xF0U)
|
|
#define PWM_DISMAP_DIS1B_SHIFT (4U)
|
|
#define PWM_DISMAP_DIS1B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1B_SHIFT)) & PWM_DISMAP_DIS1B_MASK)
|
|
#define PWM_DISMAP_DIS0X_MASK (0xF00U)
|
|
#define PWM_DISMAP_DIS0X_SHIFT (8U)
|
|
#define PWM_DISMAP_DIS0X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK)
|
|
#define PWM_DISMAP_DIS1X_MASK (0xF00U)
|
|
#define PWM_DISMAP_DIS1X_SHIFT (8U)
|
|
#define PWM_DISMAP_DIS1X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1X_SHIFT)) & PWM_DISMAP_DIS1X_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_DISMAP */
|
|
#define PWM_DISMAP_COUNT (4U)
|
|
|
|
/* The count of PWM_DISMAP */
|
|
#define PWM_DISMAP_COUNT2 (2U)
|
|
|
|
/*! @name DTCNT0 - Deadtime Count Register 0 */
|
|
/*! @{ */
|
|
#define PWM_DTCNT0_DTCNT0_MASK (0xFFFFU)
|
|
#define PWM_DTCNT0_DTCNT0_SHIFT (0U)
|
|
#define PWM_DTCNT0_DTCNT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_DTCNT0 */
|
|
#define PWM_DTCNT0_COUNT (4U)
|
|
|
|
/*! @name DTCNT1 - Deadtime Count Register 1 */
|
|
/*! @{ */
|
|
#define PWM_DTCNT1_DTCNT1_MASK (0xFFFFU)
|
|
#define PWM_DTCNT1_DTCNT1_SHIFT (0U)
|
|
#define PWM_DTCNT1_DTCNT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_DTCNT1 */
|
|
#define PWM_DTCNT1_COUNT (4U)
|
|
|
|
/*! @name CAPTCTRLA - Capture Control A Register */
|
|
/*! @{ */
|
|
#define PWM_CAPTCTRLA_ARMA_MASK (0x1U)
|
|
#define PWM_CAPTCTRLA_ARMA_SHIFT (0U)
|
|
/*! ARMA - Arm A
|
|
* 0b0..Input capture operation is disabled.
|
|
* 0b1..Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled.
|
|
*/
|
|
#define PWM_CAPTCTRLA_ARMA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK)
|
|
#define PWM_CAPTCTRLA_ONESHOTA_MASK (0x2U)
|
|
#define PWM_CAPTCTRLA_ONESHOTA_SHIFT (1U)
|
|
/*! ONESHOTA - One Shot Mode A
|
|
* 0b0..Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit.
|
|
* 0b1..One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared.
|
|
*/
|
|
#define PWM_CAPTCTRLA_ONESHOTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK)
|
|
#define PWM_CAPTCTRLA_EDGA0_MASK (0xCU)
|
|
#define PWM_CAPTCTRLA_EDGA0_SHIFT (2U)
|
|
/*! EDGA0 - Edge A 0
|
|
* 0b00..Disabled
|
|
* 0b01..Capture falling edges
|
|
* 0b10..Capture rising edges
|
|
* 0b11..Capture any edge
|
|
*/
|
|
#define PWM_CAPTCTRLA_EDGA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK)
|
|
#define PWM_CAPTCTRLA_EDGA1_MASK (0x30U)
|
|
#define PWM_CAPTCTRLA_EDGA1_SHIFT (4U)
|
|
/*! EDGA1 - Edge A 1
|
|
* 0b00..Disabled
|
|
* 0b01..Capture falling edges
|
|
* 0b10..Capture rising edges
|
|
* 0b11..Capture any edge
|
|
*/
|
|
#define PWM_CAPTCTRLA_EDGA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK)
|
|
#define PWM_CAPTCTRLA_INP_SELA_MASK (0x40U)
|
|
#define PWM_CAPTCTRLA_INP_SELA_SHIFT (6U)
|
|
/*! INP_SELA - Input Select A
|
|
* 0b0..Raw PWM_A input signal selected as source.
|
|
* 0b1..Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers.
|
|
*/
|
|
#define PWM_CAPTCTRLA_INP_SELA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK)
|
|
#define PWM_CAPTCTRLA_EDGCNTA_EN_MASK (0x80U)
|
|
#define PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT (7U)
|
|
/*! EDGCNTA_EN - Edge Counter A Enable
|
|
* 0b0..Edge counter disabled and held in reset
|
|
* 0b1..Edge counter enabled
|
|
*/
|
|
#define PWM_CAPTCTRLA_EDGCNTA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK)
|
|
#define PWM_CAPTCTRLA_CFAWM_MASK (0x300U)
|
|
#define PWM_CAPTCTRLA_CFAWM_SHIFT (8U)
|
|
#define PWM_CAPTCTRLA_CFAWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CFAWM_SHIFT)) & PWM_CAPTCTRLA_CFAWM_MASK)
|
|
#define PWM_CAPTCTRLA_CA0CNT_MASK (0x1C00U)
|
|
#define PWM_CAPTCTRLA_CA0CNT_SHIFT (10U)
|
|
#define PWM_CAPTCTRLA_CA0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA0CNT_SHIFT)) & PWM_CAPTCTRLA_CA0CNT_MASK)
|
|
#define PWM_CAPTCTRLA_CA1CNT_MASK (0xE000U)
|
|
#define PWM_CAPTCTRLA_CA1CNT_SHIFT (13U)
|
|
#define PWM_CAPTCTRLA_CA1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_CAPTCTRLA */
|
|
#define PWM_CAPTCTRLA_COUNT (4U)
|
|
|
|
/*! @name CAPTCOMPA - Capture Compare A Register */
|
|
/*! @{ */
|
|
#define PWM_CAPTCOMPA_EDGCMPA_MASK (0xFFU)
|
|
#define PWM_CAPTCOMPA_EDGCMPA_SHIFT (0U)
|
|
#define PWM_CAPTCOMPA_EDGCMPA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK)
|
|
#define PWM_CAPTCOMPA_EDGCNTA_MASK (0xFF00U)
|
|
#define PWM_CAPTCOMPA_EDGCNTA_SHIFT (8U)
|
|
#define PWM_CAPTCOMPA_EDGCNTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_CAPTCOMPA */
|
|
#define PWM_CAPTCOMPA_COUNT (4U)
|
|
|
|
/*! @name CAPTCTRLB - Capture Control B Register */
|
|
/*! @{ */
|
|
#define PWM_CAPTCTRLB_ARMB_MASK (0x1U)
|
|
#define PWM_CAPTCTRLB_ARMB_SHIFT (0U)
|
|
/*! ARMB - Arm B
|
|
* 0b0..Input capture operation is disabled.
|
|
* 0b1..Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled.
|
|
*/
|
|
#define PWM_CAPTCTRLB_ARMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK)
|
|
#define PWM_CAPTCTRLB_ONESHOTB_MASK (0x2U)
|
|
#define PWM_CAPTCTRLB_ONESHOTB_SHIFT (1U)
|
|
/*! ONESHOTB - One Shot Mode B
|
|
* 0b0..Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit.
|
|
* 0b1..One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared.
|
|
*/
|
|
#define PWM_CAPTCTRLB_ONESHOTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK)
|
|
#define PWM_CAPTCTRLB_EDGB0_MASK (0xCU)
|
|
#define PWM_CAPTCTRLB_EDGB0_SHIFT (2U)
|
|
/*! EDGB0 - Edge B 0
|
|
* 0b00..Disabled
|
|
* 0b01..Capture falling edges
|
|
* 0b10..Capture rising edges
|
|
* 0b11..Capture any edge
|
|
*/
|
|
#define PWM_CAPTCTRLB_EDGB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK)
|
|
#define PWM_CAPTCTRLB_EDGB1_MASK (0x30U)
|
|
#define PWM_CAPTCTRLB_EDGB1_SHIFT (4U)
|
|
/*! EDGB1 - Edge B 1
|
|
* 0b00..Disabled
|
|
* 0b01..Capture falling edges
|
|
* 0b10..Capture rising edges
|
|
* 0b11..Capture any edge
|
|
*/
|
|
#define PWM_CAPTCTRLB_EDGB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK)
|
|
#define PWM_CAPTCTRLB_INP_SELB_MASK (0x40U)
|
|
#define PWM_CAPTCTRLB_INP_SELB_SHIFT (6U)
|
|
/*! INP_SELB - Input Select B
|
|
* 0b0..Raw PWM_B input signal selected as source.
|
|
* 0b1..Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers.
|
|
*/
|
|
#define PWM_CAPTCTRLB_INP_SELB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK)
|
|
#define PWM_CAPTCTRLB_EDGCNTB_EN_MASK (0x80U)
|
|
#define PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT (7U)
|
|
/*! EDGCNTB_EN - Edge Counter B Enable
|
|
* 0b0..Edge counter disabled and held in reset
|
|
* 0b1..Edge counter enabled
|
|
*/
|
|
#define PWM_CAPTCTRLB_EDGCNTB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK)
|
|
#define PWM_CAPTCTRLB_CFBWM_MASK (0x300U)
|
|
#define PWM_CAPTCTRLB_CFBWM_SHIFT (8U)
|
|
#define PWM_CAPTCTRLB_CFBWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CFBWM_SHIFT)) & PWM_CAPTCTRLB_CFBWM_MASK)
|
|
#define PWM_CAPTCTRLB_CB0CNT_MASK (0x1C00U)
|
|
#define PWM_CAPTCTRLB_CB0CNT_SHIFT (10U)
|
|
#define PWM_CAPTCTRLB_CB0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB0CNT_SHIFT)) & PWM_CAPTCTRLB_CB0CNT_MASK)
|
|
#define PWM_CAPTCTRLB_CB1CNT_MASK (0xE000U)
|
|
#define PWM_CAPTCTRLB_CB1CNT_SHIFT (13U)
|
|
#define PWM_CAPTCTRLB_CB1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_CAPTCTRLB */
|
|
#define PWM_CAPTCTRLB_COUNT (4U)
|
|
|
|
/*! @name CAPTCOMPB - Capture Compare B Register */
|
|
/*! @{ */
|
|
#define PWM_CAPTCOMPB_EDGCMPB_MASK (0xFFU)
|
|
#define PWM_CAPTCOMPB_EDGCMPB_SHIFT (0U)
|
|
#define PWM_CAPTCOMPB_EDGCMPB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK)
|
|
#define PWM_CAPTCOMPB_EDGCNTB_MASK (0xFF00U)
|
|
#define PWM_CAPTCOMPB_EDGCNTB_SHIFT (8U)
|
|
#define PWM_CAPTCOMPB_EDGCNTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_CAPTCOMPB */
|
|
#define PWM_CAPTCOMPB_COUNT (4U)
|
|
|
|
/*! @name CAPTCTRLX - Capture Control X Register */
|
|
/*! @{ */
|
|
#define PWM_CAPTCTRLX_ARMX_MASK (0x1U)
|
|
#define PWM_CAPTCTRLX_ARMX_SHIFT (0U)
|
|
/*! ARMX - Arm X
|
|
* 0b0..Input capture operation is disabled.
|
|
* 0b1..Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled.
|
|
*/
|
|
#define PWM_CAPTCTRLX_ARMX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK)
|
|
#define PWM_CAPTCTRLX_ONESHOTX_MASK (0x2U)
|
|
#define PWM_CAPTCTRLX_ONESHOTX_SHIFT (1U)
|
|
/*! ONESHOTX - One Shot Mode Aux
|
|
* 0b0..Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit.
|
|
* 0b1..One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared.
|
|
*/
|
|
#define PWM_CAPTCTRLX_ONESHOTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK)
|
|
#define PWM_CAPTCTRLX_EDGX0_MASK (0xCU)
|
|
#define PWM_CAPTCTRLX_EDGX0_SHIFT (2U)
|
|
/*! EDGX0 - Edge X 0
|
|
* 0b00..Disabled
|
|
* 0b01..Capture falling edges
|
|
* 0b10..Capture rising edges
|
|
* 0b11..Capture any edge
|
|
*/
|
|
#define PWM_CAPTCTRLX_EDGX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK)
|
|
#define PWM_CAPTCTRLX_EDGX1_MASK (0x30U)
|
|
#define PWM_CAPTCTRLX_EDGX1_SHIFT (4U)
|
|
/*! EDGX1 - Edge X 1
|
|
* 0b00..Disabled
|
|
* 0b01..Capture falling edges
|
|
* 0b10..Capture rising edges
|
|
* 0b11..Capture any edge
|
|
*/
|
|
#define PWM_CAPTCTRLX_EDGX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK)
|
|
#define PWM_CAPTCTRLX_INP_SELX_MASK (0x40U)
|
|
#define PWM_CAPTCTRLX_INP_SELX_SHIFT (6U)
|
|
/*! INP_SELX - Input Select X
|
|
* 0b0..Raw PWM_X input signal selected as source.
|
|
* 0b1..Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers.
|
|
*/
|
|
#define PWM_CAPTCTRLX_INP_SELX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK)
|
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#define PWM_CAPTCTRLX_EDGCNTX_EN_MASK (0x80U)
|
|
#define PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT (7U)
|
|
/*! EDGCNTX_EN - Edge Counter X Enable
|
|
* 0b0..Edge counter disabled and held in reset
|
|
* 0b1..Edge counter enabled
|
|
*/
|
|
#define PWM_CAPTCTRLX_EDGCNTX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK)
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#define PWM_CAPTCTRLX_CFXWM_MASK (0x300U)
|
|
#define PWM_CAPTCTRLX_CFXWM_SHIFT (8U)
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#define PWM_CAPTCTRLX_CFXWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK)
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#define PWM_CAPTCTRLX_CX0CNT_MASK (0x1C00U)
|
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#define PWM_CAPTCTRLX_CX0CNT_SHIFT (10U)
|
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#define PWM_CAPTCTRLX_CX0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK)
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#define PWM_CAPTCTRLX_CX1CNT_MASK (0xE000U)
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#define PWM_CAPTCTRLX_CX1CNT_SHIFT (13U)
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#define PWM_CAPTCTRLX_CX1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK)
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/*! @} */
|
|
|
|
/* The count of PWM_CAPTCTRLX */
|
|
#define PWM_CAPTCTRLX_COUNT (4U)
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|
|
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/*! @name CAPTCOMPX - Capture Compare X Register */
|
|
/*! @{ */
|
|
#define PWM_CAPTCOMPX_EDGCMPX_MASK (0xFFU)
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#define PWM_CAPTCOMPX_EDGCMPX_SHIFT (0U)
|
|
#define PWM_CAPTCOMPX_EDGCMPX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK)
|
|
#define PWM_CAPTCOMPX_EDGCNTX_MASK (0xFF00U)
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|
#define PWM_CAPTCOMPX_EDGCNTX_SHIFT (8U)
|
|
#define PWM_CAPTCOMPX_EDGCNTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_CAPTCOMPX */
|
|
#define PWM_CAPTCOMPX_COUNT (4U)
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|
|
|
/*! @name CVAL0 - Capture Value 0 Register */
|
|
/*! @{ */
|
|
#define PWM_CVAL0_CAPTVAL0_MASK (0xFFFFU)
|
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#define PWM_CVAL0_CAPTVAL0_SHIFT (0U)
|
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#define PWM_CVAL0_CAPTVAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_CVAL0 */
|
|
#define PWM_CVAL0_COUNT (4U)
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|
|
|
/*! @name CVAL0CYC - Capture Value 0 Cycle Register */
|
|
/*! @{ */
|
|
#define PWM_CVAL0CYC_CVAL0CYC_MASK (0xFU)
|
|
#define PWM_CVAL0CYC_CVAL0CYC_SHIFT (0U)
|
|
#define PWM_CVAL0CYC_CVAL0CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_CVAL0CYC */
|
|
#define PWM_CVAL0CYC_COUNT (4U)
|
|
|
|
/*! @name CVAL1 - Capture Value 1 Register */
|
|
/*! @{ */
|
|
#define PWM_CVAL1_CAPTVAL1_MASK (0xFFFFU)
|
|
#define PWM_CVAL1_CAPTVAL1_SHIFT (0U)
|
|
#define PWM_CVAL1_CAPTVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_CVAL1 */
|
|
#define PWM_CVAL1_COUNT (4U)
|
|
|
|
/*! @name CVAL1CYC - Capture Value 1 Cycle Register */
|
|
/*! @{ */
|
|
#define PWM_CVAL1CYC_CVAL1CYC_MASK (0xFU)
|
|
#define PWM_CVAL1CYC_CVAL1CYC_SHIFT (0U)
|
|
#define PWM_CVAL1CYC_CVAL1CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_CVAL1CYC */
|
|
#define PWM_CVAL1CYC_COUNT (4U)
|
|
|
|
/*! @name CVAL2 - Capture Value 2 Register */
|
|
/*! @{ */
|
|
#define PWM_CVAL2_CAPTVAL2_MASK (0xFFFFU)
|
|
#define PWM_CVAL2_CAPTVAL2_SHIFT (0U)
|
|
#define PWM_CVAL2_CAPTVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_CVAL2 */
|
|
#define PWM_CVAL2_COUNT (4U)
|
|
|
|
/*! @name CVAL2CYC - Capture Value 2 Cycle Register */
|
|
/*! @{ */
|
|
#define PWM_CVAL2CYC_CVAL2CYC_MASK (0xFU)
|
|
#define PWM_CVAL2CYC_CVAL2CYC_SHIFT (0U)
|
|
#define PWM_CVAL2CYC_CVAL2CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_CVAL2CYC */
|
|
#define PWM_CVAL2CYC_COUNT (4U)
|
|
|
|
/*! @name CVAL3 - Capture Value 3 Register */
|
|
/*! @{ */
|
|
#define PWM_CVAL3_CAPTVAL3_MASK (0xFFFFU)
|
|
#define PWM_CVAL3_CAPTVAL3_SHIFT (0U)
|
|
#define PWM_CVAL3_CAPTVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_CVAL3 */
|
|
#define PWM_CVAL3_COUNT (4U)
|
|
|
|
/*! @name CVAL3CYC - Capture Value 3 Cycle Register */
|
|
/*! @{ */
|
|
#define PWM_CVAL3CYC_CVAL3CYC_MASK (0xFU)
|
|
#define PWM_CVAL3CYC_CVAL3CYC_SHIFT (0U)
|
|
#define PWM_CVAL3CYC_CVAL3CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_CVAL3CYC */
|
|
#define PWM_CVAL3CYC_COUNT (4U)
|
|
|
|
/*! @name CVAL4 - Capture Value 4 Register */
|
|
/*! @{ */
|
|
#define PWM_CVAL4_CAPTVAL4_MASK (0xFFFFU)
|
|
#define PWM_CVAL4_CAPTVAL4_SHIFT (0U)
|
|
#define PWM_CVAL4_CAPTVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_CVAL4 */
|
|
#define PWM_CVAL4_COUNT (4U)
|
|
|
|
/*! @name CVAL4CYC - Capture Value 4 Cycle Register */
|
|
/*! @{ */
|
|
#define PWM_CVAL4CYC_CVAL4CYC_MASK (0xFU)
|
|
#define PWM_CVAL4CYC_CVAL4CYC_SHIFT (0U)
|
|
#define PWM_CVAL4CYC_CVAL4CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_CVAL4CYC */
|
|
#define PWM_CVAL4CYC_COUNT (4U)
|
|
|
|
/*! @name CVAL5 - Capture Value 5 Register */
|
|
/*! @{ */
|
|
#define PWM_CVAL5_CAPTVAL5_MASK (0xFFFFU)
|
|
#define PWM_CVAL5_CAPTVAL5_SHIFT (0U)
|
|
#define PWM_CVAL5_CAPTVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_CVAL5 */
|
|
#define PWM_CVAL5_COUNT (4U)
|
|
|
|
/*! @name CVAL5CYC - Capture Value 5 Cycle Register */
|
|
/*! @{ */
|
|
#define PWM_CVAL5CYC_CVAL5CYC_MASK (0xFU)
|
|
#define PWM_CVAL5CYC_CVAL5CYC_SHIFT (0U)
|
|
#define PWM_CVAL5CYC_CVAL5CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of PWM_CVAL5CYC */
|
|
#define PWM_CVAL5CYC_COUNT (4U)
|
|
|
|
/*! @name OUTEN - Output Enable Register */
|
|
/*! @{ */
|
|
#define PWM_OUTEN_PWMX_EN_MASK (0xFU)
|
|
#define PWM_OUTEN_PWMX_EN_SHIFT (0U)
|
|
/*! PWMX_EN - PWM_X Output Enables
|
|
* 0b0000..PWM_X output disabled.
|
|
* 0b0001..PWM_X output enabled.
|
|
*/
|
|
#define PWM_OUTEN_PWMX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK)
|
|
#define PWM_OUTEN_PWMB_EN_MASK (0xF0U)
|
|
#define PWM_OUTEN_PWMB_EN_SHIFT (4U)
|
|
/*! PWMB_EN - PWM_B Output Enables
|
|
* 0b0000..PWM_B output disabled.
|
|
* 0b0001..PWM_B output enabled.
|
|
*/
|
|
#define PWM_OUTEN_PWMB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK)
|
|
#define PWM_OUTEN_PWMA_EN_MASK (0xF00U)
|
|
#define PWM_OUTEN_PWMA_EN_SHIFT (8U)
|
|
/*! PWMA_EN - PWM_A Output Enables
|
|
* 0b0000..PWM_A output disabled.
|
|
* 0b0001..PWM_A output enabled.
|
|
*/
|
|
#define PWM_OUTEN_PWMA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MASK - Mask Register */
|
|
/*! @{ */
|
|
#define PWM_MASK_MASKX_MASK (0xFU)
|
|
#define PWM_MASK_MASKX_SHIFT (0U)
|
|
/*! MASKX - PWM_X Masks
|
|
* 0b0000..PWM_X output normal.
|
|
* 0b0001..PWM_X output masked.
|
|
*/
|
|
#define PWM_MASK_MASKX(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK)
|
|
#define PWM_MASK_MASKB_MASK (0xF0U)
|
|
#define PWM_MASK_MASKB_SHIFT (4U)
|
|
/*! MASKB - PWM_B Masks
|
|
* 0b0000..PWM_B output normal.
|
|
* 0b0001..PWM_B output masked.
|
|
*/
|
|
#define PWM_MASK_MASKB(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK)
|
|
#define PWM_MASK_MASKA_MASK (0xF00U)
|
|
#define PWM_MASK_MASKA_SHIFT (8U)
|
|
/*! MASKA - PWM_A Masks
|
|
* 0b0000..PWM_A output normal.
|
|
* 0b0001..PWM_A output masked.
|
|
*/
|
|
#define PWM_MASK_MASKA(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK)
|
|
#define PWM_MASK_UPDATE_MASK_MASK (0xF000U)
|
|
#define PWM_MASK_UPDATE_MASK_SHIFT (12U)
|
|
/*! UPDATE_MASK - Update Mask Bits Immediately
|
|
* 0b0000..Normal operation. MASK* bits within the corresponding submodule are not updated until a FORCE_OUT event occurs within the submodule.
|
|
* 0b0001..Immediate operation. MASK* bits within the corresponding submodule are updated on the following clock edge after setting this bit.
|
|
*/
|
|
#define PWM_MASK_UPDATE_MASK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SWCOUT - Software Controlled Output Register */
|
|
/*! @{ */
|
|
#define PWM_SWCOUT_SM0OUT45_MASK (0x1U)
|
|
#define PWM_SWCOUT_SM0OUT45_SHIFT (0U)
|
|
/*! SM0OUT45 - Submodule 0 Software Controlled Output 45
|
|
* 0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45.
|
|
* 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45.
|
|
*/
|
|
#define PWM_SWCOUT_SM0OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK)
|
|
#define PWM_SWCOUT_SM0OUT23_MASK (0x2U)
|
|
#define PWM_SWCOUT_SM0OUT23_SHIFT (1U)
|
|
/*! SM0OUT23 - Submodule 0 Software Controlled Output 23
|
|
* 0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23.
|
|
* 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23.
|
|
*/
|
|
#define PWM_SWCOUT_SM0OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK)
|
|
#define PWM_SWCOUT_SM1OUT45_MASK (0x4U)
|
|
#define PWM_SWCOUT_SM1OUT45_SHIFT (2U)
|
|
/*! SM1OUT45 - Submodule 1 Software Controlled Output 45
|
|
* 0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45.
|
|
* 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45.
|
|
*/
|
|
#define PWM_SWCOUT_SM1OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK)
|
|
#define PWM_SWCOUT_SM1OUT23_MASK (0x8U)
|
|
#define PWM_SWCOUT_SM1OUT23_SHIFT (3U)
|
|
/*! SM1OUT23 - Submodule 1 Software Controlled Output 23
|
|
* 0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23.
|
|
* 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23.
|
|
*/
|
|
#define PWM_SWCOUT_SM1OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK)
|
|
#define PWM_SWCOUT_SM2OUT45_MASK (0x10U)
|
|
#define PWM_SWCOUT_SM2OUT45_SHIFT (4U)
|
|
/*! SM2OUT45 - Submodule 2 Software Controlled Output 45
|
|
* 0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45.
|
|
* 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45.
|
|
*/
|
|
#define PWM_SWCOUT_SM2OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK)
|
|
#define PWM_SWCOUT_SM2OUT23_MASK (0x20U)
|
|
#define PWM_SWCOUT_SM2OUT23_SHIFT (5U)
|
|
/*! SM2OUT23 - Submodule 2 Software Controlled Output 23
|
|
* 0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23.
|
|
* 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23.
|
|
*/
|
|
#define PWM_SWCOUT_SM2OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK)
|
|
#define PWM_SWCOUT_SM3OUT45_MASK (0x40U)
|
|
#define PWM_SWCOUT_SM3OUT45_SHIFT (6U)
|
|
/*! SM3OUT45 - Submodule 3 Software Controlled Output 45
|
|
* 0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45.
|
|
* 0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45.
|
|
*/
|
|
#define PWM_SWCOUT_SM3OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK)
|
|
#define PWM_SWCOUT_SM3OUT23_MASK (0x80U)
|
|
#define PWM_SWCOUT_SM3OUT23_SHIFT (7U)
|
|
/*! SM3OUT23 - Submodule 3 Software Controlled Output 23
|
|
* 0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23.
|
|
* 0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23.
|
|
*/
|
|
#define PWM_SWCOUT_SM3OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DTSRCSEL - PWM Source Select Register */
|
|
/*! @{ */
|
|
#define PWM_DTSRCSEL_SM0SEL45_MASK (0x3U)
|
|
#define PWM_DTSRCSEL_SM0SEL45_SHIFT (0U)
|
|
/*! SM0SEL45 - Submodule 0 PWM45 Control Select
|
|
* 0b00..Generated SM0PWM45 signal is used by the deadtime logic.
|
|
* 0b01..Inverted generated SM0PWM45 signal is used by the deadtime logic.
|
|
* 0b10..SWCOUT[SM0OUT45] is used by the deadtime logic.
|
|
* 0b11..PWM0_EXTB signal is used by the deadtime logic.
|
|
*/
|
|
#define PWM_DTSRCSEL_SM0SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK)
|
|
#define PWM_DTSRCSEL_SM0SEL23_MASK (0xCU)
|
|
#define PWM_DTSRCSEL_SM0SEL23_SHIFT (2U)
|
|
/*! SM0SEL23 - Submodule 0 PWM23 Control Select
|
|
* 0b00..Generated SM0PWM23 signal is used by the deadtime logic.
|
|
* 0b01..Inverted generated SM0PWM23 signal is used by the deadtime logic.
|
|
* 0b10..SWCOUT[SM0OUT23] is used by the deadtime logic.
|
|
* 0b11..PWM0_EXTA signal is used by the deadtime logic.
|
|
*/
|
|
#define PWM_DTSRCSEL_SM0SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK)
|
|
#define PWM_DTSRCSEL_SM1SEL45_MASK (0x30U)
|
|
#define PWM_DTSRCSEL_SM1SEL45_SHIFT (4U)
|
|
/*! SM1SEL45 - Submodule 1 PWM45 Control Select
|
|
* 0b00..Generated SM1PWM45 signal is used by the deadtime logic.
|
|
* 0b01..Inverted generated SM1PWM45 signal is used by the deadtime logic.
|
|
* 0b10..SWCOUT[SM1OUT45] is used by the deadtime logic.
|
|
* 0b11..PWM1_EXTB signal is used by the deadtime logic.
|
|
*/
|
|
#define PWM_DTSRCSEL_SM1SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK)
|
|
#define PWM_DTSRCSEL_SM1SEL23_MASK (0xC0U)
|
|
#define PWM_DTSRCSEL_SM1SEL23_SHIFT (6U)
|
|
/*! SM1SEL23 - Submodule 1 PWM23 Control Select
|
|
* 0b00..Generated SM1PWM23 signal is used by the deadtime logic.
|
|
* 0b01..Inverted generated SM1PWM23 signal is used by the deadtime logic.
|
|
* 0b10..SWCOUT[SM1OUT23] is used by the deadtime logic.
|
|
* 0b11..PWM1_EXTA signal is used by the deadtime logic.
|
|
*/
|
|
#define PWM_DTSRCSEL_SM1SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK)
|
|
#define PWM_DTSRCSEL_SM2SEL45_MASK (0x300U)
|
|
#define PWM_DTSRCSEL_SM2SEL45_SHIFT (8U)
|
|
/*! SM2SEL45 - Submodule 2 PWM45 Control Select
|
|
* 0b00..Generated SM2PWM45 signal is used by the deadtime logic.
|
|
* 0b01..Inverted generated SM2PWM45 signal is used by the deadtime logic.
|
|
* 0b10..SWCOUT[SM2OUT45] is used by the deadtime logic.
|
|
* 0b11..PWM2_EXTB signal is used by the deadtime logic.
|
|
*/
|
|
#define PWM_DTSRCSEL_SM2SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK)
|
|
#define PWM_DTSRCSEL_SM2SEL23_MASK (0xC00U)
|
|
#define PWM_DTSRCSEL_SM2SEL23_SHIFT (10U)
|
|
/*! SM2SEL23 - Submodule 2 PWM23 Control Select
|
|
* 0b00..Generated SM2PWM23 signal is used by the deadtime logic.
|
|
* 0b01..Inverted generated SM2PWM23 signal is used by the deadtime logic.
|
|
* 0b10..SWCOUT[SM2OUT23] is used by the deadtime logic.
|
|
* 0b11..PWM2_EXTA signal is used by the deadtime logic.
|
|
*/
|
|
#define PWM_DTSRCSEL_SM2SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK)
|
|
#define PWM_DTSRCSEL_SM3SEL45_MASK (0x3000U)
|
|
#define PWM_DTSRCSEL_SM3SEL45_SHIFT (12U)
|
|
/*! SM3SEL45 - Submodule 3 PWM45 Control Select
|
|
* 0b00..Generated SM3PWM45 signal is used by the deadtime logic.
|
|
* 0b01..Inverted generated SM3PWM45 signal is used by the deadtime logic.
|
|
* 0b10..SWCOUT[SM3OUT45] is used by the deadtime logic.
|
|
* 0b11..PWM3_EXTB signal is used by the deadtime logic.
|
|
*/
|
|
#define PWM_DTSRCSEL_SM3SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK)
|
|
#define PWM_DTSRCSEL_SM3SEL23_MASK (0xC000U)
|
|
#define PWM_DTSRCSEL_SM3SEL23_SHIFT (14U)
|
|
/*! SM3SEL23 - Submodule 3 PWM23 Control Select
|
|
* 0b00..Generated SM3PWM23 signal is used by the deadtime logic.
|
|
* 0b01..Inverted generated SM3PWM23 signal is used by the deadtime logic.
|
|
* 0b10..SWCOUT[SM3OUT23] is used by the deadtime logic.
|
|
* 0b11..PWM3_EXTA signal is used by the deadtime logic.
|
|
*/
|
|
#define PWM_DTSRCSEL_SM3SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MCTRL - Master Control Register */
|
|
/*! @{ */
|
|
#define PWM_MCTRL_LDOK_MASK (0xFU)
|
|
#define PWM_MCTRL_LDOK_SHIFT (0U)
|
|
/*! LDOK - Load Okay
|
|
* 0b0000..Do not load new values.
|
|
* 0b0001..Load prescaler, modulus, and PWM values of the corresponding submodule.
|
|
*/
|
|
#define PWM_MCTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK)
|
|
#define PWM_MCTRL_CLDOK_MASK (0xF0U)
|
|
#define PWM_MCTRL_CLDOK_SHIFT (4U)
|
|
#define PWM_MCTRL_CLDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK)
|
|
#define PWM_MCTRL_RUN_MASK (0xF00U)
|
|
#define PWM_MCTRL_RUN_SHIFT (8U)
|
|
/*! RUN - Run
|
|
* 0b0000..PWM generator is disabled in the corresponding submodule.
|
|
* 0b0001..PWM generator is enabled in the corresponding submodule.
|
|
*/
|
|
#define PWM_MCTRL_RUN(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK)
|
|
#define PWM_MCTRL_IPOL_MASK (0xF000U)
|
|
#define PWM_MCTRL_IPOL_SHIFT (12U)
|
|
/*! IPOL - Current Polarity
|
|
* 0b0000..PWM23 is used to generate complementary PWM pair in the corresponding submodule.
|
|
* 0b0001..PWM45 is used to generate complementary PWM pair in the corresponding submodule.
|
|
*/
|
|
#define PWM_MCTRL_IPOL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MCTRL2 - Master Control 2 Register */
|
|
/*! @{ */
|
|
#define PWM_MCTRL2_MONPLL_MASK (0x3U)
|
|
#define PWM_MCTRL2_MONPLL_SHIFT (0U)
|
|
/*! MONPLL - Monitor PLL State
|
|
* 0b00..Not locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software.
|
|
* 0b01..Not locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems.
|
|
* 0b10..Locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software. These bits are write protected until the next reset.
|
|
* 0b11..Locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems. These bits are write protected until the next reset.
|
|
*/
|
|
#define PWM_MCTRL2_MONPLL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_MONPLL_SHIFT)) & PWM_MCTRL2_MONPLL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FCTRL - Fault Control Register */
|
|
/*! @{ */
|
|
#define PWM_FCTRL_FIE_MASK (0xFU)
|
|
#define PWM_FCTRL_FIE_SHIFT (0U)
|
|
/*! FIE - Fault Interrupt Enables
|
|
* 0b0000..FAULTx CPU interrupt requests disabled.
|
|
* 0b0001..FAULTx CPU interrupt requests enabled.
|
|
*/
|
|
#define PWM_FCTRL_FIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK)
|
|
#define PWM_FCTRL_FSAFE_MASK (0xF0U)
|
|
#define PWM_FCTRL_FSAFE_SHIFT (4U)
|
|
/*! FSAFE - Fault Safety Mode
|
|
* 0b0000..Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL] without regard to the state of FSTS[FFPINx]. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in DISMAPn).
|
|
* 0b0001..Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL].
|
|
*/
|
|
#define PWM_FCTRL_FSAFE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK)
|
|
#define PWM_FCTRL_FAUTO_MASK (0xF00U)
|
|
#define PWM_FCTRL_FAUTO_SHIFT (8U)
|
|
/*! FAUTO - Automatic Fault Clearing
|
|
* 0b0000..Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending the state of FSTS[FFULL]. This is further controlled by FCTRL[FSAFE].
|
|
* 0b0001..Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL] without regard to the state of FSTS[FFLAGx].
|
|
*/
|
|
#define PWM_FCTRL_FAUTO(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK)
|
|
#define PWM_FCTRL_FLVL_MASK (0xF000U)
|
|
#define PWM_FCTRL_FLVL_SHIFT (12U)
|
|
/*! FLVL - Fault Level
|
|
* 0b0000..A logic 0 on the fault input indicates a fault condition.
|
|
* 0b0001..A logic 1 on the fault input indicates a fault condition.
|
|
*/
|
|
#define PWM_FCTRL_FLVL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FSTS - Fault Status Register */
|
|
/*! @{ */
|
|
#define PWM_FSTS_FFLAG_MASK (0xFU)
|
|
#define PWM_FSTS_FFLAG_SHIFT (0U)
|
|
/*! FFLAG - Fault Flags
|
|
* 0b0000..No fault on the FAULTx pin.
|
|
* 0b0001..Fault on the FAULTx pin.
|
|
*/
|
|
#define PWM_FSTS_FFLAG(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK)
|
|
#define PWM_FSTS_FFULL_MASK (0xF0U)
|
|
#define PWM_FSTS_FFULL_SHIFT (4U)
|
|
/*! FFULL - Full Cycle
|
|
* 0b0000..PWM outputs are not re-enabled at the start of a full cycle
|
|
* 0b0001..PWM outputs are re-enabled at the start of a full cycle
|
|
*/
|
|
#define PWM_FSTS_FFULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK)
|
|
#define PWM_FSTS_FFPIN_MASK (0xF00U)
|
|
#define PWM_FSTS_FFPIN_SHIFT (8U)
|
|
#define PWM_FSTS_FFPIN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK)
|
|
#define PWM_FSTS_FHALF_MASK (0xF000U)
|
|
#define PWM_FSTS_FHALF_SHIFT (12U)
|
|
/*! FHALF - Half Cycle Fault Recovery
|
|
* 0b0000..PWM outputs are not re-enabled at the start of a half cycle.
|
|
* 0b0001..PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0).
|
|
*/
|
|
#define PWM_FSTS_FHALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FFILT - Fault Filter Register */
|
|
/*! @{ */
|
|
#define PWM_FFILT_FILT_PER_MASK (0xFFU)
|
|
#define PWM_FFILT_FILT_PER_SHIFT (0U)
|
|
#define PWM_FFILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK)
|
|
#define PWM_FFILT_FILT_CNT_MASK (0x700U)
|
|
#define PWM_FFILT_FILT_CNT_SHIFT (8U)
|
|
#define PWM_FFILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK)
|
|
#define PWM_FFILT_GSTR_MASK (0x8000U)
|
|
#define PWM_FFILT_GSTR_SHIFT (15U)
|
|
/*! GSTR - Fault Glitch Stretch Enable
|
|
* 0b0..Fault input glitch stretching is disabled.
|
|
* 0b1..Input fault signals will be stretched to at least 2 IPBus clock cycles.
|
|
*/
|
|
#define PWM_FFILT_GSTR(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FTST - Fault Test Register */
|
|
/*! @{ */
|
|
#define PWM_FTST_FTEST_MASK (0x1U)
|
|
#define PWM_FTST_FTEST_SHIFT (0U)
|
|
/*! FTEST - Fault Test
|
|
* 0b0..No fault
|
|
* 0b1..Cause a simulated fault
|
|
*/
|
|
#define PWM_FTST_FTEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FCTRL2 - Fault Control 2 Register */
|
|
/*! @{ */
|
|
#define PWM_FCTRL2_NOCOMB_MASK (0xFU)
|
|
#define PWM_FCTRL2_NOCOMB_SHIFT (0U)
|
|
/*! NOCOMB - No Combinational Path From Fault Input To PWM Output
|
|
* 0b0000..There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined with the filtered and latched fault signals to disable the PWM outputs.
|
|
* 0b0001..The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered and latched fault signals are used to disable the PWM outputs.
|
|
*/
|
|
#define PWM_FCTRL2_NOCOMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group PWM_Register_Masks */
|
|
|
|
|
|
/* PWM - Peripheral instance base addresses */
|
|
/** Peripheral PWM1 base address */
|
|
#define PWM1_BASE (0x403DC000u)
|
|
/** Peripheral PWM1 base pointer */
|
|
#define PWM1 ((PWM_Type *)PWM1_BASE)
|
|
/** Peripheral PWM2 base address */
|
|
#define PWM2_BASE (0x403E0000u)
|
|
/** Peripheral PWM2 base pointer */
|
|
#define PWM2 ((PWM_Type *)PWM2_BASE)
|
|
/** Peripheral PWM3 base address */
|
|
#define PWM3_BASE (0x403E4000u)
|
|
/** Peripheral PWM3 base pointer */
|
|
#define PWM3 ((PWM_Type *)PWM3_BASE)
|
|
/** Peripheral PWM4 base address */
|
|
#define PWM4_BASE (0x403E8000u)
|
|
/** Peripheral PWM4 base pointer */
|
|
#define PWM4 ((PWM_Type *)PWM4_BASE)
|
|
/** Array initializer of PWM peripheral base addresses */
|
|
#define PWM_BASE_ADDRS { 0u, PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE }
|
|
/** Array initializer of PWM peripheral base pointers */
|
|
#define PWM_BASE_PTRS { (PWM_Type *)0u, PWM1, PWM2, PWM3, PWM4 }
|
|
/** Interrupt vectors for the PWM peripheral type */
|
|
#define PWM_CMP_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
|
|
#define PWM_RELOAD_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
|
|
#define PWM_CAPTURE_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
|
|
#define PWM_FAULT_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn }
|
|
#define PWM_RELOAD_ERROR_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group PWM_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- PXP Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup PXP_Peripheral_Access_Layer PXP Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** PXP - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t CTRL; /**< Control Register 0, offset: 0x0 */
|
|
__IO uint32_t CTRL_SET; /**< Control Register 0, offset: 0x4 */
|
|
__IO uint32_t CTRL_CLR; /**< Control Register 0, offset: 0x8 */
|
|
__IO uint32_t CTRL_TOG; /**< Control Register 0, offset: 0xC */
|
|
__IO uint32_t STAT; /**< Status Register, offset: 0x10 */
|
|
__IO uint32_t STAT_SET; /**< Status Register, offset: 0x14 */
|
|
__IO uint32_t STAT_CLR; /**< Status Register, offset: 0x18 */
|
|
__IO uint32_t STAT_TOG; /**< Status Register, offset: 0x1C */
|
|
__IO uint32_t OUT_CTRL; /**< Output Buffer Control Register, offset: 0x20 */
|
|
__IO uint32_t OUT_CTRL_SET; /**< Output Buffer Control Register, offset: 0x24 */
|
|
__IO uint32_t OUT_CTRL_CLR; /**< Output Buffer Control Register, offset: 0x28 */
|
|
__IO uint32_t OUT_CTRL_TOG; /**< Output Buffer Control Register, offset: 0x2C */
|
|
__IO uint32_t OUT_BUF; /**< Output Frame Buffer Pointer, offset: 0x30 */
|
|
uint8_t RESERVED_0[12];
|
|
__IO uint32_t OUT_BUF2; /**< Output Frame Buffer Pointer #2, offset: 0x40 */
|
|
uint8_t RESERVED_1[12];
|
|
__IO uint32_t OUT_PITCH; /**< Output Buffer Pitch, offset: 0x50 */
|
|
uint8_t RESERVED_2[12];
|
|
__IO uint32_t OUT_LRC; /**< Output Surface Lower Right Coordinate, offset: 0x60 */
|
|
uint8_t RESERVED_3[12];
|
|
__IO uint32_t OUT_PS_ULC; /**< Processed Surface Upper Left Coordinate, offset: 0x70 */
|
|
uint8_t RESERVED_4[12];
|
|
__IO uint32_t OUT_PS_LRC; /**< Processed Surface Lower Right Coordinate, offset: 0x80 */
|
|
uint8_t RESERVED_5[12];
|
|
__IO uint32_t OUT_AS_ULC; /**< Alpha Surface Upper Left Coordinate, offset: 0x90 */
|
|
uint8_t RESERVED_6[12];
|
|
__IO uint32_t OUT_AS_LRC; /**< Alpha Surface Lower Right Coordinate, offset: 0xA0 */
|
|
uint8_t RESERVED_7[12];
|
|
__IO uint32_t PS_CTRL; /**< Processed Surface (PS) Control Register, offset: 0xB0 */
|
|
__IO uint32_t PS_CTRL_SET; /**< Processed Surface (PS) Control Register, offset: 0xB4 */
|
|
__IO uint32_t PS_CTRL_CLR; /**< Processed Surface (PS) Control Register, offset: 0xB8 */
|
|
__IO uint32_t PS_CTRL_TOG; /**< Processed Surface (PS) Control Register, offset: 0xBC */
|
|
__IO uint32_t PS_BUF; /**< PS Input Buffer Address, offset: 0xC0 */
|
|
uint8_t RESERVED_8[12];
|
|
__IO uint32_t PS_UBUF; /**< PS U/Cb or 2 Plane UV Input Buffer Address, offset: 0xD0 */
|
|
uint8_t RESERVED_9[12];
|
|
__IO uint32_t PS_VBUF; /**< PS V/Cr Input Buffer Address, offset: 0xE0 */
|
|
uint8_t RESERVED_10[12];
|
|
__IO uint32_t PS_PITCH; /**< Processed Surface Pitch, offset: 0xF0 */
|
|
uint8_t RESERVED_11[12];
|
|
__IO uint32_t PS_BACKGROUND; /**< PS Background Color, offset: 0x100 */
|
|
uint8_t RESERVED_12[12];
|
|
__IO uint32_t PS_SCALE; /**< PS Scale Factor Register, offset: 0x110 */
|
|
uint8_t RESERVED_13[12];
|
|
__IO uint32_t PS_OFFSET; /**< PS Scale Offset Register, offset: 0x120 */
|
|
uint8_t RESERVED_14[12];
|
|
__IO uint32_t PS_CLRKEYLOW; /**< PS Color Key Low, offset: 0x130 */
|
|
uint8_t RESERVED_15[12];
|
|
__IO uint32_t PS_CLRKEYHIGH; /**< PS Color Key High, offset: 0x140 */
|
|
uint8_t RESERVED_16[12];
|
|
__IO uint32_t AS_CTRL; /**< Alpha Surface Control, offset: 0x150 */
|
|
uint8_t RESERVED_17[12];
|
|
__IO uint32_t AS_BUF; /**< Alpha Surface Buffer Pointer, offset: 0x160 */
|
|
uint8_t RESERVED_18[12];
|
|
__IO uint32_t AS_PITCH; /**< Alpha Surface Pitch, offset: 0x170 */
|
|
uint8_t RESERVED_19[12];
|
|
__IO uint32_t AS_CLRKEYLOW; /**< Overlay Color Key Low, offset: 0x180 */
|
|
uint8_t RESERVED_20[12];
|
|
__IO uint32_t AS_CLRKEYHIGH; /**< Overlay Color Key High, offset: 0x190 */
|
|
uint8_t RESERVED_21[12];
|
|
__IO uint32_t CSC1_COEF0; /**< Color Space Conversion Coefficient Register 0, offset: 0x1A0 */
|
|
uint8_t RESERVED_22[12];
|
|
__IO uint32_t CSC1_COEF1; /**< Color Space Conversion Coefficient Register 1, offset: 0x1B0 */
|
|
uint8_t RESERVED_23[12];
|
|
__IO uint32_t CSC1_COEF2; /**< Color Space Conversion Coefficient Register 2, offset: 0x1C0 */
|
|
uint8_t RESERVED_24[348];
|
|
__IO uint32_t POWER; /**< PXP Power Control Register, offset: 0x320 */
|
|
uint8_t RESERVED_25[220];
|
|
__IO uint32_t NEXT; /**< Next Frame Pointer, offset: 0x400 */
|
|
uint8_t RESERVED_26[60];
|
|
__IO uint32_t PORTER_DUFF_CTRL; /**< PXP Alpha Engine A Control Register., offset: 0x440 */
|
|
} PXP_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- PXP Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup PXP_Register_Masks PXP Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name CTRL - Control Register 0 */
|
|
/*! @{ */
|
|
#define PXP_CTRL_ENABLE_MASK (0x1U)
|
|
#define PXP_CTRL_ENABLE_SHIFT (0U)
|
|
#define PXP_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_SHIFT)) & PXP_CTRL_ENABLE_MASK)
|
|
#define PXP_CTRL_IRQ_ENABLE_MASK (0x2U)
|
|
#define PXP_CTRL_IRQ_ENABLE_SHIFT (1U)
|
|
#define PXP_CTRL_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_IRQ_ENABLE_SHIFT)) & PXP_CTRL_IRQ_ENABLE_MASK)
|
|
#define PXP_CTRL_NEXT_IRQ_ENABLE_MASK (0x4U)
|
|
#define PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT (2U)
|
|
#define PXP_CTRL_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_NEXT_IRQ_ENABLE_MASK)
|
|
#define PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK (0x10U)
|
|
#define PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT (4U)
|
|
#define PXP_CTRL_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK)
|
|
#define PXP_CTRL_RSVD0_MASK (0xE0U)
|
|
#define PXP_CTRL_RSVD0_SHIFT (5U)
|
|
#define PXP_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD0_SHIFT)) & PXP_CTRL_RSVD0_MASK)
|
|
#define PXP_CTRL_ROTATE_MASK (0x300U)
|
|
#define PXP_CTRL_ROTATE_SHIFT (8U)
|
|
/*! ROTATE
|
|
* 0b00..ROT_0
|
|
* 0b01..ROT_90
|
|
* 0b10..ROT_180
|
|
* 0b11..ROT_270
|
|
*/
|
|
#define PXP_CTRL_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROTATE_SHIFT)) & PXP_CTRL_ROTATE_MASK)
|
|
#define PXP_CTRL_HFLIP_MASK (0x400U)
|
|
#define PXP_CTRL_HFLIP_SHIFT (10U)
|
|
#define PXP_CTRL_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HFLIP_SHIFT)) & PXP_CTRL_HFLIP_MASK)
|
|
#define PXP_CTRL_VFLIP_MASK (0x800U)
|
|
#define PXP_CTRL_VFLIP_SHIFT (11U)
|
|
#define PXP_CTRL_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_VFLIP_SHIFT)) & PXP_CTRL_VFLIP_MASK)
|
|
#define PXP_CTRL_RSVD1_MASK (0x3FF000U)
|
|
#define PXP_CTRL_RSVD1_SHIFT (12U)
|
|
#define PXP_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD1_SHIFT)) & PXP_CTRL_RSVD1_MASK)
|
|
#define PXP_CTRL_ROT_POS_MASK (0x400000U)
|
|
#define PXP_CTRL_ROT_POS_SHIFT (22U)
|
|
#define PXP_CTRL_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROT_POS_SHIFT)) & PXP_CTRL_ROT_POS_MASK)
|
|
#define PXP_CTRL_BLOCK_SIZE_MASK (0x800000U)
|
|
#define PXP_CTRL_BLOCK_SIZE_SHIFT (23U)
|
|
/*! BLOCK_SIZE
|
|
* 0b0..Process 8x8 pixel blocks.
|
|
* 0b1..Process 16x16 pixel blocks.
|
|
*/
|
|
#define PXP_CTRL_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_BLOCK_SIZE_SHIFT)) & PXP_CTRL_BLOCK_SIZE_MASK)
|
|
#define PXP_CTRL_RSVD3_MASK (0xF000000U)
|
|
#define PXP_CTRL_RSVD3_SHIFT (24U)
|
|
#define PXP_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD3_SHIFT)) & PXP_CTRL_RSVD3_MASK)
|
|
#define PXP_CTRL_EN_REPEAT_MASK (0x10000000U)
|
|
#define PXP_CTRL_EN_REPEAT_SHIFT (28U)
|
|
#define PXP_CTRL_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_EN_REPEAT_SHIFT)) & PXP_CTRL_EN_REPEAT_MASK)
|
|
#define PXP_CTRL_RSVD4_MASK (0x20000000U)
|
|
#define PXP_CTRL_RSVD4_SHIFT (29U)
|
|
#define PXP_CTRL_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD4_SHIFT)) & PXP_CTRL_RSVD4_MASK)
|
|
#define PXP_CTRL_CLKGATE_MASK (0x40000000U)
|
|
#define PXP_CTRL_CLKGATE_SHIFT (30U)
|
|
#define PXP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLKGATE_SHIFT)) & PXP_CTRL_CLKGATE_MASK)
|
|
#define PXP_CTRL_SFTRST_MASK (0x80000000U)
|
|
#define PXP_CTRL_SFTRST_SHIFT (31U)
|
|
#define PXP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SFTRST_SHIFT)) & PXP_CTRL_SFTRST_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CTRL_SET - Control Register 0 */
|
|
/*! @{ */
|
|
#define PXP_CTRL_SET_ENABLE_MASK (0x1U)
|
|
#define PXP_CTRL_SET_ENABLE_SHIFT (0U)
|
|
#define PXP_CTRL_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_SHIFT)) & PXP_CTRL_SET_ENABLE_MASK)
|
|
#define PXP_CTRL_SET_IRQ_ENABLE_MASK (0x2U)
|
|
#define PXP_CTRL_SET_IRQ_ENABLE_SHIFT (1U)
|
|
#define PXP_CTRL_SET_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_IRQ_ENABLE_MASK)
|
|
#define PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK (0x4U)
|
|
#define PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT (2U)
|
|
#define PXP_CTRL_SET_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK)
|
|
#define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK (0x10U)
|
|
#define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT (4U)
|
|
#define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK)
|
|
#define PXP_CTRL_SET_RSVD0_MASK (0xE0U)
|
|
#define PXP_CTRL_SET_RSVD0_SHIFT (5U)
|
|
#define PXP_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD0_SHIFT)) & PXP_CTRL_SET_RSVD0_MASK)
|
|
#define PXP_CTRL_SET_ROTATE_MASK (0x300U)
|
|
#define PXP_CTRL_SET_ROTATE_SHIFT (8U)
|
|
/*! ROTATE
|
|
* 0b00..ROT_0
|
|
* 0b01..ROT_90
|
|
* 0b10..ROT_180
|
|
* 0b11..ROT_270
|
|
*/
|
|
#define PXP_CTRL_SET_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROTATE_SHIFT)) & PXP_CTRL_SET_ROTATE_MASK)
|
|
#define PXP_CTRL_SET_HFLIP_MASK (0x400U)
|
|
#define PXP_CTRL_SET_HFLIP_SHIFT (10U)
|
|
#define PXP_CTRL_SET_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HFLIP_SHIFT)) & PXP_CTRL_SET_HFLIP_MASK)
|
|
#define PXP_CTRL_SET_VFLIP_MASK (0x800U)
|
|
#define PXP_CTRL_SET_VFLIP_SHIFT (11U)
|
|
#define PXP_CTRL_SET_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_VFLIP_SHIFT)) & PXP_CTRL_SET_VFLIP_MASK)
|
|
#define PXP_CTRL_SET_RSVD1_MASK (0x3FF000U)
|
|
#define PXP_CTRL_SET_RSVD1_SHIFT (12U)
|
|
#define PXP_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD1_SHIFT)) & PXP_CTRL_SET_RSVD1_MASK)
|
|
#define PXP_CTRL_SET_ROT_POS_MASK (0x400000U)
|
|
#define PXP_CTRL_SET_ROT_POS_SHIFT (22U)
|
|
#define PXP_CTRL_SET_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROT_POS_SHIFT)) & PXP_CTRL_SET_ROT_POS_MASK)
|
|
#define PXP_CTRL_SET_BLOCK_SIZE_MASK (0x800000U)
|
|
#define PXP_CTRL_SET_BLOCK_SIZE_SHIFT (23U)
|
|
/*! BLOCK_SIZE
|
|
* 0b0..Process 8x8 pixel blocks.
|
|
* 0b1..Process 16x16 pixel blocks.
|
|
*/
|
|
#define PXP_CTRL_SET_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_BLOCK_SIZE_SHIFT)) & PXP_CTRL_SET_BLOCK_SIZE_MASK)
|
|
#define PXP_CTRL_SET_RSVD3_MASK (0xF000000U)
|
|
#define PXP_CTRL_SET_RSVD3_SHIFT (24U)
|
|
#define PXP_CTRL_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD3_SHIFT)) & PXP_CTRL_SET_RSVD3_MASK)
|
|
#define PXP_CTRL_SET_EN_REPEAT_MASK (0x10000000U)
|
|
#define PXP_CTRL_SET_EN_REPEAT_SHIFT (28U)
|
|
#define PXP_CTRL_SET_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_EN_REPEAT_SHIFT)) & PXP_CTRL_SET_EN_REPEAT_MASK)
|
|
#define PXP_CTRL_SET_RSVD4_MASK (0x20000000U)
|
|
#define PXP_CTRL_SET_RSVD4_SHIFT (29U)
|
|
#define PXP_CTRL_SET_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD4_SHIFT)) & PXP_CTRL_SET_RSVD4_MASK)
|
|
#define PXP_CTRL_SET_CLKGATE_MASK (0x40000000U)
|
|
#define PXP_CTRL_SET_CLKGATE_SHIFT (30U)
|
|
#define PXP_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_CLKGATE_SHIFT)) & PXP_CTRL_SET_CLKGATE_MASK)
|
|
#define PXP_CTRL_SET_SFTRST_MASK (0x80000000U)
|
|
#define PXP_CTRL_SET_SFTRST_SHIFT (31U)
|
|
#define PXP_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_SFTRST_SHIFT)) & PXP_CTRL_SET_SFTRST_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CTRL_CLR - Control Register 0 */
|
|
/*! @{ */
|
|
#define PXP_CTRL_CLR_ENABLE_MASK (0x1U)
|
|
#define PXP_CTRL_CLR_ENABLE_SHIFT (0U)
|
|
#define PXP_CTRL_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_SHIFT)) & PXP_CTRL_CLR_ENABLE_MASK)
|
|
#define PXP_CTRL_CLR_IRQ_ENABLE_MASK (0x2U)
|
|
#define PXP_CTRL_CLR_IRQ_ENABLE_SHIFT (1U)
|
|
#define PXP_CTRL_CLR_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_IRQ_ENABLE_MASK)
|
|
#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK (0x4U)
|
|
#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT (2U)
|
|
#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK)
|
|
#define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK (0x10U)
|
|
#define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT (4U)
|
|
#define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK)
|
|
#define PXP_CTRL_CLR_RSVD0_MASK (0xE0U)
|
|
#define PXP_CTRL_CLR_RSVD0_SHIFT (5U)
|
|
#define PXP_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD0_SHIFT)) & PXP_CTRL_CLR_RSVD0_MASK)
|
|
#define PXP_CTRL_CLR_ROTATE_MASK (0x300U)
|
|
#define PXP_CTRL_CLR_ROTATE_SHIFT (8U)
|
|
/*! ROTATE
|
|
* 0b00..ROT_0
|
|
* 0b01..ROT_90
|
|
* 0b10..ROT_180
|
|
* 0b11..ROT_270
|
|
*/
|
|
#define PXP_CTRL_CLR_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROTATE_SHIFT)) & PXP_CTRL_CLR_ROTATE_MASK)
|
|
#define PXP_CTRL_CLR_HFLIP_MASK (0x400U)
|
|
#define PXP_CTRL_CLR_HFLIP_SHIFT (10U)
|
|
#define PXP_CTRL_CLR_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HFLIP_SHIFT)) & PXP_CTRL_CLR_HFLIP_MASK)
|
|
#define PXP_CTRL_CLR_VFLIP_MASK (0x800U)
|
|
#define PXP_CTRL_CLR_VFLIP_SHIFT (11U)
|
|
#define PXP_CTRL_CLR_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_VFLIP_SHIFT)) & PXP_CTRL_CLR_VFLIP_MASK)
|
|
#define PXP_CTRL_CLR_RSVD1_MASK (0x3FF000U)
|
|
#define PXP_CTRL_CLR_RSVD1_SHIFT (12U)
|
|
#define PXP_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD1_SHIFT)) & PXP_CTRL_CLR_RSVD1_MASK)
|
|
#define PXP_CTRL_CLR_ROT_POS_MASK (0x400000U)
|
|
#define PXP_CTRL_CLR_ROT_POS_SHIFT (22U)
|
|
#define PXP_CTRL_CLR_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROT_POS_SHIFT)) & PXP_CTRL_CLR_ROT_POS_MASK)
|
|
#define PXP_CTRL_CLR_BLOCK_SIZE_MASK (0x800000U)
|
|
#define PXP_CTRL_CLR_BLOCK_SIZE_SHIFT (23U)
|
|
/*! BLOCK_SIZE
|
|
* 0b0..Process 8x8 pixel blocks.
|
|
* 0b1..Process 16x16 pixel blocks.
|
|
*/
|
|
#define PXP_CTRL_CLR_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_BLOCK_SIZE_SHIFT)) & PXP_CTRL_CLR_BLOCK_SIZE_MASK)
|
|
#define PXP_CTRL_CLR_RSVD3_MASK (0xF000000U)
|
|
#define PXP_CTRL_CLR_RSVD3_SHIFT (24U)
|
|
#define PXP_CTRL_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD3_SHIFT)) & PXP_CTRL_CLR_RSVD3_MASK)
|
|
#define PXP_CTRL_CLR_EN_REPEAT_MASK (0x10000000U)
|
|
#define PXP_CTRL_CLR_EN_REPEAT_SHIFT (28U)
|
|
#define PXP_CTRL_CLR_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_EN_REPEAT_SHIFT)) & PXP_CTRL_CLR_EN_REPEAT_MASK)
|
|
#define PXP_CTRL_CLR_RSVD4_MASK (0x20000000U)
|
|
#define PXP_CTRL_CLR_RSVD4_SHIFT (29U)
|
|
#define PXP_CTRL_CLR_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD4_SHIFT)) & PXP_CTRL_CLR_RSVD4_MASK)
|
|
#define PXP_CTRL_CLR_CLKGATE_MASK (0x40000000U)
|
|
#define PXP_CTRL_CLR_CLKGATE_SHIFT (30U)
|
|
#define PXP_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_CLKGATE_SHIFT)) & PXP_CTRL_CLR_CLKGATE_MASK)
|
|
#define PXP_CTRL_CLR_SFTRST_MASK (0x80000000U)
|
|
#define PXP_CTRL_CLR_SFTRST_SHIFT (31U)
|
|
#define PXP_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_SFTRST_SHIFT)) & PXP_CTRL_CLR_SFTRST_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CTRL_TOG - Control Register 0 */
|
|
/*! @{ */
|
|
#define PXP_CTRL_TOG_ENABLE_MASK (0x1U)
|
|
#define PXP_CTRL_TOG_ENABLE_SHIFT (0U)
|
|
#define PXP_CTRL_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_SHIFT)) & PXP_CTRL_TOG_ENABLE_MASK)
|
|
#define PXP_CTRL_TOG_IRQ_ENABLE_MASK (0x2U)
|
|
#define PXP_CTRL_TOG_IRQ_ENABLE_SHIFT (1U)
|
|
#define PXP_CTRL_TOG_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_IRQ_ENABLE_MASK)
|
|
#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK (0x4U)
|
|
#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT (2U)
|
|
#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK)
|
|
#define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK (0x10U)
|
|
#define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT (4U)
|
|
#define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK)
|
|
#define PXP_CTRL_TOG_RSVD0_MASK (0xE0U)
|
|
#define PXP_CTRL_TOG_RSVD0_SHIFT (5U)
|
|
#define PXP_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD0_SHIFT)) & PXP_CTRL_TOG_RSVD0_MASK)
|
|
#define PXP_CTRL_TOG_ROTATE_MASK (0x300U)
|
|
#define PXP_CTRL_TOG_ROTATE_SHIFT (8U)
|
|
/*! ROTATE
|
|
* 0b00..ROT_0
|
|
* 0b01..ROT_90
|
|
* 0b10..ROT_180
|
|
* 0b11..ROT_270
|
|
*/
|
|
#define PXP_CTRL_TOG_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROTATE_SHIFT)) & PXP_CTRL_TOG_ROTATE_MASK)
|
|
#define PXP_CTRL_TOG_HFLIP_MASK (0x400U)
|
|
#define PXP_CTRL_TOG_HFLIP_SHIFT (10U)
|
|
#define PXP_CTRL_TOG_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HFLIP_SHIFT)) & PXP_CTRL_TOG_HFLIP_MASK)
|
|
#define PXP_CTRL_TOG_VFLIP_MASK (0x800U)
|
|
#define PXP_CTRL_TOG_VFLIP_SHIFT (11U)
|
|
#define PXP_CTRL_TOG_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_VFLIP_SHIFT)) & PXP_CTRL_TOG_VFLIP_MASK)
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#define PXP_CTRL_TOG_RSVD1_MASK (0x3FF000U)
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#define PXP_CTRL_TOG_RSVD1_SHIFT (12U)
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#define PXP_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD1_SHIFT)) & PXP_CTRL_TOG_RSVD1_MASK)
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#define PXP_CTRL_TOG_ROT_POS_MASK (0x400000U)
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#define PXP_CTRL_TOG_ROT_POS_SHIFT (22U)
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#define PXP_CTRL_TOG_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROT_POS_SHIFT)) & PXP_CTRL_TOG_ROT_POS_MASK)
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#define PXP_CTRL_TOG_BLOCK_SIZE_MASK (0x800000U)
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#define PXP_CTRL_TOG_BLOCK_SIZE_SHIFT (23U)
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/*! BLOCK_SIZE
|
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* 0b0..Process 8x8 pixel blocks.
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* 0b1..Process 16x16 pixel blocks.
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*/
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#define PXP_CTRL_TOG_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_BLOCK_SIZE_SHIFT)) & PXP_CTRL_TOG_BLOCK_SIZE_MASK)
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#define PXP_CTRL_TOG_RSVD3_MASK (0xF000000U)
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#define PXP_CTRL_TOG_RSVD3_SHIFT (24U)
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#define PXP_CTRL_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD3_SHIFT)) & PXP_CTRL_TOG_RSVD3_MASK)
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#define PXP_CTRL_TOG_EN_REPEAT_MASK (0x10000000U)
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#define PXP_CTRL_TOG_EN_REPEAT_SHIFT (28U)
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#define PXP_CTRL_TOG_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_EN_REPEAT_SHIFT)) & PXP_CTRL_TOG_EN_REPEAT_MASK)
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#define PXP_CTRL_TOG_RSVD4_MASK (0x20000000U)
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#define PXP_CTRL_TOG_RSVD4_SHIFT (29U)
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#define PXP_CTRL_TOG_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD4_SHIFT)) & PXP_CTRL_TOG_RSVD4_MASK)
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#define PXP_CTRL_TOG_CLKGATE_MASK (0x40000000U)
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#define PXP_CTRL_TOG_CLKGATE_SHIFT (30U)
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#define PXP_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_CLKGATE_SHIFT)) & PXP_CTRL_TOG_CLKGATE_MASK)
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#define PXP_CTRL_TOG_SFTRST_MASK (0x80000000U)
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#define PXP_CTRL_TOG_SFTRST_SHIFT (31U)
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#define PXP_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_SFTRST_SHIFT)) & PXP_CTRL_TOG_SFTRST_MASK)
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/*! @} */
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/*! @name STAT - Status Register */
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/*! @{ */
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#define PXP_STAT_IRQ_MASK (0x1U)
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#define PXP_STAT_IRQ_SHIFT (0U)
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#define PXP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_IRQ_SHIFT)) & PXP_STAT_IRQ_MASK)
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#define PXP_STAT_AXI_WRITE_ERROR_MASK (0x2U)
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#define PXP_STAT_AXI_WRITE_ERROR_SHIFT (1U)
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#define PXP_STAT_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_AXI_WRITE_ERROR_MASK)
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#define PXP_STAT_AXI_READ_ERROR_MASK (0x4U)
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#define PXP_STAT_AXI_READ_ERROR_SHIFT (2U)
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#define PXP_STAT_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_READ_ERROR_SHIFT)) & PXP_STAT_AXI_READ_ERROR_MASK)
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#define PXP_STAT_NEXT_IRQ_MASK (0x8U)
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#define PXP_STAT_NEXT_IRQ_SHIFT (3U)
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#define PXP_STAT_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_NEXT_IRQ_SHIFT)) & PXP_STAT_NEXT_IRQ_MASK)
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#define PXP_STAT_AXI_ERROR_ID_MASK (0xF0U)
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#define PXP_STAT_AXI_ERROR_ID_SHIFT (4U)
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#define PXP_STAT_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_ERROR_ID_SHIFT)) & PXP_STAT_AXI_ERROR_ID_MASK)
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#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)
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#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
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#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK)
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#define PXP_STAT_RSVD2_MASK (0xFE00U)
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#define PXP_STAT_RSVD2_SHIFT (9U)
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#define PXP_STAT_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_RSVD2_SHIFT)) & PXP_STAT_RSVD2_MASK)
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#define PXP_STAT_BLOCKY_MASK (0xFF0000U)
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#define PXP_STAT_BLOCKY_SHIFT (16U)
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#define PXP_STAT_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKY_SHIFT)) & PXP_STAT_BLOCKY_MASK)
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#define PXP_STAT_BLOCKX_MASK (0xFF000000U)
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#define PXP_STAT_BLOCKX_SHIFT (24U)
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#define PXP_STAT_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKX_SHIFT)) & PXP_STAT_BLOCKX_MASK)
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/*! @} */
|
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|
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/*! @name STAT_SET - Status Register */
|
|
/*! @{ */
|
|
#define PXP_STAT_SET_IRQ_MASK (0x1U)
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#define PXP_STAT_SET_IRQ_SHIFT (0U)
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#define PXP_STAT_SET_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_IRQ_SHIFT)) & PXP_STAT_SET_IRQ_MASK)
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#define PXP_STAT_SET_AXI_WRITE_ERROR_MASK (0x2U)
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|
#define PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT (1U)
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|
#define PXP_STAT_SET_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_SET_AXI_WRITE_ERROR_MASK)
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|
#define PXP_STAT_SET_AXI_READ_ERROR_MASK (0x4U)
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|
#define PXP_STAT_SET_AXI_READ_ERROR_SHIFT (2U)
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|
#define PXP_STAT_SET_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_READ_ERROR_SHIFT)) & PXP_STAT_SET_AXI_READ_ERROR_MASK)
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|
#define PXP_STAT_SET_NEXT_IRQ_MASK (0x8U)
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#define PXP_STAT_SET_NEXT_IRQ_SHIFT (3U)
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#define PXP_STAT_SET_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_NEXT_IRQ_SHIFT)) & PXP_STAT_SET_NEXT_IRQ_MASK)
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|
#define PXP_STAT_SET_AXI_ERROR_ID_MASK (0xF0U)
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|
#define PXP_STAT_SET_AXI_ERROR_ID_SHIFT (4U)
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|
#define PXP_STAT_SET_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_ERROR_ID_SHIFT)) & PXP_STAT_SET_AXI_ERROR_ID_MASK)
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|
#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)
|
|
#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
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|
#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK)
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|
#define PXP_STAT_SET_RSVD2_MASK (0xFE00U)
|
|
#define PXP_STAT_SET_RSVD2_SHIFT (9U)
|
|
#define PXP_STAT_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_RSVD2_SHIFT)) & PXP_STAT_SET_RSVD2_MASK)
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|
#define PXP_STAT_SET_BLOCKY_MASK (0xFF0000U)
|
|
#define PXP_STAT_SET_BLOCKY_SHIFT (16U)
|
|
#define PXP_STAT_SET_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKY_SHIFT)) & PXP_STAT_SET_BLOCKY_MASK)
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|
#define PXP_STAT_SET_BLOCKX_MASK (0xFF000000U)
|
|
#define PXP_STAT_SET_BLOCKX_SHIFT (24U)
|
|
#define PXP_STAT_SET_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKX_SHIFT)) & PXP_STAT_SET_BLOCKX_MASK)
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|
/*! @} */
|
|
|
|
/*! @name STAT_CLR - Status Register */
|
|
/*! @{ */
|
|
#define PXP_STAT_CLR_IRQ_MASK (0x1U)
|
|
#define PXP_STAT_CLR_IRQ_SHIFT (0U)
|
|
#define PXP_STAT_CLR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_IRQ_SHIFT)) & PXP_STAT_CLR_IRQ_MASK)
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|
#define PXP_STAT_CLR_AXI_WRITE_ERROR_MASK (0x2U)
|
|
#define PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT (1U)
|
|
#define PXP_STAT_CLR_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_WRITE_ERROR_MASK)
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|
#define PXP_STAT_CLR_AXI_READ_ERROR_MASK (0x4U)
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|
#define PXP_STAT_CLR_AXI_READ_ERROR_SHIFT (2U)
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|
#define PXP_STAT_CLR_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_READ_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_READ_ERROR_MASK)
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|
#define PXP_STAT_CLR_NEXT_IRQ_MASK (0x8U)
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|
#define PXP_STAT_CLR_NEXT_IRQ_SHIFT (3U)
|
|
#define PXP_STAT_CLR_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_NEXT_IRQ_SHIFT)) & PXP_STAT_CLR_NEXT_IRQ_MASK)
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|
#define PXP_STAT_CLR_AXI_ERROR_ID_MASK (0xF0U)
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|
#define PXP_STAT_CLR_AXI_ERROR_ID_SHIFT (4U)
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|
#define PXP_STAT_CLR_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_ERROR_ID_SHIFT)) & PXP_STAT_CLR_AXI_ERROR_ID_MASK)
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|
#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)
|
|
#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
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|
#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK)
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|
#define PXP_STAT_CLR_RSVD2_MASK (0xFE00U)
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|
#define PXP_STAT_CLR_RSVD2_SHIFT (9U)
|
|
#define PXP_STAT_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_RSVD2_SHIFT)) & PXP_STAT_CLR_RSVD2_MASK)
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|
#define PXP_STAT_CLR_BLOCKY_MASK (0xFF0000U)
|
|
#define PXP_STAT_CLR_BLOCKY_SHIFT (16U)
|
|
#define PXP_STAT_CLR_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKY_SHIFT)) & PXP_STAT_CLR_BLOCKY_MASK)
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|
#define PXP_STAT_CLR_BLOCKX_MASK (0xFF000000U)
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|
#define PXP_STAT_CLR_BLOCKX_SHIFT (24U)
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|
#define PXP_STAT_CLR_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKX_SHIFT)) & PXP_STAT_CLR_BLOCKX_MASK)
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|
/*! @} */
|
|
|
|
/*! @name STAT_TOG - Status Register */
|
|
/*! @{ */
|
|
#define PXP_STAT_TOG_IRQ_MASK (0x1U)
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|
#define PXP_STAT_TOG_IRQ_SHIFT (0U)
|
|
#define PXP_STAT_TOG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_IRQ_SHIFT)) & PXP_STAT_TOG_IRQ_MASK)
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|
#define PXP_STAT_TOG_AXI_WRITE_ERROR_MASK (0x2U)
|
|
#define PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT (1U)
|
|
#define PXP_STAT_TOG_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_WRITE_ERROR_MASK)
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|
#define PXP_STAT_TOG_AXI_READ_ERROR_MASK (0x4U)
|
|
#define PXP_STAT_TOG_AXI_READ_ERROR_SHIFT (2U)
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|
#define PXP_STAT_TOG_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_READ_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_READ_ERROR_MASK)
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|
#define PXP_STAT_TOG_NEXT_IRQ_MASK (0x8U)
|
|
#define PXP_STAT_TOG_NEXT_IRQ_SHIFT (3U)
|
|
#define PXP_STAT_TOG_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_NEXT_IRQ_SHIFT)) & PXP_STAT_TOG_NEXT_IRQ_MASK)
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|
#define PXP_STAT_TOG_AXI_ERROR_ID_MASK (0xF0U)
|
|
#define PXP_STAT_TOG_AXI_ERROR_ID_SHIFT (4U)
|
|
#define PXP_STAT_TOG_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_ERROR_ID_SHIFT)) & PXP_STAT_TOG_AXI_ERROR_ID_MASK)
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|
#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)
|
|
#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
|
|
#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK)
|
|
#define PXP_STAT_TOG_RSVD2_MASK (0xFE00U)
|
|
#define PXP_STAT_TOG_RSVD2_SHIFT (9U)
|
|
#define PXP_STAT_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_RSVD2_SHIFT)) & PXP_STAT_TOG_RSVD2_MASK)
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|
#define PXP_STAT_TOG_BLOCKY_MASK (0xFF0000U)
|
|
#define PXP_STAT_TOG_BLOCKY_SHIFT (16U)
|
|
#define PXP_STAT_TOG_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKY_SHIFT)) & PXP_STAT_TOG_BLOCKY_MASK)
|
|
#define PXP_STAT_TOG_BLOCKX_MASK (0xFF000000U)
|
|
#define PXP_STAT_TOG_BLOCKX_SHIFT (24U)
|
|
#define PXP_STAT_TOG_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKX_SHIFT)) & PXP_STAT_TOG_BLOCKX_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name OUT_CTRL - Output Buffer Control Register */
|
|
/*! @{ */
|
|
#define PXP_OUT_CTRL_FORMAT_MASK (0x1FU)
|
|
#define PXP_OUT_CTRL_FORMAT_SHIFT (0U)
|
|
/*! FORMAT
|
|
* 0b00000..32-bit pixels
|
|
* 0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.)
|
|
* 0b00101..24-bit pixels (packed 24-bit format)
|
|
* 0b01000..16-bit pixels
|
|
* 0b01001..16-bit pixels
|
|
* 0b01100..16-bit pixels
|
|
* 0b01101..16-bit pixels
|
|
* 0b01110..16-bit pixels
|
|
* 0b10000..32-bit pixels (1-plane XYUV unpacked)
|
|
* 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
|
|
* 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
|
|
* 0b10100..8-bit monochrome pixels (1-plane Y luma output)
|
|
* 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
|
|
* 0b11000..16-bit pixels (2-plane UV interleaved bytes)
|
|
* 0b11001..16-bit pixels (2-plane UV)
|
|
* 0b11010..16-bit pixels (2-plane VU interleaved bytes)
|
|
* 0b11011..16-bit pixels (2-plane VU)
|
|
*/
|
|
#define PXP_OUT_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_FORMAT_SHIFT)) & PXP_OUT_CTRL_FORMAT_MASK)
|
|
#define PXP_OUT_CTRL_RSVD0_MASK (0xE0U)
|
|
#define PXP_OUT_CTRL_RSVD0_SHIFT (5U)
|
|
#define PXP_OUT_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_RSVD0_SHIFT)) & PXP_OUT_CTRL_RSVD0_MASK)
|
|
#define PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK (0x300U)
|
|
#define PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT (8U)
|
|
/*! INTERLACED_OUTPUT
|
|
* 0b00..All data written in progressive format to the OUTBUF Pointer.
|
|
* 0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer.
|
|
* 0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer.
|
|
* 0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.
|
|
*/
|
|
#define PXP_OUT_CTRL_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK)
|
|
#define PXP_OUT_CTRL_RSVD1_MASK (0x7FFC00U)
|
|
#define PXP_OUT_CTRL_RSVD1_SHIFT (10U)
|
|
#define PXP_OUT_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_RSVD1_SHIFT)) & PXP_OUT_CTRL_RSVD1_MASK)
|
|
#define PXP_OUT_CTRL_ALPHA_OUTPUT_MASK (0x800000U)
|
|
#define PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT (23U)
|
|
#define PXP_OUT_CTRL_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_ALPHA_OUTPUT_MASK)
|
|
#define PXP_OUT_CTRL_ALPHA_MASK (0xFF000000U)
|
|
#define PXP_OUT_CTRL_ALPHA_SHIFT (24U)
|
|
#define PXP_OUT_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_SHIFT)) & PXP_OUT_CTRL_ALPHA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name OUT_CTRL_SET - Output Buffer Control Register */
|
|
/*! @{ */
|
|
#define PXP_OUT_CTRL_SET_FORMAT_MASK (0x1FU)
|
|
#define PXP_OUT_CTRL_SET_FORMAT_SHIFT (0U)
|
|
/*! FORMAT
|
|
* 0b00000..32-bit pixels
|
|
* 0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.)
|
|
* 0b00101..24-bit pixels (packed 24-bit format)
|
|
* 0b01000..16-bit pixels
|
|
* 0b01001..16-bit pixels
|
|
* 0b01100..16-bit pixels
|
|
* 0b01101..16-bit pixels
|
|
* 0b01110..16-bit pixels
|
|
* 0b10000..32-bit pixels (1-plane XYUV unpacked)
|
|
* 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
|
|
* 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
|
|
* 0b10100..8-bit monochrome pixels (1-plane Y luma output)
|
|
* 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
|
|
* 0b11000..16-bit pixels (2-plane UV interleaved bytes)
|
|
* 0b11001..16-bit pixels (2-plane UV)
|
|
* 0b11010..16-bit pixels (2-plane VU interleaved bytes)
|
|
* 0b11011..16-bit pixels (2-plane VU)
|
|
*/
|
|
#define PXP_OUT_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_FORMAT_SHIFT)) & PXP_OUT_CTRL_SET_FORMAT_MASK)
|
|
#define PXP_OUT_CTRL_SET_RSVD0_MASK (0xE0U)
|
|
#define PXP_OUT_CTRL_SET_RSVD0_SHIFT (5U)
|
|
#define PXP_OUT_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_RSVD0_SHIFT)) & PXP_OUT_CTRL_SET_RSVD0_MASK)
|
|
#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK (0x300U)
|
|
#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT (8U)
|
|
/*! INTERLACED_OUTPUT
|
|
* 0b00..All data written in progressive format to the OUTBUF Pointer.
|
|
* 0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer.
|
|
* 0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer.
|
|
* 0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.
|
|
*/
|
|
#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK)
|
|
#define PXP_OUT_CTRL_SET_RSVD1_MASK (0x7FFC00U)
|
|
#define PXP_OUT_CTRL_SET_RSVD1_SHIFT (10U)
|
|
#define PXP_OUT_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_RSVD1_SHIFT)) & PXP_OUT_CTRL_SET_RSVD1_MASK)
|
|
#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK (0x800000U)
|
|
#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT (23U)
|
|
#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK)
|
|
#define PXP_OUT_CTRL_SET_ALPHA_MASK (0xFF000000U)
|
|
#define PXP_OUT_CTRL_SET_ALPHA_SHIFT (24U)
|
|
#define PXP_OUT_CTRL_SET_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name OUT_CTRL_CLR - Output Buffer Control Register */
|
|
/*! @{ */
|
|
#define PXP_OUT_CTRL_CLR_FORMAT_MASK (0x1FU)
|
|
#define PXP_OUT_CTRL_CLR_FORMAT_SHIFT (0U)
|
|
/*! FORMAT
|
|
* 0b00000..32-bit pixels
|
|
* 0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.)
|
|
* 0b00101..24-bit pixels (packed 24-bit format)
|
|
* 0b01000..16-bit pixels
|
|
* 0b01001..16-bit pixels
|
|
* 0b01100..16-bit pixels
|
|
* 0b01101..16-bit pixels
|
|
* 0b01110..16-bit pixels
|
|
* 0b10000..32-bit pixels (1-plane XYUV unpacked)
|
|
* 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
|
|
* 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
|
|
* 0b10100..8-bit monochrome pixels (1-plane Y luma output)
|
|
* 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
|
|
* 0b11000..16-bit pixels (2-plane UV interleaved bytes)
|
|
* 0b11001..16-bit pixels (2-plane UV)
|
|
* 0b11010..16-bit pixels (2-plane VU interleaved bytes)
|
|
* 0b11011..16-bit pixels (2-plane VU)
|
|
*/
|
|
#define PXP_OUT_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_FORMAT_SHIFT)) & PXP_OUT_CTRL_CLR_FORMAT_MASK)
|
|
#define PXP_OUT_CTRL_CLR_RSVD0_MASK (0xE0U)
|
|
#define PXP_OUT_CTRL_CLR_RSVD0_SHIFT (5U)
|
|
#define PXP_OUT_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_RSVD0_SHIFT)) & PXP_OUT_CTRL_CLR_RSVD0_MASK)
|
|
#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK (0x300U)
|
|
#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT (8U)
|
|
/*! INTERLACED_OUTPUT
|
|
* 0b00..All data written in progressive format to the OUTBUF Pointer.
|
|
* 0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer.
|
|
* 0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer.
|
|
* 0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.
|
|
*/
|
|
#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK)
|
|
#define PXP_OUT_CTRL_CLR_RSVD1_MASK (0x7FFC00U)
|
|
#define PXP_OUT_CTRL_CLR_RSVD1_SHIFT (10U)
|
|
#define PXP_OUT_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_RSVD1_SHIFT)) & PXP_OUT_CTRL_CLR_RSVD1_MASK)
|
|
#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK (0x800000U)
|
|
#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT (23U)
|
|
#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK)
|
|
#define PXP_OUT_CTRL_CLR_ALPHA_MASK (0xFF000000U)
|
|
#define PXP_OUT_CTRL_CLR_ALPHA_SHIFT (24U)
|
|
#define PXP_OUT_CTRL_CLR_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name OUT_CTRL_TOG - Output Buffer Control Register */
|
|
/*! @{ */
|
|
#define PXP_OUT_CTRL_TOG_FORMAT_MASK (0x1FU)
|
|
#define PXP_OUT_CTRL_TOG_FORMAT_SHIFT (0U)
|
|
/*! FORMAT
|
|
* 0b00000..32-bit pixels
|
|
* 0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.)
|
|
* 0b00101..24-bit pixels (packed 24-bit format)
|
|
* 0b01000..16-bit pixels
|
|
* 0b01001..16-bit pixels
|
|
* 0b01100..16-bit pixels
|
|
* 0b01101..16-bit pixels
|
|
* 0b01110..16-bit pixels
|
|
* 0b10000..32-bit pixels (1-plane XYUV unpacked)
|
|
* 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
|
|
* 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
|
|
* 0b10100..8-bit monochrome pixels (1-plane Y luma output)
|
|
* 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
|
|
* 0b11000..16-bit pixels (2-plane UV interleaved bytes)
|
|
* 0b11001..16-bit pixels (2-plane UV)
|
|
* 0b11010..16-bit pixels (2-plane VU interleaved bytes)
|
|
* 0b11011..16-bit pixels (2-plane VU)
|
|
*/
|
|
#define PXP_OUT_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_FORMAT_SHIFT)) & PXP_OUT_CTRL_TOG_FORMAT_MASK)
|
|
#define PXP_OUT_CTRL_TOG_RSVD0_MASK (0xE0U)
|
|
#define PXP_OUT_CTRL_TOG_RSVD0_SHIFT (5U)
|
|
#define PXP_OUT_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_RSVD0_SHIFT)) & PXP_OUT_CTRL_TOG_RSVD0_MASK)
|
|
#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK (0x300U)
|
|
#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT (8U)
|
|
/*! INTERLACED_OUTPUT
|
|
* 0b00..All data written in progressive format to the OUTBUF Pointer.
|
|
* 0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer.
|
|
* 0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer.
|
|
* 0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.
|
|
*/
|
|
#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK)
|
|
#define PXP_OUT_CTRL_TOG_RSVD1_MASK (0x7FFC00U)
|
|
#define PXP_OUT_CTRL_TOG_RSVD1_SHIFT (10U)
|
|
#define PXP_OUT_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_RSVD1_SHIFT)) & PXP_OUT_CTRL_TOG_RSVD1_MASK)
|
|
#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK (0x800000U)
|
|
#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT (23U)
|
|
#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK)
|
|
#define PXP_OUT_CTRL_TOG_ALPHA_MASK (0xFF000000U)
|
|
#define PXP_OUT_CTRL_TOG_ALPHA_SHIFT (24U)
|
|
#define PXP_OUT_CTRL_TOG_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name OUT_BUF - Output Frame Buffer Pointer */
|
|
/*! @{ */
|
|
#define PXP_OUT_BUF_ADDR_MASK (0xFFFFFFFFU)
|
|
#define PXP_OUT_BUF_ADDR_SHIFT (0U)
|
|
#define PXP_OUT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF_ADDR_SHIFT)) & PXP_OUT_BUF_ADDR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name OUT_BUF2 - Output Frame Buffer Pointer #2 */
|
|
/*! @{ */
|
|
#define PXP_OUT_BUF2_ADDR_MASK (0xFFFFFFFFU)
|
|
#define PXP_OUT_BUF2_ADDR_SHIFT (0U)
|
|
#define PXP_OUT_BUF2_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF2_ADDR_SHIFT)) & PXP_OUT_BUF2_ADDR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name OUT_PITCH - Output Buffer Pitch */
|
|
/*! @{ */
|
|
#define PXP_OUT_PITCH_PITCH_MASK (0xFFFFU)
|
|
#define PXP_OUT_PITCH_PITCH_SHIFT (0U)
|
|
#define PXP_OUT_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_PITCH_SHIFT)) & PXP_OUT_PITCH_PITCH_MASK)
|
|
#define PXP_OUT_PITCH_RSVD_MASK (0xFFFF0000U)
|
|
#define PXP_OUT_PITCH_RSVD_SHIFT (16U)
|
|
#define PXP_OUT_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_RSVD_SHIFT)) & PXP_OUT_PITCH_RSVD_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name OUT_LRC - Output Surface Lower Right Coordinate */
|
|
/*! @{ */
|
|
#define PXP_OUT_LRC_Y_MASK (0x3FFFU)
|
|
#define PXP_OUT_LRC_Y_SHIFT (0U)
|
|
#define PXP_OUT_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_Y_SHIFT)) & PXP_OUT_LRC_Y_MASK)
|
|
#define PXP_OUT_LRC_RSVD0_MASK (0xC000U)
|
|
#define PXP_OUT_LRC_RSVD0_SHIFT (14U)
|
|
#define PXP_OUT_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_RSVD0_SHIFT)) & PXP_OUT_LRC_RSVD0_MASK)
|
|
#define PXP_OUT_LRC_X_MASK (0x3FFF0000U)
|
|
#define PXP_OUT_LRC_X_SHIFT (16U)
|
|
#define PXP_OUT_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_X_SHIFT)) & PXP_OUT_LRC_X_MASK)
|
|
#define PXP_OUT_LRC_RSVD1_MASK (0xC0000000U)
|
|
#define PXP_OUT_LRC_RSVD1_SHIFT (30U)
|
|
#define PXP_OUT_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_RSVD1_SHIFT)) & PXP_OUT_LRC_RSVD1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name OUT_PS_ULC - Processed Surface Upper Left Coordinate */
|
|
/*! @{ */
|
|
#define PXP_OUT_PS_ULC_Y_MASK (0x3FFFU)
|
|
#define PXP_OUT_PS_ULC_Y_SHIFT (0U)
|
|
#define PXP_OUT_PS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_Y_SHIFT)) & PXP_OUT_PS_ULC_Y_MASK)
|
|
#define PXP_OUT_PS_ULC_RSVD0_MASK (0xC000U)
|
|
#define PXP_OUT_PS_ULC_RSVD0_SHIFT (14U)
|
|
#define PXP_OUT_PS_ULC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_RSVD0_SHIFT)) & PXP_OUT_PS_ULC_RSVD0_MASK)
|
|
#define PXP_OUT_PS_ULC_X_MASK (0x3FFF0000U)
|
|
#define PXP_OUT_PS_ULC_X_SHIFT (16U)
|
|
#define PXP_OUT_PS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_X_SHIFT)) & PXP_OUT_PS_ULC_X_MASK)
|
|
#define PXP_OUT_PS_ULC_RSVD1_MASK (0xC0000000U)
|
|
#define PXP_OUT_PS_ULC_RSVD1_SHIFT (30U)
|
|
#define PXP_OUT_PS_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_RSVD1_SHIFT)) & PXP_OUT_PS_ULC_RSVD1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name OUT_PS_LRC - Processed Surface Lower Right Coordinate */
|
|
/*! @{ */
|
|
#define PXP_OUT_PS_LRC_Y_MASK (0x3FFFU)
|
|
#define PXP_OUT_PS_LRC_Y_SHIFT (0U)
|
|
#define PXP_OUT_PS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_Y_SHIFT)) & PXP_OUT_PS_LRC_Y_MASK)
|
|
#define PXP_OUT_PS_LRC_RSVD0_MASK (0xC000U)
|
|
#define PXP_OUT_PS_LRC_RSVD0_SHIFT (14U)
|
|
#define PXP_OUT_PS_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_RSVD0_SHIFT)) & PXP_OUT_PS_LRC_RSVD0_MASK)
|
|
#define PXP_OUT_PS_LRC_X_MASK (0x3FFF0000U)
|
|
#define PXP_OUT_PS_LRC_X_SHIFT (16U)
|
|
#define PXP_OUT_PS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_X_SHIFT)) & PXP_OUT_PS_LRC_X_MASK)
|
|
#define PXP_OUT_PS_LRC_RSVD1_MASK (0xC0000000U)
|
|
#define PXP_OUT_PS_LRC_RSVD1_SHIFT (30U)
|
|
#define PXP_OUT_PS_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_RSVD1_SHIFT)) & PXP_OUT_PS_LRC_RSVD1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name OUT_AS_ULC - Alpha Surface Upper Left Coordinate */
|
|
/*! @{ */
|
|
#define PXP_OUT_AS_ULC_Y_MASK (0x3FFFU)
|
|
#define PXP_OUT_AS_ULC_Y_SHIFT (0U)
|
|
#define PXP_OUT_AS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_Y_SHIFT)) & PXP_OUT_AS_ULC_Y_MASK)
|
|
#define PXP_OUT_AS_ULC_RSVD0_MASK (0xC000U)
|
|
#define PXP_OUT_AS_ULC_RSVD0_SHIFT (14U)
|
|
#define PXP_OUT_AS_ULC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_RSVD0_SHIFT)) & PXP_OUT_AS_ULC_RSVD0_MASK)
|
|
#define PXP_OUT_AS_ULC_X_MASK (0x3FFF0000U)
|
|
#define PXP_OUT_AS_ULC_X_SHIFT (16U)
|
|
#define PXP_OUT_AS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_X_SHIFT)) & PXP_OUT_AS_ULC_X_MASK)
|
|
#define PXP_OUT_AS_ULC_RSVD1_MASK (0xC0000000U)
|
|
#define PXP_OUT_AS_ULC_RSVD1_SHIFT (30U)
|
|
#define PXP_OUT_AS_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_RSVD1_SHIFT)) & PXP_OUT_AS_ULC_RSVD1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name OUT_AS_LRC - Alpha Surface Lower Right Coordinate */
|
|
/*! @{ */
|
|
#define PXP_OUT_AS_LRC_Y_MASK (0x3FFFU)
|
|
#define PXP_OUT_AS_LRC_Y_SHIFT (0U)
|
|
#define PXP_OUT_AS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_Y_SHIFT)) & PXP_OUT_AS_LRC_Y_MASK)
|
|
#define PXP_OUT_AS_LRC_RSVD0_MASK (0xC000U)
|
|
#define PXP_OUT_AS_LRC_RSVD0_SHIFT (14U)
|
|
#define PXP_OUT_AS_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_RSVD0_SHIFT)) & PXP_OUT_AS_LRC_RSVD0_MASK)
|
|
#define PXP_OUT_AS_LRC_X_MASK (0x3FFF0000U)
|
|
#define PXP_OUT_AS_LRC_X_SHIFT (16U)
|
|
#define PXP_OUT_AS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_X_SHIFT)) & PXP_OUT_AS_LRC_X_MASK)
|
|
#define PXP_OUT_AS_LRC_RSVD1_MASK (0xC0000000U)
|
|
#define PXP_OUT_AS_LRC_RSVD1_SHIFT (30U)
|
|
#define PXP_OUT_AS_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_RSVD1_SHIFT)) & PXP_OUT_AS_LRC_RSVD1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PS_CTRL - Processed Surface (PS) Control Register */
|
|
/*! @{ */
|
|
#define PXP_PS_CTRL_FORMAT_MASK (0x1FU)
|
|
#define PXP_PS_CTRL_FORMAT_SHIFT (0U)
|
|
/*! FORMAT
|
|
* 0b00100..32-bit pixels (unpacked 24-bit format)
|
|
* 0b01100..16-bit pixels
|
|
* 0b01101..16-bit pixels
|
|
* 0b01110..16-bit pixels
|
|
* 0b10000..32-bit pixels (1-plane XYUV unpacked)
|
|
* 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
|
|
* 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
|
|
* 0b10100..8-bit monochrome pixels (1-plane Y luma output)
|
|
* 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
|
|
* 0b11000..16-bit pixels (2-plane UV interleaved bytes)
|
|
* 0b11001..16-bit pixels (2-plane UV)
|
|
* 0b11010..16-bit pixels (2-plane VU interleaved bytes)
|
|
* 0b11011..16-bit pixels (2-plane VU)
|
|
* 0b11110..16-bit pixels (3-plane format)
|
|
* 0b11111..16-bit pixels (3-plane format)
|
|
*/
|
|
#define PXP_PS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_FORMAT_SHIFT)) & PXP_PS_CTRL_FORMAT_MASK)
|
|
#define PXP_PS_CTRL_WB_SWAP_MASK (0x20U)
|
|
#define PXP_PS_CTRL_WB_SWAP_SHIFT (5U)
|
|
#define PXP_PS_CTRL_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_WB_SWAP_SHIFT)) & PXP_PS_CTRL_WB_SWAP_MASK)
|
|
#define PXP_PS_CTRL_RSVD0_MASK (0xC0U)
|
|
#define PXP_PS_CTRL_RSVD0_SHIFT (6U)
|
|
#define PXP_PS_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_RSVD0_SHIFT)) & PXP_PS_CTRL_RSVD0_MASK)
|
|
#define PXP_PS_CTRL_DECY_MASK (0x300U)
|
|
#define PXP_PS_CTRL_DECY_SHIFT (8U)
|
|
/*! DECY
|
|
* 0b00..Disable pre-decimation filter.
|
|
* 0b01..Decimate PS by 2.
|
|
* 0b10..Decimate PS by 4.
|
|
* 0b11..Decimate PS by 8.
|
|
*/
|
|
#define PXP_PS_CTRL_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECY_SHIFT)) & PXP_PS_CTRL_DECY_MASK)
|
|
#define PXP_PS_CTRL_DECX_MASK (0xC00U)
|
|
#define PXP_PS_CTRL_DECX_SHIFT (10U)
|
|
/*! DECX
|
|
* 0b00..Disable pre-decimation filter.
|
|
* 0b01..Decimate PS by 2.
|
|
* 0b10..Decimate PS by 4.
|
|
* 0b11..Decimate PS by 8.
|
|
*/
|
|
#define PXP_PS_CTRL_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECX_SHIFT)) & PXP_PS_CTRL_DECX_MASK)
|
|
#define PXP_PS_CTRL_RSVD1_MASK (0xFFFFF000U)
|
|
#define PXP_PS_CTRL_RSVD1_SHIFT (12U)
|
|
#define PXP_PS_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_RSVD1_SHIFT)) & PXP_PS_CTRL_RSVD1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PS_CTRL_SET - Processed Surface (PS) Control Register */
|
|
/*! @{ */
|
|
#define PXP_PS_CTRL_SET_FORMAT_MASK (0x1FU)
|
|
#define PXP_PS_CTRL_SET_FORMAT_SHIFT (0U)
|
|
/*! FORMAT
|
|
* 0b00100..32-bit pixels (unpacked 24-bit format)
|
|
* 0b01100..16-bit pixels
|
|
* 0b01101..16-bit pixels
|
|
* 0b01110..16-bit pixels
|
|
* 0b10000..32-bit pixels (1-plane XYUV unpacked)
|
|
* 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
|
|
* 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
|
|
* 0b10100..8-bit monochrome pixels (1-plane Y luma output)
|
|
* 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
|
|
* 0b11000..16-bit pixels (2-plane UV interleaved bytes)
|
|
* 0b11001..16-bit pixels (2-plane UV)
|
|
* 0b11010..16-bit pixels (2-plane VU interleaved bytes)
|
|
* 0b11011..16-bit pixels (2-plane VU)
|
|
* 0b11110..16-bit pixels (3-plane format)
|
|
* 0b11111..16-bit pixels (3-plane format)
|
|
*/
|
|
#define PXP_PS_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_FORMAT_SHIFT)) & PXP_PS_CTRL_SET_FORMAT_MASK)
|
|
#define PXP_PS_CTRL_SET_WB_SWAP_MASK (0x20U)
|
|
#define PXP_PS_CTRL_SET_WB_SWAP_SHIFT (5U)
|
|
#define PXP_PS_CTRL_SET_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_WB_SWAP_SHIFT)) & PXP_PS_CTRL_SET_WB_SWAP_MASK)
|
|
#define PXP_PS_CTRL_SET_RSVD0_MASK (0xC0U)
|
|
#define PXP_PS_CTRL_SET_RSVD0_SHIFT (6U)
|
|
#define PXP_PS_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_RSVD0_SHIFT)) & PXP_PS_CTRL_SET_RSVD0_MASK)
|
|
#define PXP_PS_CTRL_SET_DECY_MASK (0x300U)
|
|
#define PXP_PS_CTRL_SET_DECY_SHIFT (8U)
|
|
/*! DECY
|
|
* 0b00..Disable pre-decimation filter.
|
|
* 0b01..Decimate PS by 2.
|
|
* 0b10..Decimate PS by 4.
|
|
* 0b11..Decimate PS by 8.
|
|
*/
|
|
#define PXP_PS_CTRL_SET_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECY_SHIFT)) & PXP_PS_CTRL_SET_DECY_MASK)
|
|
#define PXP_PS_CTRL_SET_DECX_MASK (0xC00U)
|
|
#define PXP_PS_CTRL_SET_DECX_SHIFT (10U)
|
|
/*! DECX
|
|
* 0b00..Disable pre-decimation filter.
|
|
* 0b01..Decimate PS by 2.
|
|
* 0b10..Decimate PS by 4.
|
|
* 0b11..Decimate PS by 8.
|
|
*/
|
|
#define PXP_PS_CTRL_SET_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECX_SHIFT)) & PXP_PS_CTRL_SET_DECX_MASK)
|
|
#define PXP_PS_CTRL_SET_RSVD1_MASK (0xFFFFF000U)
|
|
#define PXP_PS_CTRL_SET_RSVD1_SHIFT (12U)
|
|
#define PXP_PS_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_RSVD1_SHIFT)) & PXP_PS_CTRL_SET_RSVD1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PS_CTRL_CLR - Processed Surface (PS) Control Register */
|
|
/*! @{ */
|
|
#define PXP_PS_CTRL_CLR_FORMAT_MASK (0x1FU)
|
|
#define PXP_PS_CTRL_CLR_FORMAT_SHIFT (0U)
|
|
/*! FORMAT
|
|
* 0b00100..32-bit pixels (unpacked 24-bit format)
|
|
* 0b01100..16-bit pixels
|
|
* 0b01101..16-bit pixels
|
|
* 0b01110..16-bit pixels
|
|
* 0b10000..32-bit pixels (1-plane XYUV unpacked)
|
|
* 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
|
|
* 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
|
|
* 0b10100..8-bit monochrome pixels (1-plane Y luma output)
|
|
* 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
|
|
* 0b11000..16-bit pixels (2-plane UV interleaved bytes)
|
|
* 0b11001..16-bit pixels (2-plane UV)
|
|
* 0b11010..16-bit pixels (2-plane VU interleaved bytes)
|
|
* 0b11011..16-bit pixels (2-plane VU)
|
|
* 0b11110..16-bit pixels (3-plane format)
|
|
* 0b11111..16-bit pixels (3-plane format)
|
|
*/
|
|
#define PXP_PS_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_FORMAT_SHIFT)) & PXP_PS_CTRL_CLR_FORMAT_MASK)
|
|
#define PXP_PS_CTRL_CLR_WB_SWAP_MASK (0x20U)
|
|
#define PXP_PS_CTRL_CLR_WB_SWAP_SHIFT (5U)
|
|
#define PXP_PS_CTRL_CLR_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_WB_SWAP_SHIFT)) & PXP_PS_CTRL_CLR_WB_SWAP_MASK)
|
|
#define PXP_PS_CTRL_CLR_RSVD0_MASK (0xC0U)
|
|
#define PXP_PS_CTRL_CLR_RSVD0_SHIFT (6U)
|
|
#define PXP_PS_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_RSVD0_SHIFT)) & PXP_PS_CTRL_CLR_RSVD0_MASK)
|
|
#define PXP_PS_CTRL_CLR_DECY_MASK (0x300U)
|
|
#define PXP_PS_CTRL_CLR_DECY_SHIFT (8U)
|
|
/*! DECY
|
|
* 0b00..Disable pre-decimation filter.
|
|
* 0b01..Decimate PS by 2.
|
|
* 0b10..Decimate PS by 4.
|
|
* 0b11..Decimate PS by 8.
|
|
*/
|
|
#define PXP_PS_CTRL_CLR_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECY_SHIFT)) & PXP_PS_CTRL_CLR_DECY_MASK)
|
|
#define PXP_PS_CTRL_CLR_DECX_MASK (0xC00U)
|
|
#define PXP_PS_CTRL_CLR_DECX_SHIFT (10U)
|
|
/*! DECX
|
|
* 0b00..Disable pre-decimation filter.
|
|
* 0b01..Decimate PS by 2.
|
|
* 0b10..Decimate PS by 4.
|
|
* 0b11..Decimate PS by 8.
|
|
*/
|
|
#define PXP_PS_CTRL_CLR_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECX_SHIFT)) & PXP_PS_CTRL_CLR_DECX_MASK)
|
|
#define PXP_PS_CTRL_CLR_RSVD1_MASK (0xFFFFF000U)
|
|
#define PXP_PS_CTRL_CLR_RSVD1_SHIFT (12U)
|
|
#define PXP_PS_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_RSVD1_SHIFT)) & PXP_PS_CTRL_CLR_RSVD1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PS_CTRL_TOG - Processed Surface (PS) Control Register */
|
|
/*! @{ */
|
|
#define PXP_PS_CTRL_TOG_FORMAT_MASK (0x1FU)
|
|
#define PXP_PS_CTRL_TOG_FORMAT_SHIFT (0U)
|
|
/*! FORMAT
|
|
* 0b00100..32-bit pixels (unpacked 24-bit format)
|
|
* 0b01100..16-bit pixels
|
|
* 0b01101..16-bit pixels
|
|
* 0b01110..16-bit pixels
|
|
* 0b10000..32-bit pixels (1-plane XYUV unpacked)
|
|
* 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
|
|
* 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
|
|
* 0b10100..8-bit monochrome pixels (1-plane Y luma output)
|
|
* 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
|
|
* 0b11000..16-bit pixels (2-plane UV interleaved bytes)
|
|
* 0b11001..16-bit pixels (2-plane UV)
|
|
* 0b11010..16-bit pixels (2-plane VU interleaved bytes)
|
|
* 0b11011..16-bit pixels (2-plane VU)
|
|
* 0b11110..16-bit pixels (3-plane format)
|
|
* 0b11111..16-bit pixels (3-plane format)
|
|
*/
|
|
#define PXP_PS_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_FORMAT_SHIFT)) & PXP_PS_CTRL_TOG_FORMAT_MASK)
|
|
#define PXP_PS_CTRL_TOG_WB_SWAP_MASK (0x20U)
|
|
#define PXP_PS_CTRL_TOG_WB_SWAP_SHIFT (5U)
|
|
#define PXP_PS_CTRL_TOG_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_WB_SWAP_SHIFT)) & PXP_PS_CTRL_TOG_WB_SWAP_MASK)
|
|
#define PXP_PS_CTRL_TOG_RSVD0_MASK (0xC0U)
|
|
#define PXP_PS_CTRL_TOG_RSVD0_SHIFT (6U)
|
|
#define PXP_PS_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_RSVD0_SHIFT)) & PXP_PS_CTRL_TOG_RSVD0_MASK)
|
|
#define PXP_PS_CTRL_TOG_DECY_MASK (0x300U)
|
|
#define PXP_PS_CTRL_TOG_DECY_SHIFT (8U)
|
|
/*! DECY
|
|
* 0b00..Disable pre-decimation filter.
|
|
* 0b01..Decimate PS by 2.
|
|
* 0b10..Decimate PS by 4.
|
|
* 0b11..Decimate PS by 8.
|
|
*/
|
|
#define PXP_PS_CTRL_TOG_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECY_SHIFT)) & PXP_PS_CTRL_TOG_DECY_MASK)
|
|
#define PXP_PS_CTRL_TOG_DECX_MASK (0xC00U)
|
|
#define PXP_PS_CTRL_TOG_DECX_SHIFT (10U)
|
|
/*! DECX
|
|
* 0b00..Disable pre-decimation filter.
|
|
* 0b01..Decimate PS by 2.
|
|
* 0b10..Decimate PS by 4.
|
|
* 0b11..Decimate PS by 8.
|
|
*/
|
|
#define PXP_PS_CTRL_TOG_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECX_SHIFT)) & PXP_PS_CTRL_TOG_DECX_MASK)
|
|
#define PXP_PS_CTRL_TOG_RSVD1_MASK (0xFFFFF000U)
|
|
#define PXP_PS_CTRL_TOG_RSVD1_SHIFT (12U)
|
|
#define PXP_PS_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_RSVD1_SHIFT)) & PXP_PS_CTRL_TOG_RSVD1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PS_BUF - PS Input Buffer Address */
|
|
/*! @{ */
|
|
#define PXP_PS_BUF_ADDR_MASK (0xFFFFFFFFU)
|
|
#define PXP_PS_BUF_ADDR_SHIFT (0U)
|
|
#define PXP_PS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BUF_ADDR_SHIFT)) & PXP_PS_BUF_ADDR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PS_UBUF - PS U/Cb or 2 Plane UV Input Buffer Address */
|
|
/*! @{ */
|
|
#define PXP_PS_UBUF_ADDR_MASK (0xFFFFFFFFU)
|
|
#define PXP_PS_UBUF_ADDR_SHIFT (0U)
|
|
#define PXP_PS_UBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_UBUF_ADDR_SHIFT)) & PXP_PS_UBUF_ADDR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PS_VBUF - PS V/Cr Input Buffer Address */
|
|
/*! @{ */
|
|
#define PXP_PS_VBUF_ADDR_MASK (0xFFFFFFFFU)
|
|
#define PXP_PS_VBUF_ADDR_SHIFT (0U)
|
|
#define PXP_PS_VBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_VBUF_ADDR_SHIFT)) & PXP_PS_VBUF_ADDR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PS_PITCH - Processed Surface Pitch */
|
|
/*! @{ */
|
|
#define PXP_PS_PITCH_PITCH_MASK (0xFFFFU)
|
|
#define PXP_PS_PITCH_PITCH_SHIFT (0U)
|
|
#define PXP_PS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_PITCH_SHIFT)) & PXP_PS_PITCH_PITCH_MASK)
|
|
#define PXP_PS_PITCH_RSVD_MASK (0xFFFF0000U)
|
|
#define PXP_PS_PITCH_RSVD_SHIFT (16U)
|
|
#define PXP_PS_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_RSVD_SHIFT)) & PXP_PS_PITCH_RSVD_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PS_BACKGROUND - PS Background Color */
|
|
/*! @{ */
|
|
#define PXP_PS_BACKGROUND_COLOR_MASK (0xFFFFFFU)
|
|
#define PXP_PS_BACKGROUND_COLOR_SHIFT (0U)
|
|
#define PXP_PS_BACKGROUND_COLOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_COLOR_SHIFT)) & PXP_PS_BACKGROUND_COLOR_MASK)
|
|
#define PXP_PS_BACKGROUND_RSVD_MASK (0xFF000000U)
|
|
#define PXP_PS_BACKGROUND_RSVD_SHIFT (24U)
|
|
#define PXP_PS_BACKGROUND_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_RSVD_SHIFT)) & PXP_PS_BACKGROUND_RSVD_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PS_SCALE - PS Scale Factor Register */
|
|
/*! @{ */
|
|
#define PXP_PS_SCALE_XSCALE_MASK (0x7FFFU)
|
|
#define PXP_PS_SCALE_XSCALE_SHIFT (0U)
|
|
#define PXP_PS_SCALE_XSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_XSCALE_SHIFT)) & PXP_PS_SCALE_XSCALE_MASK)
|
|
#define PXP_PS_SCALE_RSVD1_MASK (0x8000U)
|
|
#define PXP_PS_SCALE_RSVD1_SHIFT (15U)
|
|
#define PXP_PS_SCALE_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_RSVD1_SHIFT)) & PXP_PS_SCALE_RSVD1_MASK)
|
|
#define PXP_PS_SCALE_YSCALE_MASK (0x7FFF0000U)
|
|
#define PXP_PS_SCALE_YSCALE_SHIFT (16U)
|
|
#define PXP_PS_SCALE_YSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_YSCALE_SHIFT)) & PXP_PS_SCALE_YSCALE_MASK)
|
|
#define PXP_PS_SCALE_RSVD2_MASK (0x80000000U)
|
|
#define PXP_PS_SCALE_RSVD2_SHIFT (31U)
|
|
#define PXP_PS_SCALE_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_RSVD2_SHIFT)) & PXP_PS_SCALE_RSVD2_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PS_OFFSET - PS Scale Offset Register */
|
|
/*! @{ */
|
|
#define PXP_PS_OFFSET_XOFFSET_MASK (0xFFFU)
|
|
#define PXP_PS_OFFSET_XOFFSET_SHIFT (0U)
|
|
#define PXP_PS_OFFSET_XOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_XOFFSET_SHIFT)) & PXP_PS_OFFSET_XOFFSET_MASK)
|
|
#define PXP_PS_OFFSET_RSVD1_MASK (0xF000U)
|
|
#define PXP_PS_OFFSET_RSVD1_SHIFT (12U)
|
|
#define PXP_PS_OFFSET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_RSVD1_SHIFT)) & PXP_PS_OFFSET_RSVD1_MASK)
|
|
#define PXP_PS_OFFSET_YOFFSET_MASK (0xFFF0000U)
|
|
#define PXP_PS_OFFSET_YOFFSET_SHIFT (16U)
|
|
#define PXP_PS_OFFSET_YOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_YOFFSET_SHIFT)) & PXP_PS_OFFSET_YOFFSET_MASK)
|
|
#define PXP_PS_OFFSET_RSVD2_MASK (0xF0000000U)
|
|
#define PXP_PS_OFFSET_RSVD2_SHIFT (28U)
|
|
#define PXP_PS_OFFSET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_RSVD2_SHIFT)) & PXP_PS_OFFSET_RSVD2_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PS_CLRKEYLOW - PS Color Key Low */
|
|
/*! @{ */
|
|
#define PXP_PS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU)
|
|
#define PXP_PS_CLRKEYLOW_PIXEL_SHIFT (0U)
|
|
#define PXP_PS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_PS_CLRKEYLOW_PIXEL_MASK)
|
|
#define PXP_PS_CLRKEYLOW_RSVD1_MASK (0xFF000000U)
|
|
#define PXP_PS_CLRKEYLOW_RSVD1_SHIFT (24U)
|
|
#define PXP_PS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_RSVD1_SHIFT)) & PXP_PS_CLRKEYLOW_RSVD1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PS_CLRKEYHIGH - PS Color Key High */
|
|
/*! @{ */
|
|
#define PXP_PS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU)
|
|
#define PXP_PS_CLRKEYHIGH_PIXEL_SHIFT (0U)
|
|
#define PXP_PS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_PS_CLRKEYHIGH_PIXEL_MASK)
|
|
#define PXP_PS_CLRKEYHIGH_RSVD1_MASK (0xFF000000U)
|
|
#define PXP_PS_CLRKEYHIGH_RSVD1_SHIFT (24U)
|
|
#define PXP_PS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_RSVD1_SHIFT)) & PXP_PS_CLRKEYHIGH_RSVD1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name AS_CTRL - Alpha Surface Control */
|
|
/*! @{ */
|
|
#define PXP_AS_CTRL_RSVD0_MASK (0x1U)
|
|
#define PXP_AS_CTRL_RSVD0_SHIFT (0U)
|
|
#define PXP_AS_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_RSVD0_SHIFT)) & PXP_AS_CTRL_RSVD0_MASK)
|
|
#define PXP_AS_CTRL_ALPHA_CTRL_MASK (0x6U)
|
|
#define PXP_AS_CTRL_ALPHA_CTRL_SHIFT (1U)
|
|
/*! ALPHA_CTRL
|
|
* 0b00..Indicates that the AS pixel alpha value will be used to blend the AS with PS. The ALPHA field is ignored.
|
|
* 0b01..Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels.
|
|
* 0b10..Indicates that the value in the ALPHA field should be used to scale all pixel alpha values. Each pixel alpha is multiplied by the value in the ALPHA field.
|
|
* 0b11..Enable ROPs. The ROP field indicates an operation to be performed on the alpha surface and PS pixels.
|
|
*/
|
|
#define PXP_AS_CTRL_ALPHA_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_CTRL_SHIFT)) & PXP_AS_CTRL_ALPHA_CTRL_MASK)
|
|
#define PXP_AS_CTRL_ENABLE_COLORKEY_MASK (0x8U)
|
|
#define PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT (3U)
|
|
#define PXP_AS_CTRL_ENABLE_COLORKEY(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & PXP_AS_CTRL_ENABLE_COLORKEY_MASK)
|
|
#define PXP_AS_CTRL_FORMAT_MASK (0xF0U)
|
|
#define PXP_AS_CTRL_FORMAT_SHIFT (4U)
|
|
/*! FORMAT
|
|
* 0b0000..32-bit pixels with alpha
|
|
* 0b0100..32-bit pixels without alpha (unpacked 24-bit format)
|
|
* 0b1000..16-bit pixels with alpha
|
|
* 0b1001..16-bit pixels with alpha
|
|
* 0b1100..16-bit pixels without alpha
|
|
* 0b1101..16-bit pixels without alpha
|
|
* 0b1110..16-bit pixels without alpha
|
|
*/
|
|
#define PXP_AS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_FORMAT_SHIFT)) & PXP_AS_CTRL_FORMAT_MASK)
|
|
#define PXP_AS_CTRL_ALPHA_MASK (0xFF00U)
|
|
#define PXP_AS_CTRL_ALPHA_SHIFT (8U)
|
|
#define PXP_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_SHIFT)) & PXP_AS_CTRL_ALPHA_MASK)
|
|
#define PXP_AS_CTRL_ROP_MASK (0xF0000U)
|
|
#define PXP_AS_CTRL_ROP_SHIFT (16U)
|
|
/*! ROP
|
|
* 0b0000..AS AND PS
|
|
* 0b0001..nAS AND PS
|
|
* 0b0010..AS AND nPS
|
|
* 0b0011..AS OR PS
|
|
* 0b0100..nAS OR PS
|
|
* 0b0101..AS OR nPS
|
|
* 0b0110..nAS
|
|
* 0b0111..nPS
|
|
* 0b1000..AS NAND PS
|
|
* 0b1001..AS NOR PS
|
|
* 0b1010..AS XOR PS
|
|
* 0b1011..AS XNOR PS
|
|
*/
|
|
#define PXP_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ROP_SHIFT)) & PXP_AS_CTRL_ROP_MASK)
|
|
#define PXP_AS_CTRL_ALPHA_INVERT_MASK (0x100000U)
|
|
#define PXP_AS_CTRL_ALPHA_INVERT_SHIFT (20U)
|
|
#define PXP_AS_CTRL_ALPHA_INVERT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_INVERT_SHIFT)) & PXP_AS_CTRL_ALPHA_INVERT_MASK)
|
|
#define PXP_AS_CTRL_RSVD1_MASK (0xFFE00000U)
|
|
#define PXP_AS_CTRL_RSVD1_SHIFT (21U)
|
|
#define PXP_AS_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_RSVD1_SHIFT)) & PXP_AS_CTRL_RSVD1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name AS_BUF - Alpha Surface Buffer Pointer */
|
|
/*! @{ */
|
|
#define PXP_AS_BUF_ADDR_MASK (0xFFFFFFFFU)
|
|
#define PXP_AS_BUF_ADDR_SHIFT (0U)
|
|
#define PXP_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_BUF_ADDR_SHIFT)) & PXP_AS_BUF_ADDR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name AS_PITCH - Alpha Surface Pitch */
|
|
/*! @{ */
|
|
#define PXP_AS_PITCH_PITCH_MASK (0xFFFFU)
|
|
#define PXP_AS_PITCH_PITCH_SHIFT (0U)
|
|
#define PXP_AS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_PITCH_SHIFT)) & PXP_AS_PITCH_PITCH_MASK)
|
|
#define PXP_AS_PITCH_RSVD_MASK (0xFFFF0000U)
|
|
#define PXP_AS_PITCH_RSVD_SHIFT (16U)
|
|
#define PXP_AS_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_RSVD_SHIFT)) & PXP_AS_PITCH_RSVD_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name AS_CLRKEYLOW - Overlay Color Key Low */
|
|
/*! @{ */
|
|
#define PXP_AS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU)
|
|
#define PXP_AS_CLRKEYLOW_PIXEL_SHIFT (0U)
|
|
#define PXP_AS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_AS_CLRKEYLOW_PIXEL_MASK)
|
|
#define PXP_AS_CLRKEYLOW_RSVD1_MASK (0xFF000000U)
|
|
#define PXP_AS_CLRKEYLOW_RSVD1_SHIFT (24U)
|
|
#define PXP_AS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_RSVD1_SHIFT)) & PXP_AS_CLRKEYLOW_RSVD1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name AS_CLRKEYHIGH - Overlay Color Key High */
|
|
/*! @{ */
|
|
#define PXP_AS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU)
|
|
#define PXP_AS_CLRKEYHIGH_PIXEL_SHIFT (0U)
|
|
#define PXP_AS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_AS_CLRKEYHIGH_PIXEL_MASK)
|
|
#define PXP_AS_CLRKEYHIGH_RSVD1_MASK (0xFF000000U)
|
|
#define PXP_AS_CLRKEYHIGH_RSVD1_SHIFT (24U)
|
|
#define PXP_AS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_RSVD1_SHIFT)) & PXP_AS_CLRKEYHIGH_RSVD1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CSC1_COEF0 - Color Space Conversion Coefficient Register 0 */
|
|
/*! @{ */
|
|
#define PXP_CSC1_COEF0_Y_OFFSET_MASK (0x1FFU)
|
|
#define PXP_CSC1_COEF0_Y_OFFSET_SHIFT (0U)
|
|
#define PXP_CSC1_COEF0_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_Y_OFFSET_SHIFT)) & PXP_CSC1_COEF0_Y_OFFSET_MASK)
|
|
#define PXP_CSC1_COEF0_UV_OFFSET_MASK (0x3FE00U)
|
|
#define PXP_CSC1_COEF0_UV_OFFSET_SHIFT (9U)
|
|
#define PXP_CSC1_COEF0_UV_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_UV_OFFSET_SHIFT)) & PXP_CSC1_COEF0_UV_OFFSET_MASK)
|
|
#define PXP_CSC1_COEF0_C0_MASK (0x1FFC0000U)
|
|
#define PXP_CSC1_COEF0_C0_SHIFT (18U)
|
|
#define PXP_CSC1_COEF0_C0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_C0_SHIFT)) & PXP_CSC1_COEF0_C0_MASK)
|
|
#define PXP_CSC1_COEF0_RSVD1_MASK (0x20000000U)
|
|
#define PXP_CSC1_COEF0_RSVD1_SHIFT (29U)
|
|
#define PXP_CSC1_COEF0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_RSVD1_SHIFT)) & PXP_CSC1_COEF0_RSVD1_MASK)
|
|
#define PXP_CSC1_COEF0_BYPASS_MASK (0x40000000U)
|
|
#define PXP_CSC1_COEF0_BYPASS_SHIFT (30U)
|
|
#define PXP_CSC1_COEF0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_BYPASS_SHIFT)) & PXP_CSC1_COEF0_BYPASS_MASK)
|
|
#define PXP_CSC1_COEF0_YCBCR_MODE_MASK (0x80000000U)
|
|
#define PXP_CSC1_COEF0_YCBCR_MODE_SHIFT (31U)
|
|
#define PXP_CSC1_COEF0_YCBCR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_YCBCR_MODE_SHIFT)) & PXP_CSC1_COEF0_YCBCR_MODE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CSC1_COEF1 - Color Space Conversion Coefficient Register 1 */
|
|
/*! @{ */
|
|
#define PXP_CSC1_COEF1_C4_MASK (0x7FFU)
|
|
#define PXP_CSC1_COEF1_C4_SHIFT (0U)
|
|
#define PXP_CSC1_COEF1_C4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C4_SHIFT)) & PXP_CSC1_COEF1_C4_MASK)
|
|
#define PXP_CSC1_COEF1_RSVD0_MASK (0xF800U)
|
|
#define PXP_CSC1_COEF1_RSVD0_SHIFT (11U)
|
|
#define PXP_CSC1_COEF1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_RSVD0_SHIFT)) & PXP_CSC1_COEF1_RSVD0_MASK)
|
|
#define PXP_CSC1_COEF1_C1_MASK (0x7FF0000U)
|
|
#define PXP_CSC1_COEF1_C1_SHIFT (16U)
|
|
#define PXP_CSC1_COEF1_C1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C1_SHIFT)) & PXP_CSC1_COEF1_C1_MASK)
|
|
#define PXP_CSC1_COEF1_RSVD1_MASK (0xF8000000U)
|
|
#define PXP_CSC1_COEF1_RSVD1_SHIFT (27U)
|
|
#define PXP_CSC1_COEF1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_RSVD1_SHIFT)) & PXP_CSC1_COEF1_RSVD1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CSC1_COEF2 - Color Space Conversion Coefficient Register 2 */
|
|
/*! @{ */
|
|
#define PXP_CSC1_COEF2_C3_MASK (0x7FFU)
|
|
#define PXP_CSC1_COEF2_C3_SHIFT (0U)
|
|
#define PXP_CSC1_COEF2_C3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C3_SHIFT)) & PXP_CSC1_COEF2_C3_MASK)
|
|
#define PXP_CSC1_COEF2_RSVD0_MASK (0xF800U)
|
|
#define PXP_CSC1_COEF2_RSVD0_SHIFT (11U)
|
|
#define PXP_CSC1_COEF2_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_RSVD0_SHIFT)) & PXP_CSC1_COEF2_RSVD0_MASK)
|
|
#define PXP_CSC1_COEF2_C2_MASK (0x7FF0000U)
|
|
#define PXP_CSC1_COEF2_C2_SHIFT (16U)
|
|
#define PXP_CSC1_COEF2_C2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C2_SHIFT)) & PXP_CSC1_COEF2_C2_MASK)
|
|
#define PXP_CSC1_COEF2_RSVD1_MASK (0xF8000000U)
|
|
#define PXP_CSC1_COEF2_RSVD1_SHIFT (27U)
|
|
#define PXP_CSC1_COEF2_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_RSVD1_SHIFT)) & PXP_CSC1_COEF2_RSVD1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name POWER - PXP Power Control Register */
|
|
/*! @{ */
|
|
#define PXP_POWER_ROT_MEM_LP_STATE_MASK (0xE00U)
|
|
#define PXP_POWER_ROT_MEM_LP_STATE_SHIFT (9U)
|
|
/*! ROT_MEM_LP_STATE
|
|
* 0b000..Memory is not in low power state.
|
|
* 0b001..Light Sleep Mode. Low leakage mode, maintain memory contents.
|
|
* 0b010..Deep Sleep Mode. Low leakage mode, maintain memory contents.
|
|
* 0b100..Shut Down Mode. Shut Down periphery and core, no memory retention.
|
|
*/
|
|
#define PXP_POWER_ROT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_ROT_MEM_LP_STATE_SHIFT)) & PXP_POWER_ROT_MEM_LP_STATE_MASK)
|
|
#define PXP_POWER_CTRL_MASK (0xFFFFF000U)
|
|
#define PXP_POWER_CTRL_SHIFT (12U)
|
|
#define PXP_POWER_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_CTRL_SHIFT)) & PXP_POWER_CTRL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name NEXT - Next Frame Pointer */
|
|
/*! @{ */
|
|
#define PXP_NEXT_ENABLED_MASK (0x1U)
|
|
#define PXP_NEXT_ENABLED_SHIFT (0U)
|
|
#define PXP_NEXT_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_ENABLED_SHIFT)) & PXP_NEXT_ENABLED_MASK)
|
|
#define PXP_NEXT_RSVD_MASK (0x2U)
|
|
#define PXP_NEXT_RSVD_SHIFT (1U)
|
|
#define PXP_NEXT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_RSVD_SHIFT)) & PXP_NEXT_RSVD_MASK)
|
|
#define PXP_NEXT_POINTER_MASK (0xFFFFFFFCU)
|
|
#define PXP_NEXT_POINTER_SHIFT (2U)
|
|
#define PXP_NEXT_POINTER(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_POINTER_SHIFT)) & PXP_NEXT_POINTER_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PORTER_DUFF_CTRL - PXP Alpha Engine A Control Register. */
|
|
/*! @{ */
|
|
#define PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_MASK (0x1U)
|
|
#define PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_SHIFT (0U)
|
|
#define PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_SHIFT)) & PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_MASK)
|
|
#define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK (0x6U)
|
|
#define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT (1U)
|
|
#define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK)
|
|
#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK (0x18U)
|
|
#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT (3U)
|
|
#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK)
|
|
#define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK (0x20U)
|
|
#define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT (5U)
|
|
#define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK)
|
|
#define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK (0x40U)
|
|
#define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT (6U)
|
|
#define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK)
|
|
#define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK (0x300U)
|
|
#define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT (8U)
|
|
#define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK)
|
|
#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK (0xC00U)
|
|
#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT (10U)
|
|
#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK)
|
|
#define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK (0x1000U)
|
|
#define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT (12U)
|
|
#define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK)
|
|
#define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK (0x2000U)
|
|
#define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT (13U)
|
|
#define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK)
|
|
#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK (0xFF0000U)
|
|
#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT (16U)
|
|
#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK)
|
|
#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK (0xFF000000U)
|
|
#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT (24U)
|
|
#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group PXP_Register_Masks */
|
|
|
|
|
|
/* PXP - Peripheral instance base addresses */
|
|
/** Peripheral PXP base address */
|
|
#define PXP_BASE (0x402B4000u)
|
|
/** Peripheral PXP base pointer */
|
|
#define PXP ((PXP_Type *)PXP_BASE)
|
|
/** Array initializer of PXP peripheral base addresses */
|
|
#define PXP_BASE_ADDRS { PXP_BASE }
|
|
/** Array initializer of PXP peripheral base pointers */
|
|
#define PXP_BASE_PTRS { PXP }
|
|
/** Interrupt vectors for the PXP peripheral type */
|
|
#define PXP_IRQ0_IRQS { PXP_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group PXP_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- ROMC Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup ROMC_Peripheral_Access_Layer ROMC Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** ROMC - Register Layout Typedef */
|
|
typedef struct {
|
|
uint8_t RESERVED_0[212];
|
|
__IO uint32_t ROMPATCHD[8]; /**< ROMC Data Registers, array offset: 0xD4, array step: 0x4 */
|
|
__IO uint32_t ROMPATCHCNTL; /**< ROMC Control Register, offset: 0xF4 */
|
|
uint32_t ROMPATCHENH; /**< ROMC Enable Register High, offset: 0xF8 */
|
|
__IO uint32_t ROMPATCHENL; /**< ROMC Enable Register Low, offset: 0xFC */
|
|
__IO uint32_t ROMPATCHA[16]; /**< ROMC Address Registers, array offset: 0x100, array step: 0x4 */
|
|
uint8_t RESERVED_1[200];
|
|
__IO uint32_t ROMPATCHSR; /**< ROMC Status Register, offset: 0x208 */
|
|
} ROMC_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- ROMC Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup ROMC_Register_Masks ROMC Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name ROMPATCHD - ROMC Data Registers */
|
|
/*! @{ */
|
|
#define ROMC_ROMPATCHD_DATAX_MASK (0xFFFFFFFFU)
|
|
#define ROMC_ROMPATCHD_DATAX_SHIFT (0U)
|
|
#define ROMC_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHD_DATAX_SHIFT)) & ROMC_ROMPATCHD_DATAX_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of ROMC_ROMPATCHD */
|
|
#define ROMC_ROMPATCHD_COUNT (8U)
|
|
|
|
/*! @name ROMPATCHCNTL - ROMC Control Register */
|
|
/*! @{ */
|
|
#define ROMC_ROMPATCHCNTL_DATAFIX_MASK (0xFFU)
|
|
#define ROMC_ROMPATCHCNTL_DATAFIX_SHIFT (0U)
|
|
/*! DATAFIX
|
|
* 0b00000000..Address comparator triggers a opcode patch
|
|
* 0b00000001..Address comparator triggers a data fix
|
|
*/
|
|
#define ROMC_ROMPATCHCNTL_DATAFIX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DATAFIX_SHIFT)) & ROMC_ROMPATCHCNTL_DATAFIX_MASK)
|
|
#define ROMC_ROMPATCHCNTL_DIS_MASK (0x20000000U)
|
|
#define ROMC_ROMPATCHCNTL_DIS_SHIFT (29U)
|
|
/*! DIS
|
|
* 0b0..Does not affect any ROMC functions (default)
|
|
* 0b1..Disable all ROMC functions: data fixing, and opcode patching
|
|
*/
|
|
#define ROMC_ROMPATCHCNTL_DIS(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DIS_SHIFT)) & ROMC_ROMPATCHCNTL_DIS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ROMPATCHENL - ROMC Enable Register Low */
|
|
/*! @{ */
|
|
#define ROMC_ROMPATCHENL_ENABLE_MASK (0xFFFFU)
|
|
#define ROMC_ROMPATCHENL_ENABLE_SHIFT (0U)
|
|
/*! ENABLE
|
|
* 0b0000000000000000..Address comparator disabled
|
|
* 0b0000000000000001..Address comparator enabled, ROMC will trigger a opcode patch or data fix event upon matching of the associated address
|
|
*/
|
|
#define ROMC_ROMPATCHENL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHENL_ENABLE_SHIFT)) & ROMC_ROMPATCHENL_ENABLE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ROMPATCHA - ROMC Address Registers */
|
|
/*! @{ */
|
|
#define ROMC_ROMPATCHA_THUMBX_MASK (0x1U)
|
|
#define ROMC_ROMPATCHA_THUMBX_SHIFT (0U)
|
|
/*! THUMBX
|
|
* 0b0..Arm patch
|
|
* 0b1..THUMB patch (ignore if data fix)
|
|
*/
|
|
#define ROMC_ROMPATCHA_THUMBX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_THUMBX_SHIFT)) & ROMC_ROMPATCHA_THUMBX_MASK)
|
|
#define ROMC_ROMPATCHA_ADDRX_MASK (0x7FFFFEU)
|
|
#define ROMC_ROMPATCHA_ADDRX_SHIFT (1U)
|
|
#define ROMC_ROMPATCHA_ADDRX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_ADDRX_SHIFT)) & ROMC_ROMPATCHA_ADDRX_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of ROMC_ROMPATCHA */
|
|
#define ROMC_ROMPATCHA_COUNT (16U)
|
|
|
|
/*! @name ROMPATCHSR - ROMC Status Register */
|
|
/*! @{ */
|
|
#define ROMC_ROMPATCHSR_SOURCE_MASK (0x3FU)
|
|
#define ROMC_ROMPATCHSR_SOURCE_SHIFT (0U)
|
|
/*! SOURCE
|
|
* 0b000000..Address Comparator 0 matched
|
|
* 0b000001..Address Comparator 1 matched
|
|
* 0b001111..Address Comparator 15 matched
|
|
*/
|
|
#define ROMC_ROMPATCHSR_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SOURCE_SHIFT)) & ROMC_ROMPATCHSR_SOURCE_MASK)
|
|
#define ROMC_ROMPATCHSR_SW_MASK (0x20000U)
|
|
#define ROMC_ROMPATCHSR_SW_SHIFT (17U)
|
|
/*! SW
|
|
* 0b0..no event or comparator collisions
|
|
* 0b1..a collision has occurred
|
|
*/
|
|
#define ROMC_ROMPATCHSR_SW(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SW_SHIFT)) & ROMC_ROMPATCHSR_SW_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group ROMC_Register_Masks */
|
|
|
|
|
|
/* ROMC - Peripheral instance base addresses */
|
|
/** Peripheral ROMC base address */
|
|
#define ROMC_BASE (0x40180000u)
|
|
/** Peripheral ROMC base pointer */
|
|
#define ROMC ((ROMC_Type *)ROMC_BASE)
|
|
/** Array initializer of ROMC peripheral base addresses */
|
|
#define ROMC_BASE_ADDRS { ROMC_BASE }
|
|
/** Array initializer of ROMC peripheral base pointers */
|
|
#define ROMC_BASE_PTRS { ROMC }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group ROMC_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- RTWDOG Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup RTWDOG_Peripheral_Access_Layer RTWDOG Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** RTWDOG - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t CS; /**< Watchdog Control and Status Register, offset: 0x0 */
|
|
__IO uint32_t CNT; /**< Watchdog Counter Register, offset: 0x4 */
|
|
__IO uint32_t TOVAL; /**< Watchdog Timeout Value Register, offset: 0x8 */
|
|
__IO uint32_t WIN; /**< Watchdog Window Register, offset: 0xC */
|
|
} RTWDOG_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- RTWDOG Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup RTWDOG_Register_Masks RTWDOG Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name CS - Watchdog Control and Status Register */
|
|
/*! @{ */
|
|
#define RTWDOG_CS_STOP_MASK (0x1U)
|
|
#define RTWDOG_CS_STOP_SHIFT (0U)
|
|
/*! STOP - Stop Enable
|
|
* 0b0..Watchdog disabled in chip stop mode.
|
|
* 0b1..Watchdog enabled in chip stop mode.
|
|
*/
|
|
#define RTWDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_STOP_SHIFT)) & RTWDOG_CS_STOP_MASK)
|
|
#define RTWDOG_CS_WAIT_MASK (0x2U)
|
|
#define RTWDOG_CS_WAIT_SHIFT (1U)
|
|
/*! WAIT - Wait Enable
|
|
* 0b0..Watchdog disabled in chip wait mode.
|
|
* 0b1..Watchdog enabled in chip wait mode.
|
|
*/
|
|
#define RTWDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WAIT_SHIFT)) & RTWDOG_CS_WAIT_MASK)
|
|
#define RTWDOG_CS_DBG_MASK (0x4U)
|
|
#define RTWDOG_CS_DBG_SHIFT (2U)
|
|
/*! DBG - Debug Enable
|
|
* 0b0..Watchdog disabled in chip debug mode.
|
|
* 0b1..Watchdog enabled in chip debug mode.
|
|
*/
|
|
#define RTWDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_DBG_SHIFT)) & RTWDOG_CS_DBG_MASK)
|
|
#define RTWDOG_CS_TST_MASK (0x18U)
|
|
#define RTWDOG_CS_TST_SHIFT (3U)
|
|
/*! TST - Watchdog Test
|
|
* 0b00..Watchdog test mode disabled.
|
|
* 0b01..Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should use this setting to indicate that the watchdog is functioning normally in user mode.
|
|
* 0b10..Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW].
|
|
* 0b11..Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH].
|
|
*/
|
|
#define RTWDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_TST_SHIFT)) & RTWDOG_CS_TST_MASK)
|
|
#define RTWDOG_CS_UPDATE_MASK (0x20U)
|
|
#define RTWDOG_CS_UPDATE_SHIFT (5U)
|
|
/*! UPDATE - Allow updates
|
|
* 0b0..Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset.
|
|
* 0b1..Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence.
|
|
*/
|
|
#define RTWDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_UPDATE_SHIFT)) & RTWDOG_CS_UPDATE_MASK)
|
|
#define RTWDOG_CS_INT_MASK (0x40U)
|
|
#define RTWDOG_CS_INT_SHIFT (6U)
|
|
/*! INT - Watchdog Interrupt
|
|
* 0b0..Watchdog interrupts are disabled. Watchdog resets are not delayed.
|
|
* 0b1..Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks from the interrupt vector fetch.
|
|
*/
|
|
#define RTWDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_INT_SHIFT)) & RTWDOG_CS_INT_MASK)
|
|
#define RTWDOG_CS_EN_MASK (0x80U)
|
|
#define RTWDOG_CS_EN_SHIFT (7U)
|
|
/*! EN - Watchdog Enable
|
|
* 0b0..Watchdog disabled.
|
|
* 0b1..Watchdog enabled.
|
|
*/
|
|
#define RTWDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_EN_SHIFT)) & RTWDOG_CS_EN_MASK)
|
|
#define RTWDOG_CS_CLK_MASK (0x300U)
|
|
#define RTWDOG_CS_CLK_SHIFT (8U)
|
|
/*! CLK - Watchdog Clock
|
|
* 0b00..Bus clock
|
|
* 0b01..LPO clock
|
|
* 0b10..INTCLK (internal clock)
|
|
* 0b11..ERCLK (external reference clock)
|
|
*/
|
|
#define RTWDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CLK_SHIFT)) & RTWDOG_CS_CLK_MASK)
|
|
#define RTWDOG_CS_RCS_MASK (0x400U)
|
|
#define RTWDOG_CS_RCS_SHIFT (10U)
|
|
/*! RCS - Reconfiguration Success
|
|
* 0b0..Reconfiguring WDOG.
|
|
* 0b1..Reconfiguration is successful.
|
|
*/
|
|
#define RTWDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_RCS_SHIFT)) & RTWDOG_CS_RCS_MASK)
|
|
#define RTWDOG_CS_ULK_MASK (0x800U)
|
|
#define RTWDOG_CS_ULK_SHIFT (11U)
|
|
/*! ULK - Unlock status
|
|
* 0b0..WDOG is locked.
|
|
* 0b1..WDOG is unlocked.
|
|
*/
|
|
#define RTWDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_ULK_SHIFT)) & RTWDOG_CS_ULK_MASK)
|
|
#define RTWDOG_CS_PRES_MASK (0x1000U)
|
|
#define RTWDOG_CS_PRES_SHIFT (12U)
|
|
/*! PRES - Watchdog prescaler
|
|
* 0b0..256 prescaler disabled.
|
|
* 0b1..256 prescaler enabled.
|
|
*/
|
|
#define RTWDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_PRES_SHIFT)) & RTWDOG_CS_PRES_MASK)
|
|
#define RTWDOG_CS_CMD32EN_MASK (0x2000U)
|
|
#define RTWDOG_CS_CMD32EN_SHIFT (13U)
|
|
/*! CMD32EN - Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words
|
|
* 0b0..Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported.
|
|
* 0b1..Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported.
|
|
*/
|
|
#define RTWDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CMD32EN_SHIFT)) & RTWDOG_CS_CMD32EN_MASK)
|
|
#define RTWDOG_CS_FLG_MASK (0x4000U)
|
|
#define RTWDOG_CS_FLG_SHIFT (14U)
|
|
/*! FLG - Watchdog Interrupt Flag
|
|
* 0b0..No interrupt occurred.
|
|
* 0b1..An interrupt occurred.
|
|
*/
|
|
#define RTWDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_FLG_SHIFT)) & RTWDOG_CS_FLG_MASK)
|
|
#define RTWDOG_CS_WIN_MASK (0x8000U)
|
|
#define RTWDOG_CS_WIN_SHIFT (15U)
|
|
/*! WIN - Watchdog Window
|
|
* 0b0..Window mode disabled.
|
|
* 0b1..Window mode enabled.
|
|
*/
|
|
#define RTWDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WIN_SHIFT)) & RTWDOG_CS_WIN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CNT - Watchdog Counter Register */
|
|
/*! @{ */
|
|
#define RTWDOG_CNT_CNTLOW_MASK (0xFFU)
|
|
#define RTWDOG_CNT_CNTLOW_SHIFT (0U)
|
|
#define RTWDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTLOW_SHIFT)) & RTWDOG_CNT_CNTLOW_MASK)
|
|
#define RTWDOG_CNT_CNTHIGH_MASK (0xFF00U)
|
|
#define RTWDOG_CNT_CNTHIGH_SHIFT (8U)
|
|
#define RTWDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTHIGH_SHIFT)) & RTWDOG_CNT_CNTHIGH_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TOVAL - Watchdog Timeout Value Register */
|
|
/*! @{ */
|
|
#define RTWDOG_TOVAL_TOVALLOW_MASK (0xFFU)
|
|
#define RTWDOG_TOVAL_TOVALLOW_SHIFT (0U)
|
|
#define RTWDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALLOW_SHIFT)) & RTWDOG_TOVAL_TOVALLOW_MASK)
|
|
#define RTWDOG_TOVAL_TOVALHIGH_MASK (0xFF00U)
|
|
#define RTWDOG_TOVAL_TOVALHIGH_SHIFT (8U)
|
|
#define RTWDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALHIGH_SHIFT)) & RTWDOG_TOVAL_TOVALHIGH_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name WIN - Watchdog Window Register */
|
|
/*! @{ */
|
|
#define RTWDOG_WIN_WINLOW_MASK (0xFFU)
|
|
#define RTWDOG_WIN_WINLOW_SHIFT (0U)
|
|
#define RTWDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINLOW_SHIFT)) & RTWDOG_WIN_WINLOW_MASK)
|
|
#define RTWDOG_WIN_WINHIGH_MASK (0xFF00U)
|
|
#define RTWDOG_WIN_WINHIGH_SHIFT (8U)
|
|
#define RTWDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINHIGH_SHIFT)) & RTWDOG_WIN_WINHIGH_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group RTWDOG_Register_Masks */
|
|
|
|
|
|
/* RTWDOG - Peripheral instance base addresses */
|
|
/** Peripheral RTWDOG base address */
|
|
#define RTWDOG_BASE (0x400BC000u)
|
|
/** Peripheral RTWDOG base pointer */
|
|
#define RTWDOG ((RTWDOG_Type *)RTWDOG_BASE)
|
|
/** Array initializer of RTWDOG peripheral base addresses */
|
|
#define RTWDOG_BASE_ADDRS { RTWDOG_BASE }
|
|
/** Array initializer of RTWDOG peripheral base pointers */
|
|
#define RTWDOG_BASE_PTRS { RTWDOG }
|
|
/** Interrupt vectors for the RTWDOG peripheral type */
|
|
#define RTWDOG_IRQS { RTWDOG_IRQn }
|
|
/* Extra definition */
|
|
#define RTWDOG_UPDATE_KEY (0xD928C520U)
|
|
#define RTWDOG_REFRESH_KEY (0xB480A602U)
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group RTWDOG_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- SEMC Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup SEMC_Peripheral_Access_Layer SEMC Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** SEMC - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t MCR; /**< Module Control Register, offset: 0x0 */
|
|
__IO uint32_t IOCR; /**< IO Mux Control Register, offset: 0x4 */
|
|
__IO uint32_t BMCR0; /**< Master Bus (AXI) Control Register 0, offset: 0x8 */
|
|
__IO uint32_t BMCR1; /**< Master Bus (AXI) Control Register 1, offset: 0xC */
|
|
__IO uint32_t BR[9]; /**< Base Register 0 (For SDRAM CS0 device)..Base Register 8 (For NAND device), array offset: 0x10, array step: 0x4 */
|
|
uint8_t RESERVED_0[4];
|
|
__IO uint32_t INTEN; /**< Interrupt Enable Register, offset: 0x38 */
|
|
__IO uint32_t INTR; /**< Interrupt Enable Register, offset: 0x3C */
|
|
__IO uint32_t SDRAMCR0; /**< SDRAM control register 0, offset: 0x40 */
|
|
__IO uint32_t SDRAMCR1; /**< SDRAM control register 1, offset: 0x44 */
|
|
__IO uint32_t SDRAMCR2; /**< SDRAM control register 2, offset: 0x48 */
|
|
__IO uint32_t SDRAMCR3; /**< SDRAM control register 3, offset: 0x4C */
|
|
__IO uint32_t NANDCR0; /**< NAND control register 0, offset: 0x50 */
|
|
__IO uint32_t NANDCR1; /**< NAND control register 1, offset: 0x54 */
|
|
__IO uint32_t NANDCR2; /**< NAND control register 2, offset: 0x58 */
|
|
__IO uint32_t NANDCR3; /**< NAND control register 3, offset: 0x5C */
|
|
__IO uint32_t NORCR0; /**< NOR control register 0, offset: 0x60 */
|
|
__IO uint32_t NORCR1; /**< NOR control register 1, offset: 0x64 */
|
|
__IO uint32_t NORCR2; /**< NOR control register 2, offset: 0x68 */
|
|
uint32_t NORCR3; /**< NOR control register 3, offset: 0x6C */
|
|
__IO uint32_t SRAMCR0; /**< SRAM control register 0, offset: 0x70 */
|
|
__IO uint32_t SRAMCR1; /**< SRAM control register 1, offset: 0x74 */
|
|
__IO uint32_t SRAMCR2; /**< SRAM control register 2, offset: 0x78 */
|
|
uint32_t SRAMCR3; /**< SRAM control register 3, offset: 0x7C */
|
|
__IO uint32_t DBICR0; /**< DBI-B control register 0, offset: 0x80 */
|
|
__IO uint32_t DBICR1; /**< DBI-B control register 1, offset: 0x84 */
|
|
uint8_t RESERVED_1[8];
|
|
__IO uint32_t IPCR0; /**< IP Command control register 0, offset: 0x90 */
|
|
__IO uint32_t IPCR1; /**< IP Command control register 1, offset: 0x94 */
|
|
__IO uint32_t IPCR2; /**< IP Command control register 2, offset: 0x98 */
|
|
__IO uint32_t IPCMD; /**< IP Command register, offset: 0x9C */
|
|
__IO uint32_t IPTXDAT; /**< TX DATA register (for IP Command), offset: 0xA0 */
|
|
uint8_t RESERVED_2[12];
|
|
__I uint32_t IPRXDAT; /**< RX DATA register (for IP Command), offset: 0xB0 */
|
|
uint8_t RESERVED_3[12];
|
|
__I uint32_t STS0; /**< Status register 0, offset: 0xC0 */
|
|
uint32_t STS1; /**< Status register 1, offset: 0xC4 */
|
|
__I uint32_t STS2; /**< Status register 2, offset: 0xC8 */
|
|
uint32_t STS3; /**< Status register 3, offset: 0xCC */
|
|
uint32_t STS4; /**< Status register 4, offset: 0xD0 */
|
|
uint32_t STS5; /**< Status register 5, offset: 0xD4 */
|
|
uint32_t STS6; /**< Status register 6, offset: 0xD8 */
|
|
uint32_t STS7; /**< Status register 7, offset: 0xDC */
|
|
uint32_t STS8; /**< Status register 8, offset: 0xE0 */
|
|
uint32_t STS9; /**< Status register 9, offset: 0xE4 */
|
|
uint32_t STS10; /**< Status register 10, offset: 0xE8 */
|
|
uint32_t STS11; /**< Status register 11, offset: 0xEC */
|
|
__I uint32_t STS12; /**< Status register 12, offset: 0xF0 */
|
|
uint32_t STS13; /**< Status register 13, offset: 0xF4 */
|
|
uint32_t STS14; /**< Status register 14, offset: 0xF8 */
|
|
uint32_t STS15; /**< Status register 15, offset: 0xFC */
|
|
} SEMC_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- SEMC Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup SEMC_Register_Masks SEMC Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name MCR - Module Control Register */
|
|
/*! @{ */
|
|
#define SEMC_MCR_SWRST_MASK (0x1U)
|
|
#define SEMC_MCR_SWRST_SHIFT (0U)
|
|
#define SEMC_MCR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)
|
|
#define SEMC_MCR_MDIS_MASK (0x2U)
|
|
#define SEMC_MCR_MDIS_SHIFT (1U)
|
|
/*! MDIS - Module Disable
|
|
* 0b0..Module enabled
|
|
* 0b1..Module disabled.
|
|
*/
|
|
#define SEMC_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_MDIS_SHIFT)) & SEMC_MCR_MDIS_MASK)
|
|
#define SEMC_MCR_DQSMD_MASK (0x4U)
|
|
#define SEMC_MCR_DQSMD_SHIFT (2U)
|
|
/*! DQSMD - DQS (read strobe) mode
|
|
* 0b0..Dummy read strobe loopbacked internally
|
|
* 0b1..Dummy read strobe loopbacked from DQS pad
|
|
*/
|
|
#define SEMC_MCR_DQSMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSMD_SHIFT)) & SEMC_MCR_DQSMD_MASK)
|
|
#define SEMC_MCR_WPOL0_MASK (0x40U)
|
|
#define SEMC_MCR_WPOL0_SHIFT (6U)
|
|
/*! WPOL0 - WAIT/RDY# polarity for NOR/PSRAM
|
|
* 0b0..Low active
|
|
* 0b1..High active
|
|
*/
|
|
#define SEMC_MCR_WPOL0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL0_SHIFT)) & SEMC_MCR_WPOL0_MASK)
|
|
#define SEMC_MCR_WPOL1_MASK (0x80U)
|
|
#define SEMC_MCR_WPOL1_SHIFT (7U)
|
|
/*! WPOL1 - WAIT/RDY# polarity for NAND
|
|
* 0b0..Low active
|
|
* 0b1..High active
|
|
*/
|
|
#define SEMC_MCR_WPOL1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL1_SHIFT)) & SEMC_MCR_WPOL1_MASK)
|
|
#define SEMC_MCR_CTO_MASK (0xFF0000U)
|
|
#define SEMC_MCR_CTO_SHIFT (16U)
|
|
#define SEMC_MCR_CTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_CTO_SHIFT)) & SEMC_MCR_CTO_MASK)
|
|
#define SEMC_MCR_BTO_MASK (0x1F000000U)
|
|
#define SEMC_MCR_BTO_SHIFT (24U)
|
|
/*! BTO - Bus timeout cycles
|
|
* 0b00000..255*1
|
|
* 0b00001-0b11110..255*2 - 255*2^30
|
|
* 0b11111..255*2^31
|
|
*/
|
|
#define SEMC_MCR_BTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_BTO_SHIFT)) & SEMC_MCR_BTO_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name IOCR - IO Mux Control Register */
|
|
/*! @{ */
|
|
#define SEMC_IOCR_MUX_A8_MASK (0x7U)
|
|
#define SEMC_IOCR_MUX_A8_SHIFT (0U)
|
|
/*! MUX_A8 - SEMC_A8 output selection
|
|
* 0b000..SDRAM Address bit (A8)
|
|
* 0b001..NAND CE#
|
|
* 0b010..NOR CE#
|
|
* 0b011..PSRAM CE#
|
|
* 0b100..DBI CSX
|
|
* 0b101..SDRAM Address bit (A8)
|
|
* 0b110..SDRAM Address bit (A8)
|
|
* 0b111..SDRAM Address bit (A8)
|
|
*/
|
|
#define SEMC_IOCR_MUX_A8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_A8_SHIFT)) & SEMC_IOCR_MUX_A8_MASK)
|
|
#define SEMC_IOCR_MUX_CSX0_MASK (0x38U)
|
|
#define SEMC_IOCR_MUX_CSX0_SHIFT (3U)
|
|
/*! MUX_CSX0 - SEMC_CSX0 output selection
|
|
* 0b000..NOR/PSRAM Address bit 24 (A24)
|
|
* 0b001..SDRAM CS1
|
|
* 0b010..SDRAM CS2
|
|
* 0b011..SDRAM CS3
|
|
* 0b100..NAND CE#
|
|
* 0b101..NOR CE#
|
|
* 0b110..PSRAM CE#
|
|
* 0b111..DBI CSX
|
|
*/
|
|
#define SEMC_IOCR_MUX_CSX0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX0_SHIFT)) & SEMC_IOCR_MUX_CSX0_MASK)
|
|
#define SEMC_IOCR_MUX_CSX1_MASK (0x1C0U)
|
|
#define SEMC_IOCR_MUX_CSX1_SHIFT (6U)
|
|
/*! MUX_CSX1 - SEMC_CSX1 output selection
|
|
* 0b000..NOR/PSRAM Address bit 25 (A25)
|
|
* 0b001..SDRAM CS1
|
|
* 0b010..SDRAM CS2
|
|
* 0b011..SDRAM CS3
|
|
* 0b100..NAND CE#
|
|
* 0b101..NOR CE#
|
|
* 0b110..PSRAM CE#
|
|
* 0b111..DBI CSX
|
|
*/
|
|
#define SEMC_IOCR_MUX_CSX1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX1_SHIFT)) & SEMC_IOCR_MUX_CSX1_MASK)
|
|
#define SEMC_IOCR_MUX_CSX2_MASK (0xE00U)
|
|
#define SEMC_IOCR_MUX_CSX2_SHIFT (9U)
|
|
/*! MUX_CSX2 - SEMC_CSX2 output selection
|
|
* 0b000..NOR/PSRAM Address bit 26 (A26)
|
|
* 0b001..SDRAM CS1
|
|
* 0b010..SDRAM CS2
|
|
* 0b011..SDRAM CS3
|
|
* 0b100..NAND CE#
|
|
* 0b101..NOR CE#
|
|
* 0b110..PSRAM CE#
|
|
* 0b111..DBI CSX
|
|
*/
|
|
#define SEMC_IOCR_MUX_CSX2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX2_SHIFT)) & SEMC_IOCR_MUX_CSX2_MASK)
|
|
#define SEMC_IOCR_MUX_CSX3_MASK (0x7000U)
|
|
#define SEMC_IOCR_MUX_CSX3_SHIFT (12U)
|
|
/*! MUX_CSX3 - SEMC_CSX3 output selection
|
|
* 0b000..NOR/PSRAM Address bit 27 (A27)
|
|
* 0b001..SDRAM CS1
|
|
* 0b010..SDRAM CS2
|
|
* 0b011..SDRAM CS3
|
|
* 0b100..NAND CE#
|
|
* 0b101..NOR CE#
|
|
* 0b110..PSRAM CE#
|
|
* 0b111..DBI CSX
|
|
*/
|
|
#define SEMC_IOCR_MUX_CSX3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX3_SHIFT)) & SEMC_IOCR_MUX_CSX3_MASK)
|
|
#define SEMC_IOCR_MUX_RDY_MASK (0x38000U)
|
|
#define SEMC_IOCR_MUX_RDY_SHIFT (15U)
|
|
/*! MUX_RDY - SEMC_RDY function selection
|
|
* 0b000..NAND Ready/Wait# input
|
|
* 0b001..SDRAM CS1
|
|
* 0b010..SDRAM CS2
|
|
* 0b011..SDRAM CS3
|
|
* 0b100..NOR CE#
|
|
* 0b101..PSRAM CE#
|
|
* 0b110..DBI CSX
|
|
* 0b111..NOR/PSRAM Address bit 27
|
|
*/
|
|
#define SEMC_IOCR_MUX_RDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_RDY_SHIFT)) & SEMC_IOCR_MUX_RDY_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name BMCR0 - Master Bus (AXI) Control Register 0 */
|
|
/*! @{ */
|
|
#define SEMC_BMCR0_WQOS_MASK (0xFU)
|
|
#define SEMC_BMCR0_WQOS_SHIFT (0U)
|
|
#define SEMC_BMCR0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WQOS_SHIFT)) & SEMC_BMCR0_WQOS_MASK)
|
|
#define SEMC_BMCR0_WAGE_MASK (0xF0U)
|
|
#define SEMC_BMCR0_WAGE_SHIFT (4U)
|
|
#define SEMC_BMCR0_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WAGE_SHIFT)) & SEMC_BMCR0_WAGE_MASK)
|
|
#define SEMC_BMCR0_WSH_MASK (0xFF00U)
|
|
#define SEMC_BMCR0_WSH_SHIFT (8U)
|
|
#define SEMC_BMCR0_WSH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WSH_SHIFT)) & SEMC_BMCR0_WSH_MASK)
|
|
#define SEMC_BMCR0_WRWS_MASK (0xFF0000U)
|
|
#define SEMC_BMCR0_WRWS_SHIFT (16U)
|
|
#define SEMC_BMCR0_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WRWS_SHIFT)) & SEMC_BMCR0_WRWS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name BMCR1 - Master Bus (AXI) Control Register 1 */
|
|
/*! @{ */
|
|
#define SEMC_BMCR1_WQOS_MASK (0xFU)
|
|
#define SEMC_BMCR1_WQOS_SHIFT (0U)
|
|
#define SEMC_BMCR1_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WQOS_SHIFT)) & SEMC_BMCR1_WQOS_MASK)
|
|
#define SEMC_BMCR1_WAGE_MASK (0xF0U)
|
|
#define SEMC_BMCR1_WAGE_SHIFT (4U)
|
|
#define SEMC_BMCR1_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WAGE_SHIFT)) & SEMC_BMCR1_WAGE_MASK)
|
|
#define SEMC_BMCR1_WPH_MASK (0xFF00U)
|
|
#define SEMC_BMCR1_WPH_SHIFT (8U)
|
|
#define SEMC_BMCR1_WPH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WPH_SHIFT)) & SEMC_BMCR1_WPH_MASK)
|
|
#define SEMC_BMCR1_WRWS_MASK (0xFF0000U)
|
|
#define SEMC_BMCR1_WRWS_SHIFT (16U)
|
|
#define SEMC_BMCR1_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WRWS_SHIFT)) & SEMC_BMCR1_WRWS_MASK)
|
|
#define SEMC_BMCR1_WBR_MASK (0xFF000000U)
|
|
#define SEMC_BMCR1_WBR_SHIFT (24U)
|
|
#define SEMC_BMCR1_WBR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WBR_SHIFT)) & SEMC_BMCR1_WBR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name BR - Base Register 0 (For SDRAM CS0 device)..Base Register 8 (For NAND device) */
|
|
/*! @{ */
|
|
#define SEMC_BR_VLD_MASK (0x1U)
|
|
#define SEMC_BR_VLD_SHIFT (0U)
|
|
#define SEMC_BR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_VLD_SHIFT)) & SEMC_BR_VLD_MASK)
|
|
#define SEMC_BR_MS_MASK (0x3EU)
|
|
#define SEMC_BR_MS_SHIFT (1U)
|
|
/*! MS - Memory size
|
|
* 0b00000..4KB
|
|
* 0b00001..8KB
|
|
* 0b00010..16KB
|
|
* 0b00011..32KB
|
|
* 0b00100..64KB
|
|
* 0b00101..128KB
|
|
* 0b00110..256KB
|
|
* 0b00111..512KB
|
|
* 0b01000..1MB
|
|
* 0b01001..2MB
|
|
* 0b01010..4MB
|
|
* 0b01011..8MB
|
|
* 0b01100..16MB
|
|
* 0b01101..32MB
|
|
* 0b01110..64MB
|
|
* 0b01111..128MB
|
|
* 0b10000..256MB
|
|
* 0b10001..512MB
|
|
* 0b10010..1GB
|
|
* 0b10011..2GB
|
|
* 0b10100..4GB
|
|
* 0b10101..4GB
|
|
* 0b10110..4GB
|
|
* 0b10111..4GB
|
|
* 0b11000..4GB
|
|
* 0b11001..4GB
|
|
* 0b11010..4GB
|
|
* 0b11011..4GB
|
|
* 0b11100..4GB
|
|
* 0b11101..4GB
|
|
* 0b11110..4GB
|
|
* 0b11111..4GB
|
|
*/
|
|
#define SEMC_BR_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_MS_SHIFT)) & SEMC_BR_MS_MASK)
|
|
#define SEMC_BR_BA_MASK (0xFFFFF000U)
|
|
#define SEMC_BR_BA_SHIFT (12U)
|
|
#define SEMC_BR_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_BA_SHIFT)) & SEMC_BR_BA_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of SEMC_BR */
|
|
#define SEMC_BR_COUNT (9U)
|
|
|
|
/*! @name INTEN - Interrupt Enable Register */
|
|
/*! @{ */
|
|
#define SEMC_INTEN_IPCMDDONEEN_MASK (0x1U)
|
|
#define SEMC_INTEN_IPCMDDONEEN_SHIFT (0U)
|
|
#define SEMC_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK)
|
|
#define SEMC_INTEN_IPCMDERREN_MASK (0x2U)
|
|
#define SEMC_INTEN_IPCMDERREN_SHIFT (1U)
|
|
#define SEMC_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK)
|
|
#define SEMC_INTEN_AXICMDERREN_MASK (0x4U)
|
|
#define SEMC_INTEN_AXICMDERREN_SHIFT (2U)
|
|
#define SEMC_INTEN_AXICMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK)
|
|
#define SEMC_INTEN_AXIBUSERREN_MASK (0x8U)
|
|
#define SEMC_INTEN_AXIBUSERREN_SHIFT (3U)
|
|
#define SEMC_INTEN_AXIBUSERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK)
|
|
#define SEMC_INTEN_NDPAGEENDEN_MASK (0x10U)
|
|
#define SEMC_INTEN_NDPAGEENDEN_SHIFT (4U)
|
|
/*! NDPAGEENDEN - This bit enable/disable the NDPAGEEND interrupt generation.
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define SEMC_INTEN_NDPAGEENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK)
|
|
#define SEMC_INTEN_NDNOPENDEN_MASK (0x20U)
|
|
#define SEMC_INTEN_NDNOPENDEN_SHIFT (5U)
|
|
/*! NDNOPENDEN - This bit enable/disable the NDNOPEND interrupt generation.
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
|
|
#define SEMC_INTEN_NDNOPENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name INTR - Interrupt Enable Register */
|
|
/*! @{ */
|
|
#define SEMC_INTR_IPCMDDONE_MASK (0x1U)
|
|
#define SEMC_INTR_IPCMDDONE_SHIFT (0U)
|
|
#define SEMC_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK)
|
|
#define SEMC_INTR_IPCMDERR_MASK (0x2U)
|
|
#define SEMC_INTR_IPCMDERR_SHIFT (1U)
|
|
#define SEMC_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDERR_SHIFT)) & SEMC_INTR_IPCMDERR_MASK)
|
|
#define SEMC_INTR_AXICMDERR_MASK (0x4U)
|
|
#define SEMC_INTR_AXICMDERR_SHIFT (2U)
|
|
#define SEMC_INTR_AXICMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXICMDERR_SHIFT)) & SEMC_INTR_AXICMDERR_MASK)
|
|
#define SEMC_INTR_AXIBUSERR_MASK (0x8U)
|
|
#define SEMC_INTR_AXIBUSERR_SHIFT (3U)
|
|
#define SEMC_INTR_AXIBUSERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXIBUSERR_SHIFT)) & SEMC_INTR_AXIBUSERR_MASK)
|
|
#define SEMC_INTR_NDPAGEEND_MASK (0x10U)
|
|
#define SEMC_INTR_NDPAGEEND_SHIFT (4U)
|
|
#define SEMC_INTR_NDPAGEEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDPAGEEND_SHIFT)) & SEMC_INTR_NDPAGEEND_MASK)
|
|
#define SEMC_INTR_NDNOPEND_MASK (0x20U)
|
|
#define SEMC_INTR_NDNOPEND_SHIFT (5U)
|
|
#define SEMC_INTR_NDNOPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SDRAMCR0 - SDRAM control register 0 */
|
|
/*! @{ */
|
|
#define SEMC_SDRAMCR0_PS_MASK (0x1U)
|
|
#define SEMC_SDRAMCR0_PS_SHIFT (0U)
|
|
/*! PS - Port Size
|
|
* 0b0..8bit
|
|
* 0b1..16bit
|
|
*/
|
|
#define SEMC_SDRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK)
|
|
#define SEMC_SDRAMCR0_BL_MASK (0x70U)
|
|
#define SEMC_SDRAMCR0_BL_SHIFT (4U)
|
|
/*! BL - Burst Length
|
|
* 0b000..1
|
|
* 0b001..2
|
|
* 0b010..4
|
|
* 0b011..8
|
|
* 0b100..8
|
|
* 0b101..8
|
|
* 0b110..8
|
|
* 0b111..8
|
|
*/
|
|
#define SEMC_SDRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BL_SHIFT)) & SEMC_SDRAMCR0_BL_MASK)
|
|
#define SEMC_SDRAMCR0_COL_MASK (0x300U)
|
|
#define SEMC_SDRAMCR0_COL_SHIFT (8U)
|
|
/*! COL - Column address bit number
|
|
* 0b00..12 bit
|
|
* 0b01..11 bit
|
|
* 0b10..10 bit
|
|
* 0b11..9 bit
|
|
*/
|
|
#define SEMC_SDRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL_SHIFT)) & SEMC_SDRAMCR0_COL_MASK)
|
|
#define SEMC_SDRAMCR0_CL_MASK (0xC00U)
|
|
#define SEMC_SDRAMCR0_CL_SHIFT (10U)
|
|
/*! CL - CAS Latency
|
|
* 0b00..1
|
|
* 0b01..1
|
|
* 0b10..2
|
|
* 0b11..3
|
|
*/
|
|
#define SEMC_SDRAMCR0_CL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_CL_SHIFT)) & SEMC_SDRAMCR0_CL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SDRAMCR1 - SDRAM control register 1 */
|
|
/*! @{ */
|
|
#define SEMC_SDRAMCR1_PRE2ACT_MASK (0xFU)
|
|
#define SEMC_SDRAMCR1_PRE2ACT_SHIFT (0U)
|
|
#define SEMC_SDRAMCR1_PRE2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_PRE2ACT_SHIFT)) & SEMC_SDRAMCR1_PRE2ACT_MASK)
|
|
#define SEMC_SDRAMCR1_ACT2RW_MASK (0xF0U)
|
|
#define SEMC_SDRAMCR1_ACT2RW_SHIFT (4U)
|
|
#define SEMC_SDRAMCR1_ACT2RW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2RW_SHIFT)) & SEMC_SDRAMCR1_ACT2RW_MASK)
|
|
#define SEMC_SDRAMCR1_RFRC_MASK (0x1F00U)
|
|
#define SEMC_SDRAMCR1_RFRC_SHIFT (8U)
|
|
#define SEMC_SDRAMCR1_RFRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_RFRC_SHIFT)) & SEMC_SDRAMCR1_RFRC_MASK)
|
|
#define SEMC_SDRAMCR1_WRC_MASK (0xE000U)
|
|
#define SEMC_SDRAMCR1_WRC_SHIFT (13U)
|
|
#define SEMC_SDRAMCR1_WRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_WRC_SHIFT)) & SEMC_SDRAMCR1_WRC_MASK)
|
|
#define SEMC_SDRAMCR1_CKEOFF_MASK (0xF0000U)
|
|
#define SEMC_SDRAMCR1_CKEOFF_SHIFT (16U)
|
|
#define SEMC_SDRAMCR1_CKEOFF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_CKEOFF_SHIFT)) & SEMC_SDRAMCR1_CKEOFF_MASK)
|
|
#define SEMC_SDRAMCR1_ACT2PRE_MASK (0xF00000U)
|
|
#define SEMC_SDRAMCR1_ACT2PRE_SHIFT (20U)
|
|
#define SEMC_SDRAMCR1_ACT2PRE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2PRE_SHIFT)) & SEMC_SDRAMCR1_ACT2PRE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SDRAMCR2 - SDRAM control register 2 */
|
|
/*! @{ */
|
|
#define SEMC_SDRAMCR2_SRRC_MASK (0xFFU)
|
|
#define SEMC_SDRAMCR2_SRRC_SHIFT (0U)
|
|
#define SEMC_SDRAMCR2_SRRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_SRRC_SHIFT)) & SEMC_SDRAMCR2_SRRC_MASK)
|
|
#define SEMC_SDRAMCR2_REF2REF_MASK (0xFF00U)
|
|
#define SEMC_SDRAMCR2_REF2REF_SHIFT (8U)
|
|
#define SEMC_SDRAMCR2_REF2REF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_REF2REF_SHIFT)) & SEMC_SDRAMCR2_REF2REF_MASK)
|
|
#define SEMC_SDRAMCR2_ACT2ACT_MASK (0xFF0000U)
|
|
#define SEMC_SDRAMCR2_ACT2ACT_SHIFT (16U)
|
|
#define SEMC_SDRAMCR2_ACT2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ACT2ACT_SHIFT)) & SEMC_SDRAMCR2_ACT2ACT_MASK)
|
|
#define SEMC_SDRAMCR2_ITO_MASK (0xFF000000U)
|
|
#define SEMC_SDRAMCR2_ITO_SHIFT (24U)
|
|
/*! ITO - SDRAM Idle timeout
|
|
* 0b00000000..IDLE timeout period is 256*Prescale period.
|
|
* 0b00000001-0b11111111..IDLE timeout period is ITO*Prescale period.
|
|
*/
|
|
#define SEMC_SDRAMCR2_ITO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ITO_SHIFT)) & SEMC_SDRAMCR2_ITO_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SDRAMCR3 - SDRAM control register 3 */
|
|
/*! @{ */
|
|
#define SEMC_SDRAMCR3_REN_MASK (0x1U)
|
|
#define SEMC_SDRAMCR3_REN_SHIFT (0U)
|
|
#define SEMC_SDRAMCR3_REN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)
|
|
#define SEMC_SDRAMCR3_REBL_MASK (0xEU)
|
|
#define SEMC_SDRAMCR3_REBL_SHIFT (1U)
|
|
/*! REBL - Refresh burst length
|
|
* 0b000..1
|
|
* 0b001..2
|
|
* 0b010..3
|
|
* 0b011..4
|
|
* 0b100..5
|
|
* 0b101..6
|
|
* 0b110..7
|
|
* 0b111..8
|
|
*/
|
|
#define SEMC_SDRAMCR3_REBL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REBL_SHIFT)) & SEMC_SDRAMCR3_REBL_MASK)
|
|
#define SEMC_SDRAMCR3_PRESCALE_MASK (0xFF00U)
|
|
#define SEMC_SDRAMCR3_PRESCALE_SHIFT (8U)
|
|
/*! PRESCALE - Prescaler timer period
|
|
* 0b00000000..256*16 cycle
|
|
* 0b00000001-0b11111111..PRESCALE*16 cycle
|
|
*/
|
|
#define SEMC_SDRAMCR3_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_PRESCALE_SHIFT)) & SEMC_SDRAMCR3_PRESCALE_MASK)
|
|
#define SEMC_SDRAMCR3_RT_MASK (0xFF0000U)
|
|
#define SEMC_SDRAMCR3_RT_SHIFT (16U)
|
|
/*! RT - Refresh timer period
|
|
* 0b00000000..256*Prescaler period
|
|
* 0b00000001-0b11111111..RT*Prescaler period
|
|
*/
|
|
#define SEMC_SDRAMCR3_RT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_RT_SHIFT)) & SEMC_SDRAMCR3_RT_MASK)
|
|
#define SEMC_SDRAMCR3_UT_MASK (0xFF000000U)
|
|
#define SEMC_SDRAMCR3_UT_SHIFT (24U)
|
|
/*! UT - Refresh urgent threshold
|
|
* 0b00000000..256*Prescaler period
|
|
* 0b00000001-0b11111111..UT*Prescaler period
|
|
*/
|
|
#define SEMC_SDRAMCR3_UT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_UT_SHIFT)) & SEMC_SDRAMCR3_UT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name NANDCR0 - NAND control register 0 */
|
|
/*! @{ */
|
|
#define SEMC_NANDCR0_PS_MASK (0x1U)
|
|
#define SEMC_NANDCR0_PS_SHIFT (0U)
|
|
/*! PS - Port Size
|
|
* 0b0..8bit
|
|
* 0b1..16bit
|
|
*/
|
|
#define SEMC_NANDCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_PS_SHIFT)) & SEMC_NANDCR0_PS_MASK)
|
|
#define SEMC_NANDCR0_BL_MASK (0x70U)
|
|
#define SEMC_NANDCR0_BL_SHIFT (4U)
|
|
/*! BL - Burst Length
|
|
* 0b000..1
|
|
* 0b001..2
|
|
* 0b010..4
|
|
* 0b011..8
|
|
* 0b100..16
|
|
* 0b101..32
|
|
* 0b110..64
|
|
* 0b111..64
|
|
*/
|
|
#define SEMC_NANDCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_BL_SHIFT)) & SEMC_NANDCR0_BL_MASK)
|
|
#define SEMC_NANDCR0_EDO_MASK (0x80U)
|
|
#define SEMC_NANDCR0_EDO_SHIFT (7U)
|
|
/*! EDO - EDO mode enabled
|
|
* 0b0..EDO mode disabled
|
|
* 0b1..EDO mode enabled
|
|
*/
|
|
#define SEMC_NANDCR0_EDO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_EDO_SHIFT)) & SEMC_NANDCR0_EDO_MASK)
|
|
#define SEMC_NANDCR0_COL_MASK (0x700U)
|
|
#define SEMC_NANDCR0_COL_SHIFT (8U)
|
|
/*! COL - Column address bit number
|
|
* 0b000..16
|
|
* 0b001..15
|
|
* 0b010..14
|
|
* 0b011..13
|
|
* 0b100..12
|
|
* 0b101..11
|
|
* 0b110..10
|
|
* 0b111..9
|
|
*/
|
|
#define SEMC_NANDCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_COL_SHIFT)) & SEMC_NANDCR0_COL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name NANDCR1 - NAND control register 1 */
|
|
/*! @{ */
|
|
#define SEMC_NANDCR1_CES_MASK (0xFU)
|
|
#define SEMC_NANDCR1_CES_SHIFT (0U)
|
|
#define SEMC_NANDCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CES_SHIFT)) & SEMC_NANDCR1_CES_MASK)
|
|
#define SEMC_NANDCR1_CEH_MASK (0xF0U)
|
|
#define SEMC_NANDCR1_CEH_SHIFT (4U)
|
|
#define SEMC_NANDCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEH_SHIFT)) & SEMC_NANDCR1_CEH_MASK)
|
|
#define SEMC_NANDCR1_WEL_MASK (0xF00U)
|
|
#define SEMC_NANDCR1_WEL_SHIFT (8U)
|
|
#define SEMC_NANDCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEL_SHIFT)) & SEMC_NANDCR1_WEL_MASK)
|
|
#define SEMC_NANDCR1_WEH_MASK (0xF000U)
|
|
#define SEMC_NANDCR1_WEH_SHIFT (12U)
|
|
#define SEMC_NANDCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEH_SHIFT)) & SEMC_NANDCR1_WEH_MASK)
|
|
#define SEMC_NANDCR1_REL_MASK (0xF0000U)
|
|
#define SEMC_NANDCR1_REL_SHIFT (16U)
|
|
#define SEMC_NANDCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REL_SHIFT)) & SEMC_NANDCR1_REL_MASK)
|
|
#define SEMC_NANDCR1_REH_MASK (0xF00000U)
|
|
#define SEMC_NANDCR1_REH_SHIFT (20U)
|
|
#define SEMC_NANDCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REH_SHIFT)) & SEMC_NANDCR1_REH_MASK)
|
|
#define SEMC_NANDCR1_TA_MASK (0xF000000U)
|
|
#define SEMC_NANDCR1_TA_SHIFT (24U)
|
|
#define SEMC_NANDCR1_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_TA_SHIFT)) & SEMC_NANDCR1_TA_MASK)
|
|
#define SEMC_NANDCR1_CEITV_MASK (0xF0000000U)
|
|
#define SEMC_NANDCR1_CEITV_SHIFT (28U)
|
|
#define SEMC_NANDCR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEITV_SHIFT)) & SEMC_NANDCR1_CEITV_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name NANDCR2 - NAND control register 2 */
|
|
/*! @{ */
|
|
#define SEMC_NANDCR2_TWHR_MASK (0x3FU)
|
|
#define SEMC_NANDCR2_TWHR_SHIFT (0U)
|
|
#define SEMC_NANDCR2_TWHR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWHR_SHIFT)) & SEMC_NANDCR2_TWHR_MASK)
|
|
#define SEMC_NANDCR2_TRHW_MASK (0xFC0U)
|
|
#define SEMC_NANDCR2_TRHW_SHIFT (6U)
|
|
#define SEMC_NANDCR2_TRHW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRHW_SHIFT)) & SEMC_NANDCR2_TRHW_MASK)
|
|
#define SEMC_NANDCR2_TADL_MASK (0x3F000U)
|
|
#define SEMC_NANDCR2_TADL_SHIFT (12U)
|
|
#define SEMC_NANDCR2_TADL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TADL_SHIFT)) & SEMC_NANDCR2_TADL_MASK)
|
|
#define SEMC_NANDCR2_TRR_MASK (0xFC0000U)
|
|
#define SEMC_NANDCR2_TRR_SHIFT (18U)
|
|
#define SEMC_NANDCR2_TRR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRR_SHIFT)) & SEMC_NANDCR2_TRR_MASK)
|
|
#define SEMC_NANDCR2_TWB_MASK (0x3F000000U)
|
|
#define SEMC_NANDCR2_TWB_SHIFT (24U)
|
|
#define SEMC_NANDCR2_TWB(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWB_SHIFT)) & SEMC_NANDCR2_TWB_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name NANDCR3 - NAND control register 3 */
|
|
/*! @{ */
|
|
#define SEMC_NANDCR3_NDOPT1_MASK (0x1U)
|
|
#define SEMC_NANDCR3_NDOPT1_SHIFT (0U)
|
|
#define SEMC_NANDCR3_NDOPT1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT1_SHIFT)) & SEMC_NANDCR3_NDOPT1_MASK)
|
|
#define SEMC_NANDCR3_NDOPT2_MASK (0x2U)
|
|
#define SEMC_NANDCR3_NDOPT2_SHIFT (1U)
|
|
#define SEMC_NANDCR3_NDOPT2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT2_SHIFT)) & SEMC_NANDCR3_NDOPT2_MASK)
|
|
#define SEMC_NANDCR3_NDOPT3_MASK (0x4U)
|
|
#define SEMC_NANDCR3_NDOPT3_SHIFT (2U)
|
|
#define SEMC_NANDCR3_NDOPT3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT3_SHIFT)) & SEMC_NANDCR3_NDOPT3_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name NORCR0 - NOR control register 0 */
|
|
/*! @{ */
|
|
#define SEMC_NORCR0_PS_MASK (0x1U)
|
|
#define SEMC_NORCR0_PS_SHIFT (0U)
|
|
/*! PS - Port Size
|
|
* 0b0..8bit
|
|
* 0b1..16bit
|
|
*/
|
|
#define SEMC_NORCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_PS_SHIFT)) & SEMC_NORCR0_PS_MASK)
|
|
#define SEMC_NORCR0_BL_MASK (0x70U)
|
|
#define SEMC_NORCR0_BL_SHIFT (4U)
|
|
/*! BL - Burst Length
|
|
* 0b000..1
|
|
* 0b001..2
|
|
* 0b010..4
|
|
* 0b011..8
|
|
* 0b100..16
|
|
* 0b101..32
|
|
* 0b110..64
|
|
* 0b111..64
|
|
*/
|
|
#define SEMC_NORCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_BL_SHIFT)) & SEMC_NORCR0_BL_MASK)
|
|
#define SEMC_NORCR0_AM_MASK (0x300U)
|
|
#define SEMC_NORCR0_AM_SHIFT (8U)
|
|
/*! AM - Address Mode
|
|
* 0b00..Address/Data MUX mode
|
|
* 0b01..Advanced Address/Data MUX mode
|
|
* 0b10..Address/Data non-MUX mode
|
|
* 0b11..Address/Data non-MUX mode
|
|
*/
|
|
#define SEMC_NORCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_AM_SHIFT)) & SEMC_NORCR0_AM_MASK)
|
|
#define SEMC_NORCR0_ADVP_MASK (0x400U)
|
|
#define SEMC_NORCR0_ADVP_SHIFT (10U)
|
|
/*! ADVP - ADV# polarity
|
|
* 0b0..ADV# is Low Active. In ASYNC mode, device sample address with ADV# rise edge; In SYNC mode, device sample address when ADV# is LOW.
|
|
* 0b1..ADV# is High Active. In ASYNC mode, device sample address with ADV# fall edge; In SYNC mode, device sample address when ADV# is HIGH.
|
|
*/
|
|
#define SEMC_NORCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVP_SHIFT)) & SEMC_NORCR0_ADVP_MASK)
|
|
#define SEMC_NORCR0_COL_MASK (0xF000U)
|
|
#define SEMC_NORCR0_COL_SHIFT (12U)
|
|
/*! COL - Column Address bit width
|
|
* 0b0000..12 Bits
|
|
* 0b0001..11 Bits
|
|
* 0b0010..10 Bits
|
|
* 0b0011..9 Bits
|
|
* 0b0100..8 Bits
|
|
* 0b0101..7 Bits
|
|
* 0b0110..6 Bits
|
|
* 0b0111..5 Bits
|
|
* 0b1000..4 Bits
|
|
* 0b1001..3 Bits
|
|
* 0b1010..2 Bits
|
|
* 0b1011..12 Bits
|
|
* 0b1100..12 Bits
|
|
* 0b1101..12 Bits
|
|
* 0b1110..12 Bits
|
|
* 0b1111..12 Bits
|
|
*/
|
|
#define SEMC_NORCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_COL_SHIFT)) & SEMC_NORCR0_COL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name NORCR1 - NOR control register 1 */
|
|
/*! @{ */
|
|
#define SEMC_NORCR1_CES_MASK (0xFU)
|
|
#define SEMC_NORCR1_CES_SHIFT (0U)
|
|
#define SEMC_NORCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CES_SHIFT)) & SEMC_NORCR1_CES_MASK)
|
|
#define SEMC_NORCR1_CEH_MASK (0xF0U)
|
|
#define SEMC_NORCR1_CEH_SHIFT (4U)
|
|
#define SEMC_NORCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CEH_SHIFT)) & SEMC_NORCR1_CEH_MASK)
|
|
#define SEMC_NORCR1_AS_MASK (0xF00U)
|
|
#define SEMC_NORCR1_AS_SHIFT (8U)
|
|
#define SEMC_NORCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AS_SHIFT)) & SEMC_NORCR1_AS_MASK)
|
|
#define SEMC_NORCR1_AH_MASK (0xF000U)
|
|
#define SEMC_NORCR1_AH_SHIFT (12U)
|
|
#define SEMC_NORCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AH_SHIFT)) & SEMC_NORCR1_AH_MASK)
|
|
#define SEMC_NORCR1_WEL_MASK (0xF0000U)
|
|
#define SEMC_NORCR1_WEL_SHIFT (16U)
|
|
#define SEMC_NORCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEL_SHIFT)) & SEMC_NORCR1_WEL_MASK)
|
|
#define SEMC_NORCR1_WEH_MASK (0xF00000U)
|
|
#define SEMC_NORCR1_WEH_SHIFT (20U)
|
|
#define SEMC_NORCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEH_SHIFT)) & SEMC_NORCR1_WEH_MASK)
|
|
#define SEMC_NORCR1_REL_MASK (0xF000000U)
|
|
#define SEMC_NORCR1_REL_SHIFT (24U)
|
|
#define SEMC_NORCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REL_SHIFT)) & SEMC_NORCR1_REL_MASK)
|
|
#define SEMC_NORCR1_REH_MASK (0xF0000000U)
|
|
#define SEMC_NORCR1_REH_SHIFT (28U)
|
|
#define SEMC_NORCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REH_SHIFT)) & SEMC_NORCR1_REH_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name NORCR2 - NOR control register 2 */
|
|
/*! @{ */
|
|
#define SEMC_NORCR2_WDS_MASK (0xFU)
|
|
#define SEMC_NORCR2_WDS_SHIFT (0U)
|
|
#define SEMC_NORCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_WDS_SHIFT)) & SEMC_NORCR2_WDS_MASK)
|
|
#define SEMC_NORCR2_WDH_MASK (0xF0U)
|
|
#define SEMC_NORCR2_WDH_SHIFT (4U)
|
|
#define SEMC_NORCR2_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_WDH_SHIFT)) & SEMC_NORCR2_WDH_MASK)
|
|
#define SEMC_NORCR2_TA_MASK (0xF00U)
|
|
#define SEMC_NORCR2_TA_SHIFT (8U)
|
|
#define SEMC_NORCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_TA_SHIFT)) & SEMC_NORCR2_TA_MASK)
|
|
#define SEMC_NORCR2_AWDH_MASK (0xF000U)
|
|
#define SEMC_NORCR2_AWDH_SHIFT (12U)
|
|
#define SEMC_NORCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_AWDH_SHIFT)) & SEMC_NORCR2_AWDH_MASK)
|
|
#define SEMC_NORCR2_LC_MASK (0xF0000U)
|
|
#define SEMC_NORCR2_LC_SHIFT (16U)
|
|
#define SEMC_NORCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_LC_SHIFT)) & SEMC_NORCR2_LC_MASK)
|
|
#define SEMC_NORCR2_RD_MASK (0xF00000U)
|
|
#define SEMC_NORCR2_RD_SHIFT (20U)
|
|
#define SEMC_NORCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RD_SHIFT)) & SEMC_NORCR2_RD_MASK)
|
|
#define SEMC_NORCR2_CEITV_MASK (0xF000000U)
|
|
#define SEMC_NORCR2_CEITV_SHIFT (24U)
|
|
#define SEMC_NORCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_CEITV_SHIFT)) & SEMC_NORCR2_CEITV_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SRAMCR0 - SRAM control register 0 */
|
|
/*! @{ */
|
|
#define SEMC_SRAMCR0_PS_MASK (0x1U)
|
|
#define SEMC_SRAMCR0_PS_SHIFT (0U)
|
|
/*! PS - Port Size
|
|
* 0b0..8bit
|
|
* 0b1..16bit
|
|
*/
|
|
#define SEMC_SRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_PS_SHIFT)) & SEMC_SRAMCR0_PS_MASK)
|
|
#define SEMC_SRAMCR0_BL_MASK (0x70U)
|
|
#define SEMC_SRAMCR0_BL_SHIFT (4U)
|
|
/*! BL - Burst Length
|
|
* 0b000..1
|
|
* 0b001..2
|
|
* 0b010..4
|
|
* 0b011..8
|
|
* 0b100..16
|
|
* 0b101..32
|
|
* 0b110..64
|
|
* 0b111..64
|
|
*/
|
|
#define SEMC_SRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_BL_SHIFT)) & SEMC_SRAMCR0_BL_MASK)
|
|
#define SEMC_SRAMCR0_AM_MASK (0x300U)
|
|
#define SEMC_SRAMCR0_AM_SHIFT (8U)
|
|
/*! AM - Address Mode
|
|
* 0b00..Address/Data MUX mode
|
|
* 0b01..Advanced Address/Data MUX mode
|
|
* 0b10..Address/Data non-MUX mode
|
|
* 0b11..Address/Data non-MUX mode
|
|
*/
|
|
#define SEMC_SRAMCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_AM_SHIFT)) & SEMC_SRAMCR0_AM_MASK)
|
|
#define SEMC_SRAMCR0_ADVP_MASK (0x400U)
|
|
#define SEMC_SRAMCR0_ADVP_SHIFT (10U)
|
|
/*! ADVP - ADV# polarity
|
|
* 0b0..ADV# is Low Active. In ASYNC mode, device sample address with ADV# rise edge; In SYNC mode, device sample address when ADV# is LOW.
|
|
* 0b1..ADV# is High Active. In ASYNC mode, device sample address with ADV# fall edge; In SYNC mode, device sample address when ADV# is HIGH.
|
|
*/
|
|
#define SEMC_SRAMCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVP_SHIFT)) & SEMC_SRAMCR0_ADVP_MASK)
|
|
#define SEMC_SRAMCR0_COL_MASK (0xF000U)
|
|
#define SEMC_SRAMCR0_COL_SHIFT (12U)
|
|
/*! COL - Column Address bit width
|
|
* 0b0000..12 Bits
|
|
* 0b0001..11 Bits
|
|
* 0b0010..10 Bits
|
|
* 0b0011..9 Bits
|
|
* 0b0100..8 Bits
|
|
* 0b0101..7 Bits
|
|
* 0b0110..6 Bits
|
|
* 0b0111..5 Bits
|
|
* 0b1000..4 Bits
|
|
* 0b1001..3 Bits
|
|
* 0b1010..2 Bits
|
|
* 0b1011..12 Bits
|
|
* 0b1100..12 Bits
|
|
* 0b1101..12 Bits
|
|
* 0b1110..12 Bits
|
|
* 0b1111..12 Bits
|
|
*/
|
|
#define SEMC_SRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_COL_SHIFT)) & SEMC_SRAMCR0_COL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SRAMCR1 - SRAM control register 1 */
|
|
/*! @{ */
|
|
#define SEMC_SRAMCR1_CES_MASK (0xFU)
|
|
#define SEMC_SRAMCR1_CES_SHIFT (0U)
|
|
#define SEMC_SRAMCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CES_SHIFT)) & SEMC_SRAMCR1_CES_MASK)
|
|
#define SEMC_SRAMCR1_CEH_MASK (0xF0U)
|
|
#define SEMC_SRAMCR1_CEH_SHIFT (4U)
|
|
#define SEMC_SRAMCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CEH_SHIFT)) & SEMC_SRAMCR1_CEH_MASK)
|
|
#define SEMC_SRAMCR1_AS_MASK (0xF00U)
|
|
#define SEMC_SRAMCR1_AS_SHIFT (8U)
|
|
#define SEMC_SRAMCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AS_SHIFT)) & SEMC_SRAMCR1_AS_MASK)
|
|
#define SEMC_SRAMCR1_AH_MASK (0xF000U)
|
|
#define SEMC_SRAMCR1_AH_SHIFT (12U)
|
|
#define SEMC_SRAMCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AH_SHIFT)) & SEMC_SRAMCR1_AH_MASK)
|
|
#define SEMC_SRAMCR1_WEL_MASK (0xF0000U)
|
|
#define SEMC_SRAMCR1_WEL_SHIFT (16U)
|
|
#define SEMC_SRAMCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEL_SHIFT)) & SEMC_SRAMCR1_WEL_MASK)
|
|
#define SEMC_SRAMCR1_WEH_MASK (0xF00000U)
|
|
#define SEMC_SRAMCR1_WEH_SHIFT (20U)
|
|
#define SEMC_SRAMCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEH_SHIFT)) & SEMC_SRAMCR1_WEH_MASK)
|
|
#define SEMC_SRAMCR1_REL_MASK (0xF000000U)
|
|
#define SEMC_SRAMCR1_REL_SHIFT (24U)
|
|
#define SEMC_SRAMCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REL_SHIFT)) & SEMC_SRAMCR1_REL_MASK)
|
|
#define SEMC_SRAMCR1_REH_MASK (0xF0000000U)
|
|
#define SEMC_SRAMCR1_REH_SHIFT (28U)
|
|
#define SEMC_SRAMCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REH_SHIFT)) & SEMC_SRAMCR1_REH_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SRAMCR2 - SRAM control register 2 */
|
|
/*! @{ */
|
|
#define SEMC_SRAMCR2_WDS_MASK (0xFU)
|
|
#define SEMC_SRAMCR2_WDS_SHIFT (0U)
|
|
#define SEMC_SRAMCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDS_SHIFT)) & SEMC_SRAMCR2_WDS_MASK)
|
|
#define SEMC_SRAMCR2_WDH_MASK (0xF0U)
|
|
#define SEMC_SRAMCR2_WDH_SHIFT (4U)
|
|
#define SEMC_SRAMCR2_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDH_SHIFT)) & SEMC_SRAMCR2_WDH_MASK)
|
|
#define SEMC_SRAMCR2_TA_MASK (0xF00U)
|
|
#define SEMC_SRAMCR2_TA_SHIFT (8U)
|
|
#define SEMC_SRAMCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_TA_SHIFT)) & SEMC_SRAMCR2_TA_MASK)
|
|
#define SEMC_SRAMCR2_AWDH_MASK (0xF000U)
|
|
#define SEMC_SRAMCR2_AWDH_SHIFT (12U)
|
|
#define SEMC_SRAMCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_AWDH_SHIFT)) & SEMC_SRAMCR2_AWDH_MASK)
|
|
#define SEMC_SRAMCR2_LC_MASK (0xF0000U)
|
|
#define SEMC_SRAMCR2_LC_SHIFT (16U)
|
|
#define SEMC_SRAMCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_LC_SHIFT)) & SEMC_SRAMCR2_LC_MASK)
|
|
#define SEMC_SRAMCR2_RD_MASK (0xF00000U)
|
|
#define SEMC_SRAMCR2_RD_SHIFT (20U)
|
|
#define SEMC_SRAMCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RD_SHIFT)) & SEMC_SRAMCR2_RD_MASK)
|
|
#define SEMC_SRAMCR2_CEITV_MASK (0xF000000U)
|
|
#define SEMC_SRAMCR2_CEITV_SHIFT (24U)
|
|
#define SEMC_SRAMCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_CEITV_SHIFT)) & SEMC_SRAMCR2_CEITV_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DBICR0 - DBI-B control register 0 */
|
|
/*! @{ */
|
|
#define SEMC_DBICR0_PS_MASK (0x1U)
|
|
#define SEMC_DBICR0_PS_SHIFT (0U)
|
|
/*! PS - Port Size
|
|
* 0b0..8bit
|
|
* 0b1..16bit
|
|
*/
|
|
#define SEMC_DBICR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK)
|
|
#define SEMC_DBICR0_BL_MASK (0x70U)
|
|
#define SEMC_DBICR0_BL_SHIFT (4U)
|
|
/*! BL - Burst Length
|
|
* 0b000..1
|
|
* 0b001..2
|
|
* 0b010..4
|
|
* 0b011..8
|
|
* 0b100..16
|
|
* 0b101..32
|
|
* 0b110..64
|
|
* 0b111..64
|
|
*/
|
|
#define SEMC_DBICR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_BL_SHIFT)) & SEMC_DBICR0_BL_MASK)
|
|
#define SEMC_DBICR0_COL_MASK (0xF000U)
|
|
#define SEMC_DBICR0_COL_SHIFT (12U)
|
|
/*! COL - Column Address bit width
|
|
* 0b0000..12 Bits
|
|
* 0b0001..11 Bits
|
|
* 0b0010..10 Bits
|
|
* 0b0011..9 Bits
|
|
* 0b0100..8 Bits
|
|
* 0b0101..7 Bits
|
|
* 0b0110..6 Bits
|
|
* 0b0111..5 Bits
|
|
* 0b1000..4 Bits
|
|
* 0b1001..3 Bits
|
|
* 0b1010..2 Bits
|
|
* 0b1011..12 Bits
|
|
* 0b1100..12 Bits
|
|
* 0b1101..12 Bits
|
|
* 0b1110..12 Bits
|
|
* 0b1111..12 Bits
|
|
*/
|
|
#define SEMC_DBICR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_COL_SHIFT)) & SEMC_DBICR0_COL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DBICR1 - DBI-B control register 1 */
|
|
/*! @{ */
|
|
#define SEMC_DBICR1_CES_MASK (0xFU)
|
|
#define SEMC_DBICR1_CES_SHIFT (0U)
|
|
#define SEMC_DBICR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CES_SHIFT)) & SEMC_DBICR1_CES_MASK)
|
|
#define SEMC_DBICR1_CEH_MASK (0xF0U)
|
|
#define SEMC_DBICR1_CEH_SHIFT (4U)
|
|
#define SEMC_DBICR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEH_SHIFT)) & SEMC_DBICR1_CEH_MASK)
|
|
#define SEMC_DBICR1_WEL_MASK (0xF00U)
|
|
#define SEMC_DBICR1_WEL_SHIFT (8U)
|
|
#define SEMC_DBICR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEL_SHIFT)) & SEMC_DBICR1_WEL_MASK)
|
|
#define SEMC_DBICR1_WEH_MASK (0xF000U)
|
|
#define SEMC_DBICR1_WEH_SHIFT (12U)
|
|
#define SEMC_DBICR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEH_SHIFT)) & SEMC_DBICR1_WEH_MASK)
|
|
#define SEMC_DBICR1_REL_MASK (0xF0000U)
|
|
#define SEMC_DBICR1_REL_SHIFT (16U)
|
|
#define SEMC_DBICR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL_SHIFT)) & SEMC_DBICR1_REL_MASK)
|
|
#define SEMC_DBICR1_REH_MASK (0xF00000U)
|
|
#define SEMC_DBICR1_REH_SHIFT (20U)
|
|
#define SEMC_DBICR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH_SHIFT)) & SEMC_DBICR1_REH_MASK)
|
|
#define SEMC_DBICR1_CEITV_MASK (0xF000000U)
|
|
#define SEMC_DBICR1_CEITV_SHIFT (24U)
|
|
#define SEMC_DBICR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEITV_SHIFT)) & SEMC_DBICR1_CEITV_MASK)
|
|
#define SEMC_DBICR1_REL2_MASK (0x30000000U)
|
|
#define SEMC_DBICR1_REL2_SHIFT (28U)
|
|
#define SEMC_DBICR1_REL2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL2_SHIFT)) & SEMC_DBICR1_REL2_MASK)
|
|
#define SEMC_DBICR1_REH2_MASK (0xC0000000U)
|
|
#define SEMC_DBICR1_REH2_SHIFT (30U)
|
|
#define SEMC_DBICR1_REH2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH2_SHIFT)) & SEMC_DBICR1_REH2_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name IPCR0 - IP Command control register 0 */
|
|
/*! @{ */
|
|
#define SEMC_IPCR0_SA_MASK (0xFFFFFFFFU)
|
|
#define SEMC_IPCR0_SA_SHIFT (0U)
|
|
#define SEMC_IPCR0_SA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR0_SA_SHIFT)) & SEMC_IPCR0_SA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name IPCR1 - IP Command control register 1 */
|
|
/*! @{ */
|
|
#define SEMC_IPCR1_DATSZ_MASK (0x7U)
|
|
#define SEMC_IPCR1_DATSZ_SHIFT (0U)
|
|
/*! DATSZ - Data Size in Byte
|
|
* 0b000..4
|
|
* 0b001..1
|
|
* 0b010..2
|
|
* 0b011..3
|
|
* 0b100..4
|
|
* 0b101..4
|
|
* 0b110..4
|
|
* 0b111..4
|
|
*/
|
|
#define SEMC_IPCR1_DATSZ(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_DATSZ_SHIFT)) & SEMC_IPCR1_DATSZ_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name IPCR2 - IP Command control register 2 */
|
|
/*! @{ */
|
|
#define SEMC_IPCR2_BM0_MASK (0x1U)
|
|
#define SEMC_IPCR2_BM0_SHIFT (0U)
|
|
/*! BM0 - Byte Mask for Byte 0 (IPTXD bit 7:0)
|
|
* 0b0..Byte Unmasked
|
|
* 0b1..Byte Masked
|
|
*/
|
|
#define SEMC_IPCR2_BM0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM0_SHIFT)) & SEMC_IPCR2_BM0_MASK)
|
|
#define SEMC_IPCR2_BM1_MASK (0x2U)
|
|
#define SEMC_IPCR2_BM1_SHIFT (1U)
|
|
/*! BM1 - Byte Mask for Byte 1 (IPTXD bit 15:8)
|
|
* 0b0..Byte Unmasked
|
|
* 0b1..Byte Masked
|
|
*/
|
|
#define SEMC_IPCR2_BM1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM1_SHIFT)) & SEMC_IPCR2_BM1_MASK)
|
|
#define SEMC_IPCR2_BM2_MASK (0x4U)
|
|
#define SEMC_IPCR2_BM2_SHIFT (2U)
|
|
/*! BM2 - Byte Mask for Byte 2 (IPTXD bit 23:16)
|
|
* 0b0..Byte Unmasked
|
|
* 0b1..Byte Masked
|
|
*/
|
|
#define SEMC_IPCR2_BM2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM2_SHIFT)) & SEMC_IPCR2_BM2_MASK)
|
|
#define SEMC_IPCR2_BM3_MASK (0x8U)
|
|
#define SEMC_IPCR2_BM3_SHIFT (3U)
|
|
/*! BM3 - Byte Mask for Byte 3 (IPTXD bit 31:24)
|
|
* 0b0..Byte Unmasked
|
|
* 0b1..Byte Masked
|
|
*/
|
|
#define SEMC_IPCR2_BM3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name IPCMD - IP Command register */
|
|
/*! @{ */
|
|
#define SEMC_IPCMD_CMD_MASK (0xFFFFU)
|
|
#define SEMC_IPCMD_CMD_SHIFT (0U)
|
|
#define SEMC_IPCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_CMD_SHIFT)) & SEMC_IPCMD_CMD_MASK)
|
|
#define SEMC_IPCMD_KEY_MASK (0xFFFF0000U)
|
|
#define SEMC_IPCMD_KEY_SHIFT (16U)
|
|
#define SEMC_IPCMD_KEY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_KEY_SHIFT)) & SEMC_IPCMD_KEY_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name IPTXDAT - TX DATA register (for IP Command) */
|
|
/*! @{ */
|
|
#define SEMC_IPTXDAT_DAT_MASK (0xFFFFFFFFU)
|
|
#define SEMC_IPTXDAT_DAT_SHIFT (0U)
|
|
#define SEMC_IPTXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPTXDAT_DAT_SHIFT)) & SEMC_IPTXDAT_DAT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name IPRXDAT - RX DATA register (for IP Command) */
|
|
/*! @{ */
|
|
#define SEMC_IPRXDAT_DAT_MASK (0xFFFFFFFFU)
|
|
#define SEMC_IPRXDAT_DAT_SHIFT (0U)
|
|
#define SEMC_IPRXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPRXDAT_DAT_SHIFT)) & SEMC_IPRXDAT_DAT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name STS0 - Status register 0 */
|
|
/*! @{ */
|
|
#define SEMC_STS0_IDLE_MASK (0x1U)
|
|
#define SEMC_STS0_IDLE_SHIFT (0U)
|
|
#define SEMC_STS0_IDLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK)
|
|
#define SEMC_STS0_NARDY_MASK (0x2U)
|
|
#define SEMC_STS0_NARDY_SHIFT (1U)
|
|
/*! NARDY - Indicating NAND device Ready/WAIT# pin level.
|
|
* 0b0..NAND device is not ready
|
|
* 0b1..NAND device is ready
|
|
*/
|
|
#define SEMC_STS0_NARDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name STS2 - Status register 2 */
|
|
/*! @{ */
|
|
#define SEMC_STS2_NDWRPEND_MASK (0x8U)
|
|
#define SEMC_STS2_NDWRPEND_SHIFT (3U)
|
|
/*! NDWRPEND - This field indicating whether there is pending AXI command (write) to NAND device.
|
|
* 0b0..No pending
|
|
* 0b1..Pending
|
|
*/
|
|
#define SEMC_STS2_NDWRPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name STS12 - Status register 12 */
|
|
/*! @{ */
|
|
#define SEMC_STS12_NDADDR_MASK (0xFFFFFFFFU)
|
|
#define SEMC_STS12_NDADDR_SHIFT (0U)
|
|
#define SEMC_STS12_NDADDR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS12_NDADDR_SHIFT)) & SEMC_STS12_NDADDR_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group SEMC_Register_Masks */
|
|
|
|
|
|
/* SEMC - Peripheral instance base addresses */
|
|
/** Peripheral SEMC base address */
|
|
#define SEMC_BASE (0x402F0000u)
|
|
/** Peripheral SEMC base pointer */
|
|
#define SEMC ((SEMC_Type *)SEMC_BASE)
|
|
/** Array initializer of SEMC peripheral base addresses */
|
|
#define SEMC_BASE_ADDRS { SEMC_BASE }
|
|
/** Array initializer of SEMC peripheral base pointers */
|
|
#define SEMC_BASE_PTRS { SEMC }
|
|
/** Interrupt vectors for the SEMC peripheral type */
|
|
#define SEMC_IRQS { SEMC_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group SEMC_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- SNVS Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup SNVS_Peripheral_Access_Layer SNVS Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** SNVS - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t HPLR; /**< SNVS_HP Lock Register, offset: 0x0 */
|
|
__IO uint32_t HPCOMR; /**< SNVS_HP Command Register, offset: 0x4 */
|
|
__IO uint32_t HPCR; /**< SNVS_HP Control Register, offset: 0x8 */
|
|
__IO uint32_t HPSICR; /**< SNVS_HP Security Interrupt Control Register, offset: 0xC */
|
|
__IO uint32_t HPSVCR; /**< SNVS_HP Security Violation Control Register, offset: 0x10 */
|
|
__IO uint32_t HPSR; /**< SNVS_HP Status Register, offset: 0x14 */
|
|
__IO uint32_t HPSVSR; /**< SNVS_HP Security Violation Status Register, offset: 0x18 */
|
|
__IO uint32_t HPHACIVR; /**< SNVS_HP High Assurance Counter IV Register, offset: 0x1C */
|
|
__I uint32_t HPHACR; /**< SNVS_HP High Assurance Counter Register, offset: 0x20 */
|
|
__IO uint32_t HPRTCMR; /**< SNVS_HP Real Time Counter MSB Register, offset: 0x24 */
|
|
__IO uint32_t HPRTCLR; /**< SNVS_HP Real Time Counter LSB Register, offset: 0x28 */
|
|
__IO uint32_t HPTAMR; /**< SNVS_HP Time Alarm MSB Register, offset: 0x2C */
|
|
__IO uint32_t HPTALR; /**< SNVS_HP Time Alarm LSB Register, offset: 0x30 */
|
|
__IO uint32_t LPLR; /**< SNVS_LP Lock Register, offset: 0x34 */
|
|
__IO uint32_t LPCR; /**< SNVS_LP Control Register, offset: 0x38 */
|
|
__IO uint32_t LPMKCR; /**< SNVS_LP Master Key Control Register, offset: 0x3C */
|
|
__IO uint32_t LPSVCR; /**< SNVS_LP Security Violation Control Register, offset: 0x40 */
|
|
uint8_t RESERVED_0[4];
|
|
__IO uint32_t LPTDCR; /**< SNVS_LP Tamper Detectors Configuration Register, offset: 0x48 */
|
|
__IO uint32_t LPSR; /**< SNVS_LP Status Register, offset: 0x4C */
|
|
__IO uint32_t LPSRTCMR; /**< SNVS_LP Secure Real Time Counter MSB Register, offset: 0x50 */
|
|
__IO uint32_t LPSRTCLR; /**< SNVS_LP Secure Real Time Counter LSB Register, offset: 0x54 */
|
|
__IO uint32_t LPTAR; /**< SNVS_LP Time Alarm Register, offset: 0x58 */
|
|
__I uint32_t LPSMCMR; /**< SNVS_LP Secure Monotonic Counter MSB Register, offset: 0x5C */
|
|
__I uint32_t LPSMCLR; /**< SNVS_LP Secure Monotonic Counter LSB Register, offset: 0x60 */
|
|
__IO uint32_t LPPGDR; /**< SNVS_LP Power Glitch Detector Register, offset: 0x64 */
|
|
__IO uint32_t LPGPR0_LEGACY_ALIAS; /**< SNVS_LP General Purpose Register 0 (legacy alias), offset: 0x68 */
|
|
__IO uint32_t LPZMKR[8]; /**< SNVS_LP Zeroizable Master Key Register, array offset: 0x6C, array step: 0x4 */
|
|
uint8_t RESERVED_1[4];
|
|
__IO uint32_t LPGPR_ALIAS[4]; /**< SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x90, array step: 0x4 */
|
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uint8_t RESERVED_2[96];
|
|
__IO uint32_t LPGPR[8]; /**< SNVS_LP General Purpose Registers 0 .. 7, array offset: 0x100, array step: 0x4 */
|
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uint8_t RESERVED_3[2776];
|
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__I uint32_t HPVIDR1; /**< SNVS_HP Version ID Register 1, offset: 0xBF8 */
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__I uint32_t HPVIDR2; /**< SNVS_HP Version ID Register 2, offset: 0xBFC */
|
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} SNVS_Type;
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|
|
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/* ----------------------------------------------------------------------------
|
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-- SNVS Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
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* @addtogroup SNVS_Register_Masks SNVS Register Masks
|
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* @{
|
|
*/
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|
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/*! @name HPLR - SNVS_HP Lock Register */
|
|
/*! @{ */
|
|
#define SNVS_HPLR_ZMK_WSL_MASK (0x1U)
|
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#define SNVS_HPLR_ZMK_WSL_SHIFT (0U)
|
|
/*! ZMK_WSL
|
|
* 0b0..Write access is allowed
|
|
* 0b1..Write access is not allowed
|
|
*/
|
|
#define SNVS_HPLR_ZMK_WSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK)
|
|
#define SNVS_HPLR_ZMK_RSL_MASK (0x2U)
|
|
#define SNVS_HPLR_ZMK_RSL_SHIFT (1U)
|
|
/*! ZMK_RSL
|
|
* 0b0..Read access is allowed (only in software Programming mode)
|
|
* 0b1..Read access is not allowed
|
|
*/
|
|
#define SNVS_HPLR_ZMK_RSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK)
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#define SNVS_HPLR_SRTC_SL_MASK (0x4U)
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#define SNVS_HPLR_SRTC_SL_SHIFT (2U)
|
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/*! SRTC_SL
|
|
* 0b0..Write access is allowed
|
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* 0b1..Write access is not allowed
|
|
*/
|
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#define SNVS_HPLR_SRTC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK)
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#define SNVS_HPLR_LPCALB_SL_MASK (0x8U)
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#define SNVS_HPLR_LPCALB_SL_SHIFT (3U)
|
|
/*! LPCALB_SL
|
|
* 0b0..Write access is allowed
|
|
* 0b1..Write access is not allowed
|
|
*/
|
|
#define SNVS_HPLR_LPCALB_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK)
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#define SNVS_HPLR_MC_SL_MASK (0x10U)
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#define SNVS_HPLR_MC_SL_SHIFT (4U)
|
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/*! MC_SL
|
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* 0b0..Write access (increment) is allowed
|
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* 0b1..Write access (increment) is not allowed
|
|
*/
|
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#define SNVS_HPLR_MC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK)
|
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#define SNVS_HPLR_GPR_SL_MASK (0x20U)
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#define SNVS_HPLR_GPR_SL_SHIFT (5U)
|
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/*! GPR_SL
|
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* 0b0..Write access is allowed
|
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* 0b1..Write access is not allowed
|
|
*/
|
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#define SNVS_HPLR_GPR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK)
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#define SNVS_HPLR_LPSVCR_SL_MASK (0x40U)
|
|
#define SNVS_HPLR_LPSVCR_SL_SHIFT (6U)
|
|
/*! LPSVCR_SL
|
|
* 0b0..Write access is allowed
|
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* 0b1..Write access is not allowed
|
|
*/
|
|
#define SNVS_HPLR_LPSVCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK)
|
|
#define SNVS_HPLR_LPTDCR_SL_MASK (0x100U)
|
|
#define SNVS_HPLR_LPTDCR_SL_SHIFT (8U)
|
|
/*! LPTDCR_SL
|
|
* 0b0..Write access is allowed
|
|
* 0b1..Write access is not allowed
|
|
*/
|
|
#define SNVS_HPLR_LPTDCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPTDCR_SL_SHIFT)) & SNVS_HPLR_LPTDCR_SL_MASK)
|
|
#define SNVS_HPLR_MKS_SL_MASK (0x200U)
|
|
#define SNVS_HPLR_MKS_SL_SHIFT (9U)
|
|
/*! MKS_SL
|
|
* 0b0..Write access is allowed
|
|
* 0b1..Write access is not allowed
|
|
*/
|
|
#define SNVS_HPLR_MKS_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK)
|
|
#define SNVS_HPLR_HPSVCR_L_MASK (0x10000U)
|
|
#define SNVS_HPLR_HPSVCR_L_SHIFT (16U)
|
|
/*! HPSVCR_L
|
|
* 0b0..Write access is allowed
|
|
* 0b1..Write access is not allowed
|
|
*/
|
|
#define SNVS_HPLR_HPSVCR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK)
|
|
#define SNVS_HPLR_HPSICR_L_MASK (0x20000U)
|
|
#define SNVS_HPLR_HPSICR_L_SHIFT (17U)
|
|
/*! HPSICR_L
|
|
* 0b0..Write access is allowed
|
|
* 0b1..Write access is not allowed
|
|
*/
|
|
#define SNVS_HPLR_HPSICR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK)
|
|
#define SNVS_HPLR_HAC_L_MASK (0x40000U)
|
|
#define SNVS_HPLR_HAC_L_SHIFT (18U)
|
|
/*! HAC_L
|
|
* 0b0..Write access is allowed
|
|
* 0b1..Write access is not allowed
|
|
*/
|
|
#define SNVS_HPLR_HAC_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name HPCOMR - SNVS_HP Command Register */
|
|
/*! @{ */
|
|
#define SNVS_HPCOMR_SSM_ST_MASK (0x1U)
|
|
#define SNVS_HPCOMR_SSM_ST_SHIFT (0U)
|
|
#define SNVS_HPCOMR_SSM_ST(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK)
|
|
#define SNVS_HPCOMR_SSM_ST_DIS_MASK (0x2U)
|
|
#define SNVS_HPCOMR_SSM_ST_DIS_SHIFT (1U)
|
|
/*! SSM_ST_DIS
|
|
* 0b0..Secure to Trusted State transition is enabled
|
|
* 0b1..Secure to Trusted State transition is disabled
|
|
*/
|
|
#define SNVS_HPCOMR_SSM_ST_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK)
|
|
#define SNVS_HPCOMR_SSM_SFNS_DIS_MASK (0x4U)
|
|
#define SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT (2U)
|
|
/*! SSM_SFNS_DIS
|
|
* 0b0..Soft Fail to Non-Secure State transition is enabled
|
|
* 0b1..Soft Fail to Non-Secure State transition is disabled
|
|
*/
|
|
#define SNVS_HPCOMR_SSM_SFNS_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK)
|
|
#define SNVS_HPCOMR_LP_SWR_MASK (0x10U)
|
|
#define SNVS_HPCOMR_LP_SWR_SHIFT (4U)
|
|
/*! LP_SWR
|
|
* 0b0..No Action
|
|
* 0b1..Reset LP section
|
|
*/
|
|
#define SNVS_HPCOMR_LP_SWR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK)
|
|
#define SNVS_HPCOMR_LP_SWR_DIS_MASK (0x20U)
|
|
#define SNVS_HPCOMR_LP_SWR_DIS_SHIFT (5U)
|
|
/*! LP_SWR_DIS
|
|
* 0b0..LP software reset is enabled
|
|
* 0b1..LP software reset is disabled
|
|
*/
|
|
#define SNVS_HPCOMR_LP_SWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK)
|
|
#define SNVS_HPCOMR_SW_SV_MASK (0x100U)
|
|
#define SNVS_HPCOMR_SW_SV_SHIFT (8U)
|
|
#define SNVS_HPCOMR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_SV_SHIFT)) & SNVS_HPCOMR_SW_SV_MASK)
|
|
#define SNVS_HPCOMR_SW_FSV_MASK (0x200U)
|
|
#define SNVS_HPCOMR_SW_FSV_SHIFT (9U)
|
|
#define SNVS_HPCOMR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_FSV_SHIFT)) & SNVS_HPCOMR_SW_FSV_MASK)
|
|
#define SNVS_HPCOMR_SW_LPSV_MASK (0x400U)
|
|
#define SNVS_HPCOMR_SW_LPSV_SHIFT (10U)
|
|
#define SNVS_HPCOMR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_LPSV_SHIFT)) & SNVS_HPCOMR_SW_LPSV_MASK)
|
|
#define SNVS_HPCOMR_PROG_ZMK_MASK (0x1000U)
|
|
#define SNVS_HPCOMR_PROG_ZMK_SHIFT (12U)
|
|
/*! PROG_ZMK
|
|
* 0b0..No Action
|
|
* 0b1..Activate hardware key programming mechanism
|
|
*/
|
|
#define SNVS_HPCOMR_PROG_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK)
|
|
#define SNVS_HPCOMR_MKS_EN_MASK (0x2000U)
|
|
#define SNVS_HPCOMR_MKS_EN_SHIFT (13U)
|
|
/*! MKS_EN
|
|
* 0b0..OTP master key is selected as an SNVS master key
|
|
* 0b1..SNVS master key is selected according to the setting of the MASTER_KEY_SEL field of LPMKCR
|
|
*/
|
|
#define SNVS_HPCOMR_MKS_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK)
|
|
#define SNVS_HPCOMR_HAC_EN_MASK (0x10000U)
|
|
#define SNVS_HPCOMR_HAC_EN_SHIFT (16U)
|
|
/*! HAC_EN
|
|
* 0b0..High Assurance Counter is disabled
|
|
* 0b1..High Assurance Counter is enabled
|
|
*/
|
|
#define SNVS_HPCOMR_HAC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK)
|
|
#define SNVS_HPCOMR_HAC_LOAD_MASK (0x20000U)
|
|
#define SNVS_HPCOMR_HAC_LOAD_SHIFT (17U)
|
|
/*! HAC_LOAD
|
|
* 0b0..No Action
|
|
* 0b1..Load the HAC
|
|
*/
|
|
#define SNVS_HPCOMR_HAC_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK)
|
|
#define SNVS_HPCOMR_HAC_CLEAR_MASK (0x40000U)
|
|
#define SNVS_HPCOMR_HAC_CLEAR_SHIFT (18U)
|
|
/*! HAC_CLEAR
|
|
* 0b0..No Action
|
|
* 0b1..Clear the HAC
|
|
*/
|
|
#define SNVS_HPCOMR_HAC_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK)
|
|
#define SNVS_HPCOMR_HAC_STOP_MASK (0x80000U)
|
|
#define SNVS_HPCOMR_HAC_STOP_SHIFT (19U)
|
|
#define SNVS_HPCOMR_HAC_STOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_STOP_SHIFT)) & SNVS_HPCOMR_HAC_STOP_MASK)
|
|
#define SNVS_HPCOMR_NPSWA_EN_MASK (0x80000000U)
|
|
#define SNVS_HPCOMR_NPSWA_EN_SHIFT (31U)
|
|
#define SNVS_HPCOMR_NPSWA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name HPCR - SNVS_HP Control Register */
|
|
/*! @{ */
|
|
#define SNVS_HPCR_RTC_EN_MASK (0x1U)
|
|
#define SNVS_HPCR_RTC_EN_SHIFT (0U)
|
|
/*! RTC_EN
|
|
* 0b0..RTC is disabled
|
|
* 0b1..RTC is enabled
|
|
*/
|
|
#define SNVS_HPCR_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK)
|
|
#define SNVS_HPCR_HPTA_EN_MASK (0x2U)
|
|
#define SNVS_HPCR_HPTA_EN_SHIFT (1U)
|
|
/*! HPTA_EN
|
|
* 0b0..HP Time Alarm Interrupt is disabled
|
|
* 0b1..HP Time Alarm Interrupt is enabled
|
|
*/
|
|
#define SNVS_HPCR_HPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK)
|
|
#define SNVS_HPCR_DIS_PI_MASK (0x4U)
|
|
#define SNVS_HPCR_DIS_PI_SHIFT (2U)
|
|
/*! DIS_PI
|
|
* 0b0..Periodic interrupt will trigger a functional interrupt
|
|
* 0b1..Disable periodic interrupt in the function interrupt
|
|
*/
|
|
#define SNVS_HPCR_DIS_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
|
|
#define SNVS_HPCR_PI_EN_MASK (0x8U)
|
|
#define SNVS_HPCR_PI_EN_SHIFT (3U)
|
|
/*! PI_EN
|
|
* 0b0..HP Periodic Interrupt is disabled
|
|
* 0b1..HP Periodic Interrupt is enabled
|
|
*/
|
|
#define SNVS_HPCR_PI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK)
|
|
#define SNVS_HPCR_PI_FREQ_MASK (0xF0U)
|
|
#define SNVS_HPCR_PI_FREQ_SHIFT (4U)
|
|
/*! PI_FREQ
|
|
* 0b0000..- bit 0 of the HPRTCLR is selected as a source of the periodic interrupt
|
|
* 0b0001..- bit 1 of the HPRTCLR is selected as a source of the periodic interrupt
|
|
* 0b0010..- bit 2 of the HPRTCLR is selected as a source of the periodic interrupt
|
|
* 0b0011..- bit 3 of the HPRTCLR is selected as a source of the periodic interrupt
|
|
* 0b0100..- bit 4 of the HPRTCLR is selected as a source of the periodic interrupt
|
|
* 0b0101..- bit 5 of the HPRTCLR is selected as a source of the periodic interrupt
|
|
* 0b0110..- bit 6 of the HPRTCLR is selected as a source of the periodic interrupt
|
|
* 0b0111..- bit 7 of the HPRTCLR is selected as a source of the periodic interrupt
|
|
* 0b1000..- bit 8 of the HPRTCLR is selected as a source of the periodic interrupt
|
|
* 0b1001..- bit 9 of the HPRTCLR is selected as a source of the periodic interrupt
|
|
* 0b1010..- bit 10 of the HPRTCLR is selected as a source of the periodic interrupt
|
|
* 0b1011..- bit 11 of the HPRTCLR is selected as a source of the periodic interrupt
|
|
* 0b1100..- bit 12 of the HPRTCLR is selected as a source of the periodic interrupt
|
|
* 0b1101..- bit 13 of the HPRTCLR is selected as a source of the periodic interrupt
|
|
* 0b1110..- bit 14 of the HPRTCLR is selected as a source of the periodic interrupt
|
|
* 0b1111..- bit 15 of the HPRTCLR is selected as a source of the periodic interrupt
|
|
*/
|
|
#define SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK)
|
|
#define SNVS_HPCR_HPCALB_EN_MASK (0x100U)
|
|
#define SNVS_HPCR_HPCALB_EN_SHIFT (8U)
|
|
/*! HPCALB_EN
|
|
* 0b0..HP Timer calibration disabled
|
|
* 0b1..HP Timer calibration enabled
|
|
*/
|
|
#define SNVS_HPCR_HPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK)
|
|
#define SNVS_HPCR_HPCALB_VAL_MASK (0x7C00U)
|
|
#define SNVS_HPCR_HPCALB_VAL_SHIFT (10U)
|
|
/*! HPCALB_VAL
|
|
* 0b00000..+0 counts per each 32768 ticks of the counter
|
|
* 0b00001..+1 counts per each 32768 ticks of the counter
|
|
* 0b00010..+2 counts per each 32768 ticks of the counter
|
|
* 0b01111..+15 counts per each 32768 ticks of the counter
|
|
* 0b10000..-16 counts per each 32768 ticks of the counter
|
|
* 0b10001..-15 counts per each 32768 ticks of the counter
|
|
* 0b11110..-2 counts per each 32768 ticks of the counter
|
|
* 0b11111..-1 counts per each 32768 ticks of the counter
|
|
*/
|
|
#define SNVS_HPCR_HPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK)
|
|
#define SNVS_HPCR_HP_TS_MASK (0x10000U)
|
|
#define SNVS_HPCR_HP_TS_SHIFT (16U)
|
|
/*! HP_TS
|
|
* 0b0..No Action
|
|
* 0b1..Synchronize the HP Time Counter to the LP Time Counter
|
|
*/
|
|
#define SNVS_HPCR_HP_TS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK)
|
|
#define SNVS_HPCR_BTN_CONFIG_MASK (0x7000000U)
|
|
#define SNVS_HPCR_BTN_CONFIG_SHIFT (24U)
|
|
#define SNVS_HPCR_BTN_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK)
|
|
#define SNVS_HPCR_BTN_MASK_MASK (0x8000000U)
|
|
#define SNVS_HPCR_BTN_MASK_SHIFT (27U)
|
|
#define SNVS_HPCR_BTN_MASK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name HPSICR - SNVS_HP Security Interrupt Control Register */
|
|
/*! @{ */
|
|
#define SNVS_HPSICR_SV0_EN_MASK (0x1U)
|
|
#define SNVS_HPSICR_SV0_EN_SHIFT (0U)
|
|
/*! SV0_EN
|
|
* 0b0..Security Violation 0 Interrupt is Disabled
|
|
* 0b1..Security Violation 0 Interrupt is Enabled
|
|
*/
|
|
#define SNVS_HPSICR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV0_EN_SHIFT)) & SNVS_HPSICR_SV0_EN_MASK)
|
|
#define SNVS_HPSICR_SV1_EN_MASK (0x2U)
|
|
#define SNVS_HPSICR_SV1_EN_SHIFT (1U)
|
|
/*! SV1_EN
|
|
* 0b0..Security Violation 1 Interrupt is Disabled
|
|
* 0b1..Security Violation 1 Interrupt is Enabled
|
|
*/
|
|
#define SNVS_HPSICR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV1_EN_SHIFT)) & SNVS_HPSICR_SV1_EN_MASK)
|
|
#define SNVS_HPSICR_SV2_EN_MASK (0x4U)
|
|
#define SNVS_HPSICR_SV2_EN_SHIFT (2U)
|
|
/*! SV2_EN
|
|
* 0b0..Security Violation 2 Interrupt is Disabled
|
|
* 0b1..Security Violation 2 Interrupt is Enabled
|
|
*/
|
|
#define SNVS_HPSICR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV2_EN_SHIFT)) & SNVS_HPSICR_SV2_EN_MASK)
|
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#define SNVS_HPSICR_SV3_EN_MASK (0x8U)
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#define SNVS_HPSICR_SV3_EN_SHIFT (3U)
|
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/*! SV3_EN
|
|
* 0b0..Security Violation 3 Interrupt is Disabled
|
|
* 0b1..Security Violation 3 Interrupt is Enabled
|
|
*/
|
|
#define SNVS_HPSICR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV3_EN_SHIFT)) & SNVS_HPSICR_SV3_EN_MASK)
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#define SNVS_HPSICR_SV4_EN_MASK (0x10U)
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#define SNVS_HPSICR_SV4_EN_SHIFT (4U)
|
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/*! SV4_EN
|
|
* 0b0..Security Violation 4 Interrupt is Disabled
|
|
* 0b1..Security Violation 4 Interrupt is Enabled
|
|
*/
|
|
#define SNVS_HPSICR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV4_EN_SHIFT)) & SNVS_HPSICR_SV4_EN_MASK)
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#define SNVS_HPSICR_SV5_EN_MASK (0x20U)
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#define SNVS_HPSICR_SV5_EN_SHIFT (5U)
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/*! SV5_EN
|
|
* 0b0..Security Violation 5 Interrupt is Disabled
|
|
* 0b1..Security Violation 5 Interrupt is Enabled
|
|
*/
|
|
#define SNVS_HPSICR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV5_EN_SHIFT)) & SNVS_HPSICR_SV5_EN_MASK)
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#define SNVS_HPSICR_LPSVI_EN_MASK (0x80000000U)
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#define SNVS_HPSICR_LPSVI_EN_SHIFT (31U)
|
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/*! LPSVI_EN
|
|
* 0b0..LP Security Violation Interrupt is Disabled
|
|
* 0b1..LP Security Violation Interrupt is Enabled
|
|
*/
|
|
#define SNVS_HPSICR_LPSVI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK)
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/*! @} */
|
|
|
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/*! @name HPSVCR - SNVS_HP Security Violation Control Register */
|
|
/*! @{ */
|
|
#define SNVS_HPSVCR_SV0_CFG_MASK (0x1U)
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#define SNVS_HPSVCR_SV0_CFG_SHIFT (0U)
|
|
/*! SV0_CFG
|
|
* 0b0..Security Violation 0 is a non-fatal violation
|
|
* 0b1..Security Violation 0 is a fatal violation
|
|
*/
|
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#define SNVS_HPSVCR_SV0_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV0_CFG_SHIFT)) & SNVS_HPSVCR_SV0_CFG_MASK)
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#define SNVS_HPSVCR_SV1_CFG_MASK (0x2U)
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#define SNVS_HPSVCR_SV1_CFG_SHIFT (1U)
|
|
/*! SV1_CFG
|
|
* 0b0..Security Violation 1 is a non-fatal violation
|
|
* 0b1..Security Violation 1 is a fatal violation
|
|
*/
|
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#define SNVS_HPSVCR_SV1_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV1_CFG_SHIFT)) & SNVS_HPSVCR_SV1_CFG_MASK)
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#define SNVS_HPSVCR_SV2_CFG_MASK (0x4U)
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#define SNVS_HPSVCR_SV2_CFG_SHIFT (2U)
|
|
/*! SV2_CFG
|
|
* 0b0..Security Violation 2 is a non-fatal violation
|
|
* 0b1..Security Violation 2 is a fatal violation
|
|
*/
|
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#define SNVS_HPSVCR_SV2_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV2_CFG_SHIFT)) & SNVS_HPSVCR_SV2_CFG_MASK)
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#define SNVS_HPSVCR_SV3_CFG_MASK (0x8U)
|
|
#define SNVS_HPSVCR_SV3_CFG_SHIFT (3U)
|
|
/*! SV3_CFG
|
|
* 0b0..Security Violation 3 is a non-fatal violation
|
|
* 0b1..Security Violation 3 is a fatal violation
|
|
*/
|
|
#define SNVS_HPSVCR_SV3_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV3_CFG_SHIFT)) & SNVS_HPSVCR_SV3_CFG_MASK)
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#define SNVS_HPSVCR_SV4_CFG_MASK (0x10U)
|
|
#define SNVS_HPSVCR_SV4_CFG_SHIFT (4U)
|
|
/*! SV4_CFG
|
|
* 0b0..Security Violation 4 is a non-fatal violation
|
|
* 0b1..Security Violation 4 is a fatal violation
|
|
*/
|
|
#define SNVS_HPSVCR_SV4_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV4_CFG_SHIFT)) & SNVS_HPSVCR_SV4_CFG_MASK)
|
|
#define SNVS_HPSVCR_SV5_CFG_MASK (0x60U)
|
|
#define SNVS_HPSVCR_SV5_CFG_SHIFT (5U)
|
|
/*! SV5_CFG
|
|
* 0b00..Security Violation 5 is disabled
|
|
* 0b01..Security Violation 5 is a non-fatal violation
|
|
* 0b1x..Security Violation 5 is a fatal violation
|
|
*/
|
|
#define SNVS_HPSVCR_SV5_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV5_CFG_SHIFT)) & SNVS_HPSVCR_SV5_CFG_MASK)
|
|
#define SNVS_HPSVCR_LPSV_CFG_MASK (0xC0000000U)
|
|
#define SNVS_HPSVCR_LPSV_CFG_SHIFT (30U)
|
|
/*! LPSV_CFG
|
|
* 0b00..LP security violation is disabled
|
|
* 0b01..LP security violation is a non-fatal violation
|
|
* 0b1x..LP security violation is a fatal violation
|
|
*/
|
|
#define SNVS_HPSVCR_LPSV_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name HPSR - SNVS_HP Status Register */
|
|
/*! @{ */
|
|
#define SNVS_HPSR_HPTA_MASK (0x1U)
|
|
#define SNVS_HPSR_HPTA_SHIFT (0U)
|
|
/*! HPTA
|
|
* 0b0..No time alarm interrupt occurred.
|
|
* 0b1..A time alarm interrupt occurred.
|
|
*/
|
|
#define SNVS_HPSR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK)
|
|
#define SNVS_HPSR_PI_MASK (0x2U)
|
|
#define SNVS_HPSR_PI_SHIFT (1U)
|
|
/*! PI
|
|
* 0b0..No periodic interrupt occurred.
|
|
* 0b1..A periodic interrupt occurred.
|
|
*/
|
|
#define SNVS_HPSR_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK)
|
|
#define SNVS_HPSR_LPDIS_MASK (0x10U)
|
|
#define SNVS_HPSR_LPDIS_SHIFT (4U)
|
|
#define SNVS_HPSR_LPDIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_LPDIS_SHIFT)) & SNVS_HPSR_LPDIS_MASK)
|
|
#define SNVS_HPSR_BTN_MASK (0x40U)
|
|
#define SNVS_HPSR_BTN_SHIFT (6U)
|
|
#define SNVS_HPSR_BTN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK)
|
|
#define SNVS_HPSR_BI_MASK (0x80U)
|
|
#define SNVS_HPSR_BI_SHIFT (7U)
|
|
#define SNVS_HPSR_BI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK)
|
|
#define SNVS_HPSR_SSM_STATE_MASK (0xF00U)
|
|
#define SNVS_HPSR_SSM_STATE_SHIFT (8U)
|
|
/*! SSM_STATE
|
|
* 0b0000..Init
|
|
* 0b0001..Hard Fail
|
|
* 0b0011..Soft Fail
|
|
* 0b1000..Init Intermediate (transition state between Init and Check - SSM stays in this state only one clock cycle)
|
|
* 0b1001..Check
|
|
* 0b1011..Non-Secure
|
|
* 0b1101..Trusted
|
|
* 0b1111..Secure
|
|
*/
|
|
#define SNVS_HPSR_SSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK)
|
|
#define SNVS_HPSR_SECURITY_CONFIG_MASK (0xF000U)
|
|
#define SNVS_HPSR_SECURITY_CONFIG_SHIFT (12U)
|
|
/*! SECURITY_CONFIG
|
|
* 0b0000, 0b1000..FAB configuration
|
|
* 0b0001, 0b0010, 0b0011..OPEN configuration
|
|
* 0b1010, 0b1001, 0b1011..CLOSED configuration
|
|
* 0bx1xx..FIELD RETURN configuration
|
|
*/
|
|
#define SNVS_HPSR_SECURITY_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SECURITY_CONFIG_SHIFT)) & SNVS_HPSR_SECURITY_CONFIG_MASK)
|
|
#define SNVS_HPSR_OTPMK_SYNDROME_MASK (0x1FF0000U)
|
|
#define SNVS_HPSR_OTPMK_SYNDROME_SHIFT (16U)
|
|
#define SNVS_HPSR_OTPMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_SYNDROME_SHIFT)) & SNVS_HPSR_OTPMK_SYNDROME_MASK)
|
|
#define SNVS_HPSR_OTPMK_ZERO_MASK (0x8000000U)
|
|
#define SNVS_HPSR_OTPMK_ZERO_SHIFT (27U)
|
|
/*! OTPMK_ZERO
|
|
* 0b0..The OTPMK is not zero.
|
|
* 0b1..The OTPMK is zero.
|
|
*/
|
|
#define SNVS_HPSR_OTPMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK)
|
|
#define SNVS_HPSR_ZMK_ZERO_MASK (0x80000000U)
|
|
#define SNVS_HPSR_ZMK_ZERO_SHIFT (31U)
|
|
/*! ZMK_ZERO
|
|
* 0b0..The ZMK is not zero.
|
|
* 0b1..The ZMK is zero.
|
|
*/
|
|
#define SNVS_HPSR_ZMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name HPSVSR - SNVS_HP Security Violation Status Register */
|
|
/*! @{ */
|
|
#define SNVS_HPSVSR_SV0_MASK (0x1U)
|
|
#define SNVS_HPSVSR_SV0_SHIFT (0U)
|
|
/*! SV0
|
|
* 0b0..No Security Violation 0 security violation was detected.
|
|
* 0b1..Security Violation 0 security violation was detected.
|
|
*/
|
|
#define SNVS_HPSVSR_SV0(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV0_SHIFT)) & SNVS_HPSVSR_SV0_MASK)
|
|
#define SNVS_HPSVSR_SV1_MASK (0x2U)
|
|
#define SNVS_HPSVSR_SV1_SHIFT (1U)
|
|
/*! SV1
|
|
* 0b0..No Security Violation 1 security violation was detected.
|
|
* 0b1..Security Violation 1 security violation was detected.
|
|
*/
|
|
#define SNVS_HPSVSR_SV1(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV1_SHIFT)) & SNVS_HPSVSR_SV1_MASK)
|
|
#define SNVS_HPSVSR_SV2_MASK (0x4U)
|
|
#define SNVS_HPSVSR_SV2_SHIFT (2U)
|
|
/*! SV2
|
|
* 0b0..No Security Violation 2 security violation was detected.
|
|
* 0b1..Security Violation 2 security violation was detected.
|
|
*/
|
|
#define SNVS_HPSVSR_SV2(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV2_SHIFT)) & SNVS_HPSVSR_SV2_MASK)
|
|
#define SNVS_HPSVSR_SV3_MASK (0x8U)
|
|
#define SNVS_HPSVSR_SV3_SHIFT (3U)
|
|
/*! SV3
|
|
* 0b0..No Security Violation 3 security violation was detected.
|
|
* 0b1..Security Violation 3 security violation was detected.
|
|
*/
|
|
#define SNVS_HPSVSR_SV3(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV3_SHIFT)) & SNVS_HPSVSR_SV3_MASK)
|
|
#define SNVS_HPSVSR_SV4_MASK (0x10U)
|
|
#define SNVS_HPSVSR_SV4_SHIFT (4U)
|
|
/*! SV4
|
|
* 0b0..No Security Violation 4 security violation was detected.
|
|
* 0b1..Security Violation 4 security violation was detected.
|
|
*/
|
|
#define SNVS_HPSVSR_SV4(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV4_SHIFT)) & SNVS_HPSVSR_SV4_MASK)
|
|
#define SNVS_HPSVSR_SV5_MASK (0x20U)
|
|
#define SNVS_HPSVSR_SV5_SHIFT (5U)
|
|
/*! SV5
|
|
* 0b0..No Security Violation 5 security violation was detected.
|
|
* 0b1..Security Violation 5 security violation was detected.
|
|
*/
|
|
#define SNVS_HPSVSR_SV5(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK)
|
|
#define SNVS_HPSVSR_SW_SV_MASK (0x2000U)
|
|
#define SNVS_HPSVSR_SW_SV_SHIFT (13U)
|
|
#define SNVS_HPSVSR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_SV_SHIFT)) & SNVS_HPSVSR_SW_SV_MASK)
|
|
#define SNVS_HPSVSR_SW_FSV_MASK (0x4000U)
|
|
#define SNVS_HPSVSR_SW_FSV_SHIFT (14U)
|
|
#define SNVS_HPSVSR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_FSV_SHIFT)) & SNVS_HPSVSR_SW_FSV_MASK)
|
|
#define SNVS_HPSVSR_SW_LPSV_MASK (0x8000U)
|
|
#define SNVS_HPSVSR_SW_LPSV_SHIFT (15U)
|
|
#define SNVS_HPSVSR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_LPSV_SHIFT)) & SNVS_HPSVSR_SW_LPSV_MASK)
|
|
#define SNVS_HPSVSR_ZMK_SYNDROME_MASK (0x1FF0000U)
|
|
#define SNVS_HPSVSR_ZMK_SYNDROME_SHIFT (16U)
|
|
#define SNVS_HPSVSR_ZMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_SYNDROME_SHIFT)) & SNVS_HPSVSR_ZMK_SYNDROME_MASK)
|
|
#define SNVS_HPSVSR_ZMK_ECC_FAIL_MASK (0x8000000U)
|
|
#define SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT (27U)
|
|
/*! ZMK_ECC_FAIL
|
|
* 0b0..ZMK ECC Failure was not detected.
|
|
* 0b1..ZMK ECC Failure was detected.
|
|
*/
|
|
#define SNVS_HPSVSR_ZMK_ECC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK)
|
|
#define SNVS_HPSVSR_LP_SEC_VIO_MASK (0x80000000U)
|
|
#define SNVS_HPSVSR_LP_SEC_VIO_SHIFT (31U)
|
|
#define SNVS_HPSVSR_LP_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_LP_SEC_VIO_SHIFT)) & SNVS_HPSVSR_LP_SEC_VIO_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name HPHACIVR - SNVS_HP High Assurance Counter IV Register */
|
|
/*! @{ */
|
|
#define SNVS_HPHACIVR_HAC_COUNTER_IV_MASK (0xFFFFFFFFU)
|
|
#define SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT (0U)
|
|
#define SNVS_HPHACIVR_HAC_COUNTER_IV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT)) & SNVS_HPHACIVR_HAC_COUNTER_IV_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name HPHACR - SNVS_HP High Assurance Counter Register */
|
|
/*! @{ */
|
|
#define SNVS_HPHACR_HAC_COUNTER_MASK (0xFFFFFFFFU)
|
|
#define SNVS_HPHACR_HAC_COUNTER_SHIFT (0U)
|
|
#define SNVS_HPHACR_HAC_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACR_HAC_COUNTER_SHIFT)) & SNVS_HPHACR_HAC_COUNTER_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name HPRTCMR - SNVS_HP Real Time Counter MSB Register */
|
|
/*! @{ */
|
|
#define SNVS_HPRTCMR_RTC_MASK (0x7FFFU)
|
|
#define SNVS_HPRTCMR_RTC_SHIFT (0U)
|
|
#define SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name HPRTCLR - SNVS_HP Real Time Counter LSB Register */
|
|
/*! @{ */
|
|
#define SNVS_HPRTCLR_RTC_MASK (0xFFFFFFFFU)
|
|
#define SNVS_HPRTCLR_RTC_SHIFT (0U)
|
|
#define SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name HPTAMR - SNVS_HP Time Alarm MSB Register */
|
|
/*! @{ */
|
|
#define SNVS_HPTAMR_HPTA_MS_MASK (0x7FFFU)
|
|
#define SNVS_HPTAMR_HPTA_MS_SHIFT (0U)
|
|
#define SNVS_HPTAMR_HPTA_MS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name HPTALR - SNVS_HP Time Alarm LSB Register */
|
|
/*! @{ */
|
|
#define SNVS_HPTALR_HPTA_LS_MASK (0xFFFFFFFFU)
|
|
#define SNVS_HPTALR_HPTA_LS_SHIFT (0U)
|
|
#define SNVS_HPTALR_HPTA_LS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name LPLR - SNVS_LP Lock Register */
|
|
/*! @{ */
|
|
#define SNVS_LPLR_ZMK_WHL_MASK (0x1U)
|
|
#define SNVS_LPLR_ZMK_WHL_SHIFT (0U)
|
|
/*! ZMK_WHL
|
|
* 0b0..Write access is allowed.
|
|
* 0b1..Write access is not allowed.
|
|
*/
|
|
#define SNVS_LPLR_ZMK_WHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK)
|
|
#define SNVS_LPLR_ZMK_RHL_MASK (0x2U)
|
|
#define SNVS_LPLR_ZMK_RHL_SHIFT (1U)
|
|
/*! ZMK_RHL
|
|
* 0b0..Read access is allowed (only in software programming mode).
|
|
* 0b1..Read access is not allowed.
|
|
*/
|
|
#define SNVS_LPLR_ZMK_RHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK)
|
|
#define SNVS_LPLR_SRTC_HL_MASK (0x4U)
|
|
#define SNVS_LPLR_SRTC_HL_SHIFT (2U)
|
|
/*! SRTC_HL
|
|
* 0b0..Write access is allowed.
|
|
* 0b1..Write access is not allowed.
|
|
*/
|
|
#define SNVS_LPLR_SRTC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK)
|
|
#define SNVS_LPLR_LPCALB_HL_MASK (0x8U)
|
|
#define SNVS_LPLR_LPCALB_HL_SHIFT (3U)
|
|
/*! LPCALB_HL
|
|
* 0b0..Write access is allowed.
|
|
* 0b1..Write access is not allowed.
|
|
*/
|
|
#define SNVS_LPLR_LPCALB_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK)
|
|
#define SNVS_LPLR_MC_HL_MASK (0x10U)
|
|
#define SNVS_LPLR_MC_HL_SHIFT (4U)
|
|
/*! MC_HL
|
|
* 0b0..Write access (increment) is allowed.
|
|
* 0b1..Write access (increment) is not allowed.
|
|
*/
|
|
#define SNVS_LPLR_MC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK)
|
|
#define SNVS_LPLR_GPR_HL_MASK (0x20U)
|
|
#define SNVS_LPLR_GPR_HL_SHIFT (5U)
|
|
/*! GPR_HL
|
|
* 0b0..Write access is allowed.
|
|
* 0b1..Write access is not allowed.
|
|
*/
|
|
#define SNVS_LPLR_GPR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK)
|
|
#define SNVS_LPLR_LPSVCR_HL_MASK (0x40U)
|
|
#define SNVS_LPLR_LPSVCR_HL_SHIFT (6U)
|
|
/*! LPSVCR_HL
|
|
* 0b0..Write access is allowed.
|
|
* 0b1..Write access is not allowed.
|
|
*/
|
|
#define SNVS_LPLR_LPSVCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK)
|
|
#define SNVS_LPLR_LPTDCR_HL_MASK (0x100U)
|
|
#define SNVS_LPLR_LPTDCR_HL_SHIFT (8U)
|
|
/*! LPTDCR_HL
|
|
* 0b0..Write access is allowed.
|
|
* 0b1..Write access is not allowed.
|
|
*/
|
|
#define SNVS_LPLR_LPTDCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPTDCR_HL_SHIFT)) & SNVS_LPLR_LPTDCR_HL_MASK)
|
|
#define SNVS_LPLR_MKS_HL_MASK (0x200U)
|
|
#define SNVS_LPLR_MKS_HL_SHIFT (9U)
|
|
/*! MKS_HL
|
|
* 0b0..Write access is allowed.
|
|
* 0b1..Write access is not allowed.
|
|
*/
|
|
#define SNVS_LPLR_MKS_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name LPCR - SNVS_LP Control Register */
|
|
/*! @{ */
|
|
#define SNVS_LPCR_SRTC_ENV_MASK (0x1U)
|
|
#define SNVS_LPCR_SRTC_ENV_SHIFT (0U)
|
|
/*! SRTC_ENV
|
|
* 0b0..SRTC is disabled or invalid.
|
|
* 0b1..SRTC is enabled and valid.
|
|
*/
|
|
#define SNVS_LPCR_SRTC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK)
|
|
#define SNVS_LPCR_LPTA_EN_MASK (0x2U)
|
|
#define SNVS_LPCR_LPTA_EN_SHIFT (1U)
|
|
/*! LPTA_EN
|
|
* 0b0..LP time alarm interrupt is disabled.
|
|
* 0b1..LP time alarm interrupt is enabled.
|
|
*/
|
|
#define SNVS_LPCR_LPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK)
|
|
#define SNVS_LPCR_MC_ENV_MASK (0x4U)
|
|
#define SNVS_LPCR_MC_ENV_SHIFT (2U)
|
|
/*! MC_ENV
|
|
* 0b0..MC is disabled or invalid.
|
|
* 0b1..MC is enabled and valid.
|
|
*/
|
|
#define SNVS_LPCR_MC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK)
|
|
#define SNVS_LPCR_LPWUI_EN_MASK (0x8U)
|
|
#define SNVS_LPCR_LPWUI_EN_SHIFT (3U)
|
|
#define SNVS_LPCR_LPWUI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK)
|
|
#define SNVS_LPCR_SRTC_INV_EN_MASK (0x10U)
|
|
#define SNVS_LPCR_SRTC_INV_EN_SHIFT (4U)
|
|
/*! SRTC_INV_EN
|
|
* 0b0..SRTC stays valid in the case of security violation.
|
|
* 0b1..SRTC is invalidated in the case of security violation.
|
|
*/
|
|
#define SNVS_LPCR_SRTC_INV_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK)
|
|
#define SNVS_LPCR_DP_EN_MASK (0x20U)
|
|
#define SNVS_LPCR_DP_EN_SHIFT (5U)
|
|
/*! DP_EN
|
|
* 0b0..Smart PMIC enabled.
|
|
* 0b1..Dumb PMIC enabled.
|
|
*/
|
|
#define SNVS_LPCR_DP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK)
|
|
#define SNVS_LPCR_TOP_MASK (0x40U)
|
|
#define SNVS_LPCR_TOP_SHIFT (6U)
|
|
/*! TOP
|
|
* 0b0..Leave system power on.
|
|
* 0b1..Turn off system power.
|
|
*/
|
|
#define SNVS_LPCR_TOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK)
|
|
#define SNVS_LPCR_PWR_GLITCH_EN_MASK (0x80U)
|
|
#define SNVS_LPCR_PWR_GLITCH_EN_SHIFT (7U)
|
|
#define SNVS_LPCR_PWR_GLITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PWR_GLITCH_EN_SHIFT)) & SNVS_LPCR_PWR_GLITCH_EN_MASK)
|
|
#define SNVS_LPCR_LPCALB_EN_MASK (0x100U)
|
|
#define SNVS_LPCR_LPCALB_EN_SHIFT (8U)
|
|
/*! LPCALB_EN
|
|
* 0b0..SRTC Time calibration is disabled.
|
|
* 0b1..SRTC Time calibration is enabled.
|
|
*/
|
|
#define SNVS_LPCR_LPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK)
|
|
#define SNVS_LPCR_LPCALB_VAL_MASK (0x7C00U)
|
|
#define SNVS_LPCR_LPCALB_VAL_SHIFT (10U)
|
|
/*! LPCALB_VAL
|
|
* 0b00000..+0 counts per each 32768 ticks of the counter clock
|
|
* 0b00001..+1 counts per each 32768 ticks of the counter clock
|
|
* 0b00010..+2 counts per each 32768 ticks of the counter clock
|
|
* 0b01111..+15 counts per each 32768 ticks of the counter clock
|
|
* 0b10000..-16 counts per each 32768 ticks of the counter clock
|
|
* 0b10001..-15 counts per each 32768 ticks of the counter clock
|
|
* 0b11110..-2 counts per each 32768 ticks of the counter clock
|
|
* 0b11111..-1 counts per each 32768 ticks of the counter clock
|
|
*/
|
|
#define SNVS_LPCR_LPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK)
|
|
#define SNVS_LPCR_BTN_PRESS_TIME_MASK (0x30000U)
|
|
#define SNVS_LPCR_BTN_PRESS_TIME_SHIFT (16U)
|
|
#define SNVS_LPCR_BTN_PRESS_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK)
|
|
#define SNVS_LPCR_DEBOUNCE_MASK (0xC0000U)
|
|
#define SNVS_LPCR_DEBOUNCE_SHIFT (18U)
|
|
#define SNVS_LPCR_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK)
|
|
#define SNVS_LPCR_ON_TIME_MASK (0x300000U)
|
|
#define SNVS_LPCR_ON_TIME_SHIFT (20U)
|
|
#define SNVS_LPCR_ON_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK)
|
|
#define SNVS_LPCR_PK_EN_MASK (0x400000U)
|
|
#define SNVS_LPCR_PK_EN_SHIFT (22U)
|
|
#define SNVS_LPCR_PK_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK)
|
|
#define SNVS_LPCR_PK_OVERRIDE_MASK (0x800000U)
|
|
#define SNVS_LPCR_PK_OVERRIDE_SHIFT (23U)
|
|
#define SNVS_LPCR_PK_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK)
|
|
#define SNVS_LPCR_GPR_Z_DIS_MASK (0x1000000U)
|
|
#define SNVS_LPCR_GPR_Z_DIS_SHIFT (24U)
|
|
#define SNVS_LPCR_GPR_Z_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_GPR_Z_DIS_SHIFT)) & SNVS_LPCR_GPR_Z_DIS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name LPMKCR - SNVS_LP Master Key Control Register */
|
|
/*! @{ */
|
|
#define SNVS_LPMKCR_MASTER_KEY_SEL_MASK (0x3U)
|
|
#define SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT (0U)
|
|
/*! MASTER_KEY_SEL
|
|
* 0b0x..Select one time programmable master key.
|
|
* 0b10..Select zeroizable master key when MKS_EN bit is set .
|
|
* 0b11..Select combined master key when MKS_EN bit is set .
|
|
*/
|
|
#define SNVS_LPMKCR_MASTER_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK)
|
|
#define SNVS_LPMKCR_ZMK_HWP_MASK (0x4U)
|
|
#define SNVS_LPMKCR_ZMK_HWP_SHIFT (2U)
|
|
/*! ZMK_HWP
|
|
* 0b0..ZMK is in the software programming mode.
|
|
* 0b1..ZMK is in the hardware programming mode.
|
|
*/
|
|
#define SNVS_LPMKCR_ZMK_HWP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK)
|
|
#define SNVS_LPMKCR_ZMK_VAL_MASK (0x8U)
|
|
#define SNVS_LPMKCR_ZMK_VAL_SHIFT (3U)
|
|
/*! ZMK_VAL
|
|
* 0b0..ZMK is not valid.
|
|
* 0b1..ZMK is valid.
|
|
*/
|
|
#define SNVS_LPMKCR_ZMK_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK)
|
|
#define SNVS_LPMKCR_ZMK_ECC_EN_MASK (0x10U)
|
|
#define SNVS_LPMKCR_ZMK_ECC_EN_SHIFT (4U)
|
|
/*! ZMK_ECC_EN
|
|
* 0b0..ZMK ECC check is disabled.
|
|
* 0b1..ZMK ECC check is enabled.
|
|
*/
|
|
#define SNVS_LPMKCR_ZMK_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK)
|
|
#define SNVS_LPMKCR_ZMK_ECC_VALUE_MASK (0xFF80U)
|
|
#define SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT (7U)
|
|
#define SNVS_LPMKCR_ZMK_ECC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_VALUE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name LPSVCR - SNVS_LP Security Violation Control Register */
|
|
/*! @{ */
|
|
#define SNVS_LPSVCR_SV0_EN_MASK (0x1U)
|
|
#define SNVS_LPSVCR_SV0_EN_SHIFT (0U)
|
|
/*! SV0_EN
|
|
* 0b0..Security Violation 0 is disabled in the LP domain.
|
|
* 0b1..Security Violation 0 is enabled in the LP domain.
|
|
*/
|
|
#define SNVS_LPSVCR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV0_EN_SHIFT)) & SNVS_LPSVCR_SV0_EN_MASK)
|
|
#define SNVS_LPSVCR_SV1_EN_MASK (0x2U)
|
|
#define SNVS_LPSVCR_SV1_EN_SHIFT (1U)
|
|
/*! SV1_EN
|
|
* 0b0..Security Violation 1 is disabled in the LP domain.
|
|
* 0b1..Security Violation 1 is enabled in the LP domain.
|
|
*/
|
|
#define SNVS_LPSVCR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV1_EN_SHIFT)) & SNVS_LPSVCR_SV1_EN_MASK)
|
|
#define SNVS_LPSVCR_SV2_EN_MASK (0x4U)
|
|
#define SNVS_LPSVCR_SV2_EN_SHIFT (2U)
|
|
/*! SV2_EN
|
|
* 0b0..Security Violation 2 is disabled in the LP domain.
|
|
* 0b1..Security Violation 2 is enabled in the LP domain.
|
|
*/
|
|
#define SNVS_LPSVCR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV2_EN_SHIFT)) & SNVS_LPSVCR_SV2_EN_MASK)
|
|
#define SNVS_LPSVCR_SV3_EN_MASK (0x8U)
|
|
#define SNVS_LPSVCR_SV3_EN_SHIFT (3U)
|
|
/*! SV3_EN
|
|
* 0b0..Security Violation 3 is disabled in the LP domain.
|
|
* 0b1..Security Violation 3 is enabled in the LP domain.
|
|
*/
|
|
#define SNVS_LPSVCR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV3_EN_SHIFT)) & SNVS_LPSVCR_SV3_EN_MASK)
|
|
#define SNVS_LPSVCR_SV4_EN_MASK (0x10U)
|
|
#define SNVS_LPSVCR_SV4_EN_SHIFT (4U)
|
|
/*! SV4_EN
|
|
* 0b0..Security Violation 4 is disabled in the LP domain.
|
|
* 0b1..Security Violation 4 is enabled in the LP domain.
|
|
*/
|
|
#define SNVS_LPSVCR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV4_EN_SHIFT)) & SNVS_LPSVCR_SV4_EN_MASK)
|
|
#define SNVS_LPSVCR_SV5_EN_MASK (0x20U)
|
|
#define SNVS_LPSVCR_SV5_EN_SHIFT (5U)
|
|
/*! SV5_EN
|
|
* 0b0..Security Violation 5 is disabled in the LP domain.
|
|
* 0b1..Security Violation 5 is enabled in the LP domain.
|
|
*/
|
|
#define SNVS_LPSVCR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV5_EN_SHIFT)) & SNVS_LPSVCR_SV5_EN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name LPTDCR - SNVS_LP Tamper Detectors Configuration Register */
|
|
/*! @{ */
|
|
#define SNVS_LPTDCR_SRTCR_EN_MASK (0x2U)
|
|
#define SNVS_LPTDCR_SRTCR_EN_SHIFT (1U)
|
|
/*! SRTCR_EN
|
|
* 0b0..SRTC rollover is disabled.
|
|
* 0b1..SRTC rollover is enabled.
|
|
*/
|
|
#define SNVS_LPTDCR_SRTCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_SRTCR_EN_SHIFT)) & SNVS_LPTDCR_SRTCR_EN_MASK)
|
|
#define SNVS_LPTDCR_MCR_EN_MASK (0x4U)
|
|
#define SNVS_LPTDCR_MCR_EN_SHIFT (2U)
|
|
/*! MCR_EN
|
|
* 0b0..MC rollover is disabled.
|
|
* 0b1..MC rollover is enabled.
|
|
*/
|
|
#define SNVS_LPTDCR_MCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_MCR_EN_SHIFT)) & SNVS_LPTDCR_MCR_EN_MASK)
|
|
#define SNVS_LPTDCR_ET1_EN_MASK (0x200U)
|
|
#define SNVS_LPTDCR_ET1_EN_SHIFT (9U)
|
|
/*! ET1_EN
|
|
* 0b0..External tamper 1 is disabled.
|
|
* 0b1..External tamper 1 is enabled.
|
|
*/
|
|
#define SNVS_LPTDCR_ET1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1_EN_SHIFT)) & SNVS_LPTDCR_ET1_EN_MASK)
|
|
#define SNVS_LPTDCR_ET1P_MASK (0x800U)
|
|
#define SNVS_LPTDCR_ET1P_SHIFT (11U)
|
|
/*! ET1P
|
|
* 0b0..External tamper 1 is active low.
|
|
* 0b1..External tamper 1 is active high.
|
|
*/
|
|
#define SNVS_LPTDCR_ET1P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1P_SHIFT)) & SNVS_LPTDCR_ET1P_MASK)
|
|
#define SNVS_LPTDCR_PFD_OBSERV_MASK (0x4000U)
|
|
#define SNVS_LPTDCR_PFD_OBSERV_SHIFT (14U)
|
|
#define SNVS_LPTDCR_PFD_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_PFD_OBSERV_SHIFT)) & SNVS_LPTDCR_PFD_OBSERV_MASK)
|
|
#define SNVS_LPTDCR_POR_OBSERV_MASK (0x8000U)
|
|
#define SNVS_LPTDCR_POR_OBSERV_SHIFT (15U)
|
|
#define SNVS_LPTDCR_POR_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_POR_OBSERV_SHIFT)) & SNVS_LPTDCR_POR_OBSERV_MASK)
|
|
#define SNVS_LPTDCR_OSCB_MASK (0x10000000U)
|
|
#define SNVS_LPTDCR_OSCB_SHIFT (28U)
|
|
/*! OSCB
|
|
* 0b0..Normal SRTC clock oscillator not bypassed.
|
|
* 0b1..Normal SRTC clock oscillator bypassed. Alternate clock can drive the SRTC clock source.
|
|
*/
|
|
#define SNVS_LPTDCR_OSCB(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_OSCB_SHIFT)) & SNVS_LPTDCR_OSCB_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name LPSR - SNVS_LP Status Register */
|
|
/*! @{ */
|
|
#define SNVS_LPSR_LPTA_MASK (0x1U)
|
|
#define SNVS_LPSR_LPTA_SHIFT (0U)
|
|
/*! LPTA
|
|
* 0b0..No time alarm interrupt occurred.
|
|
* 0b1..A time alarm interrupt occurred.
|
|
*/
|
|
#define SNVS_LPSR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK)
|
|
#define SNVS_LPSR_SRTCR_MASK (0x2U)
|
|
#define SNVS_LPSR_SRTCR_SHIFT (1U)
|
|
/*! SRTCR
|
|
* 0b0..SRTC has not reached its maximum value.
|
|
* 0b1..SRTC has reached its maximum value.
|
|
*/
|
|
#define SNVS_LPSR_SRTCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK)
|
|
#define SNVS_LPSR_MCR_MASK (0x4U)
|
|
#define SNVS_LPSR_MCR_SHIFT (2U)
|
|
/*! MCR
|
|
* 0b0..MC has not reached its maximum value.
|
|
* 0b1..MC has reached its maximum value.
|
|
*/
|
|
#define SNVS_LPSR_MCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK)
|
|
#define SNVS_LPSR_PGD_MASK (0x8U)
|
|
#define SNVS_LPSR_PGD_SHIFT (3U)
|
|
#define SNVS_LPSR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_PGD_SHIFT)) & SNVS_LPSR_PGD_MASK)
|
|
#define SNVS_LPSR_ET1D_MASK (0x200U)
|
|
#define SNVS_LPSR_ET1D_SHIFT (9U)
|
|
/*! ET1D
|
|
* 0b0..External tampering 1 not detected.
|
|
* 0b1..External tampering 1 detected.
|
|
*/
|
|
#define SNVS_LPSR_ET1D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET1D_SHIFT)) & SNVS_LPSR_ET1D_MASK)
|
|
#define SNVS_LPSR_ESVD_MASK (0x10000U)
|
|
#define SNVS_LPSR_ESVD_SHIFT (16U)
|
|
/*! ESVD
|
|
* 0b0..No external security violation.
|
|
* 0b1..External security violation is detected.
|
|
*/
|
|
#define SNVS_LPSR_ESVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK)
|
|
#define SNVS_LPSR_EO_MASK (0x20000U)
|
|
#define SNVS_LPSR_EO_SHIFT (17U)
|
|
/*! EO
|
|
* 0b0..Emergency off was not detected.
|
|
* 0b1..Emergency off was detected.
|
|
*/
|
|
#define SNVS_LPSR_EO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK)
|
|
#define SNVS_LPSR_SPO_MASK (0x40000U)
|
|
#define SNVS_LPSR_SPO_SHIFT (18U)
|
|
/*! SPO
|
|
* 0b0..Set Power Off was not detected.
|
|
* 0b1..Set Power Off was detected.
|
|
*/
|
|
#define SNVS_LPSR_SPO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPO_SHIFT)) & SNVS_LPSR_SPO_MASK)
|
|
#define SNVS_LPSR_SED_MASK (0x100000U)
|
|
#define SNVS_LPSR_SED_SHIFT (20U)
|
|
/*! SED
|
|
* 0b0..Scan exit was not detected.
|
|
* 0b1..Scan exit was detected.
|
|
*/
|
|
#define SNVS_LPSR_SED(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SED_SHIFT)) & SNVS_LPSR_SED_MASK)
|
|
#define SNVS_LPSR_LPNS_MASK (0x40000000U)
|
|
#define SNVS_LPSR_LPNS_SHIFT (30U)
|
|
/*! LPNS
|
|
* 0b0..LP section was not programmed in the non-secure state.
|
|
* 0b1..LP section was programmed in the non-secure state.
|
|
*/
|
|
#define SNVS_LPSR_LPNS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK)
|
|
#define SNVS_LPSR_LPS_MASK (0x80000000U)
|
|
#define SNVS_LPSR_LPS_SHIFT (31U)
|
|
/*! LPS
|
|
* 0b0..LP section was not programmed in secure or trusted state.
|
|
* 0b1..LP section was programmed in secure or trusted state.
|
|
*/
|
|
#define SNVS_LPSR_LPS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name LPSRTCMR - SNVS_LP Secure Real Time Counter MSB Register */
|
|
/*! @{ */
|
|
#define SNVS_LPSRTCMR_SRTC_MASK (0x7FFFU)
|
|
#define SNVS_LPSRTCMR_SRTC_SHIFT (0U)
|
|
#define SNVS_LPSRTCMR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCMR_SRTC_SHIFT)) & SNVS_LPSRTCMR_SRTC_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name LPSRTCLR - SNVS_LP Secure Real Time Counter LSB Register */
|
|
/*! @{ */
|
|
#define SNVS_LPSRTCLR_SRTC_MASK (0xFFFFFFFFU)
|
|
#define SNVS_LPSRTCLR_SRTC_SHIFT (0U)
|
|
#define SNVS_LPSRTCLR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCLR_SRTC_SHIFT)) & SNVS_LPSRTCLR_SRTC_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name LPTAR - SNVS_LP Time Alarm Register */
|
|
/*! @{ */
|
|
#define SNVS_LPTAR_LPTA_MASK (0xFFFFFFFFU)
|
|
#define SNVS_LPTAR_LPTA_SHIFT (0U)
|
|
#define SNVS_LPTAR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTAR_LPTA_SHIFT)) & SNVS_LPTAR_LPTA_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name LPSMCMR - SNVS_LP Secure Monotonic Counter MSB Register */
|
|
/*! @{ */
|
|
#define SNVS_LPSMCMR_MON_COUNTER_MASK (0xFFFFU)
|
|
#define SNVS_LPSMCMR_MON_COUNTER_SHIFT (0U)
|
|
#define SNVS_LPSMCMR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK)
|
|
#define SNVS_LPSMCMR_MC_ERA_BITS_MASK (0xFFFF0000U)
|
|
#define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT (16U)
|
|
#define SNVS_LPSMCMR_MC_ERA_BITS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name LPSMCLR - SNVS_LP Secure Monotonic Counter LSB Register */
|
|
/*! @{ */
|
|
#define SNVS_LPSMCLR_MON_COUNTER_MASK (0xFFFFFFFFU)
|
|
#define SNVS_LPSMCLR_MON_COUNTER_SHIFT (0U)
|
|
#define SNVS_LPSMCLR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name LPPGDR - SNVS_LP Power Glitch Detector Register */
|
|
/*! @{ */
|
|
#define SNVS_LPPGDR_PGD_MASK (0xFFFFFFFFU)
|
|
#define SNVS_LPPGDR_PGD_SHIFT (0U)
|
|
#define SNVS_LPPGDR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPPGDR_PGD_SHIFT)) & SNVS_LPPGDR_PGD_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name LPGPR0_LEGACY_ALIAS - SNVS_LP General Purpose Register 0 (legacy alias) */
|
|
/*! @{ */
|
|
#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK (0xFFFFFFFFU)
|
|
#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT (0U)
|
|
#define SNVS_LPGPR0_LEGACY_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name LPZMKR - SNVS_LP Zeroizable Master Key Register */
|
|
/*! @{ */
|
|
#define SNVS_LPZMKR_ZMK_MASK (0xFFFFFFFFU)
|
|
#define SNVS_LPZMKR_ZMK_SHIFT (0U)
|
|
#define SNVS_LPZMKR_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPZMKR_ZMK_SHIFT)) & SNVS_LPZMKR_ZMK_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of SNVS_LPZMKR */
|
|
#define SNVS_LPZMKR_COUNT (8U)
|
|
|
|
/*! @name LPGPR_ALIAS - SNVS_LP General Purpose Registers 0 .. 3 */
|
|
/*! @{ */
|
|
#define SNVS_LPGPR_ALIAS_GPR_MASK (0xFFFFFFFFU)
|
|
#define SNVS_LPGPR_ALIAS_GPR_SHIFT (0U)
|
|
#define SNVS_LPGPR_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of SNVS_LPGPR_ALIAS */
|
|
#define SNVS_LPGPR_ALIAS_COUNT (4U)
|
|
|
|
/*! @name LPGPR - SNVS_LP General Purpose Registers 0 .. 7 */
|
|
/*! @{ */
|
|
#define SNVS_LPGPR_GPR_MASK (0xFFFFFFFFU)
|
|
#define SNVS_LPGPR_GPR_SHIFT (0U)
|
|
#define SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of SNVS_LPGPR */
|
|
#define SNVS_LPGPR_COUNT (8U)
|
|
|
|
/*! @name HPVIDR1 - SNVS_HP Version ID Register 1 */
|
|
/*! @{ */
|
|
#define SNVS_HPVIDR1_MINOR_REV_MASK (0xFFU)
|
|
#define SNVS_HPVIDR1_MINOR_REV_SHIFT (0U)
|
|
#define SNVS_HPVIDR1_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK)
|
|
#define SNVS_HPVIDR1_MAJOR_REV_MASK (0xFF00U)
|
|
#define SNVS_HPVIDR1_MAJOR_REV_SHIFT (8U)
|
|
#define SNVS_HPVIDR1_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK)
|
|
#define SNVS_HPVIDR1_IP_ID_MASK (0xFFFF0000U)
|
|
#define SNVS_HPVIDR1_IP_ID_SHIFT (16U)
|
|
#define SNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name HPVIDR2 - SNVS_HP Version ID Register 2 */
|
|
/*! @{ */
|
|
#define SNVS_HPVIDR2_CONFIG_OPT_MASK (0xFFU)
|
|
#define SNVS_HPVIDR2_CONFIG_OPT_SHIFT (0U)
|
|
#define SNVS_HPVIDR2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_CONFIG_OPT_SHIFT)) & SNVS_HPVIDR2_CONFIG_OPT_MASK)
|
|
#define SNVS_HPVIDR2_ECO_REV_MASK (0xFF00U)
|
|
#define SNVS_HPVIDR2_ECO_REV_SHIFT (8U)
|
|
#define SNVS_HPVIDR2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK)
|
|
#define SNVS_HPVIDR2_INTG_OPT_MASK (0xFF0000U)
|
|
#define SNVS_HPVIDR2_INTG_OPT_SHIFT (16U)
|
|
#define SNVS_HPVIDR2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_INTG_OPT_SHIFT)) & SNVS_HPVIDR2_INTG_OPT_MASK)
|
|
#define SNVS_HPVIDR2_IP_ERA_MASK (0xFF000000U)
|
|
#define SNVS_HPVIDR2_IP_ERA_SHIFT (24U)
|
|
#define SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group SNVS_Register_Masks */
|
|
|
|
|
|
/* SNVS - Peripheral instance base addresses */
|
|
/** Peripheral SNVS base address */
|
|
#define SNVS_BASE (0x400D4000u)
|
|
/** Peripheral SNVS base pointer */
|
|
#define SNVS ((SNVS_Type *)SNVS_BASE)
|
|
/** Array initializer of SNVS peripheral base addresses */
|
|
#define SNVS_BASE_ADDRS { SNVS_BASE }
|
|
/** Array initializer of SNVS peripheral base pointers */
|
|
#define SNVS_BASE_PTRS { SNVS }
|
|
/** Interrupt vectors for the SNVS peripheral type */
|
|
#define SNVS_IRQS { SNVS_LP_WRAPPER_IRQn }
|
|
#define SNVS_CONSOLIDATED_IRQS { SNVS_HP_WRAPPER_IRQn }
|
|
#define SNVS_SECURITY_IRQS { SNVS_HP_WRAPPER_TZ_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group SNVS_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- SPDIF Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup SPDIF_Peripheral_Access_Layer SPDIF Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** SPDIF - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t SCR; /**< SPDIF Configuration Register, offset: 0x0 */
|
|
__IO uint32_t SRCD; /**< CDText Control Register, offset: 0x4 */
|
|
__IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */
|
|
__IO uint32_t SIE; /**< InterruptEn Register, offset: 0xC */
|
|
union { /* offset: 0x10 */
|
|
__O uint32_t SIC; /**< InterruptClear Register, offset: 0x10 */
|
|
__I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */
|
|
};
|
|
__I uint32_t SRL; /**< SPDIFRxLeft Register, offset: 0x14 */
|
|
__I uint32_t SRR; /**< SPDIFRxRight Register, offset: 0x18 */
|
|
__I uint32_t SRCSH; /**< SPDIFRxCChannel_h Register, offset: 0x1C */
|
|
__I uint32_t SRCSL; /**< SPDIFRxCChannel_l Register, offset: 0x20 */
|
|
__I uint32_t SRU; /**< UchannelRx Register, offset: 0x24 */
|
|
__I uint32_t SRQ; /**< QchannelRx Register, offset: 0x28 */
|
|
__O uint32_t STL; /**< SPDIFTxLeft Register, offset: 0x2C */
|
|
__O uint32_t STR; /**< SPDIFTxRight Register, offset: 0x30 */
|
|
__IO uint32_t STCSCH; /**< SPDIFTxCChannelCons_h Register, offset: 0x34 */
|
|
__IO uint32_t STCSCL; /**< SPDIFTxCChannelCons_l Register, offset: 0x38 */
|
|
uint8_t RESERVED_0[8];
|
|
__I uint32_t SRFM; /**< FreqMeas Register, offset: 0x44 */
|
|
uint8_t RESERVED_1[8];
|
|
__IO uint32_t STC; /**< SPDIFTxClk Register, offset: 0x50 */
|
|
} SPDIF_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- SPDIF Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup SPDIF_Register_Masks SPDIF Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name SCR - SPDIF Configuration Register */
|
|
/*! @{ */
|
|
#define SPDIF_SCR_USRC_SEL_MASK (0x3U)
|
|
#define SPDIF_SCR_USRC_SEL_SHIFT (0U)
|
|
/*! USrc_Sel
|
|
* 0b00..No embedded U channel
|
|
* 0b01..U channel from SPDIF receive block (CD mode)
|
|
* 0b10..Reserved
|
|
* 0b11..U channel from on chip transmitter
|
|
*/
|
|
#define SPDIF_SCR_USRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK)
|
|
#define SPDIF_SCR_TXSEL_MASK (0x1CU)
|
|
#define SPDIF_SCR_TXSEL_SHIFT (2U)
|
|
/*! TxSel
|
|
* 0b000..Off and output 0
|
|
* 0b001..Feed-through SPDIFIN
|
|
* 0b101..Tx Normal operation
|
|
*/
|
|
#define SPDIF_SCR_TXSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK)
|
|
#define SPDIF_SCR_VALCTRL_MASK (0x20U)
|
|
#define SPDIF_SCR_VALCTRL_SHIFT (5U)
|
|
/*! ValCtrl
|
|
* 0b0..Outgoing Validity always set
|
|
* 0b1..Outgoing Validity always clear
|
|
*/
|
|
#define SPDIF_SCR_VALCTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK)
|
|
#define SPDIF_SCR_DMA_TX_EN_MASK (0x100U)
|
|
#define SPDIF_SCR_DMA_TX_EN_SHIFT (8U)
|
|
#define SPDIF_SCR_DMA_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_EN_SHIFT)) & SPDIF_SCR_DMA_TX_EN_MASK)
|
|
#define SPDIF_SCR_DMA_RX_EN_MASK (0x200U)
|
|
#define SPDIF_SCR_DMA_RX_EN_SHIFT (9U)
|
|
#define SPDIF_SCR_DMA_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK)
|
|
#define SPDIF_SCR_TXFIFO_CTRL_MASK (0xC00U)
|
|
#define SPDIF_SCR_TXFIFO_CTRL_SHIFT (10U)
|
|
/*! TxFIFO_Ctrl
|
|
* 0b00..Send out digital zero on SPDIF Tx
|
|
* 0b01..Tx Normal operation
|
|
* 0b10..Reset to 1 sample remaining
|
|
* 0b11..Reserved
|
|
*/
|
|
#define SPDIF_SCR_TXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK)
|
|
#define SPDIF_SCR_SOFT_RESET_MASK (0x1000U)
|
|
#define SPDIF_SCR_SOFT_RESET_SHIFT (12U)
|
|
#define SPDIF_SCR_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_SOFT_RESET_SHIFT)) & SPDIF_SCR_SOFT_RESET_MASK)
|
|
#define SPDIF_SCR_LOW_POWER_MASK (0x2000U)
|
|
#define SPDIF_SCR_LOW_POWER_SHIFT (13U)
|
|
#define SPDIF_SCR_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK)
|
|
#define SPDIF_SCR_TXFIFOEMPTY_SEL_MASK (0x18000U)
|
|
#define SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT (15U)
|
|
/*! TxFIFOEmpty_Sel
|
|
* 0b00..Empty interrupt if 0 sample in Tx left and right FIFOs
|
|
* 0b01..Empty interrupt if at most 4 sample in Tx left and right FIFOs
|
|
* 0b10..Empty interrupt if at most 8 sample in Tx left and right FIFOs
|
|
* 0b11..Empty interrupt if at most 12 sample in Tx left and right FIFOs
|
|
*/
|
|
#define SPDIF_SCR_TXFIFOEMPTY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK)
|
|
#define SPDIF_SCR_TXAUTOSYNC_MASK (0x20000U)
|
|
#define SPDIF_SCR_TXAUTOSYNC_SHIFT (17U)
|
|
/*! TxAutoSync
|
|
* 0b0..Tx FIFO auto sync off
|
|
* 0b1..Tx FIFO auto sync on
|
|
*/
|
|
#define SPDIF_SCR_TXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK)
|
|
#define SPDIF_SCR_RXAUTOSYNC_MASK (0x40000U)
|
|
#define SPDIF_SCR_RXAUTOSYNC_SHIFT (18U)
|
|
/*! RxAutoSync
|
|
* 0b0..Rx FIFO auto sync off
|
|
* 0b1..RxFIFO auto sync on
|
|
*/
|
|
#define SPDIF_SCR_RXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK)
|
|
#define SPDIF_SCR_RXFIFOFULL_SEL_MASK (0x180000U)
|
|
#define SPDIF_SCR_RXFIFOFULL_SEL_SHIFT (19U)
|
|
/*! RxFIFOFull_Sel
|
|
* 0b00..Full interrupt if at least 1 sample in Rx left and right FIFOs
|
|
* 0b01..Full interrupt if at least 4 sample in Rx left and right FIFOs
|
|
* 0b10..Full interrupt if at least 8 sample in Rx left and right FIFOs
|
|
* 0b11..Full interrupt if at least 16 sample in Rx left and right FIFO
|
|
*/
|
|
#define SPDIF_SCR_RXFIFOFULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK)
|
|
#define SPDIF_SCR_RXFIFO_RST_MASK (0x200000U)
|
|
#define SPDIF_SCR_RXFIFO_RST_SHIFT (21U)
|
|
/*! RxFIFO_Rst
|
|
* 0b0..Normal operation
|
|
* 0b1..Reset register to 1 sample remaining
|
|
*/
|
|
#define SPDIF_SCR_RXFIFO_RST(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK)
|
|
#define SPDIF_SCR_RXFIFO_OFF_ON_MASK (0x400000U)
|
|
#define SPDIF_SCR_RXFIFO_OFF_ON_SHIFT (22U)
|
|
/*! RxFIFO_Off_On
|
|
* 0b0..SPDIF Rx FIFO is on
|
|
* 0b1..SPDIF Rx FIFO is off. Does not accept data from interface
|
|
*/
|
|
#define SPDIF_SCR_RXFIFO_OFF_ON(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK)
|
|
#define SPDIF_SCR_RXFIFO_CTRL_MASK (0x800000U)
|
|
#define SPDIF_SCR_RXFIFO_CTRL_SHIFT (23U)
|
|
/*! RxFIFO_Ctrl
|
|
* 0b0..Normal operation
|
|
* 0b1..Always read zero from Rx data register
|
|
*/
|
|
#define SPDIF_SCR_RXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK)
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/*! @} */
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/*! @name SRCD - CDText Control Register */
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/*! @{ */
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#define SPDIF_SRCD_USYNCMODE_MASK (0x2U)
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#define SPDIF_SRCD_USYNCMODE_SHIFT (1U)
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/*! USyncMode
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* 0b0..Non-CD data
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* 0b1..CD user channel subcode
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*/
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#define SPDIF_SRCD_USYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK)
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/*! @} */
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/*! @name SRPC - PhaseConfig Register */
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/*! @{ */
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#define SPDIF_SRPC_GAINSEL_MASK (0x38U)
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#define SPDIF_SRPC_GAINSEL_SHIFT (3U)
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/*! GainSel
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* 0b000..24*(2**10)
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* 0b001..16*(2**10)
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* 0b010..12*(2**10)
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* 0b011..8*(2**10)
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* 0b100..6*(2**10)
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* 0b101..4*(2**10)
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* 0b110..3*(2**10)
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*/
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#define SPDIF_SRPC_GAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK)
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#define SPDIF_SRPC_LOCK_MASK (0x40U)
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#define SPDIF_SRPC_LOCK_SHIFT (6U)
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#define SPDIF_SRPC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK)
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#define SPDIF_SRPC_CLKSRC_SEL_MASK (0x780U)
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#define SPDIF_SRPC_CLKSRC_SEL_SHIFT (7U)
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/*! ClkSrc_Sel
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* 0b0000..if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K (XTALOSC)
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* 0b0001..if (DPLL Locked) SPDIF_RxClk else tx_clk (SPDIF0_CLK_ROOT)
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* 0b0011..if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK
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* 0b0101..REF_CLK_32K (XTALOSC)
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* 0b0110..tx_clk (SPDIF0_CLK_ROOT)
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* 0b1000..SPDIF_EXT_CLK
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*/
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#define SPDIF_SRPC_CLKSRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK)
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/*! @} */
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/*! @name SIE - InterruptEn Register */
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/*! @{ */
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#define SPDIF_SIE_RXFIFOFUL_MASK (0x1U)
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#define SPDIF_SIE_RXFIFOFUL_SHIFT (0U)
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#define SPDIF_SIE_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK)
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#define SPDIF_SIE_TXEM_MASK (0x2U)
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#define SPDIF_SIE_TXEM_SHIFT (1U)
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#define SPDIF_SIE_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXEM_SHIFT)) & SPDIF_SIE_TXEM_MASK)
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#define SPDIF_SIE_LOCKLOSS_MASK (0x4U)
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#define SPDIF_SIE_LOCKLOSS_SHIFT (2U)
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#define SPDIF_SIE_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCKLOSS_SHIFT)) & SPDIF_SIE_LOCKLOSS_MASK)
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#define SPDIF_SIE_RXFIFORESYN_MASK (0x8U)
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#define SPDIF_SIE_RXFIFORESYN_SHIFT (3U)
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#define SPDIF_SIE_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFORESYN_SHIFT)) & SPDIF_SIE_RXFIFORESYN_MASK)
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#define SPDIF_SIE_RXFIFOUNOV_MASK (0x10U)
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#define SPDIF_SIE_RXFIFOUNOV_SHIFT (4U)
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#define SPDIF_SIE_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOUNOV_SHIFT)) & SPDIF_SIE_RXFIFOUNOV_MASK)
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#define SPDIF_SIE_UQERR_MASK (0x20U)
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#define SPDIF_SIE_UQERR_SHIFT (5U)
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#define SPDIF_SIE_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQERR_SHIFT)) & SPDIF_SIE_UQERR_MASK)
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#define SPDIF_SIE_UQSYNC_MASK (0x40U)
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#define SPDIF_SIE_UQSYNC_SHIFT (6U)
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#define SPDIF_SIE_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSYNC_SHIFT)) & SPDIF_SIE_UQSYNC_MASK)
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#define SPDIF_SIE_QRXOV_MASK (0x80U)
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#define SPDIF_SIE_QRXOV_SHIFT (7U)
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#define SPDIF_SIE_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXOV_SHIFT)) & SPDIF_SIE_QRXOV_MASK)
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#define SPDIF_SIE_QRXFUL_MASK (0x100U)
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#define SPDIF_SIE_QRXFUL_SHIFT (8U)
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#define SPDIF_SIE_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXFUL_SHIFT)) & SPDIF_SIE_QRXFUL_MASK)
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#define SPDIF_SIE_URXOV_MASK (0x200U)
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#define SPDIF_SIE_URXOV_SHIFT (9U)
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#define SPDIF_SIE_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXOV_SHIFT)) & SPDIF_SIE_URXOV_MASK)
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#define SPDIF_SIE_URXFUL_MASK (0x400U)
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#define SPDIF_SIE_URXFUL_SHIFT (10U)
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#define SPDIF_SIE_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXFUL_SHIFT)) & SPDIF_SIE_URXFUL_MASK)
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#define SPDIF_SIE_BITERR_MASK (0x4000U)
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#define SPDIF_SIE_BITERR_SHIFT (14U)
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#define SPDIF_SIE_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BITERR_SHIFT)) & SPDIF_SIE_BITERR_MASK)
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#define SPDIF_SIE_SYMERR_MASK (0x8000U)
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#define SPDIF_SIE_SYMERR_SHIFT (15U)
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|
#define SPDIF_SIE_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SYMERR_SHIFT)) & SPDIF_SIE_SYMERR_MASK)
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#define SPDIF_SIE_VALNOGOOD_MASK (0x10000U)
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#define SPDIF_SIE_VALNOGOOD_SHIFT (16U)
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#define SPDIF_SIE_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_VALNOGOOD_SHIFT)) & SPDIF_SIE_VALNOGOOD_MASK)
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#define SPDIF_SIE_CNEW_MASK (0x20000U)
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#define SPDIF_SIE_CNEW_SHIFT (17U)
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#define SPDIF_SIE_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNEW_SHIFT)) & SPDIF_SIE_CNEW_MASK)
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|
#define SPDIF_SIE_TXRESYN_MASK (0x40000U)
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|
#define SPDIF_SIE_TXRESYN_SHIFT (18U)
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|
#define SPDIF_SIE_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXRESYN_SHIFT)) & SPDIF_SIE_TXRESYN_MASK)
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#define SPDIF_SIE_TXUNOV_MASK (0x80000U)
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|
#define SPDIF_SIE_TXUNOV_SHIFT (19U)
|
|
#define SPDIF_SIE_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXUNOV_SHIFT)) & SPDIF_SIE_TXUNOV_MASK)
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|
#define SPDIF_SIE_LOCK_MASK (0x100000U)
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|
#define SPDIF_SIE_LOCK_SHIFT (20U)
|
|
#define SPDIF_SIE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK)
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|
/*! @} */
|
|
|
|
/*! @name SIC - InterruptClear Register */
|
|
/*! @{ */
|
|
#define SPDIF_SIC_LOCKLOSS_MASK (0x4U)
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|
#define SPDIF_SIC_LOCKLOSS_SHIFT (2U)
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|
#define SPDIF_SIC_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK)
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|
#define SPDIF_SIC_RXFIFORESYN_MASK (0x8U)
|
|
#define SPDIF_SIC_RXFIFORESYN_SHIFT (3U)
|
|
#define SPDIF_SIC_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFORESYN_SHIFT)) & SPDIF_SIC_RXFIFORESYN_MASK)
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|
#define SPDIF_SIC_RXFIFOUNOV_MASK (0x10U)
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|
#define SPDIF_SIC_RXFIFOUNOV_SHIFT (4U)
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|
#define SPDIF_SIC_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFOUNOV_SHIFT)) & SPDIF_SIC_RXFIFOUNOV_MASK)
|
|
#define SPDIF_SIC_UQERR_MASK (0x20U)
|
|
#define SPDIF_SIC_UQERR_SHIFT (5U)
|
|
#define SPDIF_SIC_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQERR_SHIFT)) & SPDIF_SIC_UQERR_MASK)
|
|
#define SPDIF_SIC_UQSYNC_MASK (0x40U)
|
|
#define SPDIF_SIC_UQSYNC_SHIFT (6U)
|
|
#define SPDIF_SIC_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQSYNC_SHIFT)) & SPDIF_SIC_UQSYNC_MASK)
|
|
#define SPDIF_SIC_QRXOV_MASK (0x80U)
|
|
#define SPDIF_SIC_QRXOV_SHIFT (7U)
|
|
#define SPDIF_SIC_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_QRXOV_SHIFT)) & SPDIF_SIC_QRXOV_MASK)
|
|
#define SPDIF_SIC_URXOV_MASK (0x200U)
|
|
#define SPDIF_SIC_URXOV_SHIFT (9U)
|
|
#define SPDIF_SIC_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_URXOV_SHIFT)) & SPDIF_SIC_URXOV_MASK)
|
|
#define SPDIF_SIC_BITERR_MASK (0x4000U)
|
|
#define SPDIF_SIC_BITERR_SHIFT (14U)
|
|
#define SPDIF_SIC_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_BITERR_SHIFT)) & SPDIF_SIC_BITERR_MASK)
|
|
#define SPDIF_SIC_SYMERR_MASK (0x8000U)
|
|
#define SPDIF_SIC_SYMERR_SHIFT (15U)
|
|
#define SPDIF_SIC_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_SYMERR_SHIFT)) & SPDIF_SIC_SYMERR_MASK)
|
|
#define SPDIF_SIC_VALNOGOOD_MASK (0x10000U)
|
|
#define SPDIF_SIC_VALNOGOOD_SHIFT (16U)
|
|
#define SPDIF_SIC_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_VALNOGOOD_SHIFT)) & SPDIF_SIC_VALNOGOOD_MASK)
|
|
#define SPDIF_SIC_CNEW_MASK (0x20000U)
|
|
#define SPDIF_SIC_CNEW_SHIFT (17U)
|
|
#define SPDIF_SIC_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_CNEW_SHIFT)) & SPDIF_SIC_CNEW_MASK)
|
|
#define SPDIF_SIC_TXRESYN_MASK (0x40000U)
|
|
#define SPDIF_SIC_TXRESYN_SHIFT (18U)
|
|
#define SPDIF_SIC_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXRESYN_SHIFT)) & SPDIF_SIC_TXRESYN_MASK)
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|
#define SPDIF_SIC_TXUNOV_MASK (0x80000U)
|
|
#define SPDIF_SIC_TXUNOV_SHIFT (19U)
|
|
#define SPDIF_SIC_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXUNOV_SHIFT)) & SPDIF_SIC_TXUNOV_MASK)
|
|
#define SPDIF_SIC_LOCK_MASK (0x100000U)
|
|
#define SPDIF_SIC_LOCK_SHIFT (20U)
|
|
#define SPDIF_SIC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SIS - InterruptStat Register */
|
|
/*! @{ */
|
|
#define SPDIF_SIS_RXFIFOFUL_MASK (0x1U)
|
|
#define SPDIF_SIS_RXFIFOFUL_SHIFT (0U)
|
|
#define SPDIF_SIS_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK)
|
|
#define SPDIF_SIS_TXEM_MASK (0x2U)
|
|
#define SPDIF_SIS_TXEM_SHIFT (1U)
|
|
#define SPDIF_SIS_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXEM_SHIFT)) & SPDIF_SIS_TXEM_MASK)
|
|
#define SPDIF_SIS_LOCKLOSS_MASK (0x4U)
|
|
#define SPDIF_SIS_LOCKLOSS_SHIFT (2U)
|
|
#define SPDIF_SIS_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCKLOSS_SHIFT)) & SPDIF_SIS_LOCKLOSS_MASK)
|
|
#define SPDIF_SIS_RXFIFORESYN_MASK (0x8U)
|
|
#define SPDIF_SIS_RXFIFORESYN_SHIFT (3U)
|
|
#define SPDIF_SIS_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFORESYN_SHIFT)) & SPDIF_SIS_RXFIFORESYN_MASK)
|
|
#define SPDIF_SIS_RXFIFOUNOV_MASK (0x10U)
|
|
#define SPDIF_SIS_RXFIFOUNOV_SHIFT (4U)
|
|
#define SPDIF_SIS_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOUNOV_SHIFT)) & SPDIF_SIS_RXFIFOUNOV_MASK)
|
|
#define SPDIF_SIS_UQERR_MASK (0x20U)
|
|
#define SPDIF_SIS_UQERR_SHIFT (5U)
|
|
#define SPDIF_SIS_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQERR_SHIFT)) & SPDIF_SIS_UQERR_MASK)
|
|
#define SPDIF_SIS_UQSYNC_MASK (0x40U)
|
|
#define SPDIF_SIS_UQSYNC_SHIFT (6U)
|
|
#define SPDIF_SIS_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSYNC_SHIFT)) & SPDIF_SIS_UQSYNC_MASK)
|
|
#define SPDIF_SIS_QRXOV_MASK (0x80U)
|
|
#define SPDIF_SIS_QRXOV_SHIFT (7U)
|
|
#define SPDIF_SIS_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXOV_SHIFT)) & SPDIF_SIS_QRXOV_MASK)
|
|
#define SPDIF_SIS_QRXFUL_MASK (0x100U)
|
|
#define SPDIF_SIS_QRXFUL_SHIFT (8U)
|
|
#define SPDIF_SIS_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXFUL_SHIFT)) & SPDIF_SIS_QRXFUL_MASK)
|
|
#define SPDIF_SIS_URXOV_MASK (0x200U)
|
|
#define SPDIF_SIS_URXOV_SHIFT (9U)
|
|
#define SPDIF_SIS_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXOV_SHIFT)) & SPDIF_SIS_URXOV_MASK)
|
|
#define SPDIF_SIS_URXFUL_MASK (0x400U)
|
|
#define SPDIF_SIS_URXFUL_SHIFT (10U)
|
|
#define SPDIF_SIS_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXFUL_SHIFT)) & SPDIF_SIS_URXFUL_MASK)
|
|
#define SPDIF_SIS_BITERR_MASK (0x4000U)
|
|
#define SPDIF_SIS_BITERR_SHIFT (14U)
|
|
#define SPDIF_SIS_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BITERR_SHIFT)) & SPDIF_SIS_BITERR_MASK)
|
|
#define SPDIF_SIS_SYMERR_MASK (0x8000U)
|
|
#define SPDIF_SIS_SYMERR_SHIFT (15U)
|
|
#define SPDIF_SIS_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SYMERR_SHIFT)) & SPDIF_SIS_SYMERR_MASK)
|
|
#define SPDIF_SIS_VALNOGOOD_MASK (0x10000U)
|
|
#define SPDIF_SIS_VALNOGOOD_SHIFT (16U)
|
|
#define SPDIF_SIS_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_VALNOGOOD_SHIFT)) & SPDIF_SIS_VALNOGOOD_MASK)
|
|
#define SPDIF_SIS_CNEW_MASK (0x20000U)
|
|
#define SPDIF_SIS_CNEW_SHIFT (17U)
|
|
#define SPDIF_SIS_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNEW_SHIFT)) & SPDIF_SIS_CNEW_MASK)
|
|
#define SPDIF_SIS_TXRESYN_MASK (0x40000U)
|
|
#define SPDIF_SIS_TXRESYN_SHIFT (18U)
|
|
#define SPDIF_SIS_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXRESYN_SHIFT)) & SPDIF_SIS_TXRESYN_MASK)
|
|
#define SPDIF_SIS_TXUNOV_MASK (0x80000U)
|
|
#define SPDIF_SIS_TXUNOV_SHIFT (19U)
|
|
#define SPDIF_SIS_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXUNOV_SHIFT)) & SPDIF_SIS_TXUNOV_MASK)
|
|
#define SPDIF_SIS_LOCK_MASK (0x100000U)
|
|
#define SPDIF_SIS_LOCK_SHIFT (20U)
|
|
#define SPDIF_SIS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SRL - SPDIFRxLeft Register */
|
|
/*! @{ */
|
|
#define SPDIF_SRL_RXDATALEFT_MASK (0xFFFFFFU)
|
|
#define SPDIF_SRL_RXDATALEFT_SHIFT (0U)
|
|
#define SPDIF_SRL_RXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SRR - SPDIFRxRight Register */
|
|
/*! @{ */
|
|
#define SPDIF_SRR_RXDATARIGHT_MASK (0xFFFFFFU)
|
|
#define SPDIF_SRR_RXDATARIGHT_SHIFT (0U)
|
|
#define SPDIF_SRR_RXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SRCSH - SPDIFRxCChannel_h Register */
|
|
/*! @{ */
|
|
#define SPDIF_SRCSH_RXCCHANNEL_H_MASK (0xFFFFFFU)
|
|
#define SPDIF_SRCSH_RXCCHANNEL_H_SHIFT (0U)
|
|
#define SPDIF_SRCSH_RXCCHANNEL_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SRCSL - SPDIFRxCChannel_l Register */
|
|
/*! @{ */
|
|
#define SPDIF_SRCSL_RXCCHANNEL_L_MASK (0xFFFFFFU)
|
|
#define SPDIF_SRCSL_RXCCHANNEL_L_SHIFT (0U)
|
|
#define SPDIF_SRCSL_RXCCHANNEL_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SRU - UchannelRx Register */
|
|
/*! @{ */
|
|
#define SPDIF_SRU_RXUCHANNEL_MASK (0xFFFFFFU)
|
|
#define SPDIF_SRU_RXUCHANNEL_SHIFT (0U)
|
|
#define SPDIF_SRU_RXUCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SRQ - QchannelRx Register */
|
|
/*! @{ */
|
|
#define SPDIF_SRQ_RXQCHANNEL_MASK (0xFFFFFFU)
|
|
#define SPDIF_SRQ_RXQCHANNEL_SHIFT (0U)
|
|
#define SPDIF_SRQ_RXQCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name STL - SPDIFTxLeft Register */
|
|
/*! @{ */
|
|
#define SPDIF_STL_TXDATALEFT_MASK (0xFFFFFFU)
|
|
#define SPDIF_STL_TXDATALEFT_SHIFT (0U)
|
|
#define SPDIF_STL_TXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name STR - SPDIFTxRight Register */
|
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/*! @{ */
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#define SPDIF_STR_TXDATARIGHT_MASK (0xFFFFFFU)
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#define SPDIF_STR_TXDATARIGHT_SHIFT (0U)
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#define SPDIF_STR_TXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK)
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/*! @} */
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/*! @name STCSCH - SPDIFTxCChannelCons_h Register */
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/*! @{ */
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#define SPDIF_STCSCH_TXCCHANNELCONS_H_MASK (0xFFFFFFU)
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#define SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT (0U)
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#define SPDIF_STCSCH_TXCCHANNELCONS_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK)
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/*! @} */
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/*! @name STCSCL - SPDIFTxCChannelCons_l Register */
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/*! @{ */
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#define SPDIF_STCSCL_TXCCHANNELCONS_L_MASK (0xFFFFFFU)
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#define SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT (0U)
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#define SPDIF_STCSCL_TXCCHANNELCONS_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK)
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/*! @} */
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/*! @name SRFM - FreqMeas Register */
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/*! @{ */
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#define SPDIF_SRFM_FREQMEAS_MASK (0xFFFFFFU)
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#define SPDIF_SRFM_FREQMEAS_SHIFT (0U)
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#define SPDIF_SRFM_FREQMEAS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK)
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/*! @} */
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/*! @name STC - SPDIFTxClk Register */
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/*! @{ */
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#define SPDIF_STC_TXCLK_DF_MASK (0x7FU)
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#define SPDIF_STC_TXCLK_DF_SHIFT (0U)
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/*! TxClk_DF
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* 0b0000000..divider factor is 1
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* 0b0000001..divider factor is 2
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* 0b1111111..divider factor is 128
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*/
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#define SPDIF_STC_TXCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK)
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#define SPDIF_STC_TX_ALL_CLK_EN_MASK (0x80U)
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#define SPDIF_STC_TX_ALL_CLK_EN_SHIFT (7U)
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/*! tx_all_clk_en
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* 0b0..disable transfer clock.
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* 0b1..enable transfer clock.
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*/
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#define SPDIF_STC_TX_ALL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK)
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#define SPDIF_STC_TXCLK_SOURCE_MASK (0x700U)
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#define SPDIF_STC_TXCLK_SOURCE_SHIFT (8U)
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/*! TxClk_Source
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* 0b000..REF_CLK_32K input (XTALOSC 32 kHz clock)
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* 0b001..tx_clk input (from SPDIF0_CLK_ROOT. See CCM.)
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* 0b011..SPDIF_EXT_CLK, from pads
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* 0b101..ipg_clk input (frequency divided)
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*/
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#define SPDIF_STC_TXCLK_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK)
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#define SPDIF_STC_SYSCLK_DF_MASK (0xFF800U)
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#define SPDIF_STC_SYSCLK_DF_SHIFT (11U)
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/*! SYSCLK_DF
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* 0b000000000..no clock signal
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* 0b000000001..divider factor is 2
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* 0b111111111..divider factor is 512
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*/
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#define SPDIF_STC_SYSCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK)
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/*! @} */
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/*!
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* @}
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*/ /* end of group SPDIF_Register_Masks */
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/* SPDIF - Peripheral instance base addresses */
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/** Peripheral SPDIF base address */
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#define SPDIF_BASE (0x40380000u)
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/** Peripheral SPDIF base pointer */
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#define SPDIF ((SPDIF_Type *)SPDIF_BASE)
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/** Array initializer of SPDIF peripheral base addresses */
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#define SPDIF_BASE_ADDRS { SPDIF_BASE }
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/** Array initializer of SPDIF peripheral base pointers */
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#define SPDIF_BASE_PTRS { SPDIF }
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/** Interrupt vectors for the SPDIF peripheral type */
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#define SPDIF_IRQS { SPDIF_IRQn }
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/*!
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* @}
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*/ /* end of group SPDIF_Peripheral_Access_Layer */
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/* ----------------------------------------------------------------------------
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-- SRC Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup SRC_Peripheral_Access_Layer SRC Peripheral Access Layer
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* @{
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*/
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/** SRC - Register Layout Typedef */
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typedef struct {
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__IO uint32_t SCR; /**< SRC Control Register, offset: 0x0 */
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__I uint32_t SBMR1; /**< SRC Boot Mode Register 1, offset: 0x4 */
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__IO uint32_t SRSR; /**< SRC Reset Status Register, offset: 0x8 */
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uint8_t RESERVED_0[16];
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__I uint32_t SBMR2; /**< SRC Boot Mode Register 2, offset: 0x1C */
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__IO uint32_t GPR[10]; /**< SRC General Purpose Register 1..SRC General Purpose Register 10, array offset: 0x20, array step: 0x4 */
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} SRC_Type;
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/* ----------------------------------------------------------------------------
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-- SRC Register Masks
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup SRC_Register_Masks SRC Register Masks
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* @{
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*/
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/*! @name SCR - SRC Control Register */
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/*! @{ */
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#define SRC_SCR_MASK_WDOG_RST_MASK (0x780U)
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#define SRC_SCR_MASK_WDOG_RST_SHIFT (7U)
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/*! mask_wdog_rst
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* 0b0101..wdog_rst_b is masked
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* 0b1010..wdog_rst_b is not masked (default)
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*/
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#define SRC_SCR_MASK_WDOG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG_RST_SHIFT)) & SRC_SCR_MASK_WDOG_RST_MASK)
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#define SRC_SCR_CORE0_RST_MASK (0x2000U)
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#define SRC_SCR_CORE0_RST_SHIFT (13U)
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/*! core0_rst
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* 0b0..do not assert core0 reset
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* 0b1..assert core0 reset
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*/
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#define SRC_SCR_CORE0_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_RST_SHIFT)) & SRC_SCR_CORE0_RST_MASK)
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#define SRC_SCR_CORE0_DBG_RST_MASK (0x20000U)
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#define SRC_SCR_CORE0_DBG_RST_SHIFT (17U)
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/*! core0_dbg_rst
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* 0b0..do not assert core0 debug reset
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* 0b1..assert core0 debug reset
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|
*/
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#define SRC_SCR_CORE0_DBG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_DBG_RST_SHIFT)) & SRC_SCR_CORE0_DBG_RST_MASK)
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#define SRC_SCR_DBG_RST_MSK_PG_MASK (0x2000000U)
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#define SRC_SCR_DBG_RST_MSK_PG_SHIFT (25U)
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/*! dbg_rst_msk_pg
|
|
* 0b0..do not mask core debug resets (debug resets will be asserted after power gating event)
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* 0b1..mask core debug resets (debug resets won't be asserted after power gating event)
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*/
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#define SRC_SCR_DBG_RST_MSK_PG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DBG_RST_MSK_PG_SHIFT)) & SRC_SCR_DBG_RST_MSK_PG_MASK)
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#define SRC_SCR_MASK_WDOG3_RST_MASK (0xF0000000U)
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#define SRC_SCR_MASK_WDOG3_RST_SHIFT (28U)
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/*! mask_wdog3_rst
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|
* 0b0101..wdog3_rst_b is masked
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|
* 0b1010..wdog3_rst_b is not masked
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|
*/
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|
#define SRC_SCR_MASK_WDOG3_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG3_RST_SHIFT)) & SRC_SCR_MASK_WDOG3_RST_MASK)
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/*! @} */
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/*! @name SBMR1 - SRC Boot Mode Register 1 */
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/*! @{ */
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#define SRC_SBMR1_BOOT_CFG1_MASK (0xFFU)
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#define SRC_SBMR1_BOOT_CFG1_SHIFT (0U)
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#define SRC_SBMR1_BOOT_CFG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK)
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#define SRC_SBMR1_BOOT_CFG2_MASK (0xFF00U)
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#define SRC_SBMR1_BOOT_CFG2_SHIFT (8U)
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|
#define SRC_SBMR1_BOOT_CFG2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG2_SHIFT)) & SRC_SBMR1_BOOT_CFG2_MASK)
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|
#define SRC_SBMR1_BOOT_CFG3_MASK (0xFF0000U)
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|
#define SRC_SBMR1_BOOT_CFG3_SHIFT (16U)
|
|
#define SRC_SBMR1_BOOT_CFG3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG3_SHIFT)) & SRC_SBMR1_BOOT_CFG3_MASK)
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#define SRC_SBMR1_BOOT_CFG4_MASK (0xFF000000U)
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#define SRC_SBMR1_BOOT_CFG4_SHIFT (24U)
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|
#define SRC_SBMR1_BOOT_CFG4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SRSR - SRC Reset Status Register */
|
|
/*! @{ */
|
|
#define SRC_SRSR_IPP_RESET_B_MASK (0x1U)
|
|
#define SRC_SRSR_IPP_RESET_B_SHIFT (0U)
|
|
/*! ipp_reset_b
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|
* 0b0..Reset is not a result of ipp_reset_b pin.
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|
* 0b1..Reset is a result of ipp_reset_b pin.
|
|
*/
|
|
#define SRC_SRSR_IPP_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_SHIFT)) & SRC_SRSR_IPP_RESET_B_MASK)
|
|
#define SRC_SRSR_LOCKUP_SYSRESETREQ_MASK (0x2U)
|
|
#define SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT (1U)
|
|
/*! lockup_sysresetreq
|
|
* 0b0..Reset is not a result of the mentioned case.
|
|
* 0b1..Reset is a result of the mentioned case.
|
|
*/
|
|
#define SRC_SRSR_LOCKUP_SYSRESETREQ(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT)) & SRC_SRSR_LOCKUP_SYSRESETREQ_MASK)
|
|
#define SRC_SRSR_CSU_RESET_B_MASK (0x4U)
|
|
#define SRC_SRSR_CSU_RESET_B_SHIFT (2U)
|
|
/*! csu_reset_b
|
|
* 0b0..Reset is not a result of the csu_reset_b event.
|
|
* 0b1..Reset is a result of the csu_reset_b event.
|
|
*/
|
|
#define SRC_SRSR_CSU_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_SHIFT)) & SRC_SRSR_CSU_RESET_B_MASK)
|
|
#define SRC_SRSR_IPP_USER_RESET_B_MASK (0x8U)
|
|
#define SRC_SRSR_IPP_USER_RESET_B_SHIFT (3U)
|
|
/*! ipp_user_reset_b
|
|
* 0b0..Reset is not a result of the ipp_user_reset_b qualified as COLD reset event.
|
|
* 0b1..Reset is a result of the ipp_user_reset_b qualified as COLD reset event.
|
|
*/
|
|
#define SRC_SRSR_IPP_USER_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_MASK)
|
|
#define SRC_SRSR_WDOG_RST_B_MASK (0x10U)
|
|
#define SRC_SRSR_WDOG_RST_B_SHIFT (4U)
|
|
/*! wdog_rst_b
|
|
* 0b0..Reset is not a result of the watchdog time-out event.
|
|
* 0b1..Reset is a result of the watchdog time-out event.
|
|
*/
|
|
#define SRC_SRSR_WDOG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_SHIFT)) & SRC_SRSR_WDOG_RST_B_MASK)
|
|
#define SRC_SRSR_JTAG_RST_B_MASK (0x20U)
|
|
#define SRC_SRSR_JTAG_RST_B_SHIFT (5U)
|
|
/*! jtag_rst_b
|
|
* 0b0..Reset is not a result of HIGH-Z reset from JTAG.
|
|
* 0b1..Reset is a result of HIGH-Z reset from JTAG.
|
|
*/
|
|
#define SRC_SRSR_JTAG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_SHIFT)) & SRC_SRSR_JTAG_RST_B_MASK)
|
|
#define SRC_SRSR_JTAG_SW_RST_MASK (0x40U)
|
|
#define SRC_SRSR_JTAG_SW_RST_SHIFT (6U)
|
|
/*! jtag_sw_rst
|
|
* 0b0..Reset is not a result of software reset from JTAG.
|
|
* 0b1..Reset is a result of software reset from JTAG.
|
|
*/
|
|
#define SRC_SRSR_JTAG_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_SHIFT)) & SRC_SRSR_JTAG_SW_RST_MASK)
|
|
#define SRC_SRSR_WDOG3_RST_B_MASK (0x80U)
|
|
#define SRC_SRSR_WDOG3_RST_B_SHIFT (7U)
|
|
/*! wdog3_rst_b
|
|
* 0b0..Reset is not a result of the watchdog3 time-out event.
|
|
* 0b1..Reset is a result of the watchdog3 time-out event.
|
|
*/
|
|
#define SRC_SRSR_WDOG3_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_SHIFT)) & SRC_SRSR_WDOG3_RST_B_MASK)
|
|
#define SRC_SRSR_TEMPSENSE_RST_B_MASK (0x100U)
|
|
#define SRC_SRSR_TEMPSENSE_RST_B_SHIFT (8U)
|
|
/*! tempsense_rst_b
|
|
* 0b0..Reset is not a result of software reset from Temperature Sensor.
|
|
* 0b1..Reset is a result of software reset from Temperature Sensor.
|
|
*/
|
|
#define SRC_SRSR_TEMPSENSE_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SBMR2 - SRC Boot Mode Register 2 */
|
|
/*! @{ */
|
|
#define SRC_SBMR2_SEC_CONFIG_MASK (0x3U)
|
|
#define SRC_SBMR2_SEC_CONFIG_SHIFT (0U)
|
|
#define SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK)
|
|
#define SRC_SBMR2_DIR_BT_DIS_MASK (0x8U)
|
|
#define SRC_SBMR2_DIR_BT_DIS_SHIFT (3U)
|
|
#define SRC_SBMR2_DIR_BT_DIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_DIR_BT_DIS_SHIFT)) & SRC_SBMR2_DIR_BT_DIS_MASK)
|
|
#define SRC_SBMR2_BT_FUSE_SEL_MASK (0x10U)
|
|
#define SRC_SBMR2_BT_FUSE_SEL_SHIFT (4U)
|
|
#define SRC_SBMR2_BT_FUSE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK)
|
|
#define SRC_SBMR2_BMOD_MASK (0x3000000U)
|
|
#define SRC_SBMR2_BMOD_SHIFT (24U)
|
|
#define SRC_SBMR2_BMOD(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GPR - SRC General Purpose Register 1..SRC General Purpose Register 10 */
|
|
/*! @{ */
|
|
#define SRC_GPR_PERSISTENT_ARG0_MASK (0xFFFFFFFFU)
|
|
#define SRC_GPR_PERSISTENT_ARG0_SHIFT (0U)
|
|
#define SRC_GPR_PERSISTENT_ARG0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG0_SHIFT)) & SRC_GPR_PERSISTENT_ARG0_MASK)
|
|
#define SRC_GPR_PERSISTENT_ENTRY0_MASK (0xFFFFFFFFU)
|
|
#define SRC_GPR_PERSISTENT_ENTRY0_SHIFT (0U)
|
|
#define SRC_GPR_PERSISTENT_ENTRY0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY0_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY0_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of SRC_GPR */
|
|
#define SRC_GPR_COUNT (10U)
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group SRC_Register_Masks */
|
|
|
|
|
|
/* SRC - Peripheral instance base addresses */
|
|
/** Peripheral SRC base address */
|
|
#define SRC_BASE (0x400F8000u)
|
|
/** Peripheral SRC base pointer */
|
|
#define SRC ((SRC_Type *)SRC_BASE)
|
|
/** Array initializer of SRC peripheral base addresses */
|
|
#define SRC_BASE_ADDRS { SRC_BASE }
|
|
/** Array initializer of SRC peripheral base pointers */
|
|
#define SRC_BASE_PTRS { SRC }
|
|
/** Interrupt vectors for the SRC peripheral type */
|
|
#define SRC_IRQS { SRC_IRQn }
|
|
/* Backward compatibility */
|
|
#define SRC_SCR_MWDR_MASK SRC_SCR_MASK_WDOG_RST_MASK
|
|
#define SRC_SCR_MWDR_SHIFT SRC_SCR_MASK_WDOG_RST_SHIFT
|
|
#define SRC_SCR_MWDR(x) SRC_SCR_MASK_WDOG_RST(x)
|
|
#define SRC_SRSR_WDOG_MASK SRC_SRSR_WDOG_RST_B_MASK
|
|
#define SRC_SRSR_WDOG_SHIFT SRC_SRSR_WDOG_RST_B_SHIFT
|
|
#define SRC_SRSR_WDOG(x) SRC_SRSR_WDOG_RST_B(x)
|
|
#define SRC_SRSR_JTAG_MASK SRC_SRSR_JTAG_RST_B_MASK
|
|
#define SRC_SRSR_JTAG_SHIFT SRC_SRSR_JTAG_RST_B_SHIFT
|
|
#define SRC_SRSR_JTAG(x) SRC_SRSR_JTAG_RST_B(x)
|
|
#define SRC_SRSR_SJC_MASK SRC_SRSR_JTAG_SW_RST_MASK
|
|
#define SRC_SRSR_SJC_SHIFT SRC_SRSR_JTAG_SW_RST_SHIFT
|
|
#define SRC_SRSR_SJC(x) SRC_SRSR_JTAG_SW_RST(x)
|
|
#define SRC_SRSR_TSR_MASK SRC_SRSR_TEMPSENSE_RST_B_MASK
|
|
#define SRC_SRSR_TSR_SHIFT SRC_SRSR_TEMPSENSE_RST_B_SHIFT
|
|
#define SRC_SRSR_TSR(x) SRC_SRSR_TEMPSENSE_RST_B(x)
|
|
/* Extra definition */
|
|
#define SRC_SRSR_W1C_BITS_MASK ( SRC_SRSR_WDOG3_RST_B_MASK \
|
|
| SRC_SRSR_JTAG_SW_RST_MASK \
|
|
| SRC_SRSR_JTAG_RST_B_MASK \
|
|
| SRC_SRSR_WDOG_RST_B_MASK \
|
|
| SRC_SRSR_IPP_USER_RESET_B_MASK \
|
|
| SRC_SRSR_CSU_RESET_B_MASK \
|
|
| SRC_SRSR_LOCKUP_SYSRESETREQ_MASK \
|
|
| SRC_SRSR_IPP_RESET_B_MASK)
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group SRC_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- TEMPMON Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup TEMPMON_Peripheral_Access_Layer TEMPMON Peripheral Access Layer
|
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* @{
|
|
*/
|
|
|
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/** TEMPMON - Register Layout Typedef */
|
|
typedef struct {
|
|
uint8_t RESERVED_0[384];
|
|
__IO uint32_t TEMPSENSE0; /**< Tempsensor Control Register 0, offset: 0x180 */
|
|
__IO uint32_t TEMPSENSE0_SET; /**< Tempsensor Control Register 0, offset: 0x184 */
|
|
__IO uint32_t TEMPSENSE0_CLR; /**< Tempsensor Control Register 0, offset: 0x188 */
|
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__IO uint32_t TEMPSENSE0_TOG; /**< Tempsensor Control Register 0, offset: 0x18C */
|
|
__IO uint32_t TEMPSENSE1; /**< Tempsensor Control Register 1, offset: 0x190 */
|
|
__IO uint32_t TEMPSENSE1_SET; /**< Tempsensor Control Register 1, offset: 0x194 */
|
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__IO uint32_t TEMPSENSE1_CLR; /**< Tempsensor Control Register 1, offset: 0x198 */
|
|
__IO uint32_t TEMPSENSE1_TOG; /**< Tempsensor Control Register 1, offset: 0x19C */
|
|
uint8_t RESERVED_1[240];
|
|
__IO uint32_t TEMPSENSE2; /**< Tempsensor Control Register 2, offset: 0x290 */
|
|
__IO uint32_t TEMPSENSE2_SET; /**< Tempsensor Control Register 2, offset: 0x294 */
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|
__IO uint32_t TEMPSENSE2_CLR; /**< Tempsensor Control Register 2, offset: 0x298 */
|
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__IO uint32_t TEMPSENSE2_TOG; /**< Tempsensor Control Register 2, offset: 0x29C */
|
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} TEMPMON_Type;
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|
|
|
/* ----------------------------------------------------------------------------
|
|
-- TEMPMON Register Masks
|
|
---------------------------------------------------------------------------- */
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|
|
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/*!
|
|
* @addtogroup TEMPMON_Register_Masks TEMPMON Register Masks
|
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* @{
|
|
*/
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|
|
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/*! @name TEMPSENSE0 - Tempsensor Control Register 0 */
|
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/*! @{ */
|
|
#define TEMPMON_TEMPSENSE0_POWER_DOWN_MASK (0x1U)
|
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#define TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT (0U)
|
|
/*! POWER_DOWN
|
|
* 0b0..Enable power to the temperature sensor.
|
|
* 0b1..Power down the temperature sensor.
|
|
*/
|
|
#define TEMPMON_TEMPSENSE0_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_POWER_DOWN_MASK)
|
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#define TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK (0x2U)
|
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#define TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT (1U)
|
|
/*! MEASURE_TEMP
|
|
* 0b0..Do not start the measurement process.
|
|
* 0b1..Start the measurement process.
|
|
*/
|
|
#define TEMPMON_TEMPSENSE0_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK)
|
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#define TEMPMON_TEMPSENSE0_FINISHED_MASK (0x4U)
|
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#define TEMPMON_TEMPSENSE0_FINISHED_SHIFT (2U)
|
|
/*! FINISHED
|
|
* 0b0..Last measurement is not ready yet.
|
|
* 0b1..Last measurement is valid.
|
|
*/
|
|
#define TEMPMON_TEMPSENSE0_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_FINISHED_MASK)
|
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#define TEMPMON_TEMPSENSE0_TEMP_CNT_MASK (0xFFF00U)
|
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#define TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT (8U)
|
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#define TEMPMON_TEMPSENSE0_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TEMP_CNT_MASK)
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#define TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK (0xFFF00000U)
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#define TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT (20U)
|
|
#define TEMPMON_TEMPSENSE0_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK)
|
|
/*! @} */
|
|
|
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/*! @name TEMPSENSE0_SET - Tempsensor Control Register 0 */
|
|
/*! @{ */
|
|
#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK (0x1U)
|
|
#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT (0U)
|
|
/*! POWER_DOWN
|
|
* 0b0..Enable power to the temperature sensor.
|
|
* 0b1..Power down the temperature sensor.
|
|
*/
|
|
#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK)
|
|
#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK (0x2U)
|
|
#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT (1U)
|
|
/*! MEASURE_TEMP
|
|
* 0b0..Do not start the measurement process.
|
|
* 0b1..Start the measurement process.
|
|
*/
|
|
#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK)
|
|
#define TEMPMON_TEMPSENSE0_SET_FINISHED_MASK (0x4U)
|
|
#define TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT (2U)
|
|
/*! FINISHED
|
|
* 0b0..Last measurement is not ready yet.
|
|
* 0b1..Last measurement is valid.
|
|
*/
|
|
#define TEMPMON_TEMPSENSE0_SET_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_SET_FINISHED_MASK)
|
|
#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK (0xFFF00U)
|
|
#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT (8U)
|
|
#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK)
|
|
#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK (0xFFF00000U)
|
|
#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT (20U)
|
|
#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TEMPSENSE0_CLR - Tempsensor Control Register 0 */
|
|
/*! @{ */
|
|
#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK (0x1U)
|
|
#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT (0U)
|
|
/*! POWER_DOWN
|
|
* 0b0..Enable power to the temperature sensor.
|
|
* 0b1..Power down the temperature sensor.
|
|
*/
|
|
#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK)
|
|
#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK (0x2U)
|
|
#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT (1U)
|
|
/*! MEASURE_TEMP
|
|
* 0b0..Do not start the measurement process.
|
|
* 0b1..Start the measurement process.
|
|
*/
|
|
#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK)
|
|
#define TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK (0x4U)
|
|
#define TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT (2U)
|
|
/*! FINISHED
|
|
* 0b0..Last measurement is not ready yet.
|
|
* 0b1..Last measurement is valid.
|
|
*/
|
|
#define TEMPMON_TEMPSENSE0_CLR_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK)
|
|
#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK (0xFFF00U)
|
|
#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT (8U)
|
|
#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK)
|
|
#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK (0xFFF00000U)
|
|
#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT (20U)
|
|
#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TEMPSENSE0_TOG - Tempsensor Control Register 0 */
|
|
/*! @{ */
|
|
#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK (0x1U)
|
|
#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT (0U)
|
|
/*! POWER_DOWN
|
|
* 0b0..Enable power to the temperature sensor.
|
|
* 0b1..Power down the temperature sensor.
|
|
*/
|
|
#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK)
|
|
#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK (0x2U)
|
|
#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT (1U)
|
|
/*! MEASURE_TEMP
|
|
* 0b0..Do not start the measurement process.
|
|
* 0b1..Start the measurement process.
|
|
*/
|
|
#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK)
|
|
#define TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK (0x4U)
|
|
#define TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT (2U)
|
|
/*! FINISHED
|
|
* 0b0..Last measurement is not ready yet.
|
|
* 0b1..Last measurement is valid.
|
|
*/
|
|
#define TEMPMON_TEMPSENSE0_TOG_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK)
|
|
#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK (0xFFF00U)
|
|
#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT (8U)
|
|
#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK)
|
|
#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK (0xFFF00000U)
|
|
#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT (20U)
|
|
#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TEMPSENSE1 - Tempsensor Control Register 1 */
|
|
/*! @{ */
|
|
#define TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK (0xFFFFU)
|
|
#define TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT (0U)
|
|
#define TEMPMON_TEMPSENSE1_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TEMPSENSE1_SET - Tempsensor Control Register 1 */
|
|
/*! @{ */
|
|
#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK (0xFFFFU)
|
|
#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT (0U)
|
|
#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TEMPSENSE1_CLR - Tempsensor Control Register 1 */
|
|
/*! @{ */
|
|
#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK (0xFFFFU)
|
|
#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT (0U)
|
|
#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TEMPSENSE1_TOG - Tempsensor Control Register 1 */
|
|
/*! @{ */
|
|
#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK (0xFFFFU)
|
|
#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT (0U)
|
|
#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TEMPSENSE2 - Tempsensor Control Register 2 */
|
|
/*! @{ */
|
|
#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK (0xFFFU)
|
|
#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT (0U)
|
|
#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK)
|
|
#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK (0xFFF0000U)
|
|
#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT (16U)
|
|
#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TEMPSENSE2_SET - Tempsensor Control Register 2 */
|
|
/*! @{ */
|
|
#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK (0xFFFU)
|
|
#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT (0U)
|
|
#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK)
|
|
#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK (0xFFF0000U)
|
|
#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT (16U)
|
|
#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TEMPSENSE2_CLR - Tempsensor Control Register 2 */
|
|
/*! @{ */
|
|
#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK (0xFFFU)
|
|
#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT (0U)
|
|
#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK)
|
|
#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK (0xFFF0000U)
|
|
#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT (16U)
|
|
#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TEMPSENSE2_TOG - Tempsensor Control Register 2 */
|
|
/*! @{ */
|
|
#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK (0xFFFU)
|
|
#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT (0U)
|
|
#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK)
|
|
#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK (0xFFF0000U)
|
|
#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT (16U)
|
|
#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group TEMPMON_Register_Masks */
|
|
|
|
|
|
/* TEMPMON - Peripheral instance base addresses */
|
|
/** Peripheral TEMPMON base address */
|
|
#define TEMPMON_BASE (0x400D8000u)
|
|
/** Peripheral TEMPMON base pointer */
|
|
#define TEMPMON ((TEMPMON_Type *)TEMPMON_BASE)
|
|
/** Array initializer of TEMPMON peripheral base addresses */
|
|
#define TEMPMON_BASE_ADDRS { TEMPMON_BASE }
|
|
/** Array initializer of TEMPMON peripheral base pointers */
|
|
#define TEMPMON_BASE_PTRS { TEMPMON }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group TEMPMON_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- TMR Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup TMR_Peripheral_Access_Layer TMR Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** TMR - Register Layout Typedef */
|
|
typedef struct {
|
|
struct { /* offset: 0x0, array step: 0x20 */
|
|
__IO uint16_t COMP1; /**< Timer Channel Compare Register 1, array offset: 0x0, array step: 0x20 */
|
|
__IO uint16_t COMP2; /**< Timer Channel Compare Register 2, array offset: 0x2, array step: 0x20 */
|
|
__IO uint16_t CAPT; /**< Timer Channel Capture Register, array offset: 0x4, array step: 0x20 */
|
|
__IO uint16_t LOAD; /**< Timer Channel Load Register, array offset: 0x6, array step: 0x20 */
|
|
__IO uint16_t HOLD; /**< Timer Channel Hold Register, array offset: 0x8, array step: 0x20 */
|
|
__IO uint16_t CNTR; /**< Timer Channel Counter Register, array offset: 0xA, array step: 0x20 */
|
|
__IO uint16_t CTRL; /**< Timer Channel Control Register, array offset: 0xC, array step: 0x20 */
|
|
__IO uint16_t SCTRL; /**< Timer Channel Status and Control Register, array offset: 0xE, array step: 0x20 */
|
|
__IO uint16_t CMPLD1; /**< Timer Channel Comparator Load Register 1, array offset: 0x10, array step: 0x20 */
|
|
__IO uint16_t CMPLD2; /**< Timer Channel Comparator Load Register 2, array offset: 0x12, array step: 0x20 */
|
|
__IO uint16_t CSCTRL; /**< Timer Channel Comparator Status and Control Register, array offset: 0x14, array step: 0x20 */
|
|
__IO uint16_t FILT; /**< Timer Channel Input Filter Register, array offset: 0x16, array step: 0x20 */
|
|
__IO uint16_t DMA; /**< Timer Channel DMA Enable Register, array offset: 0x18, array step: 0x20 */
|
|
uint8_t RESERVED_0[4];
|
|
__IO uint16_t ENBL; /**< Timer Channel Enable Register, array offset: 0x1E, array step: 0x20, this item is not available for all array instances */
|
|
} CHANNEL[4];
|
|
} TMR_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- TMR Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup TMR_Register_Masks TMR Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name COMP1 - Timer Channel Compare Register 1 */
|
|
/*! @{ */
|
|
#define TMR_COMP1_COMPARISON_1_MASK (0xFFFFU)
|
|
#define TMR_COMP1_COMPARISON_1_SHIFT (0U)
|
|
#define TMR_COMP1_COMPARISON_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP1_COMPARISON_1_SHIFT)) & TMR_COMP1_COMPARISON_1_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of TMR_COMP1 */
|
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#define TMR_COMP1_COUNT (4U)
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/*! @name COMP2 - Timer Channel Compare Register 2 */
|
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/*! @{ */
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#define TMR_COMP2_COMPARISON_2_MASK (0xFFFFU)
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#define TMR_COMP2_COMPARISON_2_SHIFT (0U)
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#define TMR_COMP2_COMPARISON_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP2_COMPARISON_2_SHIFT)) & TMR_COMP2_COMPARISON_2_MASK)
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/*! @} */
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/* The count of TMR_COMP2 */
|
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#define TMR_COMP2_COUNT (4U)
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|
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/*! @name CAPT - Timer Channel Capture Register */
|
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/*! @{ */
|
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#define TMR_CAPT_CAPTURE_MASK (0xFFFFU)
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#define TMR_CAPT_CAPTURE_SHIFT (0U)
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#define TMR_CAPT_CAPTURE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CAPT_CAPTURE_SHIFT)) & TMR_CAPT_CAPTURE_MASK)
|
|
/*! @} */
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|
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/* The count of TMR_CAPT */
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#define TMR_CAPT_COUNT (4U)
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/*! @name LOAD - Timer Channel Load Register */
|
|
/*! @{ */
|
|
#define TMR_LOAD_LOAD_MASK (0xFFFFU)
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#define TMR_LOAD_LOAD_SHIFT (0U)
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#define TMR_LOAD_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_LOAD_LOAD_SHIFT)) & TMR_LOAD_LOAD_MASK)
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/*! @} */
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|
|
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/* The count of TMR_LOAD */
|
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#define TMR_LOAD_COUNT (4U)
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/*! @name HOLD - Timer Channel Hold Register */
|
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/*! @{ */
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#define TMR_HOLD_HOLD_MASK (0xFFFFU)
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#define TMR_HOLD_HOLD_SHIFT (0U)
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#define TMR_HOLD_HOLD(x) (((uint16_t)(((uint16_t)(x)) << TMR_HOLD_HOLD_SHIFT)) & TMR_HOLD_HOLD_MASK)
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|
/*! @} */
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/* The count of TMR_HOLD */
|
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#define TMR_HOLD_COUNT (4U)
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/*! @name CNTR - Timer Channel Counter Register */
|
|
/*! @{ */
|
|
#define TMR_CNTR_COUNTER_MASK (0xFFFFU)
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#define TMR_CNTR_COUNTER_SHIFT (0U)
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#define TMR_CNTR_COUNTER(x) (((uint16_t)(((uint16_t)(x)) << TMR_CNTR_COUNTER_SHIFT)) & TMR_CNTR_COUNTER_MASK)
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/*! @} */
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|
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/* The count of TMR_CNTR */
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#define TMR_CNTR_COUNT (4U)
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|
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/*! @name CTRL - Timer Channel Control Register */
|
|
/*! @{ */
|
|
#define TMR_CTRL_OUTMODE_MASK (0x7U)
|
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#define TMR_CTRL_OUTMODE_SHIFT (0U)
|
|
/*! OUTMODE - Output Mode
|
|
* 0b000..Asserted while counter is active
|
|
* 0b001..Clear OFLAG output on successful compare
|
|
* 0b010..Set OFLAG output on successful compare
|
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* 0b011..Toggle OFLAG output on successful compare
|
|
* 0b100..Toggle OFLAG output using alternating compare registers
|
|
* 0b101..Set on compare, cleared on secondary source input edge
|
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* 0b110..Set on compare, cleared on counter rollover
|
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* 0b111..Enable gated clock output while counter is active
|
|
*/
|
|
#define TMR_CTRL_OUTMODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK)
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#define TMR_CTRL_COINIT_MASK (0x8U)
|
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#define TMR_CTRL_COINIT_SHIFT (3U)
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|
/*! COINIT - Co-Channel Initialization
|
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* 0b0..Co-channel counter/timers cannot force a re-initialization of this counter/timer
|
|
* 0b1..Co-channel counter/timers may force a re-initialization of this counter/timer
|
|
*/
|
|
#define TMR_CTRL_COINIT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_COINIT_SHIFT)) & TMR_CTRL_COINIT_MASK)
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#define TMR_CTRL_DIR_MASK (0x10U)
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#define TMR_CTRL_DIR_SHIFT (4U)
|
|
/*! DIR - Count Direction
|
|
* 0b0..Count up.
|
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* 0b1..Count down.
|
|
*/
|
|
#define TMR_CTRL_DIR(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_DIR_SHIFT)) & TMR_CTRL_DIR_MASK)
|
|
#define TMR_CTRL_LENGTH_MASK (0x20U)
|
|
#define TMR_CTRL_LENGTH_SHIFT (5U)
|
|
/*! LENGTH - Count Length
|
|
* 0b0..Count until roll over at $FFFF and continue from $0000.
|
|
* 0b1..Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2 value is reached, re-initializes, counts until COMP1 value is reached, and so on.
|
|
*/
|
|
#define TMR_CTRL_LENGTH(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_LENGTH_SHIFT)) & TMR_CTRL_LENGTH_MASK)
|
|
#define TMR_CTRL_ONCE_MASK (0x40U)
|
|
#define TMR_CTRL_ONCE_SHIFT (6U)
|
|
/*! ONCE - Count Once
|
|
* 0b0..Count repeatedly.
|
|
* 0b1..Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to the COMP2 value, and then stops.
|
|
*/
|
|
#define TMR_CTRL_ONCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_ONCE_SHIFT)) & TMR_CTRL_ONCE_MASK)
|
|
#define TMR_CTRL_SCS_MASK (0x180U)
|
|
#define TMR_CTRL_SCS_SHIFT (7U)
|
|
/*! SCS - Secondary Count Source
|
|
* 0b00..Counter 0 input pin
|
|
* 0b01..Counter 1 input pin
|
|
* 0b10..Counter 2 input pin
|
|
* 0b11..Counter 3 input pin
|
|
*/
|
|
#define TMR_CTRL_SCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_SCS_SHIFT)) & TMR_CTRL_SCS_MASK)
|
|
#define TMR_CTRL_PCS_MASK (0x1E00U)
|
|
#define TMR_CTRL_PCS_SHIFT (9U)
|
|
/*! PCS - Primary Count Source
|
|
* 0b0000..Counter 0 input pin
|
|
* 0b0001..Counter 1 input pin
|
|
* 0b0010..Counter 2 input pin
|
|
* 0b0011..Counter 3 input pin
|
|
* 0b0100..Counter 0 output
|
|
* 0b0101..Counter 1 output
|
|
* 0b0110..Counter 2 output
|
|
* 0b0111..Counter 3 output
|
|
* 0b1000..IP bus clock divide by 1 prescaler
|
|
* 0b1001..IP bus clock divide by 2 prescaler
|
|
* 0b1010..IP bus clock divide by 4 prescaler
|
|
* 0b1011..IP bus clock divide by 8 prescaler
|
|
* 0b1100..IP bus clock divide by 16 prescaler
|
|
* 0b1101..IP bus clock divide by 32 prescaler
|
|
* 0b1110..IP bus clock divide by 64 prescaler
|
|
* 0b1111..IP bus clock divide by 128 prescaler
|
|
*/
|
|
#define TMR_CTRL_PCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_PCS_SHIFT)) & TMR_CTRL_PCS_MASK)
|
|
#define TMR_CTRL_CM_MASK (0xE000U)
|
|
#define TMR_CTRL_CM_SHIFT (13U)
|
|
/*! CM - Count Mode
|
|
* 0b000..No operation
|
|
* 0b001..Count rising edges of primary sourceRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. If the primary count source is IP bus clock divide by 1, only rising edges are counted regardless of the value of SCTRL[IPS].
|
|
* 0b010..Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode.
|
|
* 0b011..Count rising edges of primary source while secondary input high active
|
|
* 0b100..Quadrature count mode, uses primary and secondary sources
|
|
* 0b101..Count rising edges of primary source; secondary source specifies directionRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1.
|
|
* 0b110..Edge of secondary source triggers primary count until compare
|
|
* 0b111..Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs.
|
|
*/
|
|
#define TMR_CTRL_CM(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_CM_SHIFT)) & TMR_CTRL_CM_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of TMR_CTRL */
|
|
#define TMR_CTRL_COUNT (4U)
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|
|
|
/*! @name SCTRL - Timer Channel Status and Control Register */
|
|
/*! @{ */
|
|
#define TMR_SCTRL_OEN_MASK (0x1U)
|
|
#define TMR_SCTRL_OEN_SHIFT (0U)
|
|
/*! OEN - Output Enable
|
|
* 0b0..The external pin is configured as an input.
|
|
* 0b1..The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as their input see the driven value. The polarity of the signal is determined by OPS.
|
|
*/
|
|
#define TMR_SCTRL_OEN(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK)
|
|
#define TMR_SCTRL_OPS_MASK (0x2U)
|
|
#define TMR_SCTRL_OPS_SHIFT (1U)
|
|
/*! OPS - Output Polarity Select
|
|
* 0b0..True polarity.
|
|
* 0b1..Inverted polarity.
|
|
*/
|
|
#define TMR_SCTRL_OPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OPS_SHIFT)) & TMR_SCTRL_OPS_MASK)
|
|
#define TMR_SCTRL_FORCE_MASK (0x4U)
|
|
#define TMR_SCTRL_FORCE_SHIFT (2U)
|
|
#define TMR_SCTRL_FORCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_FORCE_SHIFT)) & TMR_SCTRL_FORCE_MASK)
|
|
#define TMR_SCTRL_VAL_MASK (0x8U)
|
|
#define TMR_SCTRL_VAL_SHIFT (3U)
|
|
#define TMR_SCTRL_VAL(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_VAL_SHIFT)) & TMR_SCTRL_VAL_MASK)
|
|
#define TMR_SCTRL_EEOF_MASK (0x10U)
|
|
#define TMR_SCTRL_EEOF_SHIFT (4U)
|
|
#define TMR_SCTRL_EEOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_EEOF_SHIFT)) & TMR_SCTRL_EEOF_MASK)
|
|
#define TMR_SCTRL_MSTR_MASK (0x20U)
|
|
#define TMR_SCTRL_MSTR_SHIFT (5U)
|
|
#define TMR_SCTRL_MSTR(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_MSTR_SHIFT)) & TMR_SCTRL_MSTR_MASK)
|
|
#define TMR_SCTRL_CAPTURE_MODE_MASK (0xC0U)
|
|
#define TMR_SCTRL_CAPTURE_MODE_SHIFT (6U)
|
|
/*! CAPTURE_MODE - Input Capture Mode
|
|
* 0b00..Capture function is disabled
|
|
* 0b01..Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input
|
|
* 0b10..Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input
|
|
* 0b11..Load capture register on both edges of input
|
|
*/
|
|
#define TMR_SCTRL_CAPTURE_MODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_CAPTURE_MODE_SHIFT)) & TMR_SCTRL_CAPTURE_MODE_MASK)
|
|
#define TMR_SCTRL_INPUT_MASK (0x100U)
|
|
#define TMR_SCTRL_INPUT_SHIFT (8U)
|
|
#define TMR_SCTRL_INPUT(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_INPUT_SHIFT)) & TMR_SCTRL_INPUT_MASK)
|
|
#define TMR_SCTRL_IPS_MASK (0x200U)
|
|
#define TMR_SCTRL_IPS_SHIFT (9U)
|
|
#define TMR_SCTRL_IPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IPS_SHIFT)) & TMR_SCTRL_IPS_MASK)
|
|
#define TMR_SCTRL_IEFIE_MASK (0x400U)
|
|
#define TMR_SCTRL_IEFIE_SHIFT (10U)
|
|
#define TMR_SCTRL_IEFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEFIE_SHIFT)) & TMR_SCTRL_IEFIE_MASK)
|
|
#define TMR_SCTRL_IEF_MASK (0x800U)
|
|
#define TMR_SCTRL_IEF_SHIFT (11U)
|
|
#define TMR_SCTRL_IEF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEF_SHIFT)) & TMR_SCTRL_IEF_MASK)
|
|
#define TMR_SCTRL_TOFIE_MASK (0x1000U)
|
|
#define TMR_SCTRL_TOFIE_SHIFT (12U)
|
|
#define TMR_SCTRL_TOFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOFIE_SHIFT)) & TMR_SCTRL_TOFIE_MASK)
|
|
#define TMR_SCTRL_TOF_MASK (0x2000U)
|
|
#define TMR_SCTRL_TOF_SHIFT (13U)
|
|
#define TMR_SCTRL_TOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOF_SHIFT)) & TMR_SCTRL_TOF_MASK)
|
|
#define TMR_SCTRL_TCFIE_MASK (0x4000U)
|
|
#define TMR_SCTRL_TCFIE_SHIFT (14U)
|
|
#define TMR_SCTRL_TCFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCFIE_SHIFT)) & TMR_SCTRL_TCFIE_MASK)
|
|
#define TMR_SCTRL_TCF_MASK (0x8000U)
|
|
#define TMR_SCTRL_TCF_SHIFT (15U)
|
|
#define TMR_SCTRL_TCF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCF_SHIFT)) & TMR_SCTRL_TCF_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of TMR_SCTRL */
|
|
#define TMR_SCTRL_COUNT (4U)
|
|
|
|
/*! @name CMPLD1 - Timer Channel Comparator Load Register 1 */
|
|
/*! @{ */
|
|
#define TMR_CMPLD1_COMPARATOR_LOAD_1_MASK (0xFFFFU)
|
|
#define TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT (0U)
|
|
#define TMR_CMPLD1_COMPARATOR_LOAD_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT)) & TMR_CMPLD1_COMPARATOR_LOAD_1_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of TMR_CMPLD1 */
|
|
#define TMR_CMPLD1_COUNT (4U)
|
|
|
|
/*! @name CMPLD2 - Timer Channel Comparator Load Register 2 */
|
|
/*! @{ */
|
|
#define TMR_CMPLD2_COMPARATOR_LOAD_2_MASK (0xFFFFU)
|
|
#define TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT (0U)
|
|
#define TMR_CMPLD2_COMPARATOR_LOAD_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT)) & TMR_CMPLD2_COMPARATOR_LOAD_2_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of TMR_CMPLD2 */
|
|
#define TMR_CMPLD2_COUNT (4U)
|
|
|
|
/*! @name CSCTRL - Timer Channel Comparator Status and Control Register */
|
|
/*! @{ */
|
|
#define TMR_CSCTRL_CL1_MASK (0x3U)
|
|
#define TMR_CSCTRL_CL1_SHIFT (0U)
|
|
/*! CL1 - Compare Load Control 1
|
|
* 0b00..Never preload
|
|
* 0b01..Load upon successful compare with the value in COMP1
|
|
* 0b10..Load upon successful compare with the value in COMP2
|
|
* 0b11..Reserved
|
|
*/
|
|
#define TMR_CSCTRL_CL1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK)
|
|
#define TMR_CSCTRL_CL2_MASK (0xCU)
|
|
#define TMR_CSCTRL_CL2_SHIFT (2U)
|
|
/*! CL2 - Compare Load Control 2
|
|
* 0b00..Never preload
|
|
* 0b01..Load upon successful compare with the value in COMP1
|
|
* 0b10..Load upon successful compare with the value in COMP2
|
|
* 0b11..Reserved
|
|
*/
|
|
#define TMR_CSCTRL_CL2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL2_SHIFT)) & TMR_CSCTRL_CL2_MASK)
|
|
#define TMR_CSCTRL_TCF1_MASK (0x10U)
|
|
#define TMR_CSCTRL_TCF1_SHIFT (4U)
|
|
#define TMR_CSCTRL_TCF1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1_SHIFT)) & TMR_CSCTRL_TCF1_MASK)
|
|
#define TMR_CSCTRL_TCF2_MASK (0x20U)
|
|
#define TMR_CSCTRL_TCF2_SHIFT (5U)
|
|
#define TMR_CSCTRL_TCF2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2_SHIFT)) & TMR_CSCTRL_TCF2_MASK)
|
|
#define TMR_CSCTRL_TCF1EN_MASK (0x40U)
|
|
#define TMR_CSCTRL_TCF1EN_SHIFT (6U)
|
|
#define TMR_CSCTRL_TCF1EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1EN_SHIFT)) & TMR_CSCTRL_TCF1EN_MASK)
|
|
#define TMR_CSCTRL_TCF2EN_MASK (0x80U)
|
|
#define TMR_CSCTRL_TCF2EN_SHIFT (7U)
|
|
#define TMR_CSCTRL_TCF2EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2EN_SHIFT)) & TMR_CSCTRL_TCF2EN_MASK)
|
|
#define TMR_CSCTRL_UP_MASK (0x200U)
|
|
#define TMR_CSCTRL_UP_SHIFT (9U)
|
|
/*! UP - Counting Direction Indicator
|
|
* 0b0..The last count was in the DOWN direction.
|
|
* 0b1..The last count was in the UP direction.
|
|
*/
|
|
#define TMR_CSCTRL_UP(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_UP_SHIFT)) & TMR_CSCTRL_UP_MASK)
|
|
#define TMR_CSCTRL_TCI_MASK (0x400U)
|
|
#define TMR_CSCTRL_TCI_SHIFT (10U)
|
|
/*! TCI - Triggered Count Initialization Control
|
|
* 0b0..Stop counter upon receiving a second trigger event while still counting from the first trigger event.
|
|
* 0b1..Reload the counter upon receiving a second trigger event while still counting from the first trigger event.
|
|
*/
|
|
#define TMR_CSCTRL_TCI(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCI_SHIFT)) & TMR_CSCTRL_TCI_MASK)
|
|
#define TMR_CSCTRL_ROC_MASK (0x800U)
|
|
#define TMR_CSCTRL_ROC_SHIFT (11U)
|
|
/*! ROC - Reload on Capture
|
|
* 0b0..Do not reload the counter on a capture event.
|
|
* 0b1..Reload the counter on a capture event.
|
|
*/
|
|
#define TMR_CSCTRL_ROC(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ROC_SHIFT)) & TMR_CSCTRL_ROC_MASK)
|
|
#define TMR_CSCTRL_ALT_LOAD_MASK (0x1000U)
|
|
#define TMR_CSCTRL_ALT_LOAD_SHIFT (12U)
|
|
/*! ALT_LOAD - Alternative Load Enable
|
|
* 0b0..Counter can be re-initialized only with the LOAD register.
|
|
* 0b1..Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction.
|
|
*/
|
|
#define TMR_CSCTRL_ALT_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ALT_LOAD_SHIFT)) & TMR_CSCTRL_ALT_LOAD_MASK)
|
|
#define TMR_CSCTRL_FAULT_MASK (0x2000U)
|
|
#define TMR_CSCTRL_FAULT_SHIFT (13U)
|
|
/*! FAULT - Fault Enable
|
|
* 0b0..Fault function disabled.
|
|
* 0b1..Fault function enabled.
|
|
*/
|
|
#define TMR_CSCTRL_FAULT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
|
|
#define TMR_CSCTRL_DBG_EN_MASK (0xC000U)
|
|
#define TMR_CSCTRL_DBG_EN_SHIFT (14U)
|
|
/*! DBG_EN - Debug Actions Enable
|
|
* 0b00..Continue with normal operation during debug mode. (default)
|
|
* 0b01..Halt TMR counter during debug mode.
|
|
* 0b10..Force TMR output to logic 0 (prior to consideration of SCTRL[OPS]).
|
|
* 0b11..Both halt counter and force output to 0 during debug mode.
|
|
*/
|
|
#define TMR_CSCTRL_DBG_EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_DBG_EN_SHIFT)) & TMR_CSCTRL_DBG_EN_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of TMR_CSCTRL */
|
|
#define TMR_CSCTRL_COUNT (4U)
|
|
|
|
/*! @name FILT - Timer Channel Input Filter Register */
|
|
/*! @{ */
|
|
#define TMR_FILT_FILT_PER_MASK (0xFFU)
|
|
#define TMR_FILT_FILT_PER_SHIFT (0U)
|
|
#define TMR_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_PER_SHIFT)) & TMR_FILT_FILT_PER_MASK)
|
|
#define TMR_FILT_FILT_CNT_MASK (0x700U)
|
|
#define TMR_FILT_FILT_CNT_SHIFT (8U)
|
|
#define TMR_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_CNT_SHIFT)) & TMR_FILT_FILT_CNT_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of TMR_FILT */
|
|
#define TMR_FILT_COUNT (4U)
|
|
|
|
/*! @name DMA - Timer Channel DMA Enable Register */
|
|
/*! @{ */
|
|
#define TMR_DMA_IEFDE_MASK (0x1U)
|
|
#define TMR_DMA_IEFDE_SHIFT (0U)
|
|
#define TMR_DMA_IEFDE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_IEFDE_SHIFT)) & TMR_DMA_IEFDE_MASK)
|
|
#define TMR_DMA_CMPLD1DE_MASK (0x2U)
|
|
#define TMR_DMA_CMPLD1DE_SHIFT (1U)
|
|
#define TMR_DMA_CMPLD1DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD1DE_SHIFT)) & TMR_DMA_CMPLD1DE_MASK)
|
|
#define TMR_DMA_CMPLD2DE_MASK (0x4U)
|
|
#define TMR_DMA_CMPLD2DE_SHIFT (2U)
|
|
#define TMR_DMA_CMPLD2DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD2DE_SHIFT)) & TMR_DMA_CMPLD2DE_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of TMR_DMA */
|
|
#define TMR_DMA_COUNT (4U)
|
|
|
|
/*! @name ENBL - Timer Channel Enable Register */
|
|
/*! @{ */
|
|
#define TMR_ENBL_ENBL_MASK (0xFU)
|
|
#define TMR_ENBL_ENBL_SHIFT (0U)
|
|
/*! ENBL - Timer Channel Enable
|
|
* 0b0000..Timer channel is disabled.
|
|
* 0b0001..Timer channel is enabled. (default)
|
|
*/
|
|
#define TMR_ENBL_ENBL(x) (((uint16_t)(((uint16_t)(x)) << TMR_ENBL_ENBL_SHIFT)) & TMR_ENBL_ENBL_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of TMR_ENBL */
|
|
#define TMR_ENBL_COUNT (4U)
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group TMR_Register_Masks */
|
|
|
|
|
|
/* TMR - Peripheral instance base addresses */
|
|
/** Peripheral TMR1 base address */
|
|
#define TMR1_BASE (0x401DC000u)
|
|
/** Peripheral TMR1 base pointer */
|
|
#define TMR1 ((TMR_Type *)TMR1_BASE)
|
|
/** Peripheral TMR2 base address */
|
|
#define TMR2_BASE (0x401E0000u)
|
|
/** Peripheral TMR2 base pointer */
|
|
#define TMR2 ((TMR_Type *)TMR2_BASE)
|
|
/** Peripheral TMR3 base address */
|
|
#define TMR3_BASE (0x401E4000u)
|
|
/** Peripheral TMR3 base pointer */
|
|
#define TMR3 ((TMR_Type *)TMR3_BASE)
|
|
/** Peripheral TMR4 base address */
|
|
#define TMR4_BASE (0x401E8000u)
|
|
/** Peripheral TMR4 base pointer */
|
|
#define TMR4 ((TMR_Type *)TMR4_BASE)
|
|
/** Array initializer of TMR peripheral base addresses */
|
|
#define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
|
|
/** Array initializer of TMR peripheral base pointers */
|
|
#define TMR_BASE_PTRS { (TMR_Type *)0u, TMR1, TMR2, TMR3, TMR4 }
|
|
/** Interrupt vectors for the TMR peripheral type */
|
|
#define TMR_IRQS { NotAvail_IRQn, TMR1_IRQn, TMR2_IRQn, TMR3_IRQn, TMR4_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group TMR_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- TRNG Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup TRNG_Peripheral_Access_Layer TRNG Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** TRNG - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t MCTL; /**< Miscellaneous Control Register, offset: 0x0 */
|
|
__IO uint32_t SCMISC; /**< Statistical Check Miscellaneous Register, offset: 0x4 */
|
|
__IO uint32_t PKRRNG; /**< Poker Range Register, offset: 0x8 */
|
|
union { /* offset: 0xC */
|
|
__IO uint32_t PKRMAX; /**< Poker Maximum Limit Register, offset: 0xC */
|
|
__I uint32_t PKRSQ; /**< Poker Square Calculation Result Register, offset: 0xC */
|
|
};
|
|
__IO uint32_t SDCTL; /**< Seed Control Register, offset: 0x10 */
|
|
union { /* offset: 0x14 */
|
|
__IO uint32_t SBLIM; /**< Sparse Bit Limit Register, offset: 0x14 */
|
|
__I uint32_t TOTSAM; /**< Total Samples Register, offset: 0x14 */
|
|
};
|
|
__IO uint32_t FRQMIN; /**< Frequency Count Minimum Limit Register, offset: 0x18 */
|
|
union { /* offset: 0x1C */
|
|
__I uint32_t FRQCNT; /**< Frequency Count Register, offset: 0x1C */
|
|
__IO uint32_t FRQMAX; /**< Frequency Count Maximum Limit Register, offset: 0x1C */
|
|
};
|
|
union { /* offset: 0x20 */
|
|
__I uint32_t SCMC; /**< Statistical Check Monobit Count Register, offset: 0x20 */
|
|
__IO uint32_t SCML; /**< Statistical Check Monobit Limit Register, offset: 0x20 */
|
|
};
|
|
union { /* offset: 0x24 */
|
|
__I uint32_t SCR1C; /**< Statistical Check Run Length 1 Count Register, offset: 0x24 */
|
|
__IO uint32_t SCR1L; /**< Statistical Check Run Length 1 Limit Register, offset: 0x24 */
|
|
};
|
|
union { /* offset: 0x28 */
|
|
__I uint32_t SCR2C; /**< Statistical Check Run Length 2 Count Register, offset: 0x28 */
|
|
__IO uint32_t SCR2L; /**< Statistical Check Run Length 2 Limit Register, offset: 0x28 */
|
|
};
|
|
union { /* offset: 0x2C */
|
|
__I uint32_t SCR3C; /**< Statistical Check Run Length 3 Count Register, offset: 0x2C */
|
|
__IO uint32_t SCR3L; /**< Statistical Check Run Length 3 Limit Register, offset: 0x2C */
|
|
};
|
|
union { /* offset: 0x30 */
|
|
__I uint32_t SCR4C; /**< Statistical Check Run Length 4 Count Register, offset: 0x30 */
|
|
__IO uint32_t SCR4L; /**< Statistical Check Run Length 4 Limit Register, offset: 0x30 */
|
|
};
|
|
union { /* offset: 0x34 */
|
|
__I uint32_t SCR5C; /**< Statistical Check Run Length 5 Count Register, offset: 0x34 */
|
|
__IO uint32_t SCR5L; /**< Statistical Check Run Length 5 Limit Register, offset: 0x34 */
|
|
};
|
|
union { /* offset: 0x38 */
|
|
__I uint32_t SCR6PC; /**< Statistical Check Run Length 6+ Count Register, offset: 0x38 */
|
|
__IO uint32_t SCR6PL; /**< Statistical Check Run Length 6+ Limit Register, offset: 0x38 */
|
|
};
|
|
__I uint32_t STATUS; /**< Status Register, offset: 0x3C */
|
|
__I uint32_t ENT[16]; /**< Entropy Read Register, array offset: 0x40, array step: 0x4 */
|
|
__I uint32_t PKRCNT10; /**< Statistical Check Poker Count 1 and 0 Register, offset: 0x80 */
|
|
__I uint32_t PKRCNT32; /**< Statistical Check Poker Count 3 and 2 Register, offset: 0x84 */
|
|
__I uint32_t PKRCNT54; /**< Statistical Check Poker Count 5 and 4 Register, offset: 0x88 */
|
|
__I uint32_t PKRCNT76; /**< Statistical Check Poker Count 7 and 6 Register, offset: 0x8C */
|
|
__I uint32_t PKRCNT98; /**< Statistical Check Poker Count 9 and 8 Register, offset: 0x90 */
|
|
__I uint32_t PKRCNTBA; /**< Statistical Check Poker Count B and A Register, offset: 0x94 */
|
|
__I uint32_t PKRCNTDC; /**< Statistical Check Poker Count D and C Register, offset: 0x98 */
|
|
__I uint32_t PKRCNTFE; /**< Statistical Check Poker Count F and E Register, offset: 0x9C */
|
|
__IO uint32_t SEC_CFG; /**< Security Configuration Register, offset: 0xA0 */
|
|
__IO uint32_t INT_CTRL; /**< Interrupt Control Register, offset: 0xA4 */
|
|
__IO uint32_t INT_MASK; /**< Mask Register, offset: 0xA8 */
|
|
__I uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0xAC */
|
|
uint8_t RESERVED_0[64];
|
|
__I uint32_t VID1; /**< Version ID Register (MS), offset: 0xF0 */
|
|
__I uint32_t VID2; /**< Version ID Register (LS), offset: 0xF4 */
|
|
} TRNG_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- TRNG Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup TRNG_Register_Masks TRNG Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name MCTL - Miscellaneous Control Register */
|
|
/*! @{ */
|
|
#define TRNG_MCTL_SAMP_MODE_MASK (0x3U)
|
|
#define TRNG_MCTL_SAMP_MODE_SHIFT (0U)
|
|
/*! SAMP_MODE
|
|
* 0b00..use Von Neumann data into both Entropy shifter and Statistical Checker
|
|
* 0b01..use raw data into both Entropy shifter and Statistical Checker
|
|
* 0b10..use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker
|
|
* 0b11..undefined/reserved.
|
|
*/
|
|
#define TRNG_MCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK)
|
|
#define TRNG_MCTL_OSC_DIV_MASK (0xCU)
|
|
#define TRNG_MCTL_OSC_DIV_SHIFT (2U)
|
|
/*! OSC_DIV
|
|
* 0b00..use ring oscillator with no divide
|
|
* 0b01..use ring oscillator divided-by-2
|
|
* 0b10..use ring oscillator divided-by-4
|
|
* 0b11..use ring oscillator divided-by-8
|
|
*/
|
|
#define TRNG_MCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK)
|
|
#define TRNG_MCTL_UNUSED4_MASK (0x10U)
|
|
#define TRNG_MCTL_UNUSED4_SHIFT (4U)
|
|
#define TRNG_MCTL_UNUSED4(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED4_SHIFT)) & TRNG_MCTL_UNUSED4_MASK)
|
|
#define TRNG_MCTL_UNUSED5_MASK (0x20U)
|
|
#define TRNG_MCTL_UNUSED5_SHIFT (5U)
|
|
#define TRNG_MCTL_UNUSED5(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED5_SHIFT)) & TRNG_MCTL_UNUSED5_MASK)
|
|
#define TRNG_MCTL_RST_DEF_MASK (0x40U)
|
|
#define TRNG_MCTL_RST_DEF_SHIFT (6U)
|
|
#define TRNG_MCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK)
|
|
#define TRNG_MCTL_FOR_SCLK_MASK (0x80U)
|
|
#define TRNG_MCTL_FOR_SCLK_SHIFT (7U)
|
|
#define TRNG_MCTL_FOR_SCLK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK)
|
|
#define TRNG_MCTL_FCT_FAIL_MASK (0x100U)
|
|
#define TRNG_MCTL_FCT_FAIL_SHIFT (8U)
|
|
#define TRNG_MCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK)
|
|
#define TRNG_MCTL_FCT_VAL_MASK (0x200U)
|
|
#define TRNG_MCTL_FCT_VAL_SHIFT (9U)
|
|
#define TRNG_MCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK)
|
|
#define TRNG_MCTL_ENT_VAL_MASK (0x400U)
|
|
#define TRNG_MCTL_ENT_VAL_SHIFT (10U)
|
|
#define TRNG_MCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK)
|
|
#define TRNG_MCTL_TST_OUT_MASK (0x800U)
|
|
#define TRNG_MCTL_TST_OUT_SHIFT (11U)
|
|
#define TRNG_MCTL_TST_OUT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK)
|
|
#define TRNG_MCTL_ERR_MASK (0x1000U)
|
|
#define TRNG_MCTL_ERR_SHIFT (12U)
|
|
#define TRNG_MCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK)
|
|
#define TRNG_MCTL_TSTOP_OK_MASK (0x2000U)
|
|
#define TRNG_MCTL_TSTOP_OK_SHIFT (13U)
|
|
#define TRNG_MCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK)
|
|
#define TRNG_MCTL_LRUN_CONT_MASK (0x4000U)
|
|
#define TRNG_MCTL_LRUN_CONT_SHIFT (14U)
|
|
#define TRNG_MCTL_LRUN_CONT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_LRUN_CONT_SHIFT)) & TRNG_MCTL_LRUN_CONT_MASK)
|
|
#define TRNG_MCTL_PRGM_MASK (0x10000U)
|
|
#define TRNG_MCTL_PRGM_SHIFT (16U)
|
|
#define TRNG_MCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SCMISC - Statistical Check Miscellaneous Register */
|
|
/*! @{ */
|
|
#define TRNG_SCMISC_LRUN_MAX_MASK (0xFFU)
|
|
#define TRNG_SCMISC_LRUN_MAX_SHIFT (0U)
|
|
#define TRNG_SCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK)
|
|
#define TRNG_SCMISC_RTY_CT_MASK (0xF0000U)
|
|
#define TRNG_SCMISC_RTY_CT_SHIFT (16U)
|
|
#define TRNG_SCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PKRRNG - Poker Range Register */
|
|
/*! @{ */
|
|
#define TRNG_PKRRNG_PKR_RNG_MASK (0xFFFFU)
|
|
#define TRNG_PKRRNG_PKR_RNG_SHIFT (0U)
|
|
#define TRNG_PKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PKRMAX - Poker Maximum Limit Register */
|
|
/*! @{ */
|
|
#define TRNG_PKRMAX_PKR_MAX_MASK (0xFFFFFFU)
|
|
#define TRNG_PKRMAX_PKR_MAX_SHIFT (0U)
|
|
#define TRNG_PKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PKRSQ - Poker Square Calculation Result Register */
|
|
/*! @{ */
|
|
#define TRNG_PKRSQ_PKR_SQ_MASK (0xFFFFFFU)
|
|
#define TRNG_PKRSQ_PKR_SQ_SHIFT (0U)
|
|
#define TRNG_PKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SDCTL - Seed Control Register */
|
|
/*! @{ */
|
|
#define TRNG_SDCTL_SAMP_SIZE_MASK (0xFFFFU)
|
|
#define TRNG_SDCTL_SAMP_SIZE_SHIFT (0U)
|
|
#define TRNG_SDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK)
|
|
#define TRNG_SDCTL_ENT_DLY_MASK (0xFFFF0000U)
|
|
#define TRNG_SDCTL_ENT_DLY_SHIFT (16U)
|
|
#define TRNG_SDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SBLIM - Sparse Bit Limit Register */
|
|
/*! @{ */
|
|
#define TRNG_SBLIM_SB_LIM_MASK (0x3FFU)
|
|
#define TRNG_SBLIM_SB_LIM_SHIFT (0U)
|
|
#define TRNG_SBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TOTSAM - Total Samples Register */
|
|
/*! @{ */
|
|
#define TRNG_TOTSAM_TOT_SAM_MASK (0xFFFFFU)
|
|
#define TRNG_TOTSAM_TOT_SAM_SHIFT (0U)
|
|
#define TRNG_TOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FRQMIN - Frequency Count Minimum Limit Register */
|
|
/*! @{ */
|
|
#define TRNG_FRQMIN_FRQ_MIN_MASK (0x3FFFFFU)
|
|
#define TRNG_FRQMIN_FRQ_MIN_SHIFT (0U)
|
|
#define TRNG_FRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FRQCNT - Frequency Count Register */
|
|
/*! @{ */
|
|
#define TRNG_FRQCNT_FRQ_CT_MASK (0x3FFFFFU)
|
|
#define TRNG_FRQCNT_FRQ_CT_SHIFT (0U)
|
|
#define TRNG_FRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FRQMAX - Frequency Count Maximum Limit Register */
|
|
/*! @{ */
|
|
#define TRNG_FRQMAX_FRQ_MAX_MASK (0x3FFFFFU)
|
|
#define TRNG_FRQMAX_FRQ_MAX_SHIFT (0U)
|
|
#define TRNG_FRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SCMC - Statistical Check Monobit Count Register */
|
|
/*! @{ */
|
|
#define TRNG_SCMC_MONO_CT_MASK (0xFFFFU)
|
|
#define TRNG_SCMC_MONO_CT_SHIFT (0U)
|
|
#define TRNG_SCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SCML - Statistical Check Monobit Limit Register */
|
|
/*! @{ */
|
|
#define TRNG_SCML_MONO_MAX_MASK (0xFFFFU)
|
|
#define TRNG_SCML_MONO_MAX_SHIFT (0U)
|
|
#define TRNG_SCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK)
|
|
#define TRNG_SCML_MONO_RNG_MASK (0xFFFF0000U)
|
|
#define TRNG_SCML_MONO_RNG_SHIFT (16U)
|
|
#define TRNG_SCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SCR1C - Statistical Check Run Length 1 Count Register */
|
|
/*! @{ */
|
|
#define TRNG_SCR1C_R1_0_CT_MASK (0x7FFFU)
|
|
#define TRNG_SCR1C_R1_0_CT_SHIFT (0U)
|
|
#define TRNG_SCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK)
|
|
#define TRNG_SCR1C_R1_1_CT_MASK (0x7FFF0000U)
|
|
#define TRNG_SCR1C_R1_1_CT_SHIFT (16U)
|
|
#define TRNG_SCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SCR1L - Statistical Check Run Length 1 Limit Register */
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/*! @{ */
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#define TRNG_SCR1L_RUN1_MAX_MASK (0x7FFFU)
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#define TRNG_SCR1L_RUN1_MAX_SHIFT (0U)
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#define TRNG_SCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK)
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#define TRNG_SCR1L_RUN1_RNG_MASK (0x7FFF0000U)
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#define TRNG_SCR1L_RUN1_RNG_SHIFT (16U)
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#define TRNG_SCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK)
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/*! @} */
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/*! @name SCR2C - Statistical Check Run Length 2 Count Register */
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/*! @{ */
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#define TRNG_SCR2C_R2_0_CT_MASK (0x3FFFU)
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#define TRNG_SCR2C_R2_0_CT_SHIFT (0U)
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#define TRNG_SCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK)
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#define TRNG_SCR2C_R2_1_CT_MASK (0x3FFF0000U)
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#define TRNG_SCR2C_R2_1_CT_SHIFT (16U)
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#define TRNG_SCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK)
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/*! @} */
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/*! @name SCR2L - Statistical Check Run Length 2 Limit Register */
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/*! @{ */
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#define TRNG_SCR2L_RUN2_MAX_MASK (0x3FFFU)
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#define TRNG_SCR2L_RUN2_MAX_SHIFT (0U)
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#define TRNG_SCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK)
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#define TRNG_SCR2L_RUN2_RNG_MASK (0x3FFF0000U)
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#define TRNG_SCR2L_RUN2_RNG_SHIFT (16U)
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#define TRNG_SCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK)
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/*! @} */
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/*! @name SCR3C - Statistical Check Run Length 3 Count Register */
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/*! @{ */
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#define TRNG_SCR3C_R3_0_CT_MASK (0x1FFFU)
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#define TRNG_SCR3C_R3_0_CT_SHIFT (0U)
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#define TRNG_SCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK)
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#define TRNG_SCR3C_R3_1_CT_MASK (0x1FFF0000U)
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#define TRNG_SCR3C_R3_1_CT_SHIFT (16U)
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#define TRNG_SCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK)
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/*! @} */
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/*! @name SCR3L - Statistical Check Run Length 3 Limit Register */
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/*! @{ */
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#define TRNG_SCR3L_RUN3_MAX_MASK (0x1FFFU)
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#define TRNG_SCR3L_RUN3_MAX_SHIFT (0U)
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#define TRNG_SCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK)
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#define TRNG_SCR3L_RUN3_RNG_MASK (0x1FFF0000U)
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#define TRNG_SCR3L_RUN3_RNG_SHIFT (16U)
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#define TRNG_SCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK)
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/*! @} */
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/*! @name SCR4C - Statistical Check Run Length 4 Count Register */
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/*! @{ */
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#define TRNG_SCR4C_R4_0_CT_MASK (0xFFFU)
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#define TRNG_SCR4C_R4_0_CT_SHIFT (0U)
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#define TRNG_SCR4C_R4_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK)
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#define TRNG_SCR4C_R4_1_CT_MASK (0xFFF0000U)
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#define TRNG_SCR4C_R4_1_CT_SHIFT (16U)
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#define TRNG_SCR4C_R4_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK)
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/*! @} */
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/*! @name SCR4L - Statistical Check Run Length 4 Limit Register */
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/*! @{ */
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#define TRNG_SCR4L_RUN4_MAX_MASK (0xFFFU)
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#define TRNG_SCR4L_RUN4_MAX_SHIFT (0U)
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#define TRNG_SCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK)
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#define TRNG_SCR4L_RUN4_RNG_MASK (0xFFF0000U)
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#define TRNG_SCR4L_RUN4_RNG_SHIFT (16U)
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#define TRNG_SCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK)
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/*! @} */
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/*! @name SCR5C - Statistical Check Run Length 5 Count Register */
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/*! @{ */
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#define TRNG_SCR5C_R5_0_CT_MASK (0x7FFU)
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#define TRNG_SCR5C_R5_0_CT_SHIFT (0U)
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#define TRNG_SCR5C_R5_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK)
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#define TRNG_SCR5C_R5_1_CT_MASK (0x7FF0000U)
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#define TRNG_SCR5C_R5_1_CT_SHIFT (16U)
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#define TRNG_SCR5C_R5_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK)
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/*! @} */
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/*! @name SCR5L - Statistical Check Run Length 5 Limit Register */
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/*! @{ */
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#define TRNG_SCR5L_RUN5_MAX_MASK (0x7FFU)
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#define TRNG_SCR5L_RUN5_MAX_SHIFT (0U)
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#define TRNG_SCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK)
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#define TRNG_SCR5L_RUN5_RNG_MASK (0x7FF0000U)
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#define TRNG_SCR5L_RUN5_RNG_SHIFT (16U)
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#define TRNG_SCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK)
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/*! @} */
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/*! @name SCR6PC - Statistical Check Run Length 6+ Count Register */
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/*! @{ */
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#define TRNG_SCR6PC_R6P_0_CT_MASK (0x7FFU)
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#define TRNG_SCR6PC_R6P_0_CT_SHIFT (0U)
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#define TRNG_SCR6PC_R6P_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK)
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#define TRNG_SCR6PC_R6P_1_CT_MASK (0x7FF0000U)
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#define TRNG_SCR6PC_R6P_1_CT_SHIFT (16U)
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#define TRNG_SCR6PC_R6P_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK)
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/*! @} */
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/*! @name SCR6PL - Statistical Check Run Length 6+ Limit Register */
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/*! @{ */
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#define TRNG_SCR6PL_RUN6P_MAX_MASK (0x7FFU)
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#define TRNG_SCR6PL_RUN6P_MAX_SHIFT (0U)
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#define TRNG_SCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK)
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#define TRNG_SCR6PL_RUN6P_RNG_MASK (0x7FF0000U)
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#define TRNG_SCR6PL_RUN6P_RNG_SHIFT (16U)
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#define TRNG_SCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK)
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/*! @} */
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/*! @name STATUS - Status Register */
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/*! @{ */
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#define TRNG_STATUS_TF1BR0_MASK (0x1U)
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#define TRNG_STATUS_TF1BR0_SHIFT (0U)
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#define TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK)
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#define TRNG_STATUS_TF1BR1_MASK (0x2U)
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#define TRNG_STATUS_TF1BR1_SHIFT (1U)
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#define TRNG_STATUS_TF1BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK)
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#define TRNG_STATUS_TF2BR0_MASK (0x4U)
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#define TRNG_STATUS_TF2BR0_SHIFT (2U)
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#define TRNG_STATUS_TF2BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK)
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#define TRNG_STATUS_TF2BR1_MASK (0x8U)
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#define TRNG_STATUS_TF2BR1_SHIFT (3U)
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#define TRNG_STATUS_TF2BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK)
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#define TRNG_STATUS_TF3BR0_MASK (0x10U)
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#define TRNG_STATUS_TF3BR0_SHIFT (4U)
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#define TRNG_STATUS_TF3BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK)
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#define TRNG_STATUS_TF3BR1_MASK (0x20U)
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#define TRNG_STATUS_TF3BR1_SHIFT (5U)
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#define TRNG_STATUS_TF3BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK)
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#define TRNG_STATUS_TF4BR0_MASK (0x40U)
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#define TRNG_STATUS_TF4BR0_SHIFT (6U)
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#define TRNG_STATUS_TF4BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK)
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#define TRNG_STATUS_TF4BR1_MASK (0x80U)
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#define TRNG_STATUS_TF4BR1_SHIFT (7U)
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#define TRNG_STATUS_TF4BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK)
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#define TRNG_STATUS_TF5BR0_MASK (0x100U)
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#define TRNG_STATUS_TF5BR0_SHIFT (8U)
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#define TRNG_STATUS_TF5BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK)
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#define TRNG_STATUS_TF5BR1_MASK (0x200U)
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#define TRNG_STATUS_TF5BR1_SHIFT (9U)
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#define TRNG_STATUS_TF5BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK)
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#define TRNG_STATUS_TF6PBR0_MASK (0x400U)
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#define TRNG_STATUS_TF6PBR0_SHIFT (10U)
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#define TRNG_STATUS_TF6PBR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK)
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#define TRNG_STATUS_TF6PBR1_MASK (0x800U)
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#define TRNG_STATUS_TF6PBR1_SHIFT (11U)
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#define TRNG_STATUS_TF6PBR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK)
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#define TRNG_STATUS_TFSB_MASK (0x1000U)
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#define TRNG_STATUS_TFSB_SHIFT (12U)
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#define TRNG_STATUS_TFSB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK)
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#define TRNG_STATUS_TFLR_MASK (0x2000U)
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#define TRNG_STATUS_TFLR_SHIFT (13U)
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#define TRNG_STATUS_TFLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK)
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#define TRNG_STATUS_TFP_MASK (0x4000U)
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#define TRNG_STATUS_TFP_SHIFT (14U)
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#define TRNG_STATUS_TFP(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK)
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#define TRNG_STATUS_TFMB_MASK (0x8000U)
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#define TRNG_STATUS_TFMB_SHIFT (15U)
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#define TRNG_STATUS_TFMB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK)
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#define TRNG_STATUS_RETRY_CT_MASK (0xF0000U)
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#define TRNG_STATUS_RETRY_CT_SHIFT (16U)
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#define TRNG_STATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK)
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/*! @} */
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/*! @name ENT - Entropy Read Register */
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/*! @{ */
|
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#define TRNG_ENT_ENT_MASK (0xFFFFFFFFU)
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#define TRNG_ENT_ENT_SHIFT (0U)
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#define TRNG_ENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK)
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/*! @} */
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/* The count of TRNG_ENT */
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#define TRNG_ENT_COUNT (16U)
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/*! @name PKRCNT10 - Statistical Check Poker Count 1 and 0 Register */
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/*! @{ */
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#define TRNG_PKRCNT10_PKR_0_CT_MASK (0xFFFFU)
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#define TRNG_PKRCNT10_PKR_0_CT_SHIFT (0U)
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#define TRNG_PKRCNT10_PKR_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK)
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#define TRNG_PKRCNT10_PKR_1_CT_MASK (0xFFFF0000U)
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#define TRNG_PKRCNT10_PKR_1_CT_SHIFT (16U)
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#define TRNG_PKRCNT10_PKR_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK)
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/*! @} */
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/*! @name PKRCNT32 - Statistical Check Poker Count 3 and 2 Register */
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/*! @{ */
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#define TRNG_PKRCNT32_PKR_2_CT_MASK (0xFFFFU)
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#define TRNG_PKRCNT32_PKR_2_CT_SHIFT (0U)
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#define TRNG_PKRCNT32_PKR_2_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK)
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#define TRNG_PKRCNT32_PKR_3_CT_MASK (0xFFFF0000U)
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#define TRNG_PKRCNT32_PKR_3_CT_SHIFT (16U)
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#define TRNG_PKRCNT32_PKR_3_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK)
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/*! @} */
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/*! @name PKRCNT54 - Statistical Check Poker Count 5 and 4 Register */
|
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/*! @{ */
|
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#define TRNG_PKRCNT54_PKR_4_CT_MASK (0xFFFFU)
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#define TRNG_PKRCNT54_PKR_4_CT_SHIFT (0U)
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#define TRNG_PKRCNT54_PKR_4_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK)
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#define TRNG_PKRCNT54_PKR_5_CT_MASK (0xFFFF0000U)
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#define TRNG_PKRCNT54_PKR_5_CT_SHIFT (16U)
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#define TRNG_PKRCNT54_PKR_5_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK)
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/*! @} */
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/*! @name PKRCNT76 - Statistical Check Poker Count 7 and 6 Register */
|
|
/*! @{ */
|
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#define TRNG_PKRCNT76_PKR_6_CT_MASK (0xFFFFU)
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#define TRNG_PKRCNT76_PKR_6_CT_SHIFT (0U)
|
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#define TRNG_PKRCNT76_PKR_6_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK)
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#define TRNG_PKRCNT76_PKR_7_CT_MASK (0xFFFF0000U)
|
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#define TRNG_PKRCNT76_PKR_7_CT_SHIFT (16U)
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#define TRNG_PKRCNT76_PKR_7_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK)
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/*! @} */
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/*! @name PKRCNT98 - Statistical Check Poker Count 9 and 8 Register */
|
|
/*! @{ */
|
|
#define TRNG_PKRCNT98_PKR_8_CT_MASK (0xFFFFU)
|
|
#define TRNG_PKRCNT98_PKR_8_CT_SHIFT (0U)
|
|
#define TRNG_PKRCNT98_PKR_8_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK)
|
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#define TRNG_PKRCNT98_PKR_9_CT_MASK (0xFFFF0000U)
|
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#define TRNG_PKRCNT98_PKR_9_CT_SHIFT (16U)
|
|
#define TRNG_PKRCNT98_PKR_9_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK)
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/*! @} */
|
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|
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/*! @name PKRCNTBA - Statistical Check Poker Count B and A Register */
|
|
/*! @{ */
|
|
#define TRNG_PKRCNTBA_PKR_A_CT_MASK (0xFFFFU)
|
|
#define TRNG_PKRCNTBA_PKR_A_CT_SHIFT (0U)
|
|
#define TRNG_PKRCNTBA_PKR_A_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK)
|
|
#define TRNG_PKRCNTBA_PKR_B_CT_MASK (0xFFFF0000U)
|
|
#define TRNG_PKRCNTBA_PKR_B_CT_SHIFT (16U)
|
|
#define TRNG_PKRCNTBA_PKR_B_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK)
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/*! @} */
|
|
|
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/*! @name PKRCNTDC - Statistical Check Poker Count D and C Register */
|
|
/*! @{ */
|
|
#define TRNG_PKRCNTDC_PKR_C_CT_MASK (0xFFFFU)
|
|
#define TRNG_PKRCNTDC_PKR_C_CT_SHIFT (0U)
|
|
#define TRNG_PKRCNTDC_PKR_C_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK)
|
|
#define TRNG_PKRCNTDC_PKR_D_CT_MASK (0xFFFF0000U)
|
|
#define TRNG_PKRCNTDC_PKR_D_CT_SHIFT (16U)
|
|
#define TRNG_PKRCNTDC_PKR_D_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK)
|
|
/*! @} */
|
|
|
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/*! @name PKRCNTFE - Statistical Check Poker Count F and E Register */
|
|
/*! @{ */
|
|
#define TRNG_PKRCNTFE_PKR_E_CT_MASK (0xFFFFU)
|
|
#define TRNG_PKRCNTFE_PKR_E_CT_SHIFT (0U)
|
|
#define TRNG_PKRCNTFE_PKR_E_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK)
|
|
#define TRNG_PKRCNTFE_PKR_F_CT_MASK (0xFFFF0000U)
|
|
#define TRNG_PKRCNTFE_PKR_F_CT_SHIFT (16U)
|
|
#define TRNG_PKRCNTFE_PKR_F_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEC_CFG - Security Configuration Register */
|
|
/*! @{ */
|
|
#define TRNG_SEC_CFG_UNUSED0_MASK (0x1U)
|
|
#define TRNG_SEC_CFG_UNUSED0_SHIFT (0U)
|
|
#define TRNG_SEC_CFG_UNUSED0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED0_SHIFT)) & TRNG_SEC_CFG_UNUSED0_MASK)
|
|
#define TRNG_SEC_CFG_NO_PRGM_MASK (0x2U)
|
|
#define TRNG_SEC_CFG_NO_PRGM_SHIFT (1U)
|
|
/*! NO_PRGM
|
|
* 0b0..Programability of registers controlled only by the Miscellaneous Control Register's access mode bit.
|
|
* 0b1..Overides Miscellaneous Control Register access mode and prevents TRNG register programming.
|
|
*/
|
|
#define TRNG_SEC_CFG_NO_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK)
|
|
#define TRNG_SEC_CFG_UNUSED2_MASK (0x4U)
|
|
#define TRNG_SEC_CFG_UNUSED2_SHIFT (2U)
|
|
#define TRNG_SEC_CFG_UNUSED2(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED2_SHIFT)) & TRNG_SEC_CFG_UNUSED2_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name INT_CTRL - Interrupt Control Register */
|
|
/*! @{ */
|
|
#define TRNG_INT_CTRL_HW_ERR_MASK (0x1U)
|
|
#define TRNG_INT_CTRL_HW_ERR_SHIFT (0U)
|
|
/*! HW_ERR
|
|
* 0b0..Corresponding bit of INT_STATUS register cleared.
|
|
* 0b1..Corresponding bit of INT_STATUS register active.
|
|
*/
|
|
#define TRNG_INT_CTRL_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK)
|
|
#define TRNG_INT_CTRL_ENT_VAL_MASK (0x2U)
|
|
#define TRNG_INT_CTRL_ENT_VAL_SHIFT (1U)
|
|
/*! ENT_VAL
|
|
* 0b0..Same behavior as bit 0 of this register.
|
|
* 0b1..Same behavior as bit 0 of this register.
|
|
*/
|
|
#define TRNG_INT_CTRL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK)
|
|
#define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK (0x4U)
|
|
#define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT (2U)
|
|
/*! FRQ_CT_FAIL
|
|
* 0b0..Same behavior as bit 0 of this register.
|
|
* 0b1..Same behavior as bit 0 of this register.
|
|
*/
|
|
#define TRNG_INT_CTRL_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK)
|
|
#define TRNG_INT_CTRL_UNUSED_MASK (0xFFFFFFF8U)
|
|
#define TRNG_INT_CTRL_UNUSED_SHIFT (3U)
|
|
#define TRNG_INT_CTRL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name INT_MASK - Mask Register */
|
|
/*! @{ */
|
|
#define TRNG_INT_MASK_HW_ERR_MASK (0x1U)
|
|
#define TRNG_INT_MASK_HW_ERR_SHIFT (0U)
|
|
/*! HW_ERR
|
|
* 0b0..Corresponding interrupt of INT_STATUS is masked.
|
|
* 0b1..Corresponding bit of INT_STATUS is active.
|
|
*/
|
|
#define TRNG_INT_MASK_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK)
|
|
#define TRNG_INT_MASK_ENT_VAL_MASK (0x2U)
|
|
#define TRNG_INT_MASK_ENT_VAL_SHIFT (1U)
|
|
/*! ENT_VAL
|
|
* 0b0..Same behavior as bit 0 of this register.
|
|
* 0b1..Same behavior as bit 0 of this register.
|
|
*/
|
|
#define TRNG_INT_MASK_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK)
|
|
#define TRNG_INT_MASK_FRQ_CT_FAIL_MASK (0x4U)
|
|
#define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT (2U)
|
|
/*! FRQ_CT_FAIL
|
|
* 0b0..Same behavior as bit 0 of this register.
|
|
* 0b1..Same behavior as bit 0 of this register.
|
|
*/
|
|
#define TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name INT_STATUS - Interrupt Status Register */
|
|
/*! @{ */
|
|
#define TRNG_INT_STATUS_HW_ERR_MASK (0x1U)
|
|
#define TRNG_INT_STATUS_HW_ERR_SHIFT (0U)
|
|
/*! HW_ERR
|
|
* 0b0..no error
|
|
* 0b1..error detected.
|
|
*/
|
|
#define TRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK)
|
|
#define TRNG_INT_STATUS_ENT_VAL_MASK (0x2U)
|
|
#define TRNG_INT_STATUS_ENT_VAL_SHIFT (1U)
|
|
/*! ENT_VAL
|
|
* 0b0..Busy generation entropy. Any value read is invalid.
|
|
* 0b1..TRNG can be stopped and entropy is valid if read.
|
|
*/
|
|
#define TRNG_INT_STATUS_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK)
|
|
#define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U)
|
|
#define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U)
|
|
/*! FRQ_CT_FAIL
|
|
* 0b0..No hardware nor self test frequency errors.
|
|
* 0b1..The frequency counter has detected a failure.
|
|
*/
|
|
#define TRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name VID1 - Version ID Register (MS) */
|
|
/*! @{ */
|
|
#define TRNG_VID1_MIN_REV_MASK (0xFFU)
|
|
#define TRNG_VID1_MIN_REV_SHIFT (0U)
|
|
/*! MIN_REV
|
|
* 0b00000000..Minor revision number for TRNG.
|
|
*/
|
|
#define TRNG_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK)
|
|
#define TRNG_VID1_MAJ_REV_MASK (0xFF00U)
|
|
#define TRNG_VID1_MAJ_REV_SHIFT (8U)
|
|
/*! MAJ_REV
|
|
* 0b00000001..Major revision number for TRNG.
|
|
*/
|
|
#define TRNG_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK)
|
|
#define TRNG_VID1_IP_ID_MASK (0xFFFF0000U)
|
|
#define TRNG_VID1_IP_ID_SHIFT (16U)
|
|
/*! IP_ID
|
|
* 0b0000000000110000..ID for TRNG.
|
|
*/
|
|
#define TRNG_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name VID2 - Version ID Register (LS) */
|
|
/*! @{ */
|
|
#define TRNG_VID2_CONFIG_OPT_MASK (0xFFU)
|
|
#define TRNG_VID2_CONFIG_OPT_SHIFT (0U)
|
|
/*! CONFIG_OPT
|
|
* 0b00000000..TRNG_CONFIG_OPT for TRNG.
|
|
*/
|
|
#define TRNG_VID2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK)
|
|
#define TRNG_VID2_ECO_REV_MASK (0xFF00U)
|
|
#define TRNG_VID2_ECO_REV_SHIFT (8U)
|
|
/*! ECO_REV
|
|
* 0b00000000..TRNG_ECO_REV for TRNG.
|
|
*/
|
|
#define TRNG_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK)
|
|
#define TRNG_VID2_INTG_OPT_MASK (0xFF0000U)
|
|
#define TRNG_VID2_INTG_OPT_SHIFT (16U)
|
|
/*! INTG_OPT
|
|
* 0b00000000..INTG_OPT for TRNG.
|
|
*/
|
|
#define TRNG_VID2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK)
|
|
#define TRNG_VID2_ERA_MASK (0xFF000000U)
|
|
#define TRNG_VID2_ERA_SHIFT (24U)
|
|
/*! ERA
|
|
* 0b00000000..COMPILE_OPT for TRNG.
|
|
*/
|
|
#define TRNG_VID2_ERA(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group TRNG_Register_Masks */
|
|
|
|
|
|
/* TRNG - Peripheral instance base addresses */
|
|
/** Peripheral TRNG base address */
|
|
#define TRNG_BASE (0x400CC000u)
|
|
/** Peripheral TRNG base pointer */
|
|
#define TRNG ((TRNG_Type *)TRNG_BASE)
|
|
/** Array initializer of TRNG peripheral base addresses */
|
|
#define TRNG_BASE_ADDRS { TRNG_BASE }
|
|
/** Array initializer of TRNG peripheral base pointers */
|
|
#define TRNG_BASE_PTRS { TRNG }
|
|
/** Interrupt vectors for the TRNG peripheral type */
|
|
#define TRNG_IRQS { TRNG_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group TRNG_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- TSC Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup TSC_Peripheral_Access_Layer TSC Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** TSC - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t BASIC_SETTING; /**< , offset: 0x0 */
|
|
uint8_t RESERVED_0[12];
|
|
__IO uint32_t PRE_CHARGE_TIME; /**< , offset: 0x10 */
|
|
uint8_t RESERVED_1[12];
|
|
__IO uint32_t FLOW_CONTROL; /**< Flow Control, offset: 0x20 */
|
|
uint8_t RESERVED_2[12];
|
|
__I uint32_t MEASEURE_VALUE; /**< Measure Value, offset: 0x30 */
|
|
uint8_t RESERVED_3[12];
|
|
__IO uint32_t INT_EN; /**< Interrupt Enable, offset: 0x40 */
|
|
uint8_t RESERVED_4[12];
|
|
__IO uint32_t INT_SIG_EN; /**< Interrupt Signal Enable, offset: 0x50 */
|
|
uint8_t RESERVED_5[12];
|
|
__IO uint32_t INT_STATUS; /**< Intterrupt Status, offset: 0x60 */
|
|
uint8_t RESERVED_6[12];
|
|
__IO uint32_t DEBUG_MODE; /**< , offset: 0x70 */
|
|
uint8_t RESERVED_7[12];
|
|
__IO uint32_t DEBUG_MODE2; /**< , offset: 0x80 */
|
|
} TSC_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- TSC Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup TSC_Register_Masks TSC Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name BASIC_SETTING - */
|
|
/*! @{ */
|
|
#define TSC_BASIC_SETTING_AUTO_MEASURE_MASK (0x1U)
|
|
#define TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT (0U)
|
|
/*! AUTO_MEASURE - Auto Measure
|
|
* 0b0..Disable Auto Measure
|
|
* 0b1..Auto Measure
|
|
*/
|
|
#define TSC_BASIC_SETTING_AUTO_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT)) & TSC_BASIC_SETTING_AUTO_MEASURE_MASK)
|
|
#define TSC_BASIC_SETTING_4_5_WIRE_MASK (0x10U)
|
|
#define TSC_BASIC_SETTING_4_5_WIRE_SHIFT (4U)
|
|
/*! 4_5_WIRE - 4/5 Wire detection
|
|
* 0b0..4-Wire Detection Mode
|
|
* 0b1..5-Wire Detection Mode
|
|
*/
|
|
#define TSC_BASIC_SETTING_4_5_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_4_5_WIRE_SHIFT)) & TSC_BASIC_SETTING_4_5_WIRE_MASK)
|
|
#define TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK (0xFFFFFF00U)
|
|
#define TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT (8U)
|
|
#define TSC_BASIC_SETTING_MEASURE_DELAY_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT)) & TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PRE_CHARGE_TIME - */
|
|
/*! @{ */
|
|
#define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_MASK (0xFFFFFFFFU)
|
|
#define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_SHIFT (0U)
|
|
#define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_SHIFT)) & TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FLOW_CONTROL - Flow Control */
|
|
/*! @{ */
|
|
#define TSC_FLOW_CONTROL_SW_RST_MASK (0x1U)
|
|
#define TSC_FLOW_CONTROL_SW_RST_SHIFT (0U)
|
|
#define TSC_FLOW_CONTROL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_SW_RST_SHIFT)) & TSC_FLOW_CONTROL_SW_RST_MASK)
|
|
#define TSC_FLOW_CONTROL_START_MEASURE_MASK (0x10U)
|
|
#define TSC_FLOW_CONTROL_START_MEASURE_SHIFT (4U)
|
|
/*! START_MEASURE - Start Measure
|
|
* 0b0..Do not start measure for now
|
|
* 0b1..Start measure the X/Y coordinate value
|
|
*/
|
|
#define TSC_FLOW_CONTROL_START_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_START_MEASURE_MASK)
|
|
#define TSC_FLOW_CONTROL_DROP_MEASURE_MASK (0x100U)
|
|
#define TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT (8U)
|
|
/*! DROP_MEASURE - Drop Measure
|
|
* 0b0..Do not drop measure for now
|
|
* 0b1..Drop the measure and controller return to idle status
|
|
*/
|
|
#define TSC_FLOW_CONTROL_DROP_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_DROP_MEASURE_MASK)
|
|
#define TSC_FLOW_CONTROL_START_SENSE_MASK (0x1000U)
|
|
#define TSC_FLOW_CONTROL_START_SENSE_SHIFT (12U)
|
|
/*! START_SENSE - Start Sense
|
|
* 0b0..Stay at idle status
|
|
* 0b1..Start sense detection and (if auto_measure set to 1) measure after detect a touch
|
|
*/
|
|
#define TSC_FLOW_CONTROL_START_SENSE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_SENSE_SHIFT)) & TSC_FLOW_CONTROL_START_SENSE_MASK)
|
|
#define TSC_FLOW_CONTROL_DISABLE_MASK (0x10000U)
|
|
#define TSC_FLOW_CONTROL_DISABLE_SHIFT (16U)
|
|
/*! DISABLE
|
|
* 0b0..Leave HW state machine control
|
|
* 0b1..SW set to idle status
|
|
*/
|
|
#define TSC_FLOW_CONTROL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DISABLE_SHIFT)) & TSC_FLOW_CONTROL_DISABLE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MEASEURE_VALUE - Measure Value */
|
|
/*! @{ */
|
|
#define TSC_MEASEURE_VALUE_Y_VALUE_MASK (0xFFFU)
|
|
#define TSC_MEASEURE_VALUE_Y_VALUE_SHIFT (0U)
|
|
#define TSC_MEASEURE_VALUE_Y_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_Y_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_Y_VALUE_MASK)
|
|
#define TSC_MEASEURE_VALUE_X_VALUE_MASK (0xFFF0000U)
|
|
#define TSC_MEASEURE_VALUE_X_VALUE_SHIFT (16U)
|
|
#define TSC_MEASEURE_VALUE_X_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_X_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_X_VALUE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name INT_EN - Interrupt Enable */
|
|
/*! @{ */
|
|
#define TSC_INT_EN_MEASURE_INT_EN_MASK (0x1U)
|
|
#define TSC_INT_EN_MEASURE_INT_EN_SHIFT (0U)
|
|
/*! MEASURE_INT_EN - Measure Interrupt Enable
|
|
* 0b0..Disable measure interrupt
|
|
* 0b1..Enable measure interrupt
|
|
*/
|
|
#define TSC_INT_EN_MEASURE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_MEASURE_INT_EN_SHIFT)) & TSC_INT_EN_MEASURE_INT_EN_MASK)
|
|
#define TSC_INT_EN_DETECT_INT_EN_MASK (0x10U)
|
|
#define TSC_INT_EN_DETECT_INT_EN_SHIFT (4U)
|
|
/*! DETECT_INT_EN - Detect Interrupt Enable
|
|
* 0b0..Disable detect interrupt
|
|
* 0b1..Enable detect interrupt
|
|
*/
|
|
#define TSC_INT_EN_DETECT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_DETECT_INT_EN_SHIFT)) & TSC_INT_EN_DETECT_INT_EN_MASK)
|
|
#define TSC_INT_EN_IDLE_SW_INT_EN_MASK (0x1000U)
|
|
#define TSC_INT_EN_IDLE_SW_INT_EN_SHIFT (12U)
|
|
/*! IDLE_SW_INT_EN - Idle Software Interrupt Enable
|
|
* 0b0..Disable idle software interrupt
|
|
* 0b1..Enable idle software interrupt
|
|
*/
|
|
#define TSC_INT_EN_IDLE_SW_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_IDLE_SW_INT_EN_SHIFT)) & TSC_INT_EN_IDLE_SW_INT_EN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name INT_SIG_EN - Interrupt Signal Enable */
|
|
/*! @{ */
|
|
#define TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK (0x1U)
|
|
#define TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT (0U)
|
|
#define TSC_INT_SIG_EN_MEASURE_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK)
|
|
#define TSC_INT_SIG_EN_DETECT_SIG_EN_MASK (0x10U)
|
|
#define TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT (4U)
|
|
/*! DETECT_SIG_EN - Detect Signal Enable
|
|
* 0b0..Disable detect signal
|
|
* 0b1..Enable detect signal
|
|
*/
|
|
#define TSC_INT_SIG_EN_DETECT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_DETECT_SIG_EN_MASK)
|
|
#define TSC_INT_SIG_EN_VALID_SIG_EN_MASK (0x100U)
|
|
#define TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT (8U)
|
|
/*! VALID_SIG_EN - Valid Signal Enable
|
|
* 0b0..Disable valid signal
|
|
* 0b1..Enable valid signal
|
|
*/
|
|
#define TSC_INT_SIG_EN_VALID_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_VALID_SIG_EN_MASK)
|
|
#define TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK (0x1000U)
|
|
#define TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT (12U)
|
|
/*! IDLE_SW_SIG_EN - Idle Software Signal Enable
|
|
* 0b0..Disable idle software signal
|
|
* 0b1..Enable idle software signal
|
|
*/
|
|
#define TSC_INT_SIG_EN_IDLE_SW_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name INT_STATUS - Intterrupt Status */
|
|
/*! @{ */
|
|
#define TSC_INT_STATUS_MEASURE_MASK (0x1U)
|
|
#define TSC_INT_STATUS_MEASURE_SHIFT (0U)
|
|
/*! MEASURE - Measure Signal
|
|
* 0b0..Does not exist a measure signal
|
|
* 0b1..Exist a measure signal
|
|
*/
|
|
#define TSC_INT_STATUS_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_MEASURE_SHIFT)) & TSC_INT_STATUS_MEASURE_MASK)
|
|
#define TSC_INT_STATUS_DETECT_MASK (0x10U)
|
|
#define TSC_INT_STATUS_DETECT_SHIFT (4U)
|
|
/*! DETECT - Detect Signal
|
|
* 0b0..Does not exist a detect signal
|
|
* 0b1..Exist detect signal
|
|
*/
|
|
#define TSC_INT_STATUS_DETECT(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_DETECT_SHIFT)) & TSC_INT_STATUS_DETECT_MASK)
|
|
#define TSC_INT_STATUS_VALID_MASK (0x100U)
|
|
#define TSC_INT_STATUS_VALID_SHIFT (8U)
|
|
/*! VALID - Valid Signal
|
|
* 0b0..There is no touch detected after measurement, indicates that the measured value is not valid
|
|
* 0b1..There is touch detection after measurement, indicates that the measure is valid
|
|
*/
|
|
#define TSC_INT_STATUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_VALID_SHIFT)) & TSC_INT_STATUS_VALID_MASK)
|
|
#define TSC_INT_STATUS_IDLE_SW_MASK (0x1000U)
|
|
#define TSC_INT_STATUS_IDLE_SW_SHIFT (12U)
|
|
/*! IDLE_SW - Idle Software
|
|
* 0b0..Haven't return to idle status
|
|
* 0b1..Already return to idle status
|
|
*/
|
|
#define TSC_INT_STATUS_IDLE_SW(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_IDLE_SW_SHIFT)) & TSC_INT_STATUS_IDLE_SW_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DEBUG_MODE - */
|
|
/*! @{ */
|
|
#define TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK (0xFFFU)
|
|
#define TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT (0U)
|
|
#define TSC_DEBUG_MODE_ADC_CONV_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT)) & TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK)
|
|
#define TSC_DEBUG_MODE_ADC_COCO_MASK (0x1000U)
|
|
#define TSC_DEBUG_MODE_ADC_COCO_SHIFT (12U)
|
|
#define TSC_DEBUG_MODE_ADC_COCO(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_MASK)
|
|
#define TSC_DEBUG_MODE_EXT_HWTS_MASK (0x1F0000U)
|
|
#define TSC_DEBUG_MODE_EXT_HWTS_SHIFT (16U)
|
|
#define TSC_DEBUG_MODE_EXT_HWTS(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_EXT_HWTS_SHIFT)) & TSC_DEBUG_MODE_EXT_HWTS_MASK)
|
|
#define TSC_DEBUG_MODE_TRIGGER_MASK (0x1000000U)
|
|
#define TSC_DEBUG_MODE_TRIGGER_SHIFT (24U)
|
|
/*! TRIGGER - Trigger
|
|
* 0b0..No hardware trigger signal
|
|
* 0b1..Hardware trigger signal, the signal must last at least 1 ips clock period
|
|
*/
|
|
#define TSC_DEBUG_MODE_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_TRIGGER_SHIFT)) & TSC_DEBUG_MODE_TRIGGER_MASK)
|
|
#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK (0x2000000U)
|
|
#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT (25U)
|
|
/*! ADC_COCO_CLEAR - ADC Coco Clear
|
|
* 0b0..No ADC COCO clear
|
|
* 0b1..Set ADC COCO clear
|
|
*/
|
|
#define TSC_DEBUG_MODE_ADC_COCO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK)
|
|
#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK (0x4000000U)
|
|
#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT (26U)
|
|
/*! ADC_COCO_CLEAR_DISABLE - ADC COCO Clear Disable
|
|
* 0b0..Allow TSC hardware generates ADC COCO clear
|
|
* 0b1..Prevent TSC from generate ADC COCO clear signal
|
|
*/
|
|
#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK)
|
|
#define TSC_DEBUG_MODE_DEBUG_EN_MASK (0x10000000U)
|
|
#define TSC_DEBUG_MODE_DEBUG_EN_SHIFT (28U)
|
|
/*! DEBUG_EN - Debug Enable
|
|
* 0b0..Enable debug mode
|
|
* 0b1..Disable debug mode
|
|
*/
|
|
#define TSC_DEBUG_MODE_DEBUG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_DEBUG_EN_SHIFT)) & TSC_DEBUG_MODE_DEBUG_EN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DEBUG_MODE2 - */
|
|
/*! @{ */
|
|
#define TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK (0x1U)
|
|
#define TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT (0U)
|
|
/*! XPUL_PULL_DOWN - XPUL Wire Pull Down Switch
|
|
* 0b0..Close the switch
|
|
* 0b1..Open up the switch
|
|
*/
|
|
#define TSC_DEBUG_MODE2_XPUL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK)
|
|
#define TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK (0x2U)
|
|
#define TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT (1U)
|
|
/*! XPUL_PULL_UP - XPUL Wire Pull Up Switch
|
|
* 0b0..Close the switch
|
|
* 0b1..Open up the switch
|
|
*/
|
|
#define TSC_DEBUG_MODE2_XPUL_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK)
|
|
#define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK (0x4U)
|
|
#define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT (2U)
|
|
/*! XPUL_200K_PULL_UP - XPUL Wire 200K Pull Up Switch
|
|
* 0b0..Close the switch
|
|
* 0b1..Open up the switch
|
|
*/
|
|
#define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK)
|
|
#define TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK (0x8U)
|
|
#define TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT (3U)
|
|
/*! XNUR_PULL_DOWN - XNUR Wire Pull Down Switch
|
|
* 0b0..Close the switch
|
|
* 0b1..Open up the switch
|
|
*/
|
|
#define TSC_DEBUG_MODE2_XNUR_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK)
|
|
#define TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK (0x10U)
|
|
#define TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT (4U)
|
|
/*! XNUR_PULL_UP - XNUR Wire Pull Up Switch
|
|
* 0b0..Close the switch
|
|
* 0b1..Open up the switch
|
|
*/
|
|
#define TSC_DEBUG_MODE2_XNUR_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK)
|
|
#define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK (0x20U)
|
|
#define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT (5U)
|
|
/*! XNUR_200K_PULL_UP - XNUR Wire 200K Pull Up Switch
|
|
* 0b0..Close the switch
|
|
* 0b1..Open up the switch
|
|
*/
|
|
#define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK)
|
|
#define TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK (0x40U)
|
|
#define TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT (6U)
|
|
/*! YPLL_PULL_DOWN - YPLL Wire Pull Down Switch
|
|
* 0b0..Close the switch
|
|
* 0b1..Open up the switch
|
|
*/
|
|
#define TSC_DEBUG_MODE2_YPLL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK)
|
|
#define TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK (0x80U)
|
|
#define TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT (7U)
|
|
/*! YPLL_PULL_UP - YPLL Wire Pull Up Switch
|
|
* 0b0..Close the switch
|
|
* 0b1..Open the switch
|
|
*/
|
|
#define TSC_DEBUG_MODE2_YPLL_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK)
|
|
#define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK (0x100U)
|
|
#define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT (8U)
|
|
/*! YPLL_200K_PULL_UP - YPLL Wire 200K Pull Up Switch
|
|
* 0b0..Close the switch
|
|
* 0b1..Open up the switch
|
|
*/
|
|
#define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK)
|
|
#define TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK (0x200U)
|
|
#define TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT (9U)
|
|
/*! YNLR_PULL_DOWN - YNLR Wire Pull Down Switch
|
|
* 0b0..Close the switch
|
|
* 0b1..Open up the switch
|
|
*/
|
|
#define TSC_DEBUG_MODE2_YNLR_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK)
|
|
#define TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK (0x400U)
|
|
#define TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT (10U)
|
|
/*! YNLR_PULL_UP - YNLR Wire Pull Up Switch
|
|
* 0b0..Close the switch
|
|
* 0b1..Open up the switch
|
|
*/
|
|
#define TSC_DEBUG_MODE2_YNLR_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK)
|
|
#define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK (0x800U)
|
|
#define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT (11U)
|
|
/*! YNLR_200K_PULL_UP - YNLR Wire 200K Pull Up Switch
|
|
* 0b0..Close the switch
|
|
* 0b1..Open up the switch
|
|
*/
|
|
#define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK)
|
|
#define TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK (0x1000U)
|
|
#define TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT (12U)
|
|
/*! WIPER_PULL_DOWN - Wiper Wire Pull Down Switch
|
|
* 0b0..Close the switch
|
|
* 0b1..Open up the switch
|
|
*/
|
|
#define TSC_DEBUG_MODE2_WIPER_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK)
|
|
#define TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK (0x2000U)
|
|
#define TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT (13U)
|
|
/*! WIPER_PULL_UP - Wiper Wire Pull Up Switch
|
|
* 0b0..Close the switch
|
|
* 0b1..Open up the switch
|
|
*/
|
|
#define TSC_DEBUG_MODE2_WIPER_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK)
|
|
#define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK (0x4000U)
|
|
#define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT (14U)
|
|
/*! WIPER_200K_PULL_UP - Wiper Wire 200K Pull Up Switch
|
|
* 0b0..Close the switch
|
|
* 0b1..Open up the switch
|
|
*/
|
|
#define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK)
|
|
#define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK (0x10000U)
|
|
#define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT (16U)
|
|
/*! DETECT_FOUR_WIRE - Detect Four Wire
|
|
* 0b0..No detect signal
|
|
* 0b1..Yes, there is a detect on the touch screen.
|
|
*/
|
|
#define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK)
|
|
#define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK (0x20000U)
|
|
#define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT (17U)
|
|
/*! DETECT_FIVE_WIRE - Detect Five Wire
|
|
* 0b0..No detect signal
|
|
* 0b1..Yes, there is a detect on the touch screen.
|
|
*/
|
|
#define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK)
|
|
#define TSC_DEBUG_MODE2_STATE_MACHINE_MASK (0x700000U)
|
|
#define TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT (20U)
|
|
/*! STATE_MACHINE - State Machine
|
|
* 0b000..Idle
|
|
* 0b001..Pre-charge
|
|
* 0b010..Detect
|
|
* 0b011..X-measure
|
|
* 0b100..Y-measure
|
|
* 0b101..Pre-charge
|
|
* 0b110..Detect
|
|
*/
|
|
#define TSC_DEBUG_MODE2_STATE_MACHINE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT)) & TSC_DEBUG_MODE2_STATE_MACHINE_MASK)
|
|
#define TSC_DEBUG_MODE2_INTERMEDIATE_MASK (0x800000U)
|
|
#define TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT (23U)
|
|
/*! INTERMEDIATE - Intermediate State
|
|
* 0b0..Not in intermedia
|
|
* 0b1..Intermedia
|
|
*/
|
|
#define TSC_DEBUG_MODE2_INTERMEDIATE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT)) & TSC_DEBUG_MODE2_INTERMEDIATE_MASK)
|
|
#define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK (0x1000000U)
|
|
#define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT (24U)
|
|
/*! DETECT_ENABLE_FOUR_WIRE - Detect Enable Four Wire
|
|
* 0b0..Do not read four wire detect value, read default value from analogue
|
|
* 0b1..Read four wire detect status from analogue
|
|
*/
|
|
#define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK)
|
|
#define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK (0x10000000U)
|
|
#define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT (28U)
|
|
/*! DETECT_ENABLE_FIVE_WIRE - Detect Enable Five Wire
|
|
* 0b0..Do not read five wire detect value, read default value from analogue
|
|
* 0b1..Read five wire detect status from analogue
|
|
*/
|
|
#define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK)
|
|
#define TSC_DEBUG_MODE2_DE_GLITCH_MASK (0x60000000U)
|
|
#define TSC_DEBUG_MODE2_DE_GLITCH_SHIFT (29U)
|
|
/*! DE_GLITCH
|
|
* 0b00..Normal function: 0x1fff ipg clock cycles; Low power mode: 0x9 low power clock cycles
|
|
* 0b01..Normal function: 0xfff ipg clock cycles; Low power mode: :0x7 low power clock cycles
|
|
* 0b10..Normal function: 0x7ff ipg clock cycles; Low power mode:0x5 low power clock cycles
|
|
* 0b11..Normal function: 0x3 ipg clock cycles; Low power mode:0x3 low power clock cycles
|
|
*/
|
|
#define TSC_DEBUG_MODE2_DE_GLITCH(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT)) & TSC_DEBUG_MODE2_DE_GLITCH_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group TSC_Register_Masks */
|
|
|
|
|
|
/* TSC - Peripheral instance base addresses */
|
|
/** Peripheral TSC base address */
|
|
#define TSC_BASE (0x400E0000u)
|
|
/** Peripheral TSC base pointer */
|
|
#define TSC ((TSC_Type *)TSC_BASE)
|
|
/** Array initializer of TSC peripheral base addresses */
|
|
#define TSC_BASE_ADDRS { TSC_BASE }
|
|
/** Array initializer of TSC peripheral base pointers */
|
|
#define TSC_BASE_PTRS { TSC }
|
|
/** Interrupt vectors for the TSC peripheral type */
|
|
#define TSC_IRQS { TSC_DIG_IRQn }
|
|
/* Backward compatibility */
|
|
#define TSC_BASIC_SETTING__4_5_WIRE_MASK TSC_BASIC_SETTING_4_5_WIRE_MASK
|
|
#define TSC_BASIC_SETTING__4_5_WIRE_SHIFT TSC_BASIC_SETTING_4_5_WIRE_SHIFT
|
|
#define TSC_BASIC_SETTING__4_5_WIRE(x) TSC_BASIC_SETTING_4_5_WIRE(x)
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group TSC_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- USB Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** USB - Register Layout Typedef */
|
|
typedef struct {
|
|
__I uint32_t ID; /**< Identification register, offset: 0x0 */
|
|
__I uint32_t HWGENERAL; /**< Hardware General, offset: 0x4 */
|
|
__I uint32_t HWHOST; /**< Host Hardware Parameters, offset: 0x8 */
|
|
__I uint32_t HWDEVICE; /**< Device Hardware Parameters, offset: 0xC */
|
|
__I uint32_t HWTXBUF; /**< TX Buffer Hardware Parameters, offset: 0x10 */
|
|
__I uint32_t HWRXBUF; /**< RX Buffer Hardware Parameters, offset: 0x14 */
|
|
uint8_t RESERVED_0[104];
|
|
__IO uint32_t GPTIMER0LD; /**< General Purpose Timer #0 Load, offset: 0x80 */
|
|
__IO uint32_t GPTIMER0CTRL; /**< General Purpose Timer #0 Controller, offset: 0x84 */
|
|
__IO uint32_t GPTIMER1LD; /**< General Purpose Timer #1 Load, offset: 0x88 */
|
|
__IO uint32_t GPTIMER1CTRL; /**< General Purpose Timer #1 Controller, offset: 0x8C */
|
|
__IO uint32_t SBUSCFG; /**< System Bus Config, offset: 0x90 */
|
|
uint8_t RESERVED_1[108];
|
|
__I uint8_t CAPLENGTH; /**< Capability Registers Length, offset: 0x100 */
|
|
uint8_t RESERVED_2[1];
|
|
__I uint16_t HCIVERSION; /**< Host Controller Interface Version, offset: 0x102 */
|
|
__I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x104 */
|
|
__I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x108 */
|
|
uint8_t RESERVED_3[20];
|
|
__I uint16_t DCIVERSION; /**< Device Controller Interface Version, offset: 0x120 */
|
|
uint8_t RESERVED_4[2];
|
|
__I uint32_t DCCPARAMS; /**< Device Controller Capability Parameters, offset: 0x124 */
|
|
uint8_t RESERVED_5[24];
|
|
__IO uint32_t USBCMD; /**< USB Command Register, offset: 0x140 */
|
|
__IO uint32_t USBSTS; /**< USB Status Register, offset: 0x144 */
|
|
__IO uint32_t USBINTR; /**< Interrupt Enable Register, offset: 0x148 */
|
|
__IO uint32_t FRINDEX; /**< USB Frame Index, offset: 0x14C */
|
|
uint8_t RESERVED_6[4];
|
|
union { /* offset: 0x154 */
|
|
__IO uint32_t DEVICEADDR; /**< Device Address, offset: 0x154 */
|
|
__IO uint32_t PERIODICLISTBASE; /**< Frame List Base Address, offset: 0x154 */
|
|
};
|
|
union { /* offset: 0x158 */
|
|
__IO uint32_t ASYNCLISTADDR; /**< Next Asynch. Address, offset: 0x158 */
|
|
__IO uint32_t ENDPTLISTADDR; /**< Endpoint List Address, offset: 0x158 */
|
|
};
|
|
uint8_t RESERVED_7[4];
|
|
__IO uint32_t BURSTSIZE; /**< Programmable Burst Size, offset: 0x160 */
|
|
__IO uint32_t TXFILLTUNING; /**< TX FIFO Fill Tuning, offset: 0x164 */
|
|
uint8_t RESERVED_8[16];
|
|
__IO uint32_t ENDPTNAK; /**< Endpoint NAK, offset: 0x178 */
|
|
__IO uint32_t ENDPTNAKEN; /**< Endpoint NAK Enable, offset: 0x17C */
|
|
__I uint32_t CONFIGFLAG; /**< Configure Flag Register, offset: 0x180 */
|
|
__IO uint32_t PORTSC1; /**< Port Status & Control, offset: 0x184 */
|
|
uint8_t RESERVED_9[28];
|
|
__IO uint32_t OTGSC; /**< On-The-Go Status & control, offset: 0x1A4 */
|
|
__IO uint32_t USBMODE; /**< USB Device Mode, offset: 0x1A8 */
|
|
__IO uint32_t ENDPTSETUPSTAT; /**< Endpoint Setup Status, offset: 0x1AC */
|
|
__IO uint32_t ENDPTPRIME; /**< Endpoint Prime, offset: 0x1B0 */
|
|
__IO uint32_t ENDPTFLUSH; /**< Endpoint Flush, offset: 0x1B4 */
|
|
__I uint32_t ENDPTSTAT; /**< Endpoint Status, offset: 0x1B8 */
|
|
__IO uint32_t ENDPTCOMPLETE; /**< Endpoint Complete, offset: 0x1BC */
|
|
__IO uint32_t ENDPTCTRL0; /**< Endpoint Control0, offset: 0x1C0 */
|
|
__IO uint32_t ENDPTCTRL[7]; /**< Endpoint Control 1..Endpoint Control 7, array offset: 0x1C4, array step: 0x4 */
|
|
} USB_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- USB Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup USB_Register_Masks USB Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name ID - Identification register */
|
|
/*! @{ */
|
|
#define USB_ID_ID_MASK (0x3FU)
|
|
#define USB_ID_ID_SHIFT (0U)
|
|
#define USB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK)
|
|
#define USB_ID_NID_MASK (0x3F00U)
|
|
#define USB_ID_NID_SHIFT (8U)
|
|
#define USB_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK)
|
|
#define USB_ID_REVISION_MASK (0xFF0000U)
|
|
#define USB_ID_REVISION_SHIFT (16U)
|
|
#define USB_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name HWGENERAL - Hardware General */
|
|
/*! @{ */
|
|
#define USB_HWGENERAL_PHYW_MASK (0x30U)
|
|
#define USB_HWGENERAL_PHYW_SHIFT (4U)
|
|
/*! PHYW
|
|
* 0b00..8 bit wide data bus Software non-programmable
|
|
* 0b01..16 bit wide data bus Software non-programmable
|
|
* 0b10..Reset to 8 bit wide data bus Software programmable
|
|
* 0b11..Reset to 16 bit wide data bus Software programmable
|
|
*/
|
|
#define USB_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK)
|
|
#define USB_HWGENERAL_PHYM_MASK (0x1C0U)
|
|
#define USB_HWGENERAL_PHYM_SHIFT (6U)
|
|
/*! PHYM
|
|
* 0b000..UTMI/UMTI+
|
|
* 0b001..ULPI DDR
|
|
* 0b010..ULPI
|
|
* 0b011..Serial Only
|
|
* 0b100..Software programmable - reset to UTMI/UTMI+
|
|
* 0b101..Software programmable - reset to ULPI DDR
|
|
* 0b110..Software programmable - reset to ULPI
|
|
* 0b111..Software programmable - reset to Serial
|
|
*/
|
|
#define USB_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK)
|
|
#define USB_HWGENERAL_SM_MASK (0x600U)
|
|
#define USB_HWGENERAL_SM_SHIFT (9U)
|
|
/*! SM
|
|
* 0b00..No Serial Engine, always use parallel signalling.
|
|
* 0b01..Serial Engine present, always use serial signalling for FS/LS.
|
|
* 0b10..Software programmable - Reset to use parallel signalling for FS/LS
|
|
* 0b11..Software programmable - Reset to use serial signalling for FS/LS
|
|
*/
|
|
#define USB_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name HWHOST - Host Hardware Parameters */
|
|
/*! @{ */
|
|
#define USB_HWHOST_HC_MASK (0x1U)
|
|
#define USB_HWHOST_HC_SHIFT (0U)
|
|
/*! HC
|
|
* 0b1..Supported
|
|
* 0b0..Not supported
|
|
*/
|
|
#define USB_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK)
|
|
#define USB_HWHOST_NPORT_MASK (0xEU)
|
|
#define USB_HWHOST_NPORT_SHIFT (1U)
|
|
#define USB_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name HWDEVICE - Device Hardware Parameters */
|
|
/*! @{ */
|
|
#define USB_HWDEVICE_DC_MASK (0x1U)
|
|
#define USB_HWDEVICE_DC_SHIFT (0U)
|
|
/*! DC
|
|
* 0b1..Supported
|
|
* 0b0..Not supported
|
|
*/
|
|
#define USB_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK)
|
|
#define USB_HWDEVICE_DEVEP_MASK (0x3EU)
|
|
#define USB_HWDEVICE_DEVEP_SHIFT (1U)
|
|
#define USB_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name HWTXBUF - TX Buffer Hardware Parameters */
|
|
/*! @{ */
|
|
#define USB_HWTXBUF_TXBURST_MASK (0xFFU)
|
|
#define USB_HWTXBUF_TXBURST_SHIFT (0U)
|
|
#define USB_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK)
|
|
#define USB_HWTXBUF_TXCHANADD_MASK (0xFF0000U)
|
|
#define USB_HWTXBUF_TXCHANADD_SHIFT (16U)
|
|
#define USB_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name HWRXBUF - RX Buffer Hardware Parameters */
|
|
/*! @{ */
|
|
#define USB_HWRXBUF_RXBURST_MASK (0xFFU)
|
|
#define USB_HWRXBUF_RXBURST_SHIFT (0U)
|
|
#define USB_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK)
|
|
#define USB_HWRXBUF_RXADD_MASK (0xFF00U)
|
|
#define USB_HWRXBUF_RXADD_SHIFT (8U)
|
|
#define USB_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GPTIMER0LD - General Purpose Timer #0 Load */
|
|
/*! @{ */
|
|
#define USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU)
|
|
#define USB_GPTIMER0LD_GPTLD_SHIFT (0U)
|
|
#define USB_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GPTIMER0CTRL - General Purpose Timer #0 Controller */
|
|
/*! @{ */
|
|
#define USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU)
|
|
#define USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U)
|
|
#define USB_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK)
|
|
#define USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U)
|
|
#define USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U)
|
|
/*! GPTMODE
|
|
* 0b0..One Shot Mode
|
|
* 0b1..Repeat Mode
|
|
*/
|
|
#define USB_GPTIMER0CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK)
|
|
#define USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000U)
|
|
#define USB_GPTIMER0CTRL_GPTRST_SHIFT (30U)
|
|
/*! GPTRST
|
|
* 0b0..No action
|
|
* 0b1..Load counter value from GPTLD bits in n_GPTIMER0LD
|
|
*/
|
|
#define USB_GPTIMER0CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK)
|
|
#define USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U)
|
|
#define USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U)
|
|
/*! GPTRUN
|
|
* 0b0..Stop counting
|
|
* 0b1..Run
|
|
*/
|
|
#define USB_GPTIMER0CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GPTIMER1LD - General Purpose Timer #1 Load */
|
|
/*! @{ */
|
|
#define USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU)
|
|
#define USB_GPTIMER1LD_GPTLD_SHIFT (0U)
|
|
#define USB_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name GPTIMER1CTRL - General Purpose Timer #1 Controller */
|
|
/*! @{ */
|
|
#define USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU)
|
|
#define USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U)
|
|
#define USB_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK)
|
|
#define USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U)
|
|
#define USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U)
|
|
/*! GPTMODE
|
|
* 0b0..One Shot Mode
|
|
* 0b1..Repeat Mode
|
|
*/
|
|
#define USB_GPTIMER1CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK)
|
|
#define USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000U)
|
|
#define USB_GPTIMER1CTRL_GPTRST_SHIFT (30U)
|
|
/*! GPTRST
|
|
* 0b0..No action
|
|
* 0b1..Load counter value from GPTLD bits in USB_n_GPTIMER0LD
|
|
*/
|
|
#define USB_GPTIMER1CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK)
|
|
#define USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U)
|
|
#define USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U)
|
|
/*! GPTRUN
|
|
* 0b0..Stop counting
|
|
* 0b1..Run
|
|
*/
|
|
#define USB_GPTIMER1CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SBUSCFG - System Bus Config */
|
|
/*! @{ */
|
|
#define USB_SBUSCFG_AHBBRST_MASK (0x7U)
|
|
#define USB_SBUSCFG_AHBBRST_SHIFT (0U)
|
|
/*! AHBBRST
|
|
* 0b000..Incremental burst of unspecified length only
|
|
* 0b001..INCR4 burst, then single transfer
|
|
* 0b010..INCR8 burst, INCR4 burst, then single transfer
|
|
* 0b011..INCR16 burst, INCR8 burst, INCR4 burst, then single transfer
|
|
* 0b100..Reserved, don't use
|
|
* 0b101..INCR4 burst, then incremental burst of unspecified length
|
|
* 0b110..INCR8 burst, INCR4 burst, then incremental burst of unspecified length
|
|
* 0b111..INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length
|
|
*/
|
|
#define USB_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CAPLENGTH - Capability Registers Length */
|
|
/*! @{ */
|
|
#define USB_CAPLENGTH_CAPLENGTH_MASK (0xFFU)
|
|
#define USB_CAPLENGTH_CAPLENGTH_SHIFT (0U)
|
|
#define USB_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name HCIVERSION - Host Controller Interface Version */
|
|
/*! @{ */
|
|
#define USB_HCIVERSION_HCIVERSION_MASK (0xFFFFU)
|
|
#define USB_HCIVERSION_HCIVERSION_SHIFT (0U)
|
|
#define USB_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name HCSPARAMS - Host Controller Structural Parameters */
|
|
/*! @{ */
|
|
#define USB_HCSPARAMS_N_PORTS_MASK (0xFU)
|
|
#define USB_HCSPARAMS_N_PORTS_SHIFT (0U)
|
|
#define USB_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK)
|
|
#define USB_HCSPARAMS_PPC_MASK (0x10U)
|
|
#define USB_HCSPARAMS_PPC_SHIFT (4U)
|
|
#define USB_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK)
|
|
#define USB_HCSPARAMS_N_PCC_MASK (0xF00U)
|
|
#define USB_HCSPARAMS_N_PCC_SHIFT (8U)
|
|
#define USB_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK)
|
|
#define USB_HCSPARAMS_N_CC_MASK (0xF000U)
|
|
#define USB_HCSPARAMS_N_CC_SHIFT (12U)
|
|
/*! N_CC
|
|
* 0b0000..There is no internal Companion Controller and port-ownership hand-off is not supported.
|
|
* 0b0001..There are internal companion controller(s) and port-ownership hand-offs is supported.
|
|
*/
|
|
#define USB_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK)
|
|
#define USB_HCSPARAMS_PI_MASK (0x10000U)
|
|
#define USB_HCSPARAMS_PI_SHIFT (16U)
|
|
#define USB_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK)
|
|
#define USB_HCSPARAMS_N_PTT_MASK (0xF00000U)
|
|
#define USB_HCSPARAMS_N_PTT_SHIFT (20U)
|
|
#define USB_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK)
|
|
#define USB_HCSPARAMS_N_TT_MASK (0xF000000U)
|
|
#define USB_HCSPARAMS_N_TT_SHIFT (24U)
|
|
#define USB_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name HCCPARAMS - Host Controller Capability Parameters */
|
|
/*! @{ */
|
|
#define USB_HCCPARAMS_ADC_MASK (0x1U)
|
|
#define USB_HCCPARAMS_ADC_SHIFT (0U)
|
|
#define USB_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK)
|
|
#define USB_HCCPARAMS_PFL_MASK (0x2U)
|
|
#define USB_HCCPARAMS_PFL_SHIFT (1U)
|
|
#define USB_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK)
|
|
#define USB_HCCPARAMS_ASP_MASK (0x4U)
|
|
#define USB_HCCPARAMS_ASP_SHIFT (2U)
|
|
#define USB_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK)
|
|
#define USB_HCCPARAMS_IST_MASK (0xF0U)
|
|
#define USB_HCCPARAMS_IST_SHIFT (4U)
|
|
#define USB_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK)
|
|
#define USB_HCCPARAMS_EECP_MASK (0xFF00U)
|
|
#define USB_HCCPARAMS_EECP_SHIFT (8U)
|
|
#define USB_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DCIVERSION - Device Controller Interface Version */
|
|
/*! @{ */
|
|
#define USB_DCIVERSION_DCIVERSION_MASK (0xFFFFU)
|
|
#define USB_DCIVERSION_DCIVERSION_SHIFT (0U)
|
|
#define USB_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DCCPARAMS - Device Controller Capability Parameters */
|
|
/*! @{ */
|
|
#define USB_DCCPARAMS_DEN_MASK (0x1FU)
|
|
#define USB_DCCPARAMS_DEN_SHIFT (0U)
|
|
#define USB_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK)
|
|
#define USB_DCCPARAMS_DC_MASK (0x80U)
|
|
#define USB_DCCPARAMS_DC_SHIFT (7U)
|
|
#define USB_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK)
|
|
#define USB_DCCPARAMS_HC_MASK (0x100U)
|
|
#define USB_DCCPARAMS_HC_SHIFT (8U)
|
|
#define USB_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name USBCMD - USB Command Register */
|
|
/*! @{ */
|
|
#define USB_USBCMD_RS_MASK (0x1U)
|
|
#define USB_USBCMD_RS_SHIFT (0U)
|
|
#define USB_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK)
|
|
#define USB_USBCMD_RST_MASK (0x2U)
|
|
#define USB_USBCMD_RST_SHIFT (1U)
|
|
#define USB_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK)
|
|
#define USB_USBCMD_FS_1_MASK (0xCU)
|
|
#define USB_USBCMD_FS_1_SHIFT (2U)
|
|
#define USB_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK)
|
|
#define USB_USBCMD_PSE_MASK (0x10U)
|
|
#define USB_USBCMD_PSE_SHIFT (4U)
|
|
/*! PSE
|
|
* 0b0..Do not process the Periodic Schedule
|
|
* 0b1..Use the PERIODICLISTBASE register to access the Periodic Schedule.
|
|
*/
|
|
#define USB_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK)
|
|
#define USB_USBCMD_ASE_MASK (0x20U)
|
|
#define USB_USBCMD_ASE_SHIFT (5U)
|
|
/*! ASE
|
|
* 0b0..Do not process the Asynchronous Schedule.
|
|
* 0b1..Use the ASYNCLISTADDR register to access the Asynchronous Schedule.
|
|
*/
|
|
#define USB_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK)
|
|
#define USB_USBCMD_IAA_MASK (0x40U)
|
|
#define USB_USBCMD_IAA_SHIFT (6U)
|
|
#define USB_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK)
|
|
#define USB_USBCMD_ASP_MASK (0x300U)
|
|
#define USB_USBCMD_ASP_SHIFT (8U)
|
|
#define USB_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK)
|
|
#define USB_USBCMD_ASPE_MASK (0x800U)
|
|
#define USB_USBCMD_ASPE_SHIFT (11U)
|
|
#define USB_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK)
|
|
#define USB_USBCMD_ATDTW_MASK (0x1000U)
|
|
#define USB_USBCMD_ATDTW_SHIFT (12U)
|
|
#define USB_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK)
|
|
#define USB_USBCMD_SUTW_MASK (0x2000U)
|
|
#define USB_USBCMD_SUTW_SHIFT (13U)
|
|
#define USB_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK)
|
|
#define USB_USBCMD_FS_2_MASK (0x8000U)
|
|
#define USB_USBCMD_FS_2_SHIFT (15U)
|
|
/*! FS_2
|
|
* 0b0..1024 elements (4096 bytes) Default value
|
|
* 0b1..512 elements (2048 bytes)
|
|
*/
|
|
#define USB_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK)
|
|
#define USB_USBCMD_ITC_MASK (0xFF0000U)
|
|
#define USB_USBCMD_ITC_SHIFT (16U)
|
|
/*! ITC
|
|
* 0b00000000..Immediate (no threshold)
|
|
* 0b00000001..1 micro-frame
|
|
* 0b00000010..2 micro-frames
|
|
* 0b00000100..4 micro-frames
|
|
* 0b00001000..8 micro-frames
|
|
* 0b00010000..16 micro-frames
|
|
* 0b00100000..32 micro-frames
|
|
* 0b01000000..64 micro-frames
|
|
*/
|
|
#define USB_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name USBSTS - USB Status Register */
|
|
/*! @{ */
|
|
#define USB_USBSTS_UI_MASK (0x1U)
|
|
#define USB_USBSTS_UI_SHIFT (0U)
|
|
#define USB_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK)
|
|
#define USB_USBSTS_UEI_MASK (0x2U)
|
|
#define USB_USBSTS_UEI_SHIFT (1U)
|
|
#define USB_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK)
|
|
#define USB_USBSTS_PCI_MASK (0x4U)
|
|
#define USB_USBSTS_PCI_SHIFT (2U)
|
|
#define USB_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK)
|
|
#define USB_USBSTS_FRI_MASK (0x8U)
|
|
#define USB_USBSTS_FRI_SHIFT (3U)
|
|
#define USB_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK)
|
|
#define USB_USBSTS_SEI_MASK (0x10U)
|
|
#define USB_USBSTS_SEI_SHIFT (4U)
|
|
#define USB_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK)
|
|
#define USB_USBSTS_AAI_MASK (0x20U)
|
|
#define USB_USBSTS_AAI_SHIFT (5U)
|
|
#define USB_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK)
|
|
#define USB_USBSTS_URI_MASK (0x40U)
|
|
#define USB_USBSTS_URI_SHIFT (6U)
|
|
#define USB_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK)
|
|
#define USB_USBSTS_SRI_MASK (0x80U)
|
|
#define USB_USBSTS_SRI_SHIFT (7U)
|
|
#define USB_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK)
|
|
#define USB_USBSTS_SLI_MASK (0x100U)
|
|
#define USB_USBSTS_SLI_SHIFT (8U)
|
|
#define USB_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK)
|
|
#define USB_USBSTS_ULPII_MASK (0x400U)
|
|
#define USB_USBSTS_ULPII_SHIFT (10U)
|
|
#define USB_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK)
|
|
#define USB_USBSTS_HCH_MASK (0x1000U)
|
|
#define USB_USBSTS_HCH_SHIFT (12U)
|
|
#define USB_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK)
|
|
#define USB_USBSTS_RCL_MASK (0x2000U)
|
|
#define USB_USBSTS_RCL_SHIFT (13U)
|
|
#define USB_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK)
|
|
#define USB_USBSTS_PS_MASK (0x4000U)
|
|
#define USB_USBSTS_PS_SHIFT (14U)
|
|
#define USB_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK)
|
|
#define USB_USBSTS_AS_MASK (0x8000U)
|
|
#define USB_USBSTS_AS_SHIFT (15U)
|
|
#define USB_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK)
|
|
#define USB_USBSTS_NAKI_MASK (0x10000U)
|
|
#define USB_USBSTS_NAKI_SHIFT (16U)
|
|
#define USB_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK)
|
|
#define USB_USBSTS_TI0_MASK (0x1000000U)
|
|
#define USB_USBSTS_TI0_SHIFT (24U)
|
|
#define USB_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK)
|
|
#define USB_USBSTS_TI1_MASK (0x2000000U)
|
|
#define USB_USBSTS_TI1_SHIFT (25U)
|
|
#define USB_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name USBINTR - Interrupt Enable Register */
|
|
/*! @{ */
|
|
#define USB_USBINTR_UE_MASK (0x1U)
|
|
#define USB_USBINTR_UE_SHIFT (0U)
|
|
#define USB_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK)
|
|
#define USB_USBINTR_UEE_MASK (0x2U)
|
|
#define USB_USBINTR_UEE_SHIFT (1U)
|
|
#define USB_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK)
|
|
#define USB_USBINTR_PCE_MASK (0x4U)
|
|
#define USB_USBINTR_PCE_SHIFT (2U)
|
|
#define USB_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK)
|
|
#define USB_USBINTR_FRE_MASK (0x8U)
|
|
#define USB_USBINTR_FRE_SHIFT (3U)
|
|
#define USB_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK)
|
|
#define USB_USBINTR_SEE_MASK (0x10U)
|
|
#define USB_USBINTR_SEE_SHIFT (4U)
|
|
#define USB_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK)
|
|
#define USB_USBINTR_AAE_MASK (0x20U)
|
|
#define USB_USBINTR_AAE_SHIFT (5U)
|
|
#define USB_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK)
|
|
#define USB_USBINTR_URE_MASK (0x40U)
|
|
#define USB_USBINTR_URE_SHIFT (6U)
|
|
#define USB_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK)
|
|
#define USB_USBINTR_SRE_MASK (0x80U)
|
|
#define USB_USBINTR_SRE_SHIFT (7U)
|
|
#define USB_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK)
|
|
#define USB_USBINTR_SLE_MASK (0x100U)
|
|
#define USB_USBINTR_SLE_SHIFT (8U)
|
|
#define USB_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK)
|
|
#define USB_USBINTR_ULPIE_MASK (0x400U)
|
|
#define USB_USBINTR_ULPIE_SHIFT (10U)
|
|
#define USB_USBINTR_ULPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_ULPIE_SHIFT)) & USB_USBINTR_ULPIE_MASK)
|
|
#define USB_USBINTR_NAKE_MASK (0x10000U)
|
|
#define USB_USBINTR_NAKE_SHIFT (16U)
|
|
#define USB_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK)
|
|
#define USB_USBINTR_UAIE_MASK (0x40000U)
|
|
#define USB_USBINTR_UAIE_SHIFT (18U)
|
|
#define USB_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK)
|
|
#define USB_USBINTR_UPIE_MASK (0x80000U)
|
|
#define USB_USBINTR_UPIE_SHIFT (19U)
|
|
#define USB_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK)
|
|
#define USB_USBINTR_TIE0_MASK (0x1000000U)
|
|
#define USB_USBINTR_TIE0_SHIFT (24U)
|
|
#define USB_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK)
|
|
#define USB_USBINTR_TIE1_MASK (0x2000000U)
|
|
#define USB_USBINTR_TIE1_SHIFT (25U)
|
|
#define USB_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FRINDEX - USB Frame Index */
|
|
/*! @{ */
|
|
#define USB_FRINDEX_FRINDEX_MASK (0x3FFFU)
|
|
#define USB_FRINDEX_FRINDEX_SHIFT (0U)
|
|
/*! FRINDEX
|
|
* 0b00000000000000..(1024) 12
|
|
* 0b00000000000001..(512) 11
|
|
* 0b00000000000010..(256) 10
|
|
* 0b00000000000011..(128) 9
|
|
* 0b00000000000100..(64) 8
|
|
* 0b00000000000101..(32) 7
|
|
* 0b00000000000110..(16) 6
|
|
* 0b00000000000111..(8) 5
|
|
*/
|
|
#define USB_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DEVICEADDR - Device Address */
|
|
/*! @{ */
|
|
#define USB_DEVICEADDR_USBADRA_MASK (0x1000000U)
|
|
#define USB_DEVICEADDR_USBADRA_SHIFT (24U)
|
|
#define USB_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK)
|
|
#define USB_DEVICEADDR_USBADR_MASK (0xFE000000U)
|
|
#define USB_DEVICEADDR_USBADR_SHIFT (25U)
|
|
#define USB_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PERIODICLISTBASE - Frame List Base Address */
|
|
/*! @{ */
|
|
#define USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U)
|
|
#define USB_PERIODICLISTBASE_BASEADR_SHIFT (12U)
|
|
#define USB_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ASYNCLISTADDR - Next Asynch. Address */
|
|
/*! @{ */
|
|
#define USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U)
|
|
#define USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U)
|
|
#define USB_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ENDPTLISTADDR - Endpoint List Address */
|
|
/*! @{ */
|
|
#define USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U)
|
|
#define USB_ENDPTLISTADDR_EPBASE_SHIFT (11U)
|
|
#define USB_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name BURSTSIZE - Programmable Burst Size */
|
|
/*! @{ */
|
|
#define USB_BURSTSIZE_RXPBURST_MASK (0xFFU)
|
|
#define USB_BURSTSIZE_RXPBURST_SHIFT (0U)
|
|
#define USB_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK)
|
|
#define USB_BURSTSIZE_TXPBURST_MASK (0x1FF00U)
|
|
#define USB_BURSTSIZE_TXPBURST_SHIFT (8U)
|
|
#define USB_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TXFILLTUNING - TX FIFO Fill Tuning */
|
|
/*! @{ */
|
|
#define USB_TXFILLTUNING_TXSCHOH_MASK (0xFFU)
|
|
#define USB_TXFILLTUNING_TXSCHOH_SHIFT (0U)
|
|
#define USB_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK)
|
|
#define USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U)
|
|
#define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U)
|
|
#define USB_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK)
|
|
#define USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U)
|
|
#define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U)
|
|
#define USB_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ENDPTNAK - Endpoint NAK */
|
|
/*! @{ */
|
|
#define USB_ENDPTNAK_EPRN_MASK (0xFFU)
|
|
#define USB_ENDPTNAK_EPRN_SHIFT (0U)
|
|
#define USB_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK)
|
|
#define USB_ENDPTNAK_EPTN_MASK (0xFF0000U)
|
|
#define USB_ENDPTNAK_EPTN_SHIFT (16U)
|
|
#define USB_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ENDPTNAKEN - Endpoint NAK Enable */
|
|
/*! @{ */
|
|
#define USB_ENDPTNAKEN_EPRNE_MASK (0xFFU)
|
|
#define USB_ENDPTNAKEN_EPRNE_SHIFT (0U)
|
|
#define USB_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK)
|
|
#define USB_ENDPTNAKEN_EPTNE_MASK (0xFF0000U)
|
|
#define USB_ENDPTNAKEN_EPTNE_SHIFT (16U)
|
|
#define USB_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CONFIGFLAG - Configure Flag Register */
|
|
/*! @{ */
|
|
#define USB_CONFIGFLAG_CF_MASK (0x1U)
|
|
#define USB_CONFIGFLAG_CF_SHIFT (0U)
|
|
/*! CF
|
|
* 0b0..Port routing control logic default-routes each port to an implementation dependent classic host controller.
|
|
* 0b1..Port routing control logic default-routes all ports to this host controller.
|
|
*/
|
|
#define USB_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PORTSC1 - Port Status & Control */
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/*! @{ */
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#define USB_PORTSC1_CCS_MASK (0x1U)
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#define USB_PORTSC1_CCS_SHIFT (0U)
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#define USB_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK)
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#define USB_PORTSC1_CSC_MASK (0x2U)
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#define USB_PORTSC1_CSC_SHIFT (1U)
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#define USB_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK)
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#define USB_PORTSC1_PE_MASK (0x4U)
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#define USB_PORTSC1_PE_SHIFT (2U)
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#define USB_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK)
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#define USB_PORTSC1_PEC_MASK (0x8U)
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#define USB_PORTSC1_PEC_SHIFT (3U)
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#define USB_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK)
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#define USB_PORTSC1_OCA_MASK (0x10U)
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#define USB_PORTSC1_OCA_SHIFT (4U)
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/*! OCA
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* 0b1..This port currently has an over-current condition
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* 0b0..This port does not have an over-current condition.
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*/
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#define USB_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK)
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#define USB_PORTSC1_OCC_MASK (0x20U)
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#define USB_PORTSC1_OCC_SHIFT (5U)
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#define USB_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK)
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#define USB_PORTSC1_FPR_MASK (0x40U)
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#define USB_PORTSC1_FPR_SHIFT (6U)
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#define USB_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK)
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#define USB_PORTSC1_SUSP_MASK (0x80U)
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#define USB_PORTSC1_SUSP_SHIFT (7U)
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#define USB_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK)
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#define USB_PORTSC1_PR_MASK (0x100U)
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#define USB_PORTSC1_PR_SHIFT (8U)
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#define USB_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK)
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#define USB_PORTSC1_HSP_MASK (0x200U)
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#define USB_PORTSC1_HSP_SHIFT (9U)
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#define USB_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK)
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#define USB_PORTSC1_LS_MASK (0xC00U)
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#define USB_PORTSC1_LS_SHIFT (10U)
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/*! LS
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* 0b00..SE0
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* 0b10..J-state
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* 0b01..K-state
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* 0b11..Undefined
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*/
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#define USB_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK)
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#define USB_PORTSC1_PP_MASK (0x1000U)
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#define USB_PORTSC1_PP_SHIFT (12U)
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#define USB_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK)
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#define USB_PORTSC1_PO_MASK (0x2000U)
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#define USB_PORTSC1_PO_SHIFT (13U)
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#define USB_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK)
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#define USB_PORTSC1_PIC_MASK (0xC000U)
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#define USB_PORTSC1_PIC_SHIFT (14U)
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/*! PIC
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* 0b00..Port indicators are off
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* 0b01..Amber
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* 0b10..Green
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* 0b11..Undefined
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*/
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#define USB_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK)
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#define USB_PORTSC1_PTC_MASK (0xF0000U)
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#define USB_PORTSC1_PTC_SHIFT (16U)
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/*! PTC
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* 0b0000..TEST_MODE_DISABLE
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* 0b0001..J_STATE
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* 0b0010..K_STATE
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* 0b0011..SE0 (host) / NAK (device)
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* 0b0100..Packet
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* 0b0101..FORCE_ENABLE_HS
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* 0b0110..FORCE_ENABLE_FS
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* 0b0111..FORCE_ENABLE_LS
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*/
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#define USB_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK)
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#define USB_PORTSC1_WKCN_MASK (0x100000U)
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#define USB_PORTSC1_WKCN_SHIFT (20U)
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#define USB_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK)
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#define USB_PORTSC1_WKDC_MASK (0x200000U)
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#define USB_PORTSC1_WKDC_SHIFT (21U)
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#define USB_PORTSC1_WKDC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK)
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#define USB_PORTSC1_WKOC_MASK (0x400000U)
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#define USB_PORTSC1_WKOC_SHIFT (22U)
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#define USB_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK)
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#define USB_PORTSC1_PHCD_MASK (0x800000U)
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#define USB_PORTSC1_PHCD_SHIFT (23U)
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/*! PHCD
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* 0b1..Disable PHY clock
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* 0b0..Enable PHY clock
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*/
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#define USB_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK)
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#define USB_PORTSC1_PFSC_MASK (0x1000000U)
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#define USB_PORTSC1_PFSC_SHIFT (24U)
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/*! PFSC
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* 0b1..Forced to full speed
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* 0b0..Normal operation
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*/
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#define USB_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK)
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#define USB_PORTSC1_PTS_2_MASK (0x2000000U)
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#define USB_PORTSC1_PTS_2_SHIFT (25U)
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#define USB_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK)
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#define USB_PORTSC1_PSPD_MASK (0xC000000U)
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#define USB_PORTSC1_PSPD_SHIFT (26U)
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/*! PSPD
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* 0b00..Full Speed
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* 0b01..Low Speed
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* 0b10..High Speed
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* 0b11..Undefined
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*/
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#define USB_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK)
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#define USB_PORTSC1_PTW_MASK (0x10000000U)
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#define USB_PORTSC1_PTW_SHIFT (28U)
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/*! PTW
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* 0b0..Select the 8-bit UTMI interface [60MHz]
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* 0b1..Select the 16-bit UTMI interface [30MHz]
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*/
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#define USB_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK)
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#define USB_PORTSC1_STS_MASK (0x20000000U)
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#define USB_PORTSC1_STS_SHIFT (29U)
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#define USB_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK)
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#define USB_PORTSC1_PTS_1_MASK (0xC0000000U)
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#define USB_PORTSC1_PTS_1_SHIFT (30U)
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#define USB_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK)
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/*! @} */
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/*! @name OTGSC - On-The-Go Status & control */
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/*! @{ */
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#define USB_OTGSC_VD_MASK (0x1U)
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#define USB_OTGSC_VD_SHIFT (0U)
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#define USB_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK)
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#define USB_OTGSC_VC_MASK (0x2U)
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#define USB_OTGSC_VC_SHIFT (1U)
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#define USB_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK)
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#define USB_OTGSC_OT_MASK (0x8U)
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#define USB_OTGSC_OT_SHIFT (3U)
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#define USB_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK)
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#define USB_OTGSC_DP_MASK (0x10U)
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#define USB_OTGSC_DP_SHIFT (4U)
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#define USB_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK)
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#define USB_OTGSC_IDPU_MASK (0x20U)
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#define USB_OTGSC_IDPU_SHIFT (5U)
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#define USB_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK)
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#define USB_OTGSC_ID_MASK (0x100U)
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#define USB_OTGSC_ID_SHIFT (8U)
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#define USB_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK)
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#define USB_OTGSC_AVV_MASK (0x200U)
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#define USB_OTGSC_AVV_SHIFT (9U)
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#define USB_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK)
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#define USB_OTGSC_ASV_MASK (0x400U)
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#define USB_OTGSC_ASV_SHIFT (10U)
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#define USB_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK)
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#define USB_OTGSC_BSV_MASK (0x800U)
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#define USB_OTGSC_BSV_SHIFT (11U)
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#define USB_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK)
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#define USB_OTGSC_BSE_MASK (0x1000U)
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#define USB_OTGSC_BSE_SHIFT (12U)
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#define USB_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK)
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#define USB_OTGSC_TOG_1MS_MASK (0x2000U)
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#define USB_OTGSC_TOG_1MS_SHIFT (13U)
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#define USB_OTGSC_TOG_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK)
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#define USB_OTGSC_DPS_MASK (0x4000U)
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#define USB_OTGSC_DPS_SHIFT (14U)
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#define USB_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK)
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#define USB_OTGSC_IDIS_MASK (0x10000U)
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#define USB_OTGSC_IDIS_SHIFT (16U)
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#define USB_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK)
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#define USB_OTGSC_AVVIS_MASK (0x20000U)
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#define USB_OTGSC_AVVIS_SHIFT (17U)
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#define USB_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK)
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#define USB_OTGSC_ASVIS_MASK (0x40000U)
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#define USB_OTGSC_ASVIS_SHIFT (18U)
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#define USB_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK)
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#define USB_OTGSC_BSVIS_MASK (0x80000U)
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#define USB_OTGSC_BSVIS_SHIFT (19U)
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#define USB_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK)
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#define USB_OTGSC_BSEIS_MASK (0x100000U)
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#define USB_OTGSC_BSEIS_SHIFT (20U)
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#define USB_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK)
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#define USB_OTGSC_STATUS_1MS_MASK (0x200000U)
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#define USB_OTGSC_STATUS_1MS_SHIFT (21U)
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#define USB_OTGSC_STATUS_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK)
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#define USB_OTGSC_DPIS_MASK (0x400000U)
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#define USB_OTGSC_DPIS_SHIFT (22U)
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#define USB_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK)
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#define USB_OTGSC_IDIE_MASK (0x1000000U)
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#define USB_OTGSC_IDIE_SHIFT (24U)
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#define USB_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK)
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#define USB_OTGSC_AVVIE_MASK (0x2000000U)
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#define USB_OTGSC_AVVIE_SHIFT (25U)
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#define USB_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK)
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#define USB_OTGSC_ASVIE_MASK (0x4000000U)
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#define USB_OTGSC_ASVIE_SHIFT (26U)
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#define USB_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK)
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#define USB_OTGSC_BSVIE_MASK (0x8000000U)
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#define USB_OTGSC_BSVIE_SHIFT (27U)
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#define USB_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK)
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#define USB_OTGSC_BSEIE_MASK (0x10000000U)
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#define USB_OTGSC_BSEIE_SHIFT (28U)
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#define USB_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK)
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#define USB_OTGSC_EN_1MS_MASK (0x20000000U)
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#define USB_OTGSC_EN_1MS_SHIFT (29U)
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#define USB_OTGSC_EN_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK)
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#define USB_OTGSC_DPIE_MASK (0x40000000U)
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#define USB_OTGSC_DPIE_SHIFT (30U)
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#define USB_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK)
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/*! @} */
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/*! @name USBMODE - USB Device Mode */
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/*! @{ */
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#define USB_USBMODE_CM_MASK (0x3U)
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#define USB_USBMODE_CM_SHIFT (0U)
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/*! CM
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* 0b00..Idle [Default for combination host/device]
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* 0b01..Reserved
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* 0b10..Device Controller [Default for device only controller]
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* 0b11..Host Controller [Default for host only controller]
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*/
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#define USB_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK)
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#define USB_USBMODE_ES_MASK (0x4U)
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#define USB_USBMODE_ES_SHIFT (2U)
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/*! ES
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|
* 0b0..Little Endian [Default]
|
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* 0b1..Big Endian
|
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*/
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#define USB_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK)
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#define USB_USBMODE_SLOM_MASK (0x8U)
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#define USB_USBMODE_SLOM_SHIFT (3U)
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/*! SLOM
|
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* 0b0..Setup Lockouts On (default);
|
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* 0b1..Setup Lockouts Off (DCD requires use of Setup Data Buffer Tripwire in USBCMDUSB Command Register .
|
|
*/
|
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#define USB_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK)
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#define USB_USBMODE_SDIS_MASK (0x10U)
|
|
#define USB_USBMODE_SDIS_SHIFT (4U)
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#define USB_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK)
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/*! @} */
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/*! @name ENDPTSETUPSTAT - Endpoint Setup Status */
|
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/*! @{ */
|
|
#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU)
|
|
#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U)
|
|
#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK)
|
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/*! @} */
|
|
|
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/*! @name ENDPTPRIME - Endpoint Prime */
|
|
/*! @{ */
|
|
#define USB_ENDPTPRIME_PERB_MASK (0xFFU)
|
|
#define USB_ENDPTPRIME_PERB_SHIFT (0U)
|
|
#define USB_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK)
|
|
#define USB_ENDPTPRIME_PETB_MASK (0xFF0000U)
|
|
#define USB_ENDPTPRIME_PETB_SHIFT (16U)
|
|
#define USB_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK)
|
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/*! @} */
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|
|
|
/*! @name ENDPTFLUSH - Endpoint Flush */
|
|
/*! @{ */
|
|
#define USB_ENDPTFLUSH_FERB_MASK (0xFFU)
|
|
#define USB_ENDPTFLUSH_FERB_SHIFT (0U)
|
|
#define USB_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK)
|
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#define USB_ENDPTFLUSH_FETB_MASK (0xFF0000U)
|
|
#define USB_ENDPTFLUSH_FETB_SHIFT (16U)
|
|
#define USB_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK)
|
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/*! @} */
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|
|
|
/*! @name ENDPTSTAT - Endpoint Status */
|
|
/*! @{ */
|
|
#define USB_ENDPTSTAT_ERBR_MASK (0xFFU)
|
|
#define USB_ENDPTSTAT_ERBR_SHIFT (0U)
|
|
#define USB_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK)
|
|
#define USB_ENDPTSTAT_ETBR_MASK (0xFF0000U)
|
|
#define USB_ENDPTSTAT_ETBR_SHIFT (16U)
|
|
#define USB_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK)
|
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/*! @} */
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|
|
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/*! @name ENDPTCOMPLETE - Endpoint Complete */
|
|
/*! @{ */
|
|
#define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFU)
|
|
#define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U)
|
|
#define USB_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK)
|
|
#define USB_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U)
|
|
#define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U)
|
|
#define USB_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ENDPTCTRL0 - Endpoint Control0 */
|
|
/*! @{ */
|
|
#define USB_ENDPTCTRL0_RXS_MASK (0x1U)
|
|
#define USB_ENDPTCTRL0_RXS_SHIFT (0U)
|
|
#define USB_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK)
|
|
#define USB_ENDPTCTRL0_RXT_MASK (0xCU)
|
|
#define USB_ENDPTCTRL0_RXT_SHIFT (2U)
|
|
#define USB_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXT_SHIFT)) & USB_ENDPTCTRL0_RXT_MASK)
|
|
#define USB_ENDPTCTRL0_RXE_MASK (0x80U)
|
|
#define USB_ENDPTCTRL0_RXE_SHIFT (7U)
|
|
#define USB_ENDPTCTRL0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXE_SHIFT)) & USB_ENDPTCTRL0_RXE_MASK)
|
|
#define USB_ENDPTCTRL0_TXS_MASK (0x10000U)
|
|
#define USB_ENDPTCTRL0_TXS_SHIFT (16U)
|
|
#define USB_ENDPTCTRL0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXS_SHIFT)) & USB_ENDPTCTRL0_TXS_MASK)
|
|
#define USB_ENDPTCTRL0_TXT_MASK (0xC0000U)
|
|
#define USB_ENDPTCTRL0_TXT_SHIFT (18U)
|
|
#define USB_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXT_SHIFT)) & USB_ENDPTCTRL0_TXT_MASK)
|
|
#define USB_ENDPTCTRL0_TXE_MASK (0x800000U)
|
|
#define USB_ENDPTCTRL0_TXE_SHIFT (23U)
|
|
#define USB_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ENDPTCTRL - Endpoint Control 1..Endpoint Control 7 */
|
|
/*! @{ */
|
|
#define USB_ENDPTCTRL_RXS_MASK (0x1U)
|
|
#define USB_ENDPTCTRL_RXS_SHIFT (0U)
|
|
#define USB_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK)
|
|
#define USB_ENDPTCTRL_RXD_MASK (0x2U)
|
|
#define USB_ENDPTCTRL_RXD_SHIFT (1U)
|
|
#define USB_ENDPTCTRL_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXD_SHIFT)) & USB_ENDPTCTRL_RXD_MASK)
|
|
#define USB_ENDPTCTRL_RXT_MASK (0xCU)
|
|
#define USB_ENDPTCTRL_RXT_SHIFT (2U)
|
|
#define USB_ENDPTCTRL_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXT_SHIFT)) & USB_ENDPTCTRL_RXT_MASK)
|
|
#define USB_ENDPTCTRL_RXI_MASK (0x20U)
|
|
#define USB_ENDPTCTRL_RXI_SHIFT (5U)
|
|
#define USB_ENDPTCTRL_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXI_SHIFT)) & USB_ENDPTCTRL_RXI_MASK)
|
|
#define USB_ENDPTCTRL_RXR_MASK (0x40U)
|
|
#define USB_ENDPTCTRL_RXR_SHIFT (6U)
|
|
#define USB_ENDPTCTRL_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXR_SHIFT)) & USB_ENDPTCTRL_RXR_MASK)
|
|
#define USB_ENDPTCTRL_RXE_MASK (0x80U)
|
|
#define USB_ENDPTCTRL_RXE_SHIFT (7U)
|
|
#define USB_ENDPTCTRL_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXE_SHIFT)) & USB_ENDPTCTRL_RXE_MASK)
|
|
#define USB_ENDPTCTRL_TXS_MASK (0x10000U)
|
|
#define USB_ENDPTCTRL_TXS_SHIFT (16U)
|
|
#define USB_ENDPTCTRL_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXS_SHIFT)) & USB_ENDPTCTRL_TXS_MASK)
|
|
#define USB_ENDPTCTRL_TXD_MASK (0x20000U)
|
|
#define USB_ENDPTCTRL_TXD_SHIFT (17U)
|
|
#define USB_ENDPTCTRL_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXD_SHIFT)) & USB_ENDPTCTRL_TXD_MASK)
|
|
#define USB_ENDPTCTRL_TXT_MASK (0xC0000U)
|
|
#define USB_ENDPTCTRL_TXT_SHIFT (18U)
|
|
#define USB_ENDPTCTRL_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXT_SHIFT)) & USB_ENDPTCTRL_TXT_MASK)
|
|
#define USB_ENDPTCTRL_TXI_MASK (0x200000U)
|
|
#define USB_ENDPTCTRL_TXI_SHIFT (21U)
|
|
#define USB_ENDPTCTRL_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXI_SHIFT)) & USB_ENDPTCTRL_TXI_MASK)
|
|
#define USB_ENDPTCTRL_TXR_MASK (0x400000U)
|
|
#define USB_ENDPTCTRL_TXR_SHIFT (22U)
|
|
#define USB_ENDPTCTRL_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXR_SHIFT)) & USB_ENDPTCTRL_TXR_MASK)
|
|
#define USB_ENDPTCTRL_TXE_MASK (0x800000U)
|
|
#define USB_ENDPTCTRL_TXE_SHIFT (23U)
|
|
#define USB_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of USB_ENDPTCTRL */
|
|
#define USB_ENDPTCTRL_COUNT (7U)
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group USB_Register_Masks */
|
|
|
|
|
|
/* USB - Peripheral instance base addresses */
|
|
/** Peripheral USB1 base address */
|
|
#define USB1_BASE (0x402E0000u)
|
|
/** Peripheral USB1 base pointer */
|
|
#define USB1 ((USB_Type *)USB1_BASE)
|
|
/** Peripheral USB2 base address */
|
|
#define USB2_BASE (0x402E0200u)
|
|
/** Peripheral USB2 base pointer */
|
|
#define USB2 ((USB_Type *)USB2_BASE)
|
|
/** Array initializer of USB peripheral base addresses */
|
|
#define USB_BASE_ADDRS { 0u, USB1_BASE, USB2_BASE }
|
|
/** Array initializer of USB peripheral base pointers */
|
|
#define USB_BASE_PTRS { (USB_Type *)0u, USB1, USB2 }
|
|
/** Interrupt vectors for the USB peripheral type */
|
|
#define USB_IRQS { NotAvail_IRQn, USB_OTG1_IRQn, USB_OTG2_IRQn }
|
|
/* Backward compatibility */
|
|
#define GPTIMER0CTL GPTIMER0CTRL
|
|
#define GPTIMER1CTL GPTIMER1CTRL
|
|
#define USB_SBUSCFG SBUSCFG
|
|
#define EPLISTADDR ENDPTLISTADDR
|
|
#define EPSETUPSR ENDPTSETUPSTAT
|
|
#define EPPRIME ENDPTPRIME
|
|
#define EPFLUSH ENDPTFLUSH
|
|
#define EPSR ENDPTSTAT
|
|
#define EPCOMPLETE ENDPTCOMPLETE
|
|
#define EPCR ENDPTCTRL
|
|
#define EPCR0 ENDPTCTRL0
|
|
#define USBHS_ID_ID_MASK USB_ID_ID_MASK
|
|
#define USBHS_ID_ID_SHIFT USB_ID_ID_SHIFT
|
|
#define USBHS_ID_ID(x) USB_ID_ID(x)
|
|
#define USBHS_ID_NID_MASK USB_ID_NID_MASK
|
|
#define USBHS_ID_NID_SHIFT USB_ID_NID_SHIFT
|
|
#define USBHS_ID_NID(x) USB_ID_NID(x)
|
|
#define USBHS_ID_REVISION_MASK USB_ID_REVISION_MASK
|
|
#define USBHS_ID_REVISION_SHIFT USB_ID_REVISION_SHIFT
|
|
#define USBHS_ID_REVISION(x) USB_ID_REVISION(x)
|
|
#define USBHS_HWGENERAL_PHYW_MASK USB_HWGENERAL_PHYW_MASK
|
|
#define USBHS_HWGENERAL_PHYW_SHIFT USB_HWGENERAL_PHYW_SHIFT
|
|
#define USBHS_HWGENERAL_PHYW(x) USB_HWGENERAL_PHYW(x)
|
|
#define USBHS_HWGENERAL_PHYM_MASK USB_HWGENERAL_PHYM_MASK
|
|
#define USBHS_HWGENERAL_PHYM_SHIFT USB_HWGENERAL_PHYM_SHIFT
|
|
#define USBHS_HWGENERAL_PHYM(x) USB_HWGENERAL_PHYM(x)
|
|
#define USBHS_HWGENERAL_SM_MASK USB_HWGENERAL_SM_MASK
|
|
#define USBHS_HWGENERAL_SM_SHIFT USB_HWGENERAL_SM_SHIFT
|
|
#define USBHS_HWGENERAL_SM(x) USB_HWGENERAL_SM(x)
|
|
#define USBHS_HWHOST_HC_MASK USB_HWHOST_HC_MASK
|
|
#define USBHS_HWHOST_HC_SHIFT USB_HWHOST_HC_SHIFT
|
|
#define USBHS_HWHOST_HC(x) USB_HWHOST_HC(x)
|
|
#define USBHS_HWHOST_NPORT_MASK USB_HWHOST_NPORT_MASK
|
|
#define USBHS_HWHOST_NPORT_SHIFT USB_HWHOST_NPORT_SHIFT
|
|
#define USBHS_HWHOST_NPORT(x) USB_HWHOST_NPORT(x)
|
|
#define USBHS_HWDEVICE_DC_MASK USB_HWDEVICE_DC_MASK
|
|
#define USBHS_HWDEVICE_DC_SHIFT USB_HWDEVICE_DC_SHIFT
|
|
#define USBHS_HWDEVICE_DC(x) USB_HWDEVICE_DC(x)
|
|
#define USBHS_HWDEVICE_DEVEP_MASK USB_HWDEVICE_DEVEP_MASK
|
|
#define USBHS_HWDEVICE_DEVEP_SHIFT USB_HWDEVICE_DEVEP_SHIFT
|
|
#define USBHS_HWDEVICE_DEVEP(x) USB_HWDEVICE_DEVEP(x)
|
|
#define USBHS_HWTXBUF_TXBURST_MASK USB_HWTXBUF_TXBURST_MASK
|
|
#define USBHS_HWTXBUF_TXBURST_SHIFT USB_HWTXBUF_TXBURST_SHIFT
|
|
#define USBHS_HWTXBUF_TXBURST(x) USB_HWTXBUF_TXBURST(x)
|
|
#define USBHS_HWTXBUF_TXCHANADD_MASK USB_HWTXBUF_TXCHANADD_MASK
|
|
#define USBHS_HWTXBUF_TXCHANADD_SHIFT USB_HWTXBUF_TXCHANADD_SHIFT
|
|
#define USBHS_HWTXBUF_TXCHANADD(x) USB_HWTXBUF_TXCHANADD(x)
|
|
#define USBHS_HWRXBUF_RXBURST_MASK USB_HWRXBUF_RXBURST_MASK
|
|
#define USBHS_HWRXBUF_RXBURST_SHIFT USB_HWRXBUF_RXBURST_SHIFT
|
|
#define USBHS_HWRXBUF_RXBURST(x) USB_HWRXBUF_RXBURST(x)
|
|
#define USBHS_HWRXBUF_RXADD_MASK USB_HWRXBUF_RXADD_MASK
|
|
#define USBHS_HWRXBUF_RXADD_SHIFT USB_HWRXBUF_RXADD_SHIFT
|
|
#define USBHS_HWRXBUF_RXADD(x) USB_HWRXBUF_RXADD(x)
|
|
#define USBHS_GPTIMER0LD_GPTLD_MASK USB_GPTIMER0LD_GPTLD_MASK
|
|
#define USBHS_GPTIMER0LD_GPTLD_SHIFT USB_GPTIMER0LD_GPTLD_SHIFT
|
|
#define USBHS_GPTIMER0LD_GPTLD(x) USB_GPTIMER0LD_GPTLD(x)
|
|
#define USBHS_GPTIMER0CTL_GPTCNT_MASK USB_GPTIMER0CTRL_GPTCNT_MASK
|
|
#define USBHS_GPTIMER0CTL_GPTCNT_SHIFT USB_GPTIMER0CTRL_GPTCNT_SHIFT
|
|
#define USBHS_GPTIMER0CTL_GPTCNT(x) USB_GPTIMER0CTRL_GPTCNT(x)
|
|
#define USBHS_GPTIMER0CTL_MODE_MASK USB_GPTIMER0CTRL_GPTMODE_MASK
|
|
#define USBHS_GPTIMER0CTL_MODE_SHIFT USB_GPTIMER0CTRL_GPTMODE_SHIFT
|
|
#define USBHS_GPTIMER0CTL_MODE(x) USB_GPTIMER0CTRL_GPTMODE(x)
|
|
#define USBHS_GPTIMER0CTL_RST_MASK USB_GPTIMER0CTRL_GPTRST_MASK
|
|
#define USBHS_GPTIMER0CTL_RST_SHIFT USB_GPTIMER0CTRL_GPTRST_SHIFT
|
|
#define USBHS_GPTIMER0CTL_RST(x) USB_GPTIMER0CTRL_GPTRST(x)
|
|
#define USBHS_GPTIMER0CTL_RUN_MASK USB_GPTIMER0CTRL_GPTRUN_MASK
|
|
#define USBHS_GPTIMER0CTL_RUN_SHIFT USB_GPTIMER0CTRL_GPTRUN_SHIFT
|
|
#define USBHS_GPTIMER0CTL_RUN(x) USB_GPTIMER0CTRL_GPTRUN(x)
|
|
#define USBHS_GPTIMER1LD_GPTLD_MASK USB_GPTIMER1LD_GPTLD_MASK
|
|
#define USBHS_GPTIMER1LD_GPTLD_SHIFT USB_GPTIMER1LD_GPTLD_SHIFT
|
|
#define USBHS_GPTIMER1LD_GPTLD(x) USB_GPTIMER1LD_GPTLD(x)
|
|
#define USBHS_GPTIMER1CTL_GPTCNT_MASK USB_GPTIMER1CTRL_GPTCNT_MASK
|
|
#define USBHS_GPTIMER1CTL_GPTCNT_SHIFT USB_GPTIMER1CTRL_GPTCNT_SHIFT
|
|
#define USBHS_GPTIMER1CTL_GPTCNT(x) USB_GPTIMER1CTRL_GPTCNT(x)
|
|
#define USBHS_GPTIMER1CTL_MODE_MASK USB_GPTIMER1CTRL_GPTMODE_MASK
|
|
#define USBHS_GPTIMER1CTL_MODE_SHIFT USB_GPTIMER1CTRL_GPTMODE_SHIFT
|
|
#define USBHS_GPTIMER1CTL_MODE(x) USB_GPTIMER1CTRL_GPTMODE(x)
|
|
#define USBHS_GPTIMER1CTL_RST_MASK USB_GPTIMER1CTRL_GPTRST_MASK
|
|
#define USBHS_GPTIMER1CTL_RST_SHIFT USB_GPTIMER1CTRL_GPTRST_SHIFT
|
|
#define USBHS_GPTIMER1CTL_RST(x) USB_GPTIMER1CTRL_GPTRST(x)
|
|
#define USBHS_GPTIMER1CTL_RUN_MASK USB_GPTIMER1CTRL_GPTRUN_MASK
|
|
#define USBHS_GPTIMER1CTL_RUN_SHIFT USB_GPTIMER1CTRL_GPTRUN_SHIFT
|
|
#define USBHS_GPTIMER1CTL_RUN(x) USB_GPTIMER1CTRL_GPTRUN(x)
|
|
#define USBHS_USB_SBUSCFG_BURSTMODE_MASK USB_SBUSCFG_AHBBRST_MASK
|
|
#define USBHS_USB_SBUSCFG_BURSTMODE_SHIFT USB_SBUSCFG_AHBBRST_SHIFT
|
|
#define USBHS_USB_SBUSCFG_BURSTMODE(x) USB_SBUSCFG_AHBBRST(x)
|
|
#define USBHS_HCIVERSION_CAPLENGTH(x) USB_HCIVERSION_CAPLENGTH(x)
|
|
#define USBHS_HCIVERSION_HCIVERSION_MASK USB_HCIVERSION_HCIVERSION_MASK
|
|
#define USBHS_HCIVERSION_HCIVERSION_SHIFT USB_HCIVERSION_HCIVERSION_SHIFT
|
|
#define USBHS_HCIVERSION_HCIVERSION(x) USB_HCIVERSION_HCIVERSION(x)
|
|
#define USBHS_HCSPARAMS_N_PORTS_MASK USB_HCSPARAMS_N_PORTS_MASK
|
|
#define USBHS_HCSPARAMS_N_PORTS_SHIFT USB_HCSPARAMS_N_PORTS_SHIFT
|
|
#define USBHS_HCSPARAMS_N_PORTS(x) USB_HCSPARAMS_N_PORTS(x)
|
|
#define USBHS_HCSPARAMS_PPC_MASK USB_HCSPARAMS_PPC_MASK
|
|
#define USBHS_HCSPARAMS_PPC_SHIFT USB_HCSPARAMS_PPC_SHIFT
|
|
#define USBHS_HCSPARAMS_PPC(x) USB_HCSPARAMS_PPC(x)
|
|
#define USBHS_HCSPARAMS_N_PCC_MASK USB_HCSPARAMS_N_PCC_MASK
|
|
#define USBHS_HCSPARAMS_N_PCC_SHIFT USB_HCSPARAMS_N_PCC_SHIFT
|
|
#define USBHS_HCSPARAMS_N_PCC(x) USB_HCSPARAMS_N_PCC(x)
|
|
#define USBHS_HCSPARAMS_N_CC_MASK USB_HCSPARAMS_N_CC_MASK
|
|
#define USBHS_HCSPARAMS_N_CC_SHIFT USB_HCSPARAMS_N_CC_SHIFT
|
|
#define USBHS_HCSPARAMS_N_CC(x) USB_HCSPARAMS_N_CC(x)
|
|
#define USBHS_HCSPARAMS_PI_MASK USB_HCSPARAMS_PI_MASK
|
|
#define USBHS_HCSPARAMS_PI_SHIFT USB_HCSPARAMS_PI_SHIFT
|
|
#define USBHS_HCSPARAMS_PI(x) USB_HCSPARAMS_PI(x)
|
|
#define USBHS_HCSPARAMS_N_PTT_MASK USB_HCSPARAMS_N_PTT_MASK
|
|
#define USBHS_HCSPARAMS_N_PTT_SHIFT USB_HCSPARAMS_N_PTT_SHIFT
|
|
#define USBHS_HCSPARAMS_N_PTT(x) USB_HCSPARAMS_N_PTT(x)
|
|
#define USBHS_HCSPARAMS_N_TT_MASK USB_HCSPARAMS_N_TT_MASK
|
|
#define USBHS_HCSPARAMS_N_TT_SHIFT USB_HCSPARAMS_N_TT_SHIFT
|
|
#define USBHS_HCSPARAMS_N_TT(x) USB_HCSPARAMS_N_TT(x)
|
|
#define USBHS_HCCPARAMS_ADC_MASK USB_HCCPARAMS_ADC_MASK
|
|
#define USBHS_HCCPARAMS_ADC_SHIFT USB_HCCPARAMS_ADC_SHIFT
|
|
#define USBHS_HCCPARAMS_ADC(x) USB_HCCPARAMS_ADC(x)
|
|
#define USBHS_HCCPARAMS_PFL_MASK USB_HCCPARAMS_PFL_MASK
|
|
#define USBHS_HCCPARAMS_PFL_SHIFT USB_HCCPARAMS_PFL_SHIFT
|
|
#define USBHS_HCCPARAMS_PFL(x) USB_HCCPARAMS_PFL(x)
|
|
#define USBHS_HCCPARAMS_ASP_MASK USB_HCCPARAMS_ASP_MASK
|
|
#define USBHS_HCCPARAMS_ASP_SHIFT USB_HCCPARAMS_ASP_SHIFT
|
|
#define USBHS_HCCPARAMS_ASP(x) USB_HCCPARAMS_ASP(x)
|
|
#define USBHS_HCCPARAMS_IST_MASK USB_HCCPARAMS_IST_MASK
|
|
#define USBHS_HCCPARAMS_IST_SHIFT USB_HCCPARAMS_IST_SHIFT
|
|
#define USBHS_HCCPARAMS_IST(x) USB_HCCPARAMS_IST(x)
|
|
#define USBHS_HCCPARAMS_EECP_MASK USB_HCCPARAMS_EECP_MASK
|
|
#define USBHS_HCCPARAMS_EECP_SHIFT USB_HCCPARAMS_EECP_SHIFT
|
|
#define USBHS_HCCPARAMS_EECP(x) USB_HCCPARAMS_EECP(x)
|
|
#define USBHS_DCIVERSION_DCIVERSION_MASK USB_DCIVERSION_DCIVERSION_MASK
|
|
#define USBHS_DCIVERSION_DCIVERSION_SHIFT USB_DCIVERSION_DCIVERSION_SHIFT
|
|
#define USBHS_DCIVERSION_DCIVERSION(x) USB_DCIVERSION_DCIVERSION(x)
|
|
#define USBHS_DCCPARAMS_DEN_MASK USB_DCCPARAMS_DEN_MASK
|
|
#define USBHS_DCCPARAMS_DEN_SHIFT USB_DCCPARAMS_DEN_SHIFT
|
|
#define USBHS_DCCPARAMS_DEN(x) USB_DCCPARAMS_DEN(x)
|
|
#define USBHS_DCCPARAMS_DC_MASK USB_DCCPARAMS_DC_MASK
|
|
#define USBHS_DCCPARAMS_DC_SHIFT USB_DCCPARAMS_DC_SHIFT
|
|
#define USBHS_DCCPARAMS_DC(x) USB_DCCPARAMS_DC(x)
|
|
#define USBHS_DCCPARAMS_HC_MASK USB_DCCPARAMS_HC_MASK
|
|
#define USBHS_DCCPARAMS_HC_SHIFT USB_DCCPARAMS_HC_SHIFT
|
|
#define USBHS_DCCPARAMS_HC(x) USB_DCCPARAMS_HC(x)
|
|
#define USBHS_USBCMD_RS_MASK USB_USBCMD_RS_MASK
|
|
#define USBHS_USBCMD_RS_SHIFT USB_USBCMD_RS_SHIFT
|
|
#define USBHS_USBCMD_RS(x) USB_USBCMD_RS(x)
|
|
#define USBHS_USBCMD_RST_MASK USB_USBCMD_RST_MASK
|
|
#define USBHS_USBCMD_RST_SHIFT USB_USBCMD_RST_SHIFT
|
|
#define USBHS_USBCMD_RST(x) USB_USBCMD_RST(x)
|
|
#define USBHS_USBCMD_FS_MASK USB_USBCMD_FS_1_MASK
|
|
#define USBHS_USBCMD_FS_SHIFT USB_USBCMD_FS_1_SHIFT
|
|
#define USBHS_USBCMD_FS(x) USB_USBCMD_FS_1(x)
|
|
#define USBHS_USBCMD_PSE_MASK USB_USBCMD_PSE_MASK
|
|
#define USBHS_USBCMD_PSE_SHIFT USB_USBCMD_PSE_SHIFT
|
|
#define USBHS_USBCMD_PSE(x) USB_USBCMD_PSE(x)
|
|
#define USBHS_USBCMD_ASE_MASK USB_USBCMD_ASE_MASK
|
|
#define USBHS_USBCMD_ASE_SHIFT USB_USBCMD_ASE_SHIFT
|
|
#define USBHS_USBCMD_ASE(x) USB_USBCMD_ASE(x)
|
|
#define USBHS_USBCMD_IAA_MASK USB_USBCMD_IAA_MASK
|
|
#define USBHS_USBCMD_IAA_SHIFT USB_USBCMD_IAA_SHIFT
|
|
#define USBHS_USBCMD_IAA(x) USB_USBCMD_IAA(x)
|
|
#define USBHS_USBCMD_ASP_MASK USB_USBCMD_ASP_MASK
|
|
#define USBHS_USBCMD_ASP_SHIFT USB_USBCMD_ASP_SHIFT
|
|
#define USBHS_USBCMD_ASP(x) USB_USBCMD_ASP(x)
|
|
#define USBHS_USBCMD_ASPE_MASK USB_USBCMD_ASPE_MASK
|
|
#define USBHS_USBCMD_ASPE_SHIFT USB_USBCMD_ASPE_SHIFT
|
|
#define USBHS_USBCMD_ASPE(x) USB_USBCMD_ASPE(x)
|
|
#define USBHS_USBCMD_ATDTW_MASK USB_USBCMD_ATDTW_MASK
|
|
#define USBHS_USBCMD_ATDTW_SHIFT USB_USBCMD_ATDTW_SHIFT
|
|
#define USBHS_USBCMD_ATDTW(x) USB_USBCMD_ATDTW(x)
|
|
#define USBHS_USBCMD_SUTW_MASK USB_USBCMD_SUTW_MASK
|
|
#define USBHS_USBCMD_SUTW_SHIFT USB_USBCMD_SUTW_SHIFT
|
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#define USBHS_USBCMD_SUTW(x) USB_USBCMD_SUTW(x)
|
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#define USBHS_USBCMD_FS2_MASK USB_USBCMD_FS_2_MASK
|
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#define USBHS_USBCMD_FS2_SHIFT USB_USBCMD_FS_2_SHIFT
|
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#define USBHS_USBCMD_FS2(x) USB_USBCMD_FS_2(x)
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#define USBHS_USBCMD_ITC_MASK USB_USBCMD_ITC_MASK
|
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#define USBHS_USBCMD_ITC_SHIFT USB_USBCMD_ITC_SHIFT
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#define USBHS_USBCMD_ITC(x) USB_USBCMD_ITC(x)
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#define USBHS_USBSTS_UI_MASK USB_USBSTS_UI_MASK
|
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#define USBHS_USBSTS_UI_SHIFT USB_USBSTS_UI_SHIFT
|
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#define USBHS_USBSTS_UI(x) USB_USBSTS_UI(x)
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#define USBHS_USBSTS_UEI_MASK USB_USBSTS_UEI_MASK
|
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#define USBHS_USBSTS_UEI_SHIFT USB_USBSTS_UEI_SHIFT
|
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#define USBHS_USBSTS_UEI(x) USB_USBSTS_UEI(x)
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#define USBHS_USBSTS_PCI_MASK USB_USBSTS_PCI_MASK
|
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#define USBHS_USBSTS_PCI_SHIFT USB_USBSTS_PCI_SHIFT
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#define USBHS_USBSTS_PCI(x) USB_USBSTS_PCI(x)
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#define USBHS_USBSTS_FRI_MASK USB_USBSTS_FRI_MASK
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#define USBHS_USBSTS_FRI_SHIFT USB_USBSTS_FRI_SHIFT
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#define USBHS_USBSTS_FRI(x) USB_USBSTS_FRI(x)
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#define USBHS_USBSTS_SEI_MASK USB_USBSTS_SEI_MASK
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#define USBHS_USBSTS_SEI_SHIFT USB_USBSTS_SEI_SHIFT
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#define USBHS_USBSTS_SEI(x) USB_USBSTS_SEI(x)
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#define USBHS_USBSTS_AAI_MASK USB_USBSTS_AAI_MASK
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#define USBHS_USBSTS_AAI_SHIFT USB_USBSTS_AAI_SHIFT
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#define USBHS_USBSTS_AAI(x) USB_USBSTS_AAI(x)
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#define USBHS_USBSTS_URI_MASK USB_USBSTS_URI_MASK
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#define USBHS_USBSTS_URI_SHIFT USB_USBSTS_URI_SHIFT
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#define USBHS_USBSTS_URI(x) USB_USBSTS_URI(x)
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#define USBHS_USBSTS_SRI_MASK USB_USBSTS_SRI_MASK
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#define USBHS_USBSTS_SRI_SHIFT USB_USBSTS_SRI_SHIFT
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#define USBHS_USBSTS_SRI(x) USB_USBSTS_SRI(x)
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#define USBHS_USBSTS_SLI_MASK USB_USBSTS_SLI_MASK
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#define USBHS_USBSTS_SLI_SHIFT USB_USBSTS_SLI_SHIFT
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#define USBHS_USBSTS_SLI(x) USB_USBSTS_SLI(x)
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#define USBHS_USBSTS_ULPII_MASK USB_USBSTS_ULPII_MASK
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#define USBHS_USBSTS_ULPII_SHIFT USB_USBSTS_ULPII_SHIFT
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#define USBHS_USBSTS_ULPII(x) USB_USBSTS_ULPII(x)
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#define USBHS_USBSTS_HCH_MASK USB_USBSTS_HCH_MASK
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#define USBHS_USBSTS_HCH_SHIFT USB_USBSTS_HCH_SHIFT
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#define USBHS_USBSTS_HCH(x) USB_USBSTS_HCH(x)
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#define USBHS_USBSTS_RCL_MASK USB_USBSTS_RCL_MASK
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#define USBHS_USBSTS_RCL_SHIFT USB_USBSTS_RCL_SHIFT
|
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#define USBHS_USBSTS_RCL(x) USB_USBSTS_RCL(x)
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#define USBHS_USBSTS_PS_MASK USB_USBSTS_PS_MASK
|
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#define USBHS_USBSTS_PS_SHIFT USB_USBSTS_PS_SHIFT
|
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#define USBHS_USBSTS_PS(x) USB_USBSTS_PS(x)
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#define USBHS_USBSTS_AS_MASK USB_USBSTS_AS_MASK
|
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#define USBHS_USBSTS_AS_SHIFT USB_USBSTS_AS_SHIFT
|
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#define USBHS_USBSTS_AS(x) USB_USBSTS_AS(x)
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#define USBHS_USBSTS_NAKI_MASK USB_USBSTS_NAKI_MASK
|
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#define USBHS_USBSTS_NAKI_SHIFT USB_USBSTS_NAKI_SHIFT
|
|
#define USBHS_USBSTS_NAKI(x) USB_USBSTS_NAKI(x)
|
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#define USBHS_USBSTS_TI0_MASK USB_USBSTS_TI0_MASK
|
|
#define USBHS_USBSTS_TI0_SHIFT USB_USBSTS_TI0_SHIFT
|
|
#define USBHS_USBSTS_TI0(x) USB_USBSTS_TI0(x)
|
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#define USBHS_USBSTS_TI1_MASK USB_USBSTS_TI1_MASK
|
|
#define USBHS_USBSTS_TI1_SHIFT USB_USBSTS_TI1_SHIFT
|
|
#define USBHS_USBSTS_TI1(x) USB_USBSTS_TI1(x)
|
|
#define USBHS_USBINTR_UE_MASK USB_USBINTR_UE_MASK
|
|
#define USBHS_USBINTR_UE_SHIFT USB_USBINTR_UE_SHIFT
|
|
#define USBHS_USBINTR_UE(x) USB_USBINTR_UE(x)
|
|
#define USBHS_USBINTR_UEE_MASK USB_USBINTR_UEE_MASK
|
|
#define USBHS_USBINTR_UEE_SHIFT USB_USBINTR_UEE_SHIFT
|
|
#define USBHS_USBINTR_UEE(x) USB_USBINTR_UEE(x)
|
|
#define USBHS_USBINTR_PCE_MASK USB_USBINTR_PCE_MASK
|
|
#define USBHS_USBINTR_PCE_SHIFT USB_USBINTR_PCE_SHIFT
|
|
#define USBHS_USBINTR_PCE(x) USB_USBINTR_PCE(x)
|
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#define USBHS_USBINTR_FRE_MASK USB_USBINTR_FRE_MASK
|
|
#define USBHS_USBINTR_FRE_SHIFT USB_USBINTR_FRE_SHIFT
|
|
#define USBHS_USBINTR_FRE(x) USB_USBINTR_FRE(x)
|
|
#define USBHS_USBINTR_SEE_MASK USB_USBINTR_SEE_MASK
|
|
#define USBHS_USBINTR_SEE_SHIFT USB_USBINTR_SEE_SHIFT
|
|
#define USBHS_USBINTR_SEE(x) USB_USBINTR_SEE(x)
|
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#define USBHS_USBINTR_AAE_MASK USB_USBINTR_AAE_MASK
|
|
#define USBHS_USBINTR_AAE_SHIFT USB_USBINTR_AAE_SHIFT
|
|
#define USBHS_USBINTR_AAE(x) USB_USBINTR_AAE(x)
|
|
#define USBHS_USBINTR_URE_MASK USB_USBINTR_URE_MASK
|
|
#define USBHS_USBINTR_URE_SHIFT USB_USBINTR_URE_SHIFT
|
|
#define USBHS_USBINTR_URE(x) USB_USBINTR_URE(x)
|
|
#define USBHS_USBINTR_SRE_MASK USB_USBINTR_SRE_MASK
|
|
#define USBHS_USBINTR_SRE_SHIFT USB_USBINTR_SRE_SHIFT
|
|
#define USBHS_USBINTR_SRE(x) USB_USBINTR_SRE(x)
|
|
#define USBHS_USBINTR_SLE_MASK USB_USBINTR_SLE_MASK
|
|
#define USBHS_USBINTR_SLE_SHIFT USB_USBINTR_SLE_SHIFT
|
|
#define USBHS_USBINTR_SLE(x) USB_USBINTR_SLE(x)
|
|
#define USBHS_USBINTR_ULPIE_MASK USB_USBINTR_ULPIE_MASK
|
|
#define USBHS_USBINTR_ULPIE_SHIFT USB_USBINTR_ULPIE_SHIFT
|
|
#define USBHS_USBINTR_ULPIE(x) USB_USBINTR_ULPIE(x)
|
|
#define USBHS_USBINTR_NAKE_MASK USB_USBINTR_NAKE_MASK
|
|
#define USBHS_USBINTR_NAKE_SHIFT USB_USBINTR_NAKE_SHIFT
|
|
#define USBHS_USBINTR_NAKE(x) USB_USBINTR_NAKE(x)
|
|
#define USBHS_USBINTR_UAIE_MASK USB_USBINTR_UAIE_MASK
|
|
#define USBHS_USBINTR_UAIE_SHIFT USB_USBINTR_UAIE_SHIFT
|
|
#define USBHS_USBINTR_UAIE(x) USB_USBINTR_UAIE(x)
|
|
#define USBHS_USBINTR_UPIE_MASK USB_USBINTR_UPIE_MASK
|
|
#define USBHS_USBINTR_UPIE_SHIFT USB_USBINTR_UPIE_SHIFT
|
|
#define USBHS_USBINTR_UPIE(x) USB_USBINTR_UPIE(x)
|
|
#define USBHS_USBINTR_TIE0_MASK USB_USBINTR_TIE0_MASK
|
|
#define USBHS_USBINTR_TIE0_SHIFT USB_USBINTR_TIE0_SHIFT
|
|
#define USBHS_USBINTR_TIE0(x) USB_USBINTR_TIE0(x)
|
|
#define USBHS_USBINTR_TIE1_MASK USB_USBINTR_TIE1_MASK
|
|
#define USBHS_USBINTR_TIE1_SHIFT USB_USBINTR_TIE1_SHIFT
|
|
#define USBHS_USBINTR_TIE1(x) USB_USBINTR_TIE1(x)
|
|
#define USBHS_FRINDEX_FRINDEX_MASK USB_FRINDEX_FRINDEX_MASK
|
|
#define USBHS_FRINDEX_FRINDEX_SHIFT USB_FRINDEX_FRINDEX_SHIFT
|
|
#define USBHS_FRINDEX_FRINDEX(x) USB_FRINDEX_FRINDEX(x)
|
|
#define USBHS_DEVICEADDR_USBADRA_MASK USB_DEVICEADDR_USBADRA_MASK
|
|
#define USBHS_DEVICEADDR_USBADRA_SHIFT USB_DEVICEADDR_USBADRA_SHIFT
|
|
#define USBHS_DEVICEADDR_USBADRA(x) USB_DEVICEADDR_USBADRA(x)
|
|
#define USBHS_DEVICEADDR_USBADR_MASK USB_DEVICEADDR_USBADR_MASK
|
|
#define USBHS_DEVICEADDR_USBADR_SHIFT USB_DEVICEADDR_USBADR_SHIFT
|
|
#define USBHS_DEVICEADDR_USBADR(x) USB_DEVICEADDR_USBADR(x)
|
|
#define USBHS_PERIODICLISTBASE_PERBASE_MASK USB_PERIODICLISTBASE_BASEADR_MASK
|
|
#define USBHS_PERIODICLISTBASE_PERBASE_SHIFT USB_PERIODICLISTBASE_BASEADR_SHIFT
|
|
#define USBHS_PERIODICLISTBASE_PERBASE(x) USB_PERIODICLISTBASE_BASEADR(x)
|
|
#define USBHS_ASYNCLISTADDR_ASYBASE_MASK USB_ASYNCLISTADDR_ASYBASE_MASK
|
|
#define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT USB_ASYNCLISTADDR_ASYBASE_SHIFT
|
|
#define USBHS_ASYNCLISTADDR_ASYBASE(x) USB_ASYNCLISTADDR_ASYBASE(x)
|
|
#define USBHS_EPLISTADDR_EPBASE_MASK USB_ENDPTLISTADDR_EPBASE_MASK
|
|
#define USBHS_EPLISTADDR_EPBASE_SHIFT USB_ENDPTLISTADDR_EPBASE_SHIFT
|
|
#define USBHS_EPLISTADDR_EPBASE(x) USB_ENDPTLISTADDR_EPBASE(x)
|
|
#define USBHS_BURSTSIZE_RXPBURST_MASK USB_BURSTSIZE_RXPBURST_MASK
|
|
#define USBHS_BURSTSIZE_RXPBURST_SHIFT USB_BURSTSIZE_RXPBURST_SHIFT
|
|
#define USBHS_BURSTSIZE_RXPBURST(x) USB_BURSTSIZE_RXPBURST(x)
|
|
#define USBHS_BURSTSIZE_TXPBURST_MASK USB_BURSTSIZE_TXPBURST_MASK
|
|
#define USBHS_BURSTSIZE_TXPBURST_SHIFT USB_BURSTSIZE_TXPBURST_SHIFT
|
|
#define USBHS_BURSTSIZE_TXPBURST(x) USB_BURSTSIZE_TXPBURST(x)
|
|
#define USBHS_TXFILLTUNING_TXSCHOH_MASK USB_TXFILLTUNING_TXSCHOH_MASK
|
|
#define USBHS_TXFILLTUNING_TXSCHOH_SHIFT USB_TXFILLTUNING_TXSCHOH_SHIFT
|
|
#define USBHS_TXFILLTUNING_TXSCHOH(x) USB_TXFILLTUNING_TXSCHOH(x)
|
|
#define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK USB_TXFILLTUNING_TXSCHHEALTH_MASK
|
|
#define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT USB_TXFILLTUNING_TXSCHHEALTH_SHIFT
|
|
#define USBHS_TXFILLTUNING_TXSCHHEALTH(x) USB_TXFILLTUNING_TXSCHHEALTH(x)
|
|
#define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK USB_TXFILLTUNING_TXFIFOTHRES_MASK
|
|
#define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT USB_TXFILLTUNING_TXFIFOTHRES_SHIFT
|
|
#define USBHS_TXFILLTUNING_TXFIFOTHRES(x) USB_TXFILLTUNING_TXFIFOTHRES(x)
|
|
#define USBHS_ENDPTNAK_EPRN_MASK USB_ENDPTNAK_EPRN_MASK
|
|
#define USBHS_ENDPTNAK_EPRN_SHIFT USB_ENDPTNAK_EPRN_SHIFT
|
|
#define USBHS_ENDPTNAK_EPRN(x) USB_ENDPTNAK_EPRN(x)
|
|
#define USBHS_ENDPTNAK_EPTN_MASK USB_ENDPTNAK_EPTN_MASK
|
|
#define USBHS_ENDPTNAK_EPTN_SHIFT USB_ENDPTNAK_EPTN_SHIFT
|
|
#define USBHS_ENDPTNAK_EPTN(x) USB_ENDPTNAK_EPTN(x)
|
|
#define USBHS_ENDPTNAKEN_EPRNE_MASK USB_ENDPTNAKEN_EPRNE_MASK
|
|
#define USBHS_ENDPTNAKEN_EPRNE_SHIFT USB_ENDPTNAKEN_EPRNE_SHIFT
|
|
#define USBHS_ENDPTNAKEN_EPRNE(x) USB_ENDPTNAKEN_EPRNE(x)
|
|
#define USBHS_ENDPTNAKEN_EPTNE_MASK USB_ENDPTNAKEN_EPTNE_MASK
|
|
#define USBHS_ENDPTNAKEN_EPTNE_SHIFT USB_ENDPTNAKEN_EPTNE_SHIFT
|
|
#define USBHS_ENDPTNAKEN_EPTNE(x) USB_ENDPTNAKEN_EPTNE(x)
|
|
#define USBHS_CONFIGFLAG_CF_MASK USB_CONFIGFLAG_CF_MASK
|
|
#define USBHS_CONFIGFLAG_CF_SHIFT USB_CONFIGFLAG_CF_SHIFT
|
|
#define USBHS_CONFIGFLAG_CF(x) USB_CONFIGFLAG_CF(x)
|
|
#define USBHS_PORTSC1_CCS_MASK USB_PORTSC1_CCS_MASK
|
|
#define USBHS_PORTSC1_CCS_SHIFT USB_PORTSC1_CCS_SHIFT
|
|
#define USBHS_PORTSC1_CCS(x) USB_PORTSC1_CCS(x)
|
|
#define USBHS_PORTSC1_CSC_MASK USB_PORTSC1_CSC_MASK
|
|
#define USBHS_PORTSC1_CSC_SHIFT USB_PORTSC1_CSC_SHIFT
|
|
#define USBHS_PORTSC1_CSC(x) USB_PORTSC1_CSC(x)
|
|
#define USBHS_PORTSC1_PE_MASK USB_PORTSC1_PE_MASK
|
|
#define USBHS_PORTSC1_PE_SHIFT USB_PORTSC1_PE_SHIFT
|
|
#define USBHS_PORTSC1_PE(x) USB_PORTSC1_PE(x)
|
|
#define USBHS_PORTSC1_PEC_MASK USB_PORTSC1_PEC_MASK
|
|
#define USBHS_PORTSC1_PEC_SHIFT USB_PORTSC1_PEC_SHIFT
|
|
#define USBHS_PORTSC1_PEC(x) USB_PORTSC1_PEC(x)
|
|
#define USBHS_PORTSC1_OCA_MASK USB_PORTSC1_OCA_MASK
|
|
#define USBHS_PORTSC1_OCA_SHIFT USB_PORTSC1_OCA_SHIFT
|
|
#define USBHS_PORTSC1_OCA(x) USB_PORTSC1_OCA(x)
|
|
#define USBHS_PORTSC1_OCC_MASK USB_PORTSC1_OCC_MASK
|
|
#define USBHS_PORTSC1_OCC_SHIFT USB_PORTSC1_OCC_SHIFT
|
|
#define USBHS_PORTSC1_OCC(x) USB_PORTSC1_OCC(x)
|
|
#define USBHS_PORTSC1_FPR_MASK USB_PORTSC1_FPR_MASK
|
|
#define USBHS_PORTSC1_FPR_SHIFT USB_PORTSC1_FPR_SHIFT
|
|
#define USBHS_PORTSC1_FPR(x) USB_PORTSC1_FPR(x)
|
|
#define USBHS_PORTSC1_SUSP_MASK USB_PORTSC1_SUSP_MASK
|
|
#define USBHS_PORTSC1_SUSP_SHIFT USB_PORTSC1_SUSP_SHIFT
|
|
#define USBHS_PORTSC1_SUSP(x) USB_PORTSC1_SUSP(x)
|
|
#define USBHS_PORTSC1_PR_MASK USB_PORTSC1_PR_MASK
|
|
#define USBHS_PORTSC1_PR_SHIFT USB_PORTSC1_PR_SHIFT
|
|
#define USBHS_PORTSC1_PR(x) USB_PORTSC1_PR(x)
|
|
#define USBHS_PORTSC1_HSP_MASK USB_PORTSC1_HSP_MASK
|
|
#define USBHS_PORTSC1_HSP_SHIFT USB_PORTSC1_HSP_SHIFT
|
|
#define USBHS_PORTSC1_HSP(x) USB_PORTSC1_HSP(x)
|
|
#define USBHS_PORTSC1_LS_MASK USB_PORTSC1_LS_MASK
|
|
#define USBHS_PORTSC1_LS_SHIFT USB_PORTSC1_LS_SHIFT
|
|
#define USBHS_PORTSC1_LS(x) USB_PORTSC1_LS(x)
|
|
#define USBHS_PORTSC1_PP_MASK USB_PORTSC1_PP_MASK
|
|
#define USBHS_PORTSC1_PP_SHIFT USB_PORTSC1_PP_SHIFT
|
|
#define USBHS_PORTSC1_PP(x) USB_PORTSC1_PP(x)
|
|
#define USBHS_PORTSC1_PO_MASK USB_PORTSC1_PO_MASK
|
|
#define USBHS_PORTSC1_PO_SHIFT USB_PORTSC1_PO_SHIFT
|
|
#define USBHS_PORTSC1_PO(x) USB_PORTSC1_PO(x)
|
|
#define USBHS_PORTSC1_PIC_MASK USB_PORTSC1_PIC_MASK
|
|
#define USBHS_PORTSC1_PIC_SHIFT USB_PORTSC1_PIC_SHIFT
|
|
#define USBHS_PORTSC1_PIC(x) USB_PORTSC1_PIC(x)
|
|
#define USBHS_PORTSC1_PTC_MASK USB_PORTSC1_PTC_MASK
|
|
#define USBHS_PORTSC1_PTC_SHIFT USB_PORTSC1_PTC_SHIFT
|
|
#define USBHS_PORTSC1_PTC(x) USB_PORTSC1_PTC(x)
|
|
#define USBHS_PORTSC1_WKCN_MASK USB_PORTSC1_WKCN_MASK
|
|
#define USBHS_PORTSC1_WKCN_SHIFT USB_PORTSC1_WKCN_SHIFT
|
|
#define USBHS_PORTSC1_WKCN(x) USB_PORTSC1_WKCN(x)
|
|
#define USBHS_PORTSC1_WKDS_MASK USB_PORTSC1_WKDC_MASK
|
|
#define USBHS_PORTSC1_WKDS_SHIFT USB_PORTSC1_WKDC_SHIFT
|
|
#define USBHS_PORTSC1_WKDS(x) USB_PORTSC1_WKDC(x)
|
|
#define USBHS_PORTSC1_WKOC_MASK USB_PORTSC1_WKOC_MASK
|
|
#define USBHS_PORTSC1_WKOC_SHIFT USB_PORTSC1_WKOC_SHIFT
|
|
#define USBHS_PORTSC1_WKOC(x) USB_PORTSC1_WKOC(x)
|
|
#define USBHS_PORTSC1_PHCD_MASK USB_PORTSC1_PHCD_MASK
|
|
#define USBHS_PORTSC1_PHCD_SHIFT USB_PORTSC1_PHCD_SHIFT
|
|
#define USBHS_PORTSC1_PHCD(x) USB_PORTSC1_PHCD(x)
|
|
#define USBHS_PORTSC1_PFSC_MASK USB_PORTSC1_PFSC_MASK
|
|
#define USBHS_PORTSC1_PFSC_SHIFT USB_PORTSC1_PFSC_SHIFT
|
|
#define USBHS_PORTSC1_PFSC(x) USB_PORTSC1_PFSC(x)
|
|
#define USBHS_PORTSC1_PTS2_MASK USB_PORTSC1_PTS_2_MASK
|
|
#define USBHS_PORTSC1_PTS2_SHIFT USB_PORTSC1_PTS_2_SHIFT
|
|
#define USBHS_PORTSC1_PTS2(x) USB_PORTSC1_PTS_2(x)
|
|
#define USBHS_PORTSC1_PSPD_MASK USB_PORTSC1_PSPD_MASK
|
|
#define USBHS_PORTSC1_PSPD_SHIFT USB_PORTSC1_PSPD_SHIFT
|
|
#define USBHS_PORTSC1_PSPD(x) USB_PORTSC1_PSPD(x)
|
|
#define USBHS_PORTSC1_PTW_MASK USB_PORTSC1_PTW_MASK
|
|
#define USBHS_PORTSC1_PTW_SHIFT USB_PORTSC1_PTW_SHIFT
|
|
#define USBHS_PORTSC1_PTW(x) USB_PORTSC1_PTW(x)
|
|
#define USBHS_PORTSC1_STS_MASK USB_PORTSC1_STS_MASK
|
|
#define USBHS_PORTSC1_STS_SHIFT USB_PORTSC1_STS_SHIFT
|
|
#define USBHS_PORTSC1_STS(x) USB_PORTSC1_STS(x)
|
|
#define USBHS_PORTSC1_PTS_MASK USB_PORTSC1_PTS_1_MASK
|
|
#define USBHS_PORTSC1_PTS_SHIFT USB_PORTSC1_PTS_1_SHIFT
|
|
#define USBHS_PORTSC1_PTS(x) USB_PORTSC1_PTS_1(x)
|
|
#define USBHS_OTGSC_VD_MASK USB_OTGSC_VD_MASK
|
|
#define USBHS_OTGSC_VD_SHIFT USB_OTGSC_VD_SHIFT
|
|
#define USBHS_OTGSC_VD(x) USB_OTGSC_VD(x)
|
|
#define USBHS_OTGSC_VC_MASK USB_OTGSC_VC_MASK
|
|
#define USBHS_OTGSC_VC_SHIFT USB_OTGSC_VC_SHIFT
|
|
#define USBHS_OTGSC_VC(x) USB_OTGSC_VC(x)
|
|
#define USBHS_OTGSC_OT_MASK USB_OTGSC_OT_MASK
|
|
#define USBHS_OTGSC_OT_SHIFT USB_OTGSC_OT_SHIFT
|
|
#define USBHS_OTGSC_OT(x) USB_OTGSC_OT(x)
|
|
#define USBHS_OTGSC_DP_MASK USB_OTGSC_DP_MASK
|
|
#define USBHS_OTGSC_DP_SHIFT USB_OTGSC_DP_SHIFT
|
|
#define USBHS_OTGSC_DP(x) USB_OTGSC_DP(x)
|
|
#define USBHS_OTGSC_IDPU_MASK USB_OTGSC_IDPU_MASK
|
|
#define USBHS_OTGSC_IDPU_SHIFT USB_OTGSC_IDPU_SHIFT
|
|
#define USBHS_OTGSC_IDPU(x) USB_OTGSC_IDPU(x)
|
|
#define USBHS_OTGSC_ID_MASK USB_OTGSC_ID_MASK
|
|
#define USBHS_OTGSC_ID_SHIFT USB_OTGSC_ID_SHIFT
|
|
#define USBHS_OTGSC_ID(x) USB_OTGSC_ID(x)
|
|
#define USBHS_OTGSC_AVV_MASK USB_OTGSC_AVV_MASK
|
|
#define USBHS_OTGSC_AVV_SHIFT USB_OTGSC_AVV_SHIFT
|
|
#define USBHS_OTGSC_AVV(x) USB_OTGSC_AVV(x)
|
|
#define USBHS_OTGSC_ASV_MASK USB_OTGSC_ASV_MASK
|
|
#define USBHS_OTGSC_ASV_SHIFT USB_OTGSC_ASV_SHIFT
|
|
#define USBHS_OTGSC_ASV(x) USB_OTGSC_ASV(x)
|
|
#define USBHS_OTGSC_BSV_MASK USB_OTGSC_BSV_MASK
|
|
#define USBHS_OTGSC_BSV_SHIFT USB_OTGSC_BSV_SHIFT
|
|
#define USBHS_OTGSC_BSV(x) USB_OTGSC_BSV(x)
|
|
#define USBHS_OTGSC_BSE_MASK USB_OTGSC_BSE_MASK
|
|
#define USBHS_OTGSC_BSE_SHIFT USB_OTGSC_BSE_SHIFT
|
|
#define USBHS_OTGSC_BSE(x) USB_OTGSC_BSE(x)
|
|
#define USBHS_OTGSC_MST_MASK USB_OTGSC_TOG_1MS_MASK
|
|
#define USBHS_OTGSC_MST_SHIFT USB_OTGSC_TOG_1MS_SHIFT
|
|
#define USBHS_OTGSC_MST(x) USB_OTGSC_TOG_1MS(x)
|
|
#define USBHS_OTGSC_DPS_MASK USB_OTGSC_DPS_MASK
|
|
#define USBHS_OTGSC_DPS_SHIFT USB_OTGSC_DPS_SHIFT
|
|
#define USBHS_OTGSC_DPS(x) USB_OTGSC_DPS(x)
|
|
#define USBHS_OTGSC_IDIS_MASK USB_OTGSC_IDIS_MASK
|
|
#define USBHS_OTGSC_IDIS_SHIFT USB_OTGSC_IDIS_SHIFT
|
|
#define USBHS_OTGSC_IDIS(x) USB_OTGSC_IDIS(x)
|
|
#define USBHS_OTGSC_AVVIS_MASK USB_OTGSC_AVVIS_MASK
|
|
#define USBHS_OTGSC_AVVIS_SHIFT USB_OTGSC_AVVIS_SHIFT
|
|
#define USBHS_OTGSC_AVVIS(x) USB_OTGSC_AVVIS(x)
|
|
#define USBHS_OTGSC_ASVIS_MASK USB_OTGSC_ASVIS_MASK
|
|
#define USBHS_OTGSC_ASVIS_SHIFT USB_OTGSC_ASVIS_SHIFT
|
|
#define USBHS_OTGSC_ASVIS(x) USB_OTGSC_ASVIS(x)
|
|
#define USBHS_OTGSC_BSVIS_MASK USB_OTGSC_BSVIS_MASK
|
|
#define USBHS_OTGSC_BSVIS_SHIFT USB_OTGSC_BSVIS_SHIFT
|
|
#define USBHS_OTGSC_BSVIS(x) USB_OTGSC_BSVIS(x)
|
|
#define USBHS_OTGSC_BSEIS_MASK USB_OTGSC_BSEIS_MASK
|
|
#define USBHS_OTGSC_BSEIS_SHIFT USB_OTGSC_BSEIS_SHIFT
|
|
#define USBHS_OTGSC_BSEIS(x) USB_OTGSC_BSEIS(x)
|
|
#define USBHS_OTGSC_MSS_MASK USB_OTGSC_STATUS_1MS_MASK
|
|
#define USBHS_OTGSC_MSS_SHIFT USB_OTGSC_STATUS_1MS_SHIFT
|
|
#define USBHS_OTGSC_MSS(x) USB_OTGSC_STATUS_1MS(x)
|
|
#define USBHS_OTGSC_DPIS_MASK USB_OTGSC_DPIS_MASK
|
|
#define USBHS_OTGSC_DPIS_SHIFT USB_OTGSC_DPIS_SHIFT
|
|
#define USBHS_OTGSC_DPIS(x) USB_OTGSC_DPIS(x)
|
|
#define USBHS_OTGSC_IDIE_MASK USB_OTGSC_IDIE_MASK
|
|
#define USBHS_OTGSC_IDIE_SHIFT USB_OTGSC_IDIE_SHIFT
|
|
#define USBHS_OTGSC_IDIE(x) USB_OTGSC_IDIE(x)
|
|
#define USBHS_OTGSC_AVVIE_MASK USB_OTGSC_AVVIE_MASK
|
|
#define USBHS_OTGSC_AVVIE_SHIFT USB_OTGSC_AVVIE_SHIFT
|
|
#define USBHS_OTGSC_AVVIE(x) USB_OTGSC_AVVIE(x)
|
|
#define USBHS_OTGSC_ASVIE_MASK USB_OTGSC_ASVIE_MASK
|
|
#define USBHS_OTGSC_ASVIE_SHIFT USB_OTGSC_ASVIE_SHIFT
|
|
#define USBHS_OTGSC_ASVIE(x) USB_OTGSC_ASVIE(x)
|
|
#define USBHS_OTGSC_BSVIE_MASK USB_OTGSC_BSVIE_MASK
|
|
#define USBHS_OTGSC_BSVIE_SHIFT USB_OTGSC_BSVIE_SHIFT
|
|
#define USBHS_OTGSC_BSVIE(x) USB_OTGSC_BSVIE(x)
|
|
#define USBHS_OTGSC_BSEIE_MASK USB_OTGSC_BSEIE_MASK
|
|
#define USBHS_OTGSC_BSEIE_SHIFT USB_OTGSC_BSEIE_SHIFT
|
|
#define USBHS_OTGSC_BSEIE(x) USB_OTGSC_BSEIE(x)
|
|
#define USBHS_OTGSC_MSE_MASK USB_OTGSC_EN_1MS_MASK
|
|
#define USBHS_OTGSC_MSE_SHIFT USB_OTGSC_EN_1MS_SHIFT
|
|
#define USBHS_OTGSC_MSE(x) USB_OTGSC_EN_1MS(x)
|
|
#define USBHS_OTGSC_DPIE_MASK USB_OTGSC_DPIE_MASK
|
|
#define USBHS_OTGSC_DPIE_SHIFT USB_OTGSC_DPIE_SHIFT
|
|
#define USBHS_OTGSC_DPIE(x) USB_OTGSC_DPIE(x)
|
|
#define USBHS_USBMODE_CM_MASK USB_USBMODE_CM_MASK
|
|
#define USBHS_USBMODE_CM_SHIFT USB_USBMODE_CM_SHIFT
|
|
#define USBHS_USBMODE_CM(x) USB_USBMODE_CM(x)
|
|
#define USBHS_USBMODE_ES_MASK USB_USBMODE_ES_MASK
|
|
#define USBHS_USBMODE_ES_SHIFT USB_USBMODE_ES_SHIFT
|
|
#define USBHS_USBMODE_ES(x) USB_USBMODE_ES(x)
|
|
#define USBHS_USBMODE_SLOM_MASK USB_USBMODE_SLOM_MASK
|
|
#define USBHS_USBMODE_SLOM_SHIFT USB_USBMODE_SLOM_SHIFT
|
|
#define USBHS_USBMODE_SLOM(x) USB_USBMODE_SLOM(x)
|
|
#define USBHS_USBMODE_SDIS_MASK USB_USBMODE_SDIS_MASK
|
|
#define USBHS_USBMODE_SDIS_SHIFT USB_USBMODE_SDIS_SHIFT
|
|
#define USBHS_USBMODE_SDIS(x) USB_USBMODE_SDIS(x)
|
|
#define USBHS_EPSETUPSR_EPSETUPSTAT_MASK USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK
|
|
#define USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT
|
|
#define USBHS_EPSETUPSR_EPSETUPSTAT(x) USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x)
|
|
#define USBHS_EPPRIME_PERB_MASK USB_ENDPTPRIME_PERB_MASK
|
|
#define USBHS_EPPRIME_PERB_SHIFT USB_ENDPTPRIME_PERB_SHIFT
|
|
#define USBHS_EPPRIME_PERB(x) USB_ENDPTPRIME_PERB(x)
|
|
#define USBHS_EPPRIME_PETB_MASK USB_ENDPTPRIME_PETB_MASK
|
|
#define USBHS_EPPRIME_PETB_SHIFT USB_ENDPTPRIME_PETB_SHIFT
|
|
#define USBHS_EPPRIME_PETB(x) USB_ENDPTPRIME_PETB(x)
|
|
#define USBHS_EPFLUSH_FERB_MASK USB_ENDPTFLUSH_FERB_MASK
|
|
#define USBHS_EPFLUSH_FERB_SHIFT USB_ENDPTFLUSH_FERB_SHIFT
|
|
#define USBHS_EPFLUSH_FERB(x) USB_ENDPTFLUSH_FERB(x)
|
|
#define USBHS_EPFLUSH_FETB_MASK USB_ENDPTFLUSH_FETB_MASK
|
|
#define USBHS_EPFLUSH_FETB_SHIFT USB_ENDPTFLUSH_FETB_SHIFT
|
|
#define USBHS_EPFLUSH_FETB(x) USB_ENDPTFLUSH_FETB(x)
|
|
#define USBHS_EPSR_ERBR_MASK USB_ENDPTSTAT_ERBR_MASK
|
|
#define USBHS_EPSR_ERBR_SHIFT USB_ENDPTSTAT_ERBR_SHIFT
|
|
#define USBHS_EPSR_ERBR(x) USB_ENDPTSTAT_ERBR(x)
|
|
#define USBHS_EPSR_ETBR_MASK USB_ENDPTSTAT_ETBR_MASK
|
|
#define USBHS_EPSR_ETBR_SHIFT USB_ENDPTSTAT_ETBR_SHIFT
|
|
#define USBHS_EPSR_ETBR(x) USB_ENDPTSTAT_ETBR(x)
|
|
#define USBHS_EPCOMPLETE_ERCE_MASK USB_ENDPTCOMPLETE_ERCE_MASK
|
|
#define USBHS_EPCOMPLETE_ERCE_SHIFT USB_ENDPTCOMPLETE_ERCE_SHIFT
|
|
#define USBHS_EPCOMPLETE_ERCE(x) USB_ENDPTCOMPLETE_ERCE(x)
|
|
#define USBHS_EPCOMPLETE_ETCE_MASK USB_ENDPTCOMPLETE_ETCE_MASK
|
|
#define USBHS_EPCOMPLETE_ETCE_SHIFT USB_ENDPTCOMPLETE_ETCE_SHIFT
|
|
#define USBHS_EPCOMPLETE_ETCE(x) USB_ENDPTCOMPLETE_ETCE(x)
|
|
#define USBHS_EPCR0_RXS_MASK USB_ENDPTCTRL0_RXS_MASK
|
|
#define USBHS_EPCR0_RXS_SHIFT USB_ENDPTCTRL0_RXS_SHIFT
|
|
#define USBHS_EPCR0_RXS(x) USB_ENDPTCTRL0_RXS(x)
|
|
#define USBHS_EPCR0_RXT_MASK USB_ENDPTCTRL0_RXT_MASK
|
|
#define USBHS_EPCR0_RXT_SHIFT USB_ENDPTCTRL0_RXT_SHIFT
|
|
#define USBHS_EPCR0_RXT(x) USB_ENDPTCTRL0_RXT(x)
|
|
#define USBHS_EPCR0_RXE_MASK USB_ENDPTCTRL0_RXE_MASK
|
|
#define USBHS_EPCR0_RXE_SHIFT USB_ENDPTCTRL0_RXE_SHIFT
|
|
#define USBHS_EPCR0_RXE(x) USB_ENDPTCTRL0_RXE(x)
|
|
#define USBHS_EPCR0_TXS_MASK USB_ENDPTCTRL0_TXS_MASK
|
|
#define USBHS_EPCR0_TXS_SHIFT USB_ENDPTCTRL0_TXS_SHIFT
|
|
#define USBHS_EPCR0_TXS(x) USB_ENDPTCTRL0_TXS(x)
|
|
#define USBHS_EPCR0_TXT_MASK USB_ENDPTCTRL0_TXT_MASK
|
|
#define USBHS_EPCR0_TXT_SHIFT USB_ENDPTCTRL0_TXT_SHIFT
|
|
#define USBHS_EPCR0_TXT(x) USB_ENDPTCTRL0_TXT(x)
|
|
#define USBHS_EPCR0_TXE_MASK USB_ENDPTCTRL0_TXE_MASK
|
|
#define USBHS_EPCR0_TXE_SHIFT USB_ENDPTCTRL0_TXE_SHIFT
|
|
#define USBHS_EPCR0_TXE(x) USB_ENDPTCTRL0_TXE(x)
|
|
#define USBHS_EPCR_RXS_MASK USB_ENDPTCTRL_RXS_MASK
|
|
#define USBHS_EPCR_RXS_SHIFT USB_ENDPTCTRL_RXS_SHIFT
|
|
#define USBHS_EPCR_RXS(x) USB_ENDPTCTRL_RXS(x)
|
|
#define USBHS_EPCR_RXD_MASK USB_ENDPTCTRL_RXD_MASK
|
|
#define USBHS_EPCR_RXD_SHIFT USB_ENDPTCTRL_RXD_SHIFT
|
|
#define USBHS_EPCR_RXD(x) USB_ENDPTCTRL_RXD(x)
|
|
#define USBHS_EPCR_RXT_MASK USB_ENDPTCTRL_RXT_MASK
|
|
#define USBHS_EPCR_RXT_SHIFT USB_ENDPTCTRL_RXT_SHIFT
|
|
#define USBHS_EPCR_RXT(x) USB_ENDPTCTRL_RXT(x)
|
|
#define USBHS_EPCR_RXI_MASK USB_ENDPTCTRL_RXI_MASK
|
|
#define USBHS_EPCR_RXI_SHIFT USB_ENDPTCTRL_RXI_SHIFT
|
|
#define USBHS_EPCR_RXI(x) USB_ENDPTCTRL_RXI(x)
|
|
#define USBHS_EPCR_RXR_MASK USB_ENDPTCTRL_RXR_MASK
|
|
#define USBHS_EPCR_RXR_SHIFT USB_ENDPTCTRL_RXR_SHIFT
|
|
#define USBHS_EPCR_RXR(x) USB_ENDPTCTRL_RXR(x)
|
|
#define USBHS_EPCR_RXE_MASK USB_ENDPTCTRL_RXE_MASK
|
|
#define USBHS_EPCR_RXE_SHIFT USB_ENDPTCTRL_RXE_SHIFT
|
|
#define USBHS_EPCR_RXE(x) USB_ENDPTCTRL_RXE(x)
|
|
#define USBHS_EPCR_TXS_MASK USB_ENDPTCTRL_TXS_MASK
|
|
#define USBHS_EPCR_TXS_SHIFT USB_ENDPTCTRL_TXS_SHIFT
|
|
#define USBHS_EPCR_TXS(x) USB_ENDPTCTRL_TXS(x)
|
|
#define USBHS_EPCR_TXD_MASK USB_ENDPTCTRL_TXD_MASK
|
|
#define USBHS_EPCR_TXD_SHIFT USB_ENDPTCTRL_TXD_SHIFT
|
|
#define USBHS_EPCR_TXD(x) USB_ENDPTCTRL_TXD(x)
|
|
#define USBHS_EPCR_TXT_MASK USB_ENDPTCTRL_TXT_MASK
|
|
#define USBHS_EPCR_TXT_SHIFT USB_ENDPTCTRL_TXT_SHIFT
|
|
#define USBHS_EPCR_TXT(x) USB_ENDPTCTRL_TXT(x)
|
|
#define USBHS_EPCR_TXI_MASK USB_ENDPTCTRL_TXI_MASK
|
|
#define USBHS_EPCR_TXI_SHIFT USB_ENDPTCTRL_TXI_SHIFT
|
|
#define USBHS_EPCR_TXI(x) USB_ENDPTCTRL_TXI(x)
|
|
#define USBHS_EPCR_TXR_MASK USB_ENDPTCTRL_TXR_MASK
|
|
#define USBHS_EPCR_TXR_SHIFT USB_ENDPTCTRL_TXR_SHIFT
|
|
#define USBHS_EPCR_TXR(x) USB_ENDPTCTRL_TXR(x)
|
|
#define USBHS_EPCR_TXE_MASK USB_ENDPTCTRL_TXE_MASK
|
|
#define USBHS_EPCR_TXE_SHIFT USB_ENDPTCTRL_TXE_SHIFT
|
|
#define USBHS_EPCR_TXE(x) USB_ENDPTCTRL_TXE(x)
|
|
#define USBHS_EPCR_COUNT USB_ENDPTCTRL_COUNT
|
|
#define USBHS_Type USB_Type
|
|
#define USBHS_BASE_ADDRS { USB1_BASE, USB2_BASE }
|
|
#define USBHS_IRQS { USB_OTG1_IRQn, USB_OTG2_IRQn }
|
|
#define USBHS_IRQHandler USB_OTG1_IRQHandler
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group USB_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- USBNC Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup USBNC_Peripheral_Access_Layer USBNC Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** USBNC - Register Layout Typedef */
|
|
typedef struct {
|
|
uint8_t RESERVED_0[2048];
|
|
__IO uint32_t USB_OTGn_CTRL; /**< USB OTG1 Control Register..USB OTG2 Control Register, offset: 0x800 */
|
|
uint8_t RESERVED_1[20];
|
|
__IO uint32_t USB_OTGn_PHY_CTRL_0; /**< OTG1 UTMI PHY Control 0 Register..OTG2 UTMI PHY Control 0 Register, offset: 0x818 */
|
|
} USBNC_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- USBNC Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup USBNC_Register_Masks USBNC Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name USB_OTGn_CTRL - USB OTG1 Control Register..USB OTG2 Control Register */
|
|
/*! @{ */
|
|
#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK (0x80U)
|
|
#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT (7U)
|
|
/*! OVER_CUR_DIS
|
|
* 0b1..Disables overcurrent detection
|
|
* 0b0..Enables overcurrent detection
|
|
*/
|
|
#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK)
|
|
#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK (0x100U)
|
|
#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT (8U)
|
|
/*! OVER_CUR_POL
|
|
* 0b1..Low active (low on this signal represents an overcurrent condition)
|
|
* 0b0..High active (high on this signal represents an overcurrent condition)
|
|
*/
|
|
#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK)
|
|
#define USBNC_USB_OTGn_CTRL_PWR_POL_MASK (0x200U)
|
|
#define USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT (9U)
|
|
/*! PWR_POL
|
|
* 0b1..PMIC Power Pin is High active.
|
|
* 0b0..PMIC Power Pin is Low active.
|
|
*/
|
|
#define USBNC_USB_OTGn_CTRL_PWR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_PWR_POL_MASK)
|
|
#define USBNC_USB_OTGn_CTRL_WIE_MASK (0x400U)
|
|
#define USBNC_USB_OTGn_CTRL_WIE_SHIFT (10U)
|
|
/*! WIE
|
|
* 0b1..Interrupt Enabled
|
|
* 0b0..Interrupt Disabled
|
|
*/
|
|
#define USBNC_USB_OTGn_CTRL_WIE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIE_SHIFT)) & USBNC_USB_OTGn_CTRL_WIE_MASK)
|
|
#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK (0x4000U)
|
|
#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT (14U)
|
|
/*! WKUP_SW_EN
|
|
* 0b1..Enable
|
|
* 0b0..Disable
|
|
*/
|
|
#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK)
|
|
#define USBNC_USB_OTGn_CTRL_WKUP_SW_MASK (0x8000U)
|
|
#define USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT (15U)
|
|
/*! WKUP_SW
|
|
* 0b1..Force wake-up
|
|
* 0b0..Inactive
|
|
*/
|
|
#define USBNC_USB_OTGn_CTRL_WKUP_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_MASK)
|
|
#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK (0x10000U)
|
|
#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT (16U)
|
|
/*! WKUP_ID_EN
|
|
* 0b1..Enable
|
|
* 0b0..Disable
|
|
*/
|
|
#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK)
|
|
#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK (0x20000U)
|
|
#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT (17U)
|
|
/*! WKUP_VBUS_EN
|
|
* 0b1..Enable
|
|
* 0b0..Disable
|
|
*/
|
|
#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK)
|
|
#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK (0x20000000U)
|
|
#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT (29U)
|
|
/*! WKUP_DPDM_EN
|
|
* 0b1..(Default) DPDM changes wake-up to be enabled, it is for device only.
|
|
* 0b0..DPDM changes wake-up to be disabled only when VBUS is 0.
|
|
*/
|
|
#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK)
|
|
#define USBNC_USB_OTGn_CTRL_WIR_MASK (0x80000000U)
|
|
#define USBNC_USB_OTGn_CTRL_WIR_SHIFT (31U)
|
|
/*! WIR
|
|
* 0b1..Wake-up Interrupt Request received
|
|
* 0b0..No wake-up interrupt request received
|
|
*/
|
|
#define USBNC_USB_OTGn_CTRL_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIR_SHIFT)) & USBNC_USB_OTGn_CTRL_WIR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name USB_OTGn_PHY_CTRL_0 - OTG1 UTMI PHY Control 0 Register..OTG2 UTMI PHY Control 0 Register */
|
|
/*! @{ */
|
|
#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK (0x80000000U)
|
|
#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT (31U)
|
|
/*! UTMI_CLK_VLD
|
|
* 0b1..Valid
|
|
* 0b0..Invalid
|
|
*/
|
|
#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT)) & USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group USBNC_Register_Masks */
|
|
|
|
|
|
/* USBNC - Peripheral instance base addresses */
|
|
/** Peripheral USBNC1 base address */
|
|
#define USBNC1_BASE (0x402E0000u)
|
|
/** Peripheral USBNC1 base pointer */
|
|
#define USBNC1 ((USBNC_Type *)USBNC1_BASE)
|
|
/** Peripheral USBNC2 base address */
|
|
#define USBNC2_BASE (0x402E0004u)
|
|
/** Peripheral USBNC2 base pointer */
|
|
#define USBNC2 ((USBNC_Type *)USBNC2_BASE)
|
|
/** Array initializer of USBNC peripheral base addresses */
|
|
#define USBNC_BASE_ADDRS { 0u, USBNC1_BASE, USBNC2_BASE }
|
|
/** Array initializer of USBNC peripheral base pointers */
|
|
#define USBNC_BASE_PTRS { (USBNC_Type *)0u, USBNC1, USBNC2 }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group USBNC_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- USBPHY Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** USBPHY - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t PWD; /**< USB PHY Power-Down Register, offset: 0x0 */
|
|
__IO uint32_t PWD_SET; /**< USB PHY Power-Down Register, offset: 0x4 */
|
|
__IO uint32_t PWD_CLR; /**< USB PHY Power-Down Register, offset: 0x8 */
|
|
__IO uint32_t PWD_TOG; /**< USB PHY Power-Down Register, offset: 0xC */
|
|
__IO uint32_t TX; /**< USB PHY Transmitter Control Register, offset: 0x10 */
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__IO uint32_t TX_SET; /**< USB PHY Transmitter Control Register, offset: 0x14 */
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__IO uint32_t TX_CLR; /**< USB PHY Transmitter Control Register, offset: 0x18 */
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__IO uint32_t TX_TOG; /**< USB PHY Transmitter Control Register, offset: 0x1C */
|
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__IO uint32_t RX; /**< USB PHY Receiver Control Register, offset: 0x20 */
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__IO uint32_t RX_SET; /**< USB PHY Receiver Control Register, offset: 0x24 */
|
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__IO uint32_t RX_CLR; /**< USB PHY Receiver Control Register, offset: 0x28 */
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__IO uint32_t RX_TOG; /**< USB PHY Receiver Control Register, offset: 0x2C */
|
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__IO uint32_t CTRL; /**< USB PHY General Control Register, offset: 0x30 */
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__IO uint32_t CTRL_SET; /**< USB PHY General Control Register, offset: 0x34 */
|
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__IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x38 */
|
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__IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */
|
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__IO uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */
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|
uint8_t RESERVED_0[12];
|
|
__IO uint32_t DEBUGr; /**< USB PHY Debug Register, offset: 0x50 */
|
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__IO uint32_t DEBUG_SET; /**< USB PHY Debug Register, offset: 0x54 */
|
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__IO uint32_t DEBUG_CLR; /**< USB PHY Debug Register, offset: 0x58 */
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__IO uint32_t DEBUG_TOG; /**< USB PHY Debug Register, offset: 0x5C */
|
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__I uint32_t DEBUG0_STATUS; /**< UTMI Debug Status Register 0, offset: 0x60 */
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uint8_t RESERVED_1[12];
|
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__IO uint32_t DEBUG1; /**< UTMI Debug Status Register 1, offset: 0x70 */
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__IO uint32_t DEBUG1_SET; /**< UTMI Debug Status Register 1, offset: 0x74 */
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__IO uint32_t DEBUG1_CLR; /**< UTMI Debug Status Register 1, offset: 0x78 */
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__IO uint32_t DEBUG1_TOG; /**< UTMI Debug Status Register 1, offset: 0x7C */
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__I uint32_t VERSION; /**< UTMI RTL Version, offset: 0x80 */
|
|
} USBPHY_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
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-- USBPHY Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
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/*!
|
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* @addtogroup USBPHY_Register_Masks USBPHY Register Masks
|
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* @{
|
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*/
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/*! @name PWD - USB PHY Power-Down Register */
|
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/*! @{ */
|
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#define USBPHY_PWD_RSVD0_MASK (0x3FFU)
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#define USBPHY_PWD_RSVD0_SHIFT (0U)
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#define USBPHY_PWD_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD0_SHIFT)) & USBPHY_PWD_RSVD0_MASK)
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#define USBPHY_PWD_TXPWDFS_MASK (0x400U)
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#define USBPHY_PWD_TXPWDFS_SHIFT (10U)
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#define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK)
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#define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U)
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#define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U)
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#define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK)
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#define USBPHY_PWD_TXPWDV2I_MASK (0x1000U)
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#define USBPHY_PWD_TXPWDV2I_SHIFT (12U)
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#define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK)
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|
#define USBPHY_PWD_RSVD1_MASK (0x1E000U)
|
|
#define USBPHY_PWD_RSVD1_SHIFT (13U)
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#define USBPHY_PWD_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD1_SHIFT)) & USBPHY_PWD_RSVD1_MASK)
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#define USBPHY_PWD_RXPWDENV_MASK (0x20000U)
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|
#define USBPHY_PWD_RXPWDENV_SHIFT (17U)
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#define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK)
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#define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U)
|
|
#define USBPHY_PWD_RXPWD1PT1_SHIFT (18U)
|
|
#define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK)
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|
#define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U)
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|
#define USBPHY_PWD_RXPWDDIFF_SHIFT (19U)
|
|
#define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK)
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|
#define USBPHY_PWD_RXPWDRX_MASK (0x100000U)
|
|
#define USBPHY_PWD_RXPWDRX_SHIFT (20U)
|
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#define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK)
|
|
#define USBPHY_PWD_RSVD2_MASK (0xFFE00000U)
|
|
#define USBPHY_PWD_RSVD2_SHIFT (21U)
|
|
#define USBPHY_PWD_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD2_SHIFT)) & USBPHY_PWD_RSVD2_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PWD_SET - USB PHY Power-Down Register */
|
|
/*! @{ */
|
|
#define USBPHY_PWD_SET_RSVD0_MASK (0x3FFU)
|
|
#define USBPHY_PWD_SET_RSVD0_SHIFT (0U)
|
|
#define USBPHY_PWD_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD0_SHIFT)) & USBPHY_PWD_SET_RSVD0_MASK)
|
|
#define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U)
|
|
#define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U)
|
|
#define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK)
|
|
#define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U)
|
|
#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U)
|
|
#define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK)
|
|
#define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U)
|
|
#define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U)
|
|
#define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK)
|
|
#define USBPHY_PWD_SET_RSVD1_MASK (0x1E000U)
|
|
#define USBPHY_PWD_SET_RSVD1_SHIFT (13U)
|
|
#define USBPHY_PWD_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD1_SHIFT)) & USBPHY_PWD_SET_RSVD1_MASK)
|
|
#define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U)
|
|
#define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U)
|
|
#define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK)
|
|
#define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U)
|
|
#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U)
|
|
#define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK)
|
|
#define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U)
|
|
#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U)
|
|
#define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK)
|
|
#define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U)
|
|
#define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U)
|
|
#define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK)
|
|
#define USBPHY_PWD_SET_RSVD2_MASK (0xFFE00000U)
|
|
#define USBPHY_PWD_SET_RSVD2_SHIFT (21U)
|
|
#define USBPHY_PWD_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD2_SHIFT)) & USBPHY_PWD_SET_RSVD2_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PWD_CLR - USB PHY Power-Down Register */
|
|
/*! @{ */
|
|
#define USBPHY_PWD_CLR_RSVD0_MASK (0x3FFU)
|
|
#define USBPHY_PWD_CLR_RSVD0_SHIFT (0U)
|
|
#define USBPHY_PWD_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD0_SHIFT)) & USBPHY_PWD_CLR_RSVD0_MASK)
|
|
#define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U)
|
|
#define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U)
|
|
#define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK)
|
|
#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U)
|
|
#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U)
|
|
#define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK)
|
|
#define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U)
|
|
#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U)
|
|
#define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK)
|
|
#define USBPHY_PWD_CLR_RSVD1_MASK (0x1E000U)
|
|
#define USBPHY_PWD_CLR_RSVD1_SHIFT (13U)
|
|
#define USBPHY_PWD_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD1_SHIFT)) & USBPHY_PWD_CLR_RSVD1_MASK)
|
|
#define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U)
|
|
#define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U)
|
|
#define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK)
|
|
#define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U)
|
|
#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U)
|
|
#define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK)
|
|
#define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U)
|
|
#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U)
|
|
#define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK)
|
|
#define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U)
|
|
#define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U)
|
|
#define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK)
|
|
#define USBPHY_PWD_CLR_RSVD2_MASK (0xFFE00000U)
|
|
#define USBPHY_PWD_CLR_RSVD2_SHIFT (21U)
|
|
#define USBPHY_PWD_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD2_SHIFT)) & USBPHY_PWD_CLR_RSVD2_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PWD_TOG - USB PHY Power-Down Register */
|
|
/*! @{ */
|
|
#define USBPHY_PWD_TOG_RSVD0_MASK (0x3FFU)
|
|
#define USBPHY_PWD_TOG_RSVD0_SHIFT (0U)
|
|
#define USBPHY_PWD_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD0_SHIFT)) & USBPHY_PWD_TOG_RSVD0_MASK)
|
|
#define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U)
|
|
#define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U)
|
|
#define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK)
|
|
#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U)
|
|
#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U)
|
|
#define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK)
|
|
#define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U)
|
|
#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U)
|
|
#define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK)
|
|
#define USBPHY_PWD_TOG_RSVD1_MASK (0x1E000U)
|
|
#define USBPHY_PWD_TOG_RSVD1_SHIFT (13U)
|
|
#define USBPHY_PWD_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD1_SHIFT)) & USBPHY_PWD_TOG_RSVD1_MASK)
|
|
#define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U)
|
|
#define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U)
|
|
#define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK)
|
|
#define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U)
|
|
#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U)
|
|
#define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK)
|
|
#define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U)
|
|
#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U)
|
|
#define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK)
|
|
#define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U)
|
|
#define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U)
|
|
#define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK)
|
|
#define USBPHY_PWD_TOG_RSVD2_MASK (0xFFE00000U)
|
|
#define USBPHY_PWD_TOG_RSVD2_SHIFT (21U)
|
|
#define USBPHY_PWD_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD2_SHIFT)) & USBPHY_PWD_TOG_RSVD2_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TX - USB PHY Transmitter Control Register */
|
|
/*! @{ */
|
|
#define USBPHY_TX_D_CAL_MASK (0xFU)
|
|
#define USBPHY_TX_D_CAL_SHIFT (0U)
|
|
#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK)
|
|
#define USBPHY_TX_RSVD0_MASK (0xF0U)
|
|
#define USBPHY_TX_RSVD0_SHIFT (4U)
|
|
#define USBPHY_TX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD0_SHIFT)) & USBPHY_TX_RSVD0_MASK)
|
|
#define USBPHY_TX_TXCAL45DN_MASK (0xF00U)
|
|
#define USBPHY_TX_TXCAL45DN_SHIFT (8U)
|
|
#define USBPHY_TX_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DN_SHIFT)) & USBPHY_TX_TXCAL45DN_MASK)
|
|
#define USBPHY_TX_RSVD1_MASK (0xF000U)
|
|
#define USBPHY_TX_RSVD1_SHIFT (12U)
|
|
#define USBPHY_TX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD1_SHIFT)) & USBPHY_TX_RSVD1_MASK)
|
|
#define USBPHY_TX_TXCAL45DP_MASK (0xF0000U)
|
|
#define USBPHY_TX_TXCAL45DP_SHIFT (16U)
|
|
#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK)
|
|
#define USBPHY_TX_RSVD2_MASK (0x3F00000U)
|
|
#define USBPHY_TX_RSVD2_SHIFT (20U)
|
|
#define USBPHY_TX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD2_SHIFT)) & USBPHY_TX_RSVD2_MASK)
|
|
#define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
|
|
#define USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT (26U)
|
|
#define USBPHY_TX_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_USBPHY_TX_EDGECTRL_MASK)
|
|
#define USBPHY_TX_RSVD5_MASK (0xE0000000U)
|
|
#define USBPHY_TX_RSVD5_SHIFT (29U)
|
|
#define USBPHY_TX_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD5_SHIFT)) & USBPHY_TX_RSVD5_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TX_SET - USB PHY Transmitter Control Register */
|
|
/*! @{ */
|
|
#define USBPHY_TX_SET_D_CAL_MASK (0xFU)
|
|
#define USBPHY_TX_SET_D_CAL_SHIFT (0U)
|
|
#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK)
|
|
#define USBPHY_TX_SET_RSVD0_MASK (0xF0U)
|
|
#define USBPHY_TX_SET_RSVD0_SHIFT (4U)
|
|
#define USBPHY_TX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD0_SHIFT)) & USBPHY_TX_SET_RSVD0_MASK)
|
|
#define USBPHY_TX_SET_TXCAL45DN_MASK (0xF00U)
|
|
#define USBPHY_TX_SET_TXCAL45DN_SHIFT (8U)
|
|
#define USBPHY_TX_SET_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DN_SHIFT)) & USBPHY_TX_SET_TXCAL45DN_MASK)
|
|
#define USBPHY_TX_SET_RSVD1_MASK (0xF000U)
|
|
#define USBPHY_TX_SET_RSVD1_SHIFT (12U)
|
|
#define USBPHY_TX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD1_SHIFT)) & USBPHY_TX_SET_RSVD1_MASK)
|
|
#define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U)
|
|
#define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U)
|
|
#define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK)
|
|
#define USBPHY_TX_SET_RSVD2_MASK (0x3F00000U)
|
|
#define USBPHY_TX_SET_RSVD2_SHIFT (20U)
|
|
#define USBPHY_TX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD2_SHIFT)) & USBPHY_TX_SET_RSVD2_MASK)
|
|
#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
|
|
#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT (26U)
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#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK)
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#define USBPHY_TX_SET_RSVD5_MASK (0xE0000000U)
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#define USBPHY_TX_SET_RSVD5_SHIFT (29U)
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#define USBPHY_TX_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD5_SHIFT)) & USBPHY_TX_SET_RSVD5_MASK)
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/*! @} */
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/*! @name TX_CLR - USB PHY Transmitter Control Register */
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/*! @{ */
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#define USBPHY_TX_CLR_D_CAL_MASK (0xFU)
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#define USBPHY_TX_CLR_D_CAL_SHIFT (0U)
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#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK)
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#define USBPHY_TX_CLR_RSVD0_MASK (0xF0U)
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#define USBPHY_TX_CLR_RSVD0_SHIFT (4U)
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#define USBPHY_TX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD0_SHIFT)) & USBPHY_TX_CLR_RSVD0_MASK)
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#define USBPHY_TX_CLR_TXCAL45DN_MASK (0xF00U)
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#define USBPHY_TX_CLR_TXCAL45DN_SHIFT (8U)
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#define USBPHY_TX_CLR_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXCAL45DN_MASK)
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#define USBPHY_TX_CLR_RSVD1_MASK (0xF000U)
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#define USBPHY_TX_CLR_RSVD1_SHIFT (12U)
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#define USBPHY_TX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD1_SHIFT)) & USBPHY_TX_CLR_RSVD1_MASK)
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#define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U)
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#define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U)
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#define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK)
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#define USBPHY_TX_CLR_RSVD2_MASK (0x3F00000U)
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#define USBPHY_TX_CLR_RSVD2_SHIFT (20U)
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#define USBPHY_TX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD2_SHIFT)) & USBPHY_TX_CLR_RSVD2_MASK)
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#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
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#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT (26U)
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#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK)
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#define USBPHY_TX_CLR_RSVD5_MASK (0xE0000000U)
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#define USBPHY_TX_CLR_RSVD5_SHIFT (29U)
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#define USBPHY_TX_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD5_SHIFT)) & USBPHY_TX_CLR_RSVD5_MASK)
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/*! @} */
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/*! @name TX_TOG - USB PHY Transmitter Control Register */
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/*! @{ */
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#define USBPHY_TX_TOG_D_CAL_MASK (0xFU)
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#define USBPHY_TX_TOG_D_CAL_SHIFT (0U)
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#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK)
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#define USBPHY_TX_TOG_RSVD0_MASK (0xF0U)
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#define USBPHY_TX_TOG_RSVD0_SHIFT (4U)
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#define USBPHY_TX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD0_SHIFT)) & USBPHY_TX_TOG_RSVD0_MASK)
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#define USBPHY_TX_TOG_TXCAL45DN_MASK (0xF00U)
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#define USBPHY_TX_TOG_TXCAL45DN_SHIFT (8U)
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#define USBPHY_TX_TOG_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXCAL45DN_MASK)
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#define USBPHY_TX_TOG_RSVD1_MASK (0xF000U)
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#define USBPHY_TX_TOG_RSVD1_SHIFT (12U)
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#define USBPHY_TX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD1_SHIFT)) & USBPHY_TX_TOG_RSVD1_MASK)
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#define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U)
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#define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U)
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#define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK)
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#define USBPHY_TX_TOG_RSVD2_MASK (0x3F00000U)
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#define USBPHY_TX_TOG_RSVD2_SHIFT (20U)
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#define USBPHY_TX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD2_SHIFT)) & USBPHY_TX_TOG_RSVD2_MASK)
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#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
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#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT (26U)
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#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK)
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#define USBPHY_TX_TOG_RSVD5_MASK (0xE0000000U)
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#define USBPHY_TX_TOG_RSVD5_SHIFT (29U)
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#define USBPHY_TX_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD5_SHIFT)) & USBPHY_TX_TOG_RSVD5_MASK)
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/*! @} */
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/*! @name RX - USB PHY Receiver Control Register */
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/*! @{ */
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#define USBPHY_RX_ENVADJ_MASK (0x7U)
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#define USBPHY_RX_ENVADJ_SHIFT (0U)
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#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK)
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#define USBPHY_RX_RSVD0_MASK (0x8U)
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#define USBPHY_RX_RSVD0_SHIFT (3U)
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#define USBPHY_RX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD0_SHIFT)) & USBPHY_RX_RSVD0_MASK)
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#define USBPHY_RX_DISCONADJ_MASK (0x70U)
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#define USBPHY_RX_DISCONADJ_SHIFT (4U)
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#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK)
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#define USBPHY_RX_RSVD1_MASK (0x3FFF80U)
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#define USBPHY_RX_RSVD1_SHIFT (7U)
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#define USBPHY_RX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD1_SHIFT)) & USBPHY_RX_RSVD1_MASK)
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#define USBPHY_RX_RXDBYPASS_MASK (0x400000U)
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#define USBPHY_RX_RXDBYPASS_SHIFT (22U)
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#define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK)
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#define USBPHY_RX_RSVD2_MASK (0xFF800000U)
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#define USBPHY_RX_RSVD2_SHIFT (23U)
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#define USBPHY_RX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD2_SHIFT)) & USBPHY_RX_RSVD2_MASK)
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/*! @} */
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/*! @name RX_SET - USB PHY Receiver Control Register */
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/*! @{ */
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#define USBPHY_RX_SET_ENVADJ_MASK (0x7U)
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#define USBPHY_RX_SET_ENVADJ_SHIFT (0U)
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#define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK)
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#define USBPHY_RX_SET_RSVD0_MASK (0x8U)
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#define USBPHY_RX_SET_RSVD0_SHIFT (3U)
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#define USBPHY_RX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD0_SHIFT)) & USBPHY_RX_SET_RSVD0_MASK)
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#define USBPHY_RX_SET_DISCONADJ_MASK (0x70U)
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#define USBPHY_RX_SET_DISCONADJ_SHIFT (4U)
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#define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK)
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#define USBPHY_RX_SET_RSVD1_MASK (0x3FFF80U)
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#define USBPHY_RX_SET_RSVD1_SHIFT (7U)
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#define USBPHY_RX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD1_SHIFT)) & USBPHY_RX_SET_RSVD1_MASK)
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#define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U)
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#define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U)
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#define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK)
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#define USBPHY_RX_SET_RSVD2_MASK (0xFF800000U)
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#define USBPHY_RX_SET_RSVD2_SHIFT (23U)
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#define USBPHY_RX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD2_SHIFT)) & USBPHY_RX_SET_RSVD2_MASK)
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/*! @} */
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/*! @name RX_CLR - USB PHY Receiver Control Register */
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/*! @{ */
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#define USBPHY_RX_CLR_ENVADJ_MASK (0x7U)
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#define USBPHY_RX_CLR_ENVADJ_SHIFT (0U)
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#define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK)
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#define USBPHY_RX_CLR_RSVD0_MASK (0x8U)
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#define USBPHY_RX_CLR_RSVD0_SHIFT (3U)
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#define USBPHY_RX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD0_SHIFT)) & USBPHY_RX_CLR_RSVD0_MASK)
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#define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U)
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#define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U)
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#define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK)
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#define USBPHY_RX_CLR_RSVD1_MASK (0x3FFF80U)
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#define USBPHY_RX_CLR_RSVD1_SHIFT (7U)
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#define USBPHY_RX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD1_SHIFT)) & USBPHY_RX_CLR_RSVD1_MASK)
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#define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U)
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#define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U)
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#define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK)
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#define USBPHY_RX_CLR_RSVD2_MASK (0xFF800000U)
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#define USBPHY_RX_CLR_RSVD2_SHIFT (23U)
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#define USBPHY_RX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD2_SHIFT)) & USBPHY_RX_CLR_RSVD2_MASK)
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/*! @} */
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/*! @name RX_TOG - USB PHY Receiver Control Register */
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/*! @{ */
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#define USBPHY_RX_TOG_ENVADJ_MASK (0x7U)
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#define USBPHY_RX_TOG_ENVADJ_SHIFT (0U)
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#define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK)
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#define USBPHY_RX_TOG_RSVD0_MASK (0x8U)
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#define USBPHY_RX_TOG_RSVD0_SHIFT (3U)
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#define USBPHY_RX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD0_SHIFT)) & USBPHY_RX_TOG_RSVD0_MASK)
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#define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U)
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#define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U)
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#define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK)
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#define USBPHY_RX_TOG_RSVD1_MASK (0x3FFF80U)
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#define USBPHY_RX_TOG_RSVD1_SHIFT (7U)
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#define USBPHY_RX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD1_SHIFT)) & USBPHY_RX_TOG_RSVD1_MASK)
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#define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U)
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#define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U)
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#define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK)
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#define USBPHY_RX_TOG_RSVD2_MASK (0xFF800000U)
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#define USBPHY_RX_TOG_RSVD2_SHIFT (23U)
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#define USBPHY_RX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD2_SHIFT)) & USBPHY_RX_TOG_RSVD2_MASK)
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/*! @} */
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/*! @name CTRL - USB PHY General Control Register */
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/*! @{ */
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#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK (0x1U)
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#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT (0U)
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#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK)
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#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U)
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#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U)
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#define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK)
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#define USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U)
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#define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U)
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#define USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK)
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#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U)
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#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U)
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#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK)
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#define USBPHY_CTRL_ENDEVPLUGINDETECT_MASK (0x10U)
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#define USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT (4U)
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#define USBPHY_CTRL_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDETECT_MASK)
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#define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U)
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#define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U)
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#define USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK)
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#define USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK (0x40U)
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#define USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT (6U)
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#define USBPHY_CTRL_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK)
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#define USBPHY_CTRL_ENOTGIDDETECT_MASK (0x80U)
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#define USBPHY_CTRL_ENOTGIDDETECT_SHIFT (7U)
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#define USBPHY_CTRL_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_ENOTGIDDETECT_MASK)
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#define USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U)
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#define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U)
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#define USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK)
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#define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U)
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#define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U)
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#define USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK)
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#define USBPHY_CTRL_RESUME_IRQ_MASK (0x400U)
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#define USBPHY_CTRL_RESUME_IRQ_SHIFT (10U)
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#define USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK)
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#define USBPHY_CTRL_ENIRQDEVPLUGIN_MASK (0x800U)
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#define USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT (11U)
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#define USBPHY_CTRL_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_ENIRQDEVPLUGIN_MASK)
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#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U)
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#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U)
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#define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK)
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#define USBPHY_CTRL_DATA_ON_LRADC_MASK (0x2000U)
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#define USBPHY_CTRL_DATA_ON_LRADC_SHIFT (13U)
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#define USBPHY_CTRL_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_DATA_ON_LRADC_MASK)
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#define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U)
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#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U)
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#define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK)
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#define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U)
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#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U)
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#define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK)
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#define USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U)
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#define USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U)
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#define USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK)
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#define USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U)
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#define USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U)
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#define USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK)
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#define USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK (0x40000U)
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#define USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT (18U)
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#define USBPHY_CTRL_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK)
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#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U)
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#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U)
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#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK)
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#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
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#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U)
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#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK)
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#define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK (0x200000U)
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#define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT (21U)
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#define USBPHY_CTRL_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK)
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#define USBPHY_CTRL_ENIDCHG_WKUP_MASK (0x400000U)
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#define USBPHY_CTRL_ENIDCHG_WKUP_SHIFT (22U)
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#define USBPHY_CTRL_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENIDCHG_WKUP_MASK)
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#define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK (0x800000U)
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#define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT (23U)
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#define USBPHY_CTRL_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK)
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#define USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U)
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#define USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U)
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#define USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK)
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#define USBPHY_CTRL_RSVD1_MASK (0x6000000U)
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#define USBPHY_CTRL_RSVD1_SHIFT (25U)
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#define USBPHY_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RSVD1_SHIFT)) & USBPHY_CTRL_RSVD1_MASK)
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#define USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U)
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#define USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U)
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#define USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK)
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#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U)
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#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U)
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#define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK)
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#define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U)
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#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U)
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#define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK)
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#define USBPHY_CTRL_CLKGATE_MASK (0x40000000U)
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#define USBPHY_CTRL_CLKGATE_SHIFT (30U)
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#define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK)
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#define USBPHY_CTRL_SFTRST_MASK (0x80000000U)
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#define USBPHY_CTRL_SFTRST_SHIFT (31U)
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#define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK)
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/*! @} */
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/*! @name CTRL_SET - USB PHY General Control Register */
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/*! @{ */
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#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK (0x1U)
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#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT (0U)
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#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK)
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#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U)
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#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U)
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#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK)
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#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U)
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#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U)
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#define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK)
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#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U)
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#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U)
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#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK)
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#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK (0x10U)
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#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT (4U)
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#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK)
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#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U)
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#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U)
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#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK)
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#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK (0x40U)
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#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT (6U)
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#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK)
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#define USBPHY_CTRL_SET_ENOTGIDDETECT_MASK (0x80U)
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#define USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT (7U)
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#define USBPHY_CTRL_SET_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_SET_ENOTGIDDETECT_MASK)
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#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U)
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#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U)
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#define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK)
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#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U)
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#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U)
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#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK)
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#define USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U)
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#define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U)
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#define USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK)
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#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK (0x800U)
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#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT (11U)
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#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK)
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#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U)
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#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U)
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#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK)
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#define USBPHY_CTRL_SET_DATA_ON_LRADC_MASK (0x2000U)
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#define USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT (13U)
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#define USBPHY_CTRL_SET_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_SET_DATA_ON_LRADC_MASK)
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#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U)
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#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U)
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#define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK)
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#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U)
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#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U)
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#define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK)
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#define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U)
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#define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U)
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#define USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK)
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#define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U)
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#define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U)
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#define USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK)
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#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK (0x40000U)
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#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT (18U)
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#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK)
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#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U)
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#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U)
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#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK)
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#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
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#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U)
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#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK)
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#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK (0x200000U)
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#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT (21U)
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#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK)
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#define USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK (0x400000U)
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#define USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT (22U)
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#define USBPHY_CTRL_SET_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK)
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#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK (0x800000U)
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#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT (23U)
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#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK)
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#define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U)
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#define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U)
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#define USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK)
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#define USBPHY_CTRL_SET_RSVD1_MASK (0x6000000U)
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#define USBPHY_CTRL_SET_RSVD1_SHIFT (25U)
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#define USBPHY_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RSVD1_SHIFT)) & USBPHY_CTRL_SET_RSVD1_MASK)
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#define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U)
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#define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U)
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#define USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK)
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#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U)
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#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U)
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#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK)
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#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U)
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#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U)
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#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK)
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#define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U)
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#define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U)
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#define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK)
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#define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U)
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#define USBPHY_CTRL_SET_SFTRST_SHIFT (31U)
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#define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK)
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/*! @} */
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/*! @name CTRL_CLR - USB PHY General Control Register */
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/*! @{ */
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#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK (0x1U)
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#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT (0U)
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#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK)
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#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U)
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#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U)
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#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK)
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#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U)
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#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U)
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#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK)
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#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U)
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#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U)
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#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK)
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#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK (0x10U)
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#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT (4U)
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#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK)
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#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U)
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#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U)
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#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK)
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#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK (0x40U)
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#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT (6U)
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#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK)
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#define USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK (0x80U)
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#define USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT (7U)
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#define USBPHY_CTRL_CLR_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK)
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#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U)
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#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U)
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#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK)
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#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U)
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#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U)
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#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK)
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#define USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U)
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#define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U)
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#define USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK)
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#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK (0x800U)
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#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT (11U)
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#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK)
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#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U)
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#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U)
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#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK)
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#define USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK (0x2000U)
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#define USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT (13U)
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#define USBPHY_CTRL_CLR_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK)
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#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U)
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#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U)
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#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK)
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#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U)
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#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U)
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#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK)
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#define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U)
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#define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U)
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#define USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK)
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#define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U)
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#define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U)
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#define USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK)
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#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK (0x40000U)
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#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT (18U)
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#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK)
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#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U)
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#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U)
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#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK)
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#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
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#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U)
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#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK)
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#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK (0x200000U)
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#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT (21U)
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#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK)
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#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK (0x400000U)
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#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT (22U)
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#define USBPHY_CTRL_CLR_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK)
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#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK (0x800000U)
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#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT (23U)
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#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK)
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#define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U)
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#define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U)
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#define USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK)
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#define USBPHY_CTRL_CLR_RSVD1_MASK (0x6000000U)
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#define USBPHY_CTRL_CLR_RSVD1_SHIFT (25U)
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#define USBPHY_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RSVD1_SHIFT)) & USBPHY_CTRL_CLR_RSVD1_MASK)
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#define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U)
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#define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U)
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#define USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK)
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#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U)
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#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U)
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#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK)
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#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U)
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#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U)
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#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK)
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#define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U)
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#define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U)
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#define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK)
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#define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U)
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#define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U)
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#define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK)
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/*! @} */
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/*! @name CTRL_TOG - USB PHY General Control Register */
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/*! @{ */
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#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK (0x1U)
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#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT (0U)
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#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK)
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#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U)
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#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U)
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#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK)
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#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U)
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#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U)
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#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK)
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#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U)
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#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U)
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#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK)
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#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK (0x10U)
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#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT (4U)
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#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK)
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#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U)
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#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U)
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#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK)
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#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK (0x40U)
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#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT (6U)
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#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK)
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#define USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK (0x80U)
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#define USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT (7U)
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#define USBPHY_CTRL_TOG_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK)
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#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U)
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#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U)
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#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK)
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#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U)
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#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U)
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#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK)
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#define USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U)
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#define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U)
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#define USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK)
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#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK (0x800U)
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#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT (11U)
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#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK)
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#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U)
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#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U)
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#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK)
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#define USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK (0x2000U)
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#define USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT (13U)
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#define USBPHY_CTRL_TOG_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK)
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#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U)
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#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U)
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#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK)
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#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U)
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#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U)
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#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK)
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#define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U)
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#define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U)
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#define USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK)
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#define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U)
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#define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U)
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#define USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK)
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#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK (0x40000U)
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#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT (18U)
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#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK)
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#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U)
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#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U)
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#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK)
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#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
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#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U)
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#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK)
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#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK (0x200000U)
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#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT (21U)
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#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK)
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#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK (0x400000U)
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#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT (22U)
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#define USBPHY_CTRL_TOG_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK)
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#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK (0x800000U)
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#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT (23U)
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#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK)
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#define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U)
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#define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U)
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#define USBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK)
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#define USBPHY_CTRL_TOG_RSVD1_MASK (0x6000000U)
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#define USBPHY_CTRL_TOG_RSVD1_SHIFT (25U)
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#define USBPHY_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RSVD1_SHIFT)) & USBPHY_CTRL_TOG_RSVD1_MASK)
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#define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U)
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#define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U)
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#define USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK)
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#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U)
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#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U)
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#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK)
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#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U)
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#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U)
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#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK)
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#define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U)
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#define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U)
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#define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK)
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#define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U)
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#define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U)
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#define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK)
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/*! @} */
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/*! @name STATUS - USB PHY Status Register */
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/*! @{ */
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#define USBPHY_STATUS_RSVD0_MASK (0x7U)
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#define USBPHY_STATUS_RSVD0_SHIFT (0U)
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#define USBPHY_STATUS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD0_SHIFT)) & USBPHY_STATUS_RSVD0_MASK)
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#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U)
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#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U)
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#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK)
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#define USBPHY_STATUS_RSVD1_MASK (0x30U)
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#define USBPHY_STATUS_RSVD1_SHIFT (4U)
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#define USBPHY_STATUS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD1_SHIFT)) & USBPHY_STATUS_RSVD1_MASK)
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#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U)
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#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U)
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#define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK)
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#define USBPHY_STATUS_RSVD2_MASK (0x80U)
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#define USBPHY_STATUS_RSVD2_SHIFT (7U)
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#define USBPHY_STATUS_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD2_SHIFT)) & USBPHY_STATUS_RSVD2_MASK)
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#define USBPHY_STATUS_OTGID_STATUS_MASK (0x100U)
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#define USBPHY_STATUS_OTGID_STATUS_SHIFT (8U)
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#define USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK)
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#define USBPHY_STATUS_RSVD3_MASK (0x200U)
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#define USBPHY_STATUS_RSVD3_SHIFT (9U)
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#define USBPHY_STATUS_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD3_SHIFT)) & USBPHY_STATUS_RSVD3_MASK)
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#define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U)
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#define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U)
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#define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK)
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#define USBPHY_STATUS_RSVD4_MASK (0xFFFFF800U)
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#define USBPHY_STATUS_RSVD4_SHIFT (11U)
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#define USBPHY_STATUS_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD4_SHIFT)) & USBPHY_STATUS_RSVD4_MASK)
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/*! @} */
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/*! @name DEBUG - USB PHY Debug Register */
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/*! @{ */
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#define USBPHY_DEBUG_OTGIDPIOLOCK_MASK (0x1U)
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#define USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT (0U)
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#define USBPHY_DEBUG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK)
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#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK (0x2U)
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#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT (1U)
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#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK)
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#define USBPHY_DEBUG_HSTPULLDOWN_MASK (0xCU)
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#define USBPHY_DEBUG_HSTPULLDOWN_SHIFT (2U)
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#define USBPHY_DEBUG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK)
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#define USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x30U)
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#define USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT (4U)
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#define USBPHY_DEBUG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK)
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#define USBPHY_DEBUG_RSVD0_MASK (0xC0U)
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#define USBPHY_DEBUG_RSVD0_SHIFT (6U)
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#define USBPHY_DEBUG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD0_SHIFT)) & USBPHY_DEBUG_RSVD0_MASK)
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#define USBPHY_DEBUG_TX2RXCOUNT_MASK (0xF00U)
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#define USBPHY_DEBUG_TX2RXCOUNT_SHIFT (8U)
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#define USBPHY_DEBUG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK)
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#define USBPHY_DEBUG_ENTX2RXCOUNT_MASK (0x1000U)
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#define USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT (12U)
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#define USBPHY_DEBUG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK)
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#define USBPHY_DEBUG_RSVD1_MASK (0xE000U)
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#define USBPHY_DEBUG_RSVD1_SHIFT (13U)
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#define USBPHY_DEBUG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD1_SHIFT)) & USBPHY_DEBUG_RSVD1_MASK)
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#define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1F0000U)
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#define USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT (16U)
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#define USBPHY_DEBUG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK)
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#define USBPHY_DEBUG_RSVD2_MASK (0xE00000U)
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#define USBPHY_DEBUG_RSVD2_SHIFT (21U)
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#define USBPHY_DEBUG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD2_SHIFT)) & USBPHY_DEBUG_RSVD2_MASK)
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#define USBPHY_DEBUG_ENSQUELCHRESET_MASK (0x1000000U)
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#define USBPHY_DEBUG_ENSQUELCHRESET_SHIFT (24U)
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#define USBPHY_DEBUG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK)
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#define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0x1E000000U)
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#define USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT (25U)
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#define USBPHY_DEBUG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK)
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#define USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK (0x20000000U)
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#define USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT (29U)
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#define USBPHY_DEBUG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK)
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#define USBPHY_DEBUG_CLKGATE_MASK (0x40000000U)
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#define USBPHY_DEBUG_CLKGATE_SHIFT (30U)
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#define USBPHY_DEBUG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK)
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#define USBPHY_DEBUG_RSVD3_MASK (0x80000000U)
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#define USBPHY_DEBUG_RSVD3_SHIFT (31U)
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#define USBPHY_DEBUG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD3_SHIFT)) & USBPHY_DEBUG_RSVD3_MASK)
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/*! @} */
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/*! @name DEBUG_SET - USB PHY Debug Register */
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/*! @{ */
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#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK (0x1U)
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#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT (0U)
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#define USBPHY_DEBUG_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK)
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#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U)
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#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U)
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#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK)
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#define USBPHY_DEBUG_SET_HSTPULLDOWN_MASK (0xCU)
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#define USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT (2U)
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#define USBPHY_DEBUG_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK)
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#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK (0x30U)
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#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT (4U)
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#define USBPHY_DEBUG_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK)
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#define USBPHY_DEBUG_SET_RSVD0_MASK (0xC0U)
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#define USBPHY_DEBUG_SET_RSVD0_SHIFT (6U)
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#define USBPHY_DEBUG_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD0_SHIFT)) & USBPHY_DEBUG_SET_RSVD0_MASK)
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#define USBPHY_DEBUG_SET_TX2RXCOUNT_MASK (0xF00U)
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#define USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT (8U)
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#define USBPHY_DEBUG_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK)
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#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK (0x1000U)
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#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT (12U)
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#define USBPHY_DEBUG_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK)
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#define USBPHY_DEBUG_SET_RSVD1_MASK (0xE000U)
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#define USBPHY_DEBUG_SET_RSVD1_SHIFT (13U)
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#define USBPHY_DEBUG_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD1_SHIFT)) & USBPHY_DEBUG_SET_RSVD1_MASK)
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#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U)
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#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT (16U)
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#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK)
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#define USBPHY_DEBUG_SET_RSVD2_MASK (0xE00000U)
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#define USBPHY_DEBUG_SET_RSVD2_SHIFT (21U)
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#define USBPHY_DEBUG_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD2_SHIFT)) & USBPHY_DEBUG_SET_RSVD2_MASK)
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#define USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK (0x1000000U)
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#define USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT (24U)
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#define USBPHY_DEBUG_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK)
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#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U)
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#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT (25U)
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#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK)
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#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK (0x20000000U)
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#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT (29U)
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#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK)
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#define USBPHY_DEBUG_SET_CLKGATE_MASK (0x40000000U)
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#define USBPHY_DEBUG_SET_CLKGATE_SHIFT (30U)
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#define USBPHY_DEBUG_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK)
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#define USBPHY_DEBUG_SET_RSVD3_MASK (0x80000000U)
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#define USBPHY_DEBUG_SET_RSVD3_SHIFT (31U)
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#define USBPHY_DEBUG_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD3_SHIFT)) & USBPHY_DEBUG_SET_RSVD3_MASK)
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/*! @} */
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/*! @name DEBUG_CLR - USB PHY Debug Register */
|
|
/*! @{ */
|
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#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK (0x1U)
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#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT (0U)
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#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK)
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#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U)
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#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U)
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#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK)
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#define USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK (0xCU)
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#define USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT (2U)
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#define USBPHY_DEBUG_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK)
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#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK (0x30U)
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#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT (4U)
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#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK)
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#define USBPHY_DEBUG_CLR_RSVD0_MASK (0xC0U)
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#define USBPHY_DEBUG_CLR_RSVD0_SHIFT (6U)
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#define USBPHY_DEBUG_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG_CLR_RSVD0_MASK)
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#define USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK (0xF00U)
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#define USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT (8U)
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#define USBPHY_DEBUG_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK)
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#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK (0x1000U)
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#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT (12U)
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#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK)
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#define USBPHY_DEBUG_CLR_RSVD1_MASK (0xE000U)
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#define USBPHY_DEBUG_CLR_RSVD1_SHIFT (13U)
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#define USBPHY_DEBUG_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG_CLR_RSVD1_MASK)
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#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U)
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#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT (16U)
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#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK)
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#define USBPHY_DEBUG_CLR_RSVD2_MASK (0xE00000U)
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#define USBPHY_DEBUG_CLR_RSVD2_SHIFT (21U)
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#define USBPHY_DEBUG_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD2_SHIFT)) & USBPHY_DEBUG_CLR_RSVD2_MASK)
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#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK (0x1000000U)
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#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT (24U)
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#define USBPHY_DEBUG_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK)
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#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U)
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#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT (25U)
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#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK)
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#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U)
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#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT (29U)
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#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)
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#define USBPHY_DEBUG_CLR_CLKGATE_MASK (0x40000000U)
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#define USBPHY_DEBUG_CLR_CLKGATE_SHIFT (30U)
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#define USBPHY_DEBUG_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK)
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#define USBPHY_DEBUG_CLR_RSVD3_MASK (0x80000000U)
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#define USBPHY_DEBUG_CLR_RSVD3_SHIFT (31U)
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#define USBPHY_DEBUG_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD3_SHIFT)) & USBPHY_DEBUG_CLR_RSVD3_MASK)
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/*! @} */
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/*! @name DEBUG_TOG - USB PHY Debug Register */
|
|
/*! @{ */
|
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#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK (0x1U)
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#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT (0U)
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#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK)
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#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U)
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#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U)
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#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK)
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#define USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK (0xCU)
|
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#define USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT (2U)
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#define USBPHY_DEBUG_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK)
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#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK (0x30U)
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#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT (4U)
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#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK)
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#define USBPHY_DEBUG_TOG_RSVD0_MASK (0xC0U)
|
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#define USBPHY_DEBUG_TOG_RSVD0_SHIFT (6U)
|
|
#define USBPHY_DEBUG_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG_TOG_RSVD0_MASK)
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#define USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK (0xF00U)
|
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#define USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT (8U)
|
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#define USBPHY_DEBUG_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK)
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#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK (0x1000U)
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#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT (12U)
|
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#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK)
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#define USBPHY_DEBUG_TOG_RSVD1_MASK (0xE000U)
|
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#define USBPHY_DEBUG_TOG_RSVD1_SHIFT (13U)
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#define USBPHY_DEBUG_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG_TOG_RSVD1_MASK)
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#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U)
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#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT (16U)
|
|
#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK)
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#define USBPHY_DEBUG_TOG_RSVD2_MASK (0xE00000U)
|
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#define USBPHY_DEBUG_TOG_RSVD2_SHIFT (21U)
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#define USBPHY_DEBUG_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD2_SHIFT)) & USBPHY_DEBUG_TOG_RSVD2_MASK)
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#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK (0x1000000U)
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#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT (24U)
|
|
#define USBPHY_DEBUG_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK)
|
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#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U)
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#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT (25U)
|
|
#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK)
|
|
#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U)
|
|
#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT (29U)
|
|
#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK)
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#define USBPHY_DEBUG_TOG_CLKGATE_MASK (0x40000000U)
|
|
#define USBPHY_DEBUG_TOG_CLKGATE_SHIFT (30U)
|
|
#define USBPHY_DEBUG_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK)
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#define USBPHY_DEBUG_TOG_RSVD3_MASK (0x80000000U)
|
|
#define USBPHY_DEBUG_TOG_RSVD3_SHIFT (31U)
|
|
#define USBPHY_DEBUG_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD3_SHIFT)) & USBPHY_DEBUG_TOG_RSVD3_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DEBUG0_STATUS - UTMI Debug Status Register 0 */
|
|
/*! @{ */
|
|
#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU)
|
|
#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U)
|
|
#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK)
|
|
#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK (0x3FF0000U)
|
|
#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT (16U)
|
|
#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK)
|
|
#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0xFC000000U)
|
|
#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U)
|
|
#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DEBUG1 - UTMI Debug Status Register 1 */
|
|
/*! @{ */
|
|
#define USBPHY_DEBUG1_RSVD0_MASK (0x1FFFU)
|
|
#define USBPHY_DEBUG1_RSVD0_SHIFT (0U)
|
|
#define USBPHY_DEBUG1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD0_SHIFT)) & USBPHY_DEBUG1_RSVD0_MASK)
|
|
#define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U)
|
|
#define USBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U)
|
|
#define USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK)
|
|
#define USBPHY_DEBUG1_RSVD1_MASK (0xFFFF8000U)
|
|
#define USBPHY_DEBUG1_RSVD1_SHIFT (15U)
|
|
#define USBPHY_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD1_SHIFT)) & USBPHY_DEBUG1_RSVD1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DEBUG1_SET - UTMI Debug Status Register 1 */
|
|
/*! @{ */
|
|
#define USBPHY_DEBUG1_SET_RSVD0_MASK (0x1FFFU)
|
|
#define USBPHY_DEBUG1_SET_RSVD0_SHIFT (0U)
|
|
#define USBPHY_DEBUG1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD0_SHIFT)) & USBPHY_DEBUG1_SET_RSVD0_MASK)
|
|
#define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U)
|
|
#define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U)
|
|
#define USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK)
|
|
#define USBPHY_DEBUG1_SET_RSVD1_MASK (0xFFFF8000U)
|
|
#define USBPHY_DEBUG1_SET_RSVD1_SHIFT (15U)
|
|
#define USBPHY_DEBUG1_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD1_SHIFT)) & USBPHY_DEBUG1_SET_RSVD1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DEBUG1_CLR - UTMI Debug Status Register 1 */
|
|
/*! @{ */
|
|
#define USBPHY_DEBUG1_CLR_RSVD0_MASK (0x1FFFU)
|
|
#define USBPHY_DEBUG1_CLR_RSVD0_SHIFT (0U)
|
|
#define USBPHY_DEBUG1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD0_MASK)
|
|
#define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U)
|
|
#define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U)
|
|
#define USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK)
|
|
#define USBPHY_DEBUG1_CLR_RSVD1_MASK (0xFFFF8000U)
|
|
#define USBPHY_DEBUG1_CLR_RSVD1_SHIFT (15U)
|
|
#define USBPHY_DEBUG1_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DEBUG1_TOG - UTMI Debug Status Register 1 */
|
|
/*! @{ */
|
|
#define USBPHY_DEBUG1_TOG_RSVD0_MASK (0x1FFFU)
|
|
#define USBPHY_DEBUG1_TOG_RSVD0_SHIFT (0U)
|
|
#define USBPHY_DEBUG1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD0_MASK)
|
|
#define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U)
|
|
#define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U)
|
|
#define USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK)
|
|
#define USBPHY_DEBUG1_TOG_RSVD1_MASK (0xFFFF8000U)
|
|
#define USBPHY_DEBUG1_TOG_RSVD1_SHIFT (15U)
|
|
#define USBPHY_DEBUG1_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name VERSION - UTMI RTL Version */
|
|
/*! @{ */
|
|
#define USBPHY_VERSION_STEP_MASK (0xFFFFU)
|
|
#define USBPHY_VERSION_STEP_SHIFT (0U)
|
|
#define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK)
|
|
#define USBPHY_VERSION_MINOR_MASK (0xFF0000U)
|
|
#define USBPHY_VERSION_MINOR_SHIFT (16U)
|
|
#define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK)
|
|
#define USBPHY_VERSION_MAJOR_MASK (0xFF000000U)
|
|
#define USBPHY_VERSION_MAJOR_SHIFT (24U)
|
|
#define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group USBPHY_Register_Masks */
|
|
|
|
|
|
/* USBPHY - Peripheral instance base addresses */
|
|
/** Peripheral USBPHY1 base address */
|
|
#define USBPHY1_BASE (0x400D9000u)
|
|
/** Peripheral USBPHY1 base pointer */
|
|
#define USBPHY1 ((USBPHY_Type *)USBPHY1_BASE)
|
|
/** Peripheral USBPHY2 base address */
|
|
#define USBPHY2_BASE (0x400DA000u)
|
|
/** Peripheral USBPHY2 base pointer */
|
|
#define USBPHY2 ((USBPHY_Type *)USBPHY2_BASE)
|
|
/** Array initializer of USBPHY peripheral base addresses */
|
|
#define USBPHY_BASE_ADDRS { 0u, USBPHY1_BASE, USBPHY2_BASE }
|
|
/** Array initializer of USBPHY peripheral base pointers */
|
|
#define USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY1, USBPHY2 }
|
|
/** Interrupt vectors for the USBPHY peripheral type */
|
|
#define USBPHY_IRQS { NotAvail_IRQn, USB_PHY1_IRQn, USB_PHY2_IRQn }
|
|
/* Backward compatibility */
|
|
#define USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASK
|
|
#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT
|
|
#define USBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x)
|
|
#define USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASK
|
|
#define USBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFT
|
|
#define USBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x)
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group USBPHY_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- USB_ANALOG Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup USB_ANALOG_Peripheral_Access_Layer USB_ANALOG Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** USB_ANALOG - Register Layout Typedef */
|
|
typedef struct {
|
|
uint8_t RESERVED_0[416];
|
|
struct { /* offset: 0x1A0, array step: 0x60 */
|
|
__IO uint32_t VBUS_DETECT; /**< USB VBUS Detect Register, array offset: 0x1A0, array step: 0x60 */
|
|
__IO uint32_t VBUS_DETECT_SET; /**< USB VBUS Detect Register, array offset: 0x1A4, array step: 0x60 */
|
|
__IO uint32_t VBUS_DETECT_CLR; /**< USB VBUS Detect Register, array offset: 0x1A8, array step: 0x60 */
|
|
__IO uint32_t VBUS_DETECT_TOG; /**< USB VBUS Detect Register, array offset: 0x1AC, array step: 0x60 */
|
|
__IO uint32_t CHRG_DETECT; /**< USB Charger Detect Register, array offset: 0x1B0, array step: 0x60 */
|
|
__IO uint32_t CHRG_DETECT_SET; /**< USB Charger Detect Register, array offset: 0x1B4, array step: 0x60 */
|
|
__IO uint32_t CHRG_DETECT_CLR; /**< USB Charger Detect Register, array offset: 0x1B8, array step: 0x60 */
|
|
__IO uint32_t CHRG_DETECT_TOG; /**< USB Charger Detect Register, array offset: 0x1BC, array step: 0x60 */
|
|
__I uint32_t VBUS_DETECT_STAT; /**< USB VBUS Detect Status Register, array offset: 0x1C0, array step: 0x60 */
|
|
uint8_t RESERVED_0[12];
|
|
__I uint32_t CHRG_DETECT_STAT; /**< USB Charger Detect Status Register, array offset: 0x1D0, array step: 0x60 */
|
|
uint8_t RESERVED_1[28];
|
|
__IO uint32_t MISC; /**< USB Misc Register, array offset: 0x1F0, array step: 0x60 */
|
|
__IO uint32_t MISC_SET; /**< USB Misc Register, array offset: 0x1F4, array step: 0x60 */
|
|
__IO uint32_t MISC_CLR; /**< USB Misc Register, array offset: 0x1F8, array step: 0x60 */
|
|
__IO uint32_t MISC_TOG; /**< USB Misc Register, array offset: 0x1FC, array step: 0x60 */
|
|
} INSTANCE[2];
|
|
__I uint32_t DIGPROG; /**< Chip Silicon Version, offset: 0x260 */
|
|
} USB_ANALOG_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- USB_ANALOG Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup USB_ANALOG_Register_Masks USB_ANALOG Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name VBUS_DETECT - USB VBUS Detect Register */
|
|
/*! @{ */
|
|
#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U)
|
|
#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U)
|
|
/*! VBUSVALID_THRESH
|
|
* 0b000..4.0V
|
|
* 0b001..4.1V
|
|
* 0b010..4.2V
|
|
* 0b011..4.3V
|
|
* 0b100..4.4V (default)
|
|
* 0b101..4.5V
|
|
* 0b110..4.6V
|
|
* 0b111..4.7V
|
|
*/
|
|
#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK)
|
|
#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)
|
|
#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
|
|
#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK)
|
|
#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U)
|
|
#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U)
|
|
#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK)
|
|
#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK (0x8000000U)
|
|
#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT (27U)
|
|
#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of USB_ANALOG_VBUS_DETECT */
|
|
#define USB_ANALOG_VBUS_DETECT_COUNT (2U)
|
|
|
|
/*! @name VBUS_DETECT_SET - USB VBUS Detect Register */
|
|
/*! @{ */
|
|
#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U)
|
|
#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U)
|
|
/*! VBUSVALID_THRESH
|
|
* 0b000..4.0V
|
|
* 0b001..4.1V
|
|
* 0b010..4.2V
|
|
* 0b011..4.3V
|
|
* 0b100..4.4V (default)
|
|
* 0b101..4.5V
|
|
* 0b110..4.6V
|
|
* 0b111..4.7V
|
|
*/
|
|
#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK)
|
|
#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)
|
|
#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
|
|
#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK)
|
|
#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U)
|
|
#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U)
|
|
#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK)
|
|
#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK (0x8000000U)
|
|
#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT (27U)
|
|
#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of USB_ANALOG_VBUS_DETECT_SET */
|
|
#define USB_ANALOG_VBUS_DETECT_SET_COUNT (2U)
|
|
|
|
/*! @name VBUS_DETECT_CLR - USB VBUS Detect Register */
|
|
/*! @{ */
|
|
#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U)
|
|
#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U)
|
|
/*! VBUSVALID_THRESH
|
|
* 0b000..4.0V
|
|
* 0b001..4.1V
|
|
* 0b010..4.2V
|
|
* 0b011..4.3V
|
|
* 0b100..4.4V (default)
|
|
* 0b101..4.5V
|
|
* 0b110..4.6V
|
|
* 0b111..4.7V
|
|
*/
|
|
#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK)
|
|
#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)
|
|
#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
|
|
#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK)
|
|
#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U)
|
|
#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U)
|
|
#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK)
|
|
#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK (0x8000000U)
|
|
#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT (27U)
|
|
#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of USB_ANALOG_VBUS_DETECT_CLR */
|
|
#define USB_ANALOG_VBUS_DETECT_CLR_COUNT (2U)
|
|
|
|
/*! @name VBUS_DETECT_TOG - USB VBUS Detect Register */
|
|
/*! @{ */
|
|
#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U)
|
|
#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U)
|
|
/*! VBUSVALID_THRESH
|
|
* 0b000..4.0V
|
|
* 0b001..4.1V
|
|
* 0b010..4.2V
|
|
* 0b011..4.3V
|
|
* 0b100..4.4V (default)
|
|
* 0b101..4.5V
|
|
* 0b110..4.6V
|
|
* 0b111..4.7V
|
|
*/
|
|
#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK)
|
|
#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)
|
|
#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
|
|
#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK)
|
|
#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U)
|
|
#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U)
|
|
#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK)
|
|
#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK (0x8000000U)
|
|
#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT (27U)
|
|
#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of USB_ANALOG_VBUS_DETECT_TOG */
|
|
#define USB_ANALOG_VBUS_DETECT_TOG_COUNT (2U)
|
|
|
|
/*! @name CHRG_DETECT - USB Charger Detect Register */
|
|
/*! @{ */
|
|
#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK (0x40000U)
|
|
#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT (18U)
|
|
/*! CHK_CONTACT - Check the contact of USB plug
|
|
* 0b0..Do not check the contact of USB plug.
|
|
* 0b1..Check whether the USB plug has been in contact with each other
|
|
*/
|
|
#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK)
|
|
#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK (0x80000U)
|
|
#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT (19U)
|
|
/*! CHK_CHRG_B - Check the charger connection
|
|
* 0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port.
|
|
* 0b1..Do not check whether a charger is connected to the USB port.
|
|
*/
|
|
#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK)
|
|
#define USB_ANALOG_CHRG_DETECT_EN_B_MASK (0x100000U)
|
|
#define USB_ANALOG_CHRG_DETECT_EN_B_SHIFT (20U)
|
|
/*! EN_B
|
|
* 0b0..Enable the charger detector.
|
|
* 0b1..Disable the charger detector.
|
|
*/
|
|
#define USB_ANALOG_CHRG_DETECT_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_EN_B_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of USB_ANALOG_CHRG_DETECT */
|
|
#define USB_ANALOG_CHRG_DETECT_COUNT (2U)
|
|
|
|
/*! @name CHRG_DETECT_SET - USB Charger Detect Register */
|
|
/*! @{ */
|
|
#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK (0x40000U)
|
|
#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT (18U)
|
|
/*! CHK_CONTACT - Check the contact of USB plug
|
|
* 0b0..Do not check the contact of USB plug.
|
|
* 0b1..Check whether the USB plug has been in contact with each other
|
|
*/
|
|
#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK)
|
|
#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK (0x80000U)
|
|
#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT (19U)
|
|
/*! CHK_CHRG_B - Check the charger connection
|
|
* 0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port.
|
|
* 0b1..Do not check whether a charger is connected to the USB port.
|
|
*/
|
|
#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK)
|
|
#define USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK (0x100000U)
|
|
#define USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT (20U)
|
|
/*! EN_B
|
|
* 0b0..Enable the charger detector.
|
|
* 0b1..Disable the charger detector.
|
|
*/
|
|
#define USB_ANALOG_CHRG_DETECT_SET_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of USB_ANALOG_CHRG_DETECT_SET */
|
|
#define USB_ANALOG_CHRG_DETECT_SET_COUNT (2U)
|
|
|
|
/*! @name CHRG_DETECT_CLR - USB Charger Detect Register */
|
|
/*! @{ */
|
|
#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK (0x40000U)
|
|
#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT (18U)
|
|
/*! CHK_CONTACT - Check the contact of USB plug
|
|
* 0b0..Do not check the contact of USB plug.
|
|
* 0b1..Check whether the USB plug has been in contact with each other
|
|
*/
|
|
#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK)
|
|
#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK (0x80000U)
|
|
#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT (19U)
|
|
/*! CHK_CHRG_B - Check the charger connection
|
|
* 0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port.
|
|
* 0b1..Do not check whether a charger is connected to the USB port.
|
|
*/
|
|
#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK)
|
|
#define USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK (0x100000U)
|
|
#define USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT (20U)
|
|
/*! EN_B
|
|
* 0b0..Enable the charger detector.
|
|
* 0b1..Disable the charger detector.
|
|
*/
|
|
#define USB_ANALOG_CHRG_DETECT_CLR_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of USB_ANALOG_CHRG_DETECT_CLR */
|
|
#define USB_ANALOG_CHRG_DETECT_CLR_COUNT (2U)
|
|
|
|
/*! @name CHRG_DETECT_TOG - USB Charger Detect Register */
|
|
/*! @{ */
|
|
#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK (0x40000U)
|
|
#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT (18U)
|
|
/*! CHK_CONTACT - Check the contact of USB plug
|
|
* 0b0..Do not check the contact of USB plug.
|
|
* 0b1..Check whether the USB plug has been in contact with each other
|
|
*/
|
|
#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK)
|
|
#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK (0x80000U)
|
|
#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT (19U)
|
|
/*! CHK_CHRG_B - Check the charger connection
|
|
* 0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port.
|
|
* 0b1..Do not check whether a charger is connected to the USB port.
|
|
*/
|
|
#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK)
|
|
#define USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK (0x100000U)
|
|
#define USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT (20U)
|
|
/*! EN_B
|
|
* 0b0..Enable the charger detector.
|
|
* 0b1..Disable the charger detector.
|
|
*/
|
|
#define USB_ANALOG_CHRG_DETECT_TOG_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of USB_ANALOG_CHRG_DETECT_TOG */
|
|
#define USB_ANALOG_CHRG_DETECT_TOG_COUNT (2U)
|
|
|
|
/*! @name VBUS_DETECT_STAT - USB VBUS Detect Status Register */
|
|
/*! @{ */
|
|
#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK (0x1U)
|
|
#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT (0U)
|
|
#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK)
|
|
#define USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK (0x2U)
|
|
#define USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT (1U)
|
|
#define USB_ANALOG_VBUS_DETECT_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK)
|
|
#define USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK (0x4U)
|
|
#define USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT (2U)
|
|
#define USB_ANALOG_VBUS_DETECT_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK)
|
|
#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK (0x8U)
|
|
#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT (3U)
|
|
#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of USB_ANALOG_VBUS_DETECT_STAT */
|
|
#define USB_ANALOG_VBUS_DETECT_STAT_COUNT (2U)
|
|
|
|
/*! @name CHRG_DETECT_STAT - USB Charger Detect Status Register */
|
|
/*! @{ */
|
|
#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK (0x1U)
|
|
#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT (0U)
|
|
/*! PLUG_CONTACT
|
|
* 0b0..The USB plug has not made contact.
|
|
* 0b1..The USB plug has made good contact.
|
|
*/
|
|
#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK)
|
|
#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK (0x2U)
|
|
#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT (1U)
|
|
/*! CHRG_DETECTED
|
|
* 0b0..The USB port is not connected to a charger.
|
|
* 0b1..A charger (either a dedicated charger or a host charger) is connected to the USB port.
|
|
*/
|
|
#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK)
|
|
#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK (0x4U)
|
|
#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT (2U)
|
|
#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK)
|
|
#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK (0x8U)
|
|
#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT (3U)
|
|
#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of USB_ANALOG_CHRG_DETECT_STAT */
|
|
#define USB_ANALOG_CHRG_DETECT_STAT_COUNT (2U)
|
|
|
|
/*! @name MISC - USB Misc Register */
|
|
/*! @{ */
|
|
#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK (0x1U)
|
|
#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT (0U)
|
|
#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK)
|
|
#define USB_ANALOG_MISC_EN_DEGLITCH_MASK (0x2U)
|
|
#define USB_ANALOG_MISC_EN_DEGLITCH_SHIFT (1U)
|
|
#define USB_ANALOG_MISC_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_EN_DEGLITCH_MASK)
|
|
#define USB_ANALOG_MISC_EN_CLK_UTMI_MASK (0x40000000U)
|
|
#define USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT (30U)
|
|
#define USB_ANALOG_MISC_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_EN_CLK_UTMI_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of USB_ANALOG_MISC */
|
|
#define USB_ANALOG_MISC_COUNT (2U)
|
|
|
|
/*! @name MISC_SET - USB Misc Register */
|
|
/*! @{ */
|
|
#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK (0x1U)
|
|
#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT (0U)
|
|
#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK)
|
|
#define USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK (0x2U)
|
|
#define USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT (1U)
|
|
#define USB_ANALOG_MISC_SET_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK)
|
|
#define USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK (0x40000000U)
|
|
#define USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT (30U)
|
|
#define USB_ANALOG_MISC_SET_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of USB_ANALOG_MISC_SET */
|
|
#define USB_ANALOG_MISC_SET_COUNT (2U)
|
|
|
|
/*! @name MISC_CLR - USB Misc Register */
|
|
/*! @{ */
|
|
#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK (0x1U)
|
|
#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT (0U)
|
|
#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK)
|
|
#define USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK (0x2U)
|
|
#define USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT (1U)
|
|
#define USB_ANALOG_MISC_CLR_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK)
|
|
#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK (0x40000000U)
|
|
#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT (30U)
|
|
#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of USB_ANALOG_MISC_CLR */
|
|
#define USB_ANALOG_MISC_CLR_COUNT (2U)
|
|
|
|
/*! @name MISC_TOG - USB Misc Register */
|
|
/*! @{ */
|
|
#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK (0x1U)
|
|
#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT (0U)
|
|
#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK)
|
|
#define USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK (0x2U)
|
|
#define USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT (1U)
|
|
#define USB_ANALOG_MISC_TOG_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK)
|
|
#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK (0x40000000U)
|
|
#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT (30U)
|
|
#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK)
|
|
/*! @} */
|
|
|
|
/* The count of USB_ANALOG_MISC_TOG */
|
|
#define USB_ANALOG_MISC_TOG_COUNT (2U)
|
|
|
|
/*! @name DIGPROG - Chip Silicon Version */
|
|
/*! @{ */
|
|
#define USB_ANALOG_DIGPROG_SILICON_REVISION_MASK (0xFFFFFFFFU)
|
|
#define USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT (0U)
|
|
/*! SILICON_REVISION
|
|
* 0b00000000011010100000000000000001..Silicon revision 1.1
|
|
*/
|
|
#define USB_ANALOG_DIGPROG_SILICON_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT)) & USB_ANALOG_DIGPROG_SILICON_REVISION_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group USB_ANALOG_Register_Masks */
|
|
|
|
|
|
/* USB_ANALOG - Peripheral instance base addresses */
|
|
/** Peripheral USB_ANALOG base address */
|
|
#define USB_ANALOG_BASE (0x400D8000u)
|
|
/** Peripheral USB_ANALOG base pointer */
|
|
#define USB_ANALOG ((USB_ANALOG_Type *)USB_ANALOG_BASE)
|
|
/** Array initializer of USB_ANALOG peripheral base addresses */
|
|
#define USB_ANALOG_BASE_ADDRS { USB_ANALOG_BASE }
|
|
/** Array initializer of USB_ANALOG peripheral base pointers */
|
|
#define USB_ANALOG_BASE_PTRS { USB_ANALOG }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group USB_ANALOG_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- USDHC Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** USDHC - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t DS_ADDR; /**< DMA System Address, offset: 0x0 */
|
|
__IO uint32_t BLK_ATT; /**< Block Attributes, offset: 0x4 */
|
|
__IO uint32_t CMD_ARG; /**< Command Argument, offset: 0x8 */
|
|
__IO uint32_t CMD_XFR_TYP; /**< Command Transfer Type, offset: 0xC */
|
|
__I uint32_t CMD_RSP0; /**< Command Response0, offset: 0x10 */
|
|
__I uint32_t CMD_RSP1; /**< Command Response1, offset: 0x14 */
|
|
__I uint32_t CMD_RSP2; /**< Command Response2, offset: 0x18 */
|
|
__I uint32_t CMD_RSP3; /**< Command Response3, offset: 0x1C */
|
|
__IO uint32_t DATA_BUFF_ACC_PORT; /**< Data Buffer Access Port, offset: 0x20 */
|
|
__I uint32_t PRES_STATE; /**< Present State, offset: 0x24 */
|
|
__IO uint32_t PROT_CTRL; /**< Protocol Control, offset: 0x28 */
|
|
__IO uint32_t SYS_CTRL; /**< System Control, offset: 0x2C */
|
|
__IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */
|
|
__IO uint32_t INT_STATUS_EN; /**< Interrupt Status Enable, offset: 0x34 */
|
|
__IO uint32_t INT_SIGNAL_EN; /**< Interrupt Signal Enable, offset: 0x38 */
|
|
__IO uint32_t AUTOCMD12_ERR_STATUS; /**< Auto CMD12 Error Status, offset: 0x3C */
|
|
__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */
|
|
__IO uint32_t WTMK_LVL; /**< Watermark Level, offset: 0x44 */
|
|
__IO uint32_t MIX_CTRL; /**< Mixer Control, offset: 0x48 */
|
|
uint8_t RESERVED_0[4];
|
|
__O uint32_t FORCE_EVENT; /**< Force Event, offset: 0x50 */
|
|
__I uint32_t ADMA_ERR_STATUS; /**< ADMA Error Status Register, offset: 0x54 */
|
|
__IO uint32_t ADMA_SYS_ADDR; /**< ADMA System Address, offset: 0x58 */
|
|
uint8_t RESERVED_1[4];
|
|
__IO uint32_t DLL_CTRL; /**< DLL (Delay Line) Control, offset: 0x60 */
|
|
__I uint32_t DLL_STATUS; /**< DLL Status, offset: 0x64 */
|
|
__IO uint32_t CLK_TUNE_CTRL_STATUS; /**< CLK Tuning Control and Status, offset: 0x68 */
|
|
uint8_t RESERVED_2[84];
|
|
__IO uint32_t VEND_SPEC; /**< Vendor Specific Register, offset: 0xC0 */
|
|
__IO uint32_t MMC_BOOT; /**< MMC Boot Register, offset: 0xC4 */
|
|
__IO uint32_t VEND_SPEC2; /**< Vendor Specific 2 Register, offset: 0xC8 */
|
|
__IO uint32_t TUNING_CTRL; /**< Tuning Control Register, offset: 0xCC */
|
|
} USDHC_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- USDHC Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup USDHC_Register_Masks USDHC Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name DS_ADDR - DMA System Address */
|
|
/*! @{ */
|
|
#define USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU)
|
|
#define USDHC_DS_ADDR_DS_ADDR_SHIFT (0U)
|
|
#define USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name BLK_ATT - Block Attributes */
|
|
/*! @{ */
|
|
#define USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU)
|
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#define USDHC_BLK_ATT_BLKSIZE_SHIFT (0U)
|
|
/*! BLKSIZE - Block Size
|
|
* 0b1000000000000..4096 Bytes
|
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* 0b0100000000000..2048 Bytes
|
|
* 0b0001000000000..512 Bytes
|
|
* 0b0000111111111..511 Bytes
|
|
* 0b0000000000100..4 Bytes
|
|
* 0b0000000000011..3 Bytes
|
|
* 0b0000000000010..2 Bytes
|
|
* 0b0000000000001..1 Byte
|
|
* 0b0000000000000..No data transfer
|
|
*/
|
|
#define USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)
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#define USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U)
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#define USDHC_BLK_ATT_BLKCNT_SHIFT (16U)
|
|
/*! BLKCNT - Block Count
|
|
* 0b1111111111111111..65535 blocks
|
|
* 0b0000000000000010..2 blocks
|
|
* 0b0000000000000001..1 block
|
|
* 0b0000000000000000..Stop Count
|
|
*/
|
|
#define USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)
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/*! @} */
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|
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/*! @name CMD_ARG - Command Argument */
|
|
/*! @{ */
|
|
#define USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU)
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#define USDHC_CMD_ARG_CMDARG_SHIFT (0U)
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#define USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK)
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/*! @} */
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|
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/*! @name CMD_XFR_TYP - Command Transfer Type */
|
|
/*! @{ */
|
|
#define USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U)
|
|
#define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U)
|
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/*! RSPTYP - Response Type Select
|
|
* 0b00..No Response
|
|
* 0b01..Response Length 136
|
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* 0b10..Response Length 48
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* 0b11..Response Length 48, check Busy after response
|
|
*/
|
|
#define USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)
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#define USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U)
|
|
#define USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U)
|
|
/*! CCCEN - Command CRC Check Enable
|
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* 0b1..Enable
|
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* 0b0..Disable
|
|
*/
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|
#define USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)
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#define USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U)
|
|
#define USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U)
|
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/*! CICEN - Command Index Check Enable
|
|
* 0b1..Enable
|
|
* 0b0..Disable
|
|
*/
|
|
#define USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)
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#define USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U)
|
|
#define USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U)
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|
/*! DPSEL - Data Present Select
|
|
* 0b1..Data Present
|
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* 0b0..No Data Present
|
|
*/
|
|
#define USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)
|
|
#define USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U)
|
|
#define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U)
|
|
/*! CMDTYP - Command Type
|
|
* 0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR
|
|
* 0b10..Resume CMD52 for writing Function Select in CCCR
|
|
* 0b01..Suspend CMD52 for writing Bus Suspend in CCCR
|
|
* 0b00..Normal Other commands
|
|
*/
|
|
#define USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)
|
|
#define USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U)
|
|
#define USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U)
|
|
#define USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CMD_RSP0 - Command Response0 */
|
|
/*! @{ */
|
|
#define USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU)
|
|
#define USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U)
|
|
#define USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CMD_RSP1 - Command Response1 */
|
|
/*! @{ */
|
|
#define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU)
|
|
#define USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U)
|
|
#define USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CMD_RSP2 - Command Response2 */
|
|
/*! @{ */
|
|
#define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU)
|
|
#define USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U)
|
|
#define USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CMD_RSP3 - Command Response3 */
|
|
/*! @{ */
|
|
#define USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU)
|
|
#define USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U)
|
|
#define USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */
|
|
/*! @{ */
|
|
#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU)
|
|
#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U)
|
|
#define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PRES_STATE - Present State */
|
|
/*! @{ */
|
|
#define USDHC_PRES_STATE_CIHB_MASK (0x1U)
|
|
#define USDHC_PRES_STATE_CIHB_SHIFT (0U)
|
|
/*! CIHB - Command Inhibit (CMD)
|
|
* 0b1..Cannot issue command
|
|
* 0b0..Can issue command using only CMD line
|
|
*/
|
|
#define USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)
|
|
#define USDHC_PRES_STATE_CDIHB_MASK (0x2U)
|
|
#define USDHC_PRES_STATE_CDIHB_SHIFT (1U)
|
|
/*! CDIHB - Command Inhibit (DATA)
|
|
* 0b1..Cannot issue command which uses the DATA line
|
|
* 0b0..Can issue command which uses the DATA line
|
|
*/
|
|
#define USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)
|
|
#define USDHC_PRES_STATE_DLA_MASK (0x4U)
|
|
#define USDHC_PRES_STATE_DLA_SHIFT (2U)
|
|
/*! DLA - Data Line Active
|
|
* 0b1..DATA Line Active
|
|
* 0b0..DATA Line Inactive
|
|
*/
|
|
#define USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)
|
|
#define USDHC_PRES_STATE_SDSTB_MASK (0x8U)
|
|
#define USDHC_PRES_STATE_SDSTB_SHIFT (3U)
|
|
/*! SDSTB - SD Clock Stable
|
|
* 0b1..Clock is stable.
|
|
* 0b0..Clock is changing frequency and not stable.
|
|
*/
|
|
#define USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)
|
|
#define USDHC_PRES_STATE_IPGOFF_MASK (0x10U)
|
|
#define USDHC_PRES_STATE_IPGOFF_SHIFT (4U)
|
|
/*! IPGOFF - IPG_CLK Gated Off Internally
|
|
* 0b1..IPG_CLK is gated off.
|
|
* 0b0..IPG_CLK is active.
|
|
*/
|
|
#define USDHC_PRES_STATE_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK)
|
|
#define USDHC_PRES_STATE_HCKOFF_MASK (0x20U)
|
|
#define USDHC_PRES_STATE_HCKOFF_SHIFT (5U)
|
|
/*! HCKOFF - HCLK Gated Off Internally
|
|
* 0b1..HCLK is gated off.
|
|
* 0b0..HCLK is active.
|
|
*/
|
|
#define USDHC_PRES_STATE_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK)
|
|
#define USDHC_PRES_STATE_PEROFF_MASK (0x40U)
|
|
#define USDHC_PRES_STATE_PEROFF_SHIFT (6U)
|
|
/*! PEROFF - IPG_PERCLK Gated Off Internally
|
|
* 0b1..IPG_PERCLK is gated off.
|
|
* 0b0..IPG_PERCLK is active.
|
|
*/
|
|
#define USDHC_PRES_STATE_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK)
|
|
#define USDHC_PRES_STATE_SDOFF_MASK (0x80U)
|
|
#define USDHC_PRES_STATE_SDOFF_SHIFT (7U)
|
|
/*! SDOFF - SD Clock Gated Off Internally
|
|
* 0b1..SD Clock is gated off.
|
|
* 0b0..SD Clock is active.
|
|
*/
|
|
#define USDHC_PRES_STATE_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK)
|
|
#define USDHC_PRES_STATE_WTA_MASK (0x100U)
|
|
#define USDHC_PRES_STATE_WTA_SHIFT (8U)
|
|
/*! WTA - Write Transfer Active
|
|
* 0b1..Transferring data
|
|
* 0b0..No valid data
|
|
*/
|
|
#define USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)
|
|
#define USDHC_PRES_STATE_RTA_MASK (0x200U)
|
|
#define USDHC_PRES_STATE_RTA_SHIFT (9U)
|
|
/*! RTA - Read Transfer Active
|
|
* 0b1..Transferring data
|
|
* 0b0..No valid data
|
|
*/
|
|
#define USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)
|
|
#define USDHC_PRES_STATE_BWEN_MASK (0x400U)
|
|
#define USDHC_PRES_STATE_BWEN_SHIFT (10U)
|
|
/*! BWEN - Buffer Write Enable
|
|
* 0b1..Write enable
|
|
* 0b0..Write disable
|
|
*/
|
|
#define USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)
|
|
#define USDHC_PRES_STATE_BREN_MASK (0x800U)
|
|
#define USDHC_PRES_STATE_BREN_SHIFT (11U)
|
|
/*! BREN - Buffer Read Enable
|
|
* 0b1..Read enable
|
|
* 0b0..Read disable
|
|
*/
|
|
#define USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)
|
|
#define USDHC_PRES_STATE_RTR_MASK (0x1000U)
|
|
#define USDHC_PRES_STATE_RTR_SHIFT (12U)
|
|
/*! RTR - Re-Tuning Request (only for SD3.0 SDR104 mode and EMMC HS200 mode)
|
|
* 0b1..Sampling clock needs re-tuning
|
|
* 0b0..Fixed or well tuned sampling clock
|
|
*/
|
|
#define USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK)
|
|
#define USDHC_PRES_STATE_TSCD_MASK (0x8000U)
|
|
#define USDHC_PRES_STATE_TSCD_SHIFT (15U)
|
|
/*! TSCD - Tape Select Change Done
|
|
* 0b1..Delay cell select change is finished.
|
|
* 0b0..Delay cell select change is not finished.
|
|
*/
|
|
#define USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK)
|
|
#define USDHC_PRES_STATE_CINST_MASK (0x10000U)
|
|
#define USDHC_PRES_STATE_CINST_SHIFT (16U)
|
|
/*! CINST - Card Inserted
|
|
* 0b1..Card Inserted
|
|
* 0b0..Power on Reset or No Card
|
|
*/
|
|
#define USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)
|
|
#define USDHC_PRES_STATE_CDPL_MASK (0x40000U)
|
|
#define USDHC_PRES_STATE_CDPL_SHIFT (18U)
|
|
/*! CDPL - Card Detect Pin Level
|
|
* 0b1..Card present (CD_B = 0)
|
|
* 0b0..No card present (CD_B = 1)
|
|
*/
|
|
#define USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK)
|
|
#define USDHC_PRES_STATE_WPSPL_MASK (0x80000U)
|
|
#define USDHC_PRES_STATE_WPSPL_SHIFT (19U)
|
|
/*! WPSPL - Write Protect Switch Pin Level
|
|
* 0b1..Write enabled (WP = 0)
|
|
* 0b0..Write protected (WP = 1)
|
|
*/
|
|
#define USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK)
|
|
#define USDHC_PRES_STATE_CLSL_MASK (0x800000U)
|
|
#define USDHC_PRES_STATE_CLSL_SHIFT (23U)
|
|
#define USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)
|
|
#define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U)
|
|
#define USDHC_PRES_STATE_DLSL_SHIFT (24U)
|
|
/*! DLSL - DATA[7:0] Line Signal Level
|
|
* 0b00000111..Data 7 line signal level
|
|
* 0b00000110..Data 6 line signal level
|
|
* 0b00000101..Data 5 line signal level
|
|
* 0b00000100..Data 4 line signal level
|
|
* 0b00000011..Data 3 line signal level
|
|
* 0b00000010..Data 2 line signal level
|
|
* 0b00000001..Data 1 line signal level
|
|
* 0b00000000..Data 0 line signal level
|
|
*/
|
|
#define USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name PROT_CTRL - Protocol Control */
|
|
/*! @{ */
|
|
#define USDHC_PROT_CTRL_LCTL_MASK (0x1U)
|
|
#define USDHC_PROT_CTRL_LCTL_SHIFT (0U)
|
|
/*! LCTL - LED Control
|
|
* 0b1..LED on
|
|
* 0b0..LED off
|
|
*/
|
|
#define USDHC_PROT_CTRL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK)
|
|
#define USDHC_PROT_CTRL_DTW_MASK (0x6U)
|
|
#define USDHC_PROT_CTRL_DTW_SHIFT (1U)
|
|
/*! DTW - Data Transfer Width
|
|
* 0b10..8-bit mode
|
|
* 0b01..4-bit mode
|
|
* 0b00..1-bit mode
|
|
* 0b11..Reserved
|
|
*/
|
|
#define USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)
|
|
#define USDHC_PROT_CTRL_D3CD_MASK (0x8U)
|
|
#define USDHC_PROT_CTRL_D3CD_SHIFT (3U)
|
|
/*! D3CD - DATA3 as Card Detection Pin
|
|
* 0b1..DATA3 as Card Detection Pin
|
|
* 0b0..DATA3 does not monitor Card Insertion
|
|
*/
|
|
#define USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)
|
|
#define USDHC_PROT_CTRL_EMODE_MASK (0x30U)
|
|
#define USDHC_PROT_CTRL_EMODE_SHIFT (4U)
|
|
/*! EMODE - Endian Mode
|
|
* 0b00..Big Endian Mode
|
|
* 0b01..Half Word Big Endian Mode
|
|
* 0b10..Little Endian Mode
|
|
* 0b11..Reserved
|
|
*/
|
|
#define USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)
|
|
#define USDHC_PROT_CTRL_CDTL_MASK (0x40U)
|
|
#define USDHC_PROT_CTRL_CDTL_SHIFT (6U)
|
|
/*! CDTL - Card Detect Test Level
|
|
* 0b1..Card Detect Test Level is 1, card inserted
|
|
* 0b0..Card Detect Test Level is 0, no card inserted
|
|
*/
|
|
#define USDHC_PROT_CTRL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK)
|
|
#define USDHC_PROT_CTRL_CDSS_MASK (0x80U)
|
|
#define USDHC_PROT_CTRL_CDSS_SHIFT (7U)
|
|
/*! CDSS - Card Detect Signal Selection
|
|
* 0b1..Card Detection Test Level is selected (for test purpose).
|
|
* 0b0..Card Detection Level is selected (for normal purpose).
|
|
*/
|
|
#define USDHC_PROT_CTRL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK)
|
|
#define USDHC_PROT_CTRL_DMASEL_MASK (0x300U)
|
|
#define USDHC_PROT_CTRL_DMASEL_SHIFT (8U)
|
|
/*! DMASEL - DMA Select
|
|
* 0b00..No DMA or Simple DMA is selected
|
|
* 0b01..ADMA1 is selected
|
|
* 0b10..ADMA2 is selected
|
|
* 0b11..reserved
|
|
*/
|
|
#define USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)
|
|
#define USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U)
|
|
#define USDHC_PROT_CTRL_SABGREQ_SHIFT (16U)
|
|
/*! SABGREQ - Stop At Block Gap Request
|
|
* 0b1..Stop
|
|
* 0b0..Transfer
|
|
*/
|
|
#define USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)
|
|
#define USDHC_PROT_CTRL_CREQ_MASK (0x20000U)
|
|
#define USDHC_PROT_CTRL_CREQ_SHIFT (17U)
|
|
/*! CREQ - Continue Request
|
|
* 0b1..Restart
|
|
* 0b0..No effect
|
|
*/
|
|
#define USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)
|
|
#define USDHC_PROT_CTRL_RWCTL_MASK (0x40000U)
|
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#define USDHC_PROT_CTRL_RWCTL_SHIFT (18U)
|
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/*! RWCTL - Read Wait Control
|
|
* 0b1..Enable Read Wait Control, and assert Read Wait without stopping SD Clock at block gap when SABGREQ bit is set
|
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* 0b0..Disable Read Wait Control, and stop SD Clock at block gap when SABGREQ bit is set
|
|
*/
|
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#define USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)
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#define USDHC_PROT_CTRL_IABG_MASK (0x80000U)
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#define USDHC_PROT_CTRL_IABG_SHIFT (19U)
|
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/*! IABG - Interrupt At Block Gap
|
|
* 0b1..Enabled
|
|
* 0b0..Disabled
|
|
*/
|
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#define USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)
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#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U)
|
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#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U)
|
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#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)
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#define USDHC_PROT_CTRL_WECINT_MASK (0x1000000U)
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#define USDHC_PROT_CTRL_WECINT_SHIFT (24U)
|
|
/*! WECINT - Wakeup Event Enable On Card Interrupt
|
|
* 0b1..Enable
|
|
* 0b0..Disable
|
|
*/
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|
#define USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)
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#define USDHC_PROT_CTRL_WECINS_MASK (0x2000000U)
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#define USDHC_PROT_CTRL_WECINS_SHIFT (25U)
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|
/*! WECINS - Wakeup Event Enable On SD Card Insertion
|
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* 0b1..Enable
|
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* 0b0..Disable
|
|
*/
|
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#define USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)
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#define USDHC_PROT_CTRL_WECRM_MASK (0x4000000U)
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#define USDHC_PROT_CTRL_WECRM_SHIFT (26U)
|
|
/*! WECRM - Wakeup Event Enable On SD Card Removal
|
|
* 0b1..Enable
|
|
* 0b0..Disable
|
|
*/
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|
#define USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)
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#define USDHC_PROT_CTRL_BURST_LEN_EN_MASK (0x38000000U)
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#define USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT (27U)
|
|
/*! BURST_LEN_EN - BURST length enable for INCR, INCR4 / INCR8 / INCR16, INCR4-WRAP / INCR8-WRAP / INCR16-WRAP
|
|
* 0bxx1..Burst length is enabled for INCR
|
|
* 0bx1x..Burst length is enabled for INCR4 / INCR8 / INCR16
|
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* 0b1xx..Burst length is enabled for INCR4-WRAP / INCR8-WRAP / INCR16-WRAP
|
|
*/
|
|
#define USDHC_PROT_CTRL_BURST_LEN_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK)
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#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U)
|
|
#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U)
|
|
/*! NON_EXACT_BLK_RD - NON_EXACT_BLK_RD
|
|
* 0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read.
|
|
* 0b0..The block read is exact block read. Host driver doesn't need to issue abort command to terminate this multi-block read.
|
|
*/
|
|
#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)
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|
/*! @} */
|
|
|
|
/*! @name SYS_CTRL - System Control */
|
|
/*! @{ */
|
|
#define USDHC_SYS_CTRL_DVS_MASK (0xF0U)
|
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#define USDHC_SYS_CTRL_DVS_SHIFT (4U)
|
|
/*! DVS - Divisor
|
|
* 0b0000..Divide-by-1
|
|
* 0b0001..Divide-by-2
|
|
* 0b1110..Divide-by-15
|
|
* 0b1111..Divide-by-16
|
|
*/
|
|
#define USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)
|
|
#define USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U)
|
|
#define USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U)
|
|
#define USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)
|
|
#define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U)
|
|
#define USDHC_SYS_CTRL_DTOCV_SHIFT (16U)
|
|
/*! DTOCV - Data Timeout Counter Value
|
|
* 0b1111..SDCLK x 2 29
|
|
* 0b1110..SDCLK x 2 28
|
|
* 0b1101..SDCLK x 2 27
|
|
* 0b0001..SDCLK x 2 15
|
|
* 0b0000..SDCLK x 2 14
|
|
*/
|
|
#define USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)
|
|
#define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U)
|
|
#define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U)
|
|
#define USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)
|
|
#define USDHC_SYS_CTRL_RSTA_MASK (0x1000000U)
|
|
#define USDHC_SYS_CTRL_RSTA_SHIFT (24U)
|
|
/*! RSTA - Software Reset For ALL
|
|
* 0b1..Reset
|
|
* 0b0..No Reset
|
|
*/
|
|
#define USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)
|
|
#define USDHC_SYS_CTRL_RSTC_MASK (0x2000000U)
|
|
#define USDHC_SYS_CTRL_RSTC_SHIFT (25U)
|
|
/*! RSTC - Software Reset For CMD Line
|
|
* 0b1..Reset
|
|
* 0b0..No Reset
|
|
*/
|
|
#define USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)
|
|
#define USDHC_SYS_CTRL_RSTD_MASK (0x4000000U)
|
|
#define USDHC_SYS_CTRL_RSTD_SHIFT (26U)
|
|
/*! RSTD - Software Reset For DATA Line
|
|
* 0b1..Reset
|
|
* 0b0..No Reset
|
|
*/
|
|
#define USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)
|
|
#define USDHC_SYS_CTRL_INITA_MASK (0x8000000U)
|
|
#define USDHC_SYS_CTRL_INITA_SHIFT (27U)
|
|
#define USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK)
|
|
#define USDHC_SYS_CTRL_RSTT_MASK (0x10000000U)
|
|
#define USDHC_SYS_CTRL_RSTT_SHIFT (28U)
|
|
#define USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name INT_STATUS - Interrupt Status */
|
|
/*! @{ */
|
|
#define USDHC_INT_STATUS_CC_MASK (0x1U)
|
|
#define USDHC_INT_STATUS_CC_SHIFT (0U)
|
|
/*! CC - Command Complete
|
|
* 0b1..Command complete
|
|
* 0b0..Command not complete
|
|
*/
|
|
#define USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)
|
|
#define USDHC_INT_STATUS_TC_MASK (0x2U)
|
|
#define USDHC_INT_STATUS_TC_SHIFT (1U)
|
|
/*! TC - Transfer Complete
|
|
* 0b1..Transfer complete
|
|
* 0b0..Transfer not complete
|
|
*/
|
|
#define USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)
|
|
#define USDHC_INT_STATUS_BGE_MASK (0x4U)
|
|
#define USDHC_INT_STATUS_BGE_SHIFT (2U)
|
|
/*! BGE - Block Gap Event
|
|
* 0b1..Transaction stopped at block gap
|
|
* 0b0..No block gap event
|
|
*/
|
|
#define USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)
|
|
#define USDHC_INT_STATUS_DINT_MASK (0x8U)
|
|
#define USDHC_INT_STATUS_DINT_SHIFT (3U)
|
|
/*! DINT - DMA Interrupt
|
|
* 0b1..DMA Interrupt is generated
|
|
* 0b0..No DMA Interrupt
|
|
*/
|
|
#define USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)
|
|
#define USDHC_INT_STATUS_BWR_MASK (0x10U)
|
|
#define USDHC_INT_STATUS_BWR_SHIFT (4U)
|
|
/*! BWR - Buffer Write Ready
|
|
* 0b1..Ready to write buffer:
|
|
* 0b0..Not ready to write buffer
|
|
*/
|
|
#define USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)
|
|
#define USDHC_INT_STATUS_BRR_MASK (0x20U)
|
|
#define USDHC_INT_STATUS_BRR_SHIFT (5U)
|
|
/*! BRR - Buffer Read Ready
|
|
* 0b1..Ready to read buffer
|
|
* 0b0..Not ready to read buffer
|
|
*/
|
|
#define USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)
|
|
#define USDHC_INT_STATUS_CINS_MASK (0x40U)
|
|
#define USDHC_INT_STATUS_CINS_SHIFT (6U)
|
|
/*! CINS - Card Insertion
|
|
* 0b1..Card inserted
|
|
* 0b0..Card state unstable or removed
|
|
*/
|
|
#define USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)
|
|
#define USDHC_INT_STATUS_CRM_MASK (0x80U)
|
|
#define USDHC_INT_STATUS_CRM_SHIFT (7U)
|
|
/*! CRM - Card Removal
|
|
* 0b1..Card removed
|
|
* 0b0..Card state unstable or inserted
|
|
*/
|
|
#define USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)
|
|
#define USDHC_INT_STATUS_CINT_MASK (0x100U)
|
|
#define USDHC_INT_STATUS_CINT_SHIFT (8U)
|
|
/*! CINT - Card Interrupt
|
|
* 0b1..Generate Card Interrupt
|
|
* 0b0..No Card Interrupt
|
|
*/
|
|
#define USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)
|
|
#define USDHC_INT_STATUS_RTE_MASK (0x1000U)
|
|
#define USDHC_INT_STATUS_RTE_SHIFT (12U)
|
|
/*! RTE - Re-Tuning Event: (only for SD3.0 SDR104 mode and EMMC HS200 mode)
|
|
* 0b1..Re-Tuning should be performed
|
|
* 0b0..Re-Tuning is not required
|
|
*/
|
|
#define USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK)
|
|
#define USDHC_INT_STATUS_TP_MASK (0x4000U)
|
|
#define USDHC_INT_STATUS_TP_SHIFT (14U)
|
|
#define USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK)
|
|
#define USDHC_INT_STATUS_CTOE_MASK (0x10000U)
|
|
#define USDHC_INT_STATUS_CTOE_SHIFT (16U)
|
|
/*! CTOE - Command Timeout Error
|
|
* 0b1..Time out
|
|
* 0b0..No Error
|
|
*/
|
|
#define USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)
|
|
#define USDHC_INT_STATUS_CCE_MASK (0x20000U)
|
|
#define USDHC_INT_STATUS_CCE_SHIFT (17U)
|
|
/*! CCE - Command CRC Error
|
|
* 0b1..CRC Error Generated.
|
|
* 0b0..No Error
|
|
*/
|
|
#define USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)
|
|
#define USDHC_INT_STATUS_CEBE_MASK (0x40000U)
|
|
#define USDHC_INT_STATUS_CEBE_SHIFT (18U)
|
|
/*! CEBE - Command End Bit Error
|
|
* 0b1..End Bit Error Generated
|
|
* 0b0..No Error
|
|
*/
|
|
#define USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)
|
|
#define USDHC_INT_STATUS_CIE_MASK (0x80000U)
|
|
#define USDHC_INT_STATUS_CIE_SHIFT (19U)
|
|
/*! CIE - Command Index Error
|
|
* 0b1..Error
|
|
* 0b0..No Error
|
|
*/
|
|
#define USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)
|
|
#define USDHC_INT_STATUS_DTOE_MASK (0x100000U)
|
|
#define USDHC_INT_STATUS_DTOE_SHIFT (20U)
|
|
/*! DTOE - Data Timeout Error
|
|
* 0b1..Time out
|
|
* 0b0..No Error
|
|
*/
|
|
#define USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)
|
|
#define USDHC_INT_STATUS_DCE_MASK (0x200000U)
|
|
#define USDHC_INT_STATUS_DCE_SHIFT (21U)
|
|
/*! DCE - Data CRC Error
|
|
* 0b1..Error
|
|
* 0b0..No Error
|
|
*/
|
|
#define USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)
|
|
#define USDHC_INT_STATUS_DEBE_MASK (0x400000U)
|
|
#define USDHC_INT_STATUS_DEBE_SHIFT (22U)
|
|
/*! DEBE - Data End Bit Error
|
|
* 0b1..Error
|
|
* 0b0..No Error
|
|
*/
|
|
#define USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)
|
|
#define USDHC_INT_STATUS_AC12E_MASK (0x1000000U)
|
|
#define USDHC_INT_STATUS_AC12E_SHIFT (24U)
|
|
/*! AC12E - Auto CMD12 Error
|
|
* 0b1..Error
|
|
* 0b0..No Error
|
|
*/
|
|
#define USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)
|
|
#define USDHC_INT_STATUS_TNE_MASK (0x4000000U)
|
|
#define USDHC_INT_STATUS_TNE_SHIFT (26U)
|
|
#define USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK)
|
|
#define USDHC_INT_STATUS_DMAE_MASK (0x10000000U)
|
|
#define USDHC_INT_STATUS_DMAE_SHIFT (28U)
|
|
/*! DMAE - DMA Error
|
|
* 0b1..Error
|
|
* 0b0..No Error
|
|
*/
|
|
#define USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name INT_STATUS_EN - Interrupt Status Enable */
|
|
/*! @{ */
|
|
#define USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U)
|
|
#define USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U)
|
|
/*! CCSEN - Command Complete Status Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
|
|
#define USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)
|
|
#define USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U)
|
|
#define USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U)
|
|
/*! TCSEN - Transfer Complete Status Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
|
|
#define USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)
|
|
#define USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U)
|
|
#define USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U)
|
|
/*! BGESEN - Block Gap Event Status Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
|
|
#define USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)
|
|
#define USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U)
|
|
#define USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U)
|
|
/*! DINTSEN - DMA Interrupt Status Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
|
|
#define USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)
|
|
#define USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U)
|
|
#define USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U)
|
|
/*! BWRSEN - Buffer Write Ready Status Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
|
|
#define USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)
|
|
#define USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U)
|
|
#define USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U)
|
|
/*! BRRSEN - Buffer Read Ready Status Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
|
|
#define USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)
|
|
#define USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U)
|
|
#define USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U)
|
|
/*! CINSSEN - Card Insertion Status Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
|
|
#define USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)
|
|
#define USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U)
|
|
#define USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U)
|
|
/*! CRMSEN - Card Removal Status Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
|
|
#define USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)
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#define USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U)
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#define USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U)
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/*! CINTSEN - Card Interrupt Status Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
|
|
#define USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)
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#define USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U)
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#define USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U)
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/*! RTESEN - Re-Tuning Event Status Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
|
|
#define USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK)
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#define USDHC_INT_STATUS_EN_TPSEN_MASK (0x4000U)
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#define USDHC_INT_STATUS_EN_TPSEN_SHIFT (14U)
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/*! TPSEN - Tuning Pass Status Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
|
|
#define USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK)
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#define USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U)
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#define USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U)
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/*! CTOESEN - Command Timeout Error Status Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
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|
#define USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)
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#define USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U)
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#define USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U)
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/*! CCESEN - Command CRC Error Status Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
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|
#define USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)
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#define USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U)
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#define USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U)
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/*! CEBESEN - Command End Bit Error Status Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
|
|
#define USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)
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#define USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U)
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#define USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U)
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/*! CIESEN - Command Index Error Status Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
|
|
#define USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)
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#define USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U)
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#define USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U)
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/*! DTOESEN - Data Timeout Error Status Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
|
|
#define USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)
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#define USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U)
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#define USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U)
|
|
/*! DCESEN - Data CRC Error Status Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
|
|
#define USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)
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#define USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U)
|
|
#define USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U)
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|
/*! DEBESEN - Data End Bit Error Status Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
|
|
#define USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)
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|
#define USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U)
|
|
#define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U)
|
|
/*! AC12ESEN - Auto CMD12 Error Status Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
|
|
#define USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)
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|
#define USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U)
|
|
#define USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U)
|
|
/*! TNESEN - Tuning Error Status Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
|
|
#define USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK)
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|
#define USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U)
|
|
#define USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U)
|
|
/*! DMAESEN - DMA Error Status Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
|
|
#define USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)
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|
/*! @} */
|
|
|
|
/*! @name INT_SIGNAL_EN - Interrupt Signal Enable */
|
|
/*! @{ */
|
|
#define USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U)
|
|
#define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U)
|
|
/*! CCIEN - Command Complete Interrupt Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
|
|
#define USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)
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|
#define USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U)
|
|
#define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U)
|
|
/*! TCIEN - Transfer Complete Interrupt Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
|
|
#define USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)
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|
#define USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U)
|
|
#define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U)
|
|
/*! BGEIEN - Block Gap Event Interrupt Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
|
|
#define USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)
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|
#define USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U)
|
|
#define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U)
|
|
/*! DINTIEN - DMA Interrupt Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
|
|
#define USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)
|
|
#define USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U)
|
|
#define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U)
|
|
/*! BWRIEN - Buffer Write Ready Interrupt Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
|
|
#define USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)
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|
#define USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U)
|
|
#define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U)
|
|
/*! BRRIEN - Buffer Read Ready Interrupt Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
|
|
#define USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)
|
|
#define USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U)
|
|
#define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U)
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|
/*! CINSIEN - Card Insertion Interrupt Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
|
|
#define USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)
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|
#define USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U)
|
|
#define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U)
|
|
/*! CRMIEN - Card Removal Interrupt Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
|
|
#define USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)
|
|
#define USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U)
|
|
#define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U)
|
|
/*! CINTIEN - Card Interrupt Interrupt Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
|
|
#define USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)
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|
#define USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U)
|
|
#define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U)
|
|
/*! RTEIEN - Re-Tuning Event Interrupt Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
|
|
#define USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK)
|
|
#define USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x4000U)
|
|
#define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (14U)
|
|
/*! TPIEN - Tuning Pass Interrupt Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
|
|
#define USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK)
|
|
#define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U)
|
|
#define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U)
|
|
/*! CTOEIEN - Command Timeout Error Interrupt Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
|
|
#define USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)
|
|
#define USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U)
|
|
#define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U)
|
|
/*! CCEIEN - Command CRC Error Interrupt Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
|
|
#define USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)
|
|
#define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U)
|
|
#define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U)
|
|
/*! CEBEIEN - Command End Bit Error Interrupt Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
|
|
#define USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)
|
|
#define USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U)
|
|
#define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U)
|
|
/*! CIEIEN - Command Index Error Interrupt Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
|
|
#define USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)
|
|
#define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U)
|
|
#define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U)
|
|
/*! DTOEIEN - Data Timeout Error Interrupt Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
|
|
#define USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)
|
|
#define USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U)
|
|
#define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U)
|
|
/*! DCEIEN - Data CRC Error Interrupt Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
|
|
#define USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)
|
|
#define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U)
|
|
#define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U)
|
|
/*! DEBEIEN - Data End Bit Error Interrupt Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
|
|
#define USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)
|
|
#define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U)
|
|
#define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U)
|
|
/*! AC12EIEN - Auto CMD12 Error Interrupt Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
|
|
#define USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)
|
|
#define USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U)
|
|
#define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U)
|
|
/*! TNEIEN - Tuning Error Interrupt Enable
|
|
* 0b1..Enabled
|
|
* 0b0..Masked
|
|
*/
|
|
#define USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK)
|
|
#define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U)
|
|
#define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U)
|
|
/*! DMAEIEN - DMA Error Interrupt Enable
|
|
* 0b1..Enable
|
|
* 0b0..Masked
|
|
*/
|
|
#define USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */
|
|
/*! @{ */
|
|
#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U)
|
|
#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U)
|
|
/*! AC12NE - Auto CMD12 Not Executed
|
|
* 0b1..Not executed
|
|
* 0b0..Executed
|
|
*/
|
|
#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)
|
|
#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U)
|
|
#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U)
|
|
/*! AC12TOE - Auto CMD12 / 23 Timeout Error
|
|
* 0b1..Time out
|
|
* 0b0..No error
|
|
*/
|
|
#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)
|
|
#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U)
|
|
#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U)
|
|
/*! AC12EBE - Auto CMD12 / 23 End Bit Error
|
|
* 0b1..End Bit Error Generated
|
|
* 0b0..No error
|
|
*/
|
|
#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)
|
|
#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U)
|
|
#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U)
|
|
/*! AC12CE - Auto CMD12 / 23 CRC Error
|
|
* 0b1..CRC Error Met in Auto CMD12/23 Response
|
|
* 0b0..No CRC error
|
|
*/
|
|
#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)
|
|
#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U)
|
|
#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U)
|
|
/*! AC12IE - Auto CMD12 / 23 Index Error
|
|
* 0b1..Error, the CMD index in response is not CMD12/23
|
|
* 0b0..No error
|
|
*/
|
|
#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)
|
|
#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U)
|
|
#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U)
|
|
/*! CNIBAC12E - Command Not Issued By Auto CMD12 Error
|
|
* 0b1..Not Issued
|
|
* 0b0..No error
|
|
*/
|
|
#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)
|
|
#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U)
|
|
#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U)
|
|
#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK)
|
|
#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U)
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#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U)
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/*! SMP_CLK_SEL - Sample Clock Select
|
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* 0b1..Tuned clock is used to sample data
|
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* 0b0..Fixed clock is used to sample data
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*/
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#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK)
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/*! @} */
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/*! @name HOST_CTRL_CAP - Host Controller Capabilities */
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/*! @{ */
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#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U)
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#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U)
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#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK)
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#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U)
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#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U)
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#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK)
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#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U)
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#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U)
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#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK)
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#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK (0xF00U)
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#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT (8U)
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#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT)) & USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK)
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#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U)
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#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U)
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/*! USE_TUNING_SDR50 - Use Tuning for SDR50
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* 0b1..SDR50 requires tuning
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* 0b0..SDR does not require tuning
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*/
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#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK)
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#define USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK (0xC000U)
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#define USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT (14U)
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/*! RETUNING_MODE - Retuning Mode
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* 0b00..Mode 1
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* 0b01..Mode 2
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* 0b10..Mode 3
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* 0b11..Reserved
|
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*/
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#define USDHC_HOST_CTRL_CAP_RETUNING_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT)) & USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK)
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#define USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U)
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#define USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U)
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/*! MBL - Max Block Length
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* 0b000..512 bytes
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* 0b001..1024 bytes
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* 0b010..2048 bytes
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* 0b011..4096 bytes
|
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*/
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#define USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)
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#define USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U)
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#define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U)
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/*! ADMAS - ADMA Support
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* 0b1..Advanced DMA Supported
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* 0b0..Advanced DMA Not supported
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|
*/
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#define USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)
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#define USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U)
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#define USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U)
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/*! HSS - High Speed Support
|
|
* 0b1..High Speed Supported
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* 0b0..High Speed Not Supported
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*/
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#define USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)
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#define USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U)
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#define USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U)
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/*! DMAS - DMA Support
|
|
* 0b1..DMA Supported
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* 0b0..DMA not supported
|
|
*/
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#define USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)
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#define USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U)
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|
#define USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U)
|
|
/*! SRS - Suspend / Resume Support
|
|
* 0b1..Supported
|
|
* 0b0..Not supported
|
|
*/
|
|
#define USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)
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#define USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U)
|
|
#define USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U)
|
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/*! VS33 - Voltage Support 3.3V
|
|
* 0b1..3.3V supported
|
|
* 0b0..3.3V not supported
|
|
*/
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|
#define USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)
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#define USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U)
|
|
#define USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U)
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|
/*! VS30 - Voltage Support 3.0 V
|
|
* 0b1..3.0V supported
|
|
* 0b0..3.0V not supported
|
|
*/
|
|
#define USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)
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|
#define USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U)
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|
#define USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U)
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/*! VS18 - Voltage Support 1.8 V
|
|
* 0b1..1.8V supported
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|
* 0b0..1.8V not supported
|
|
*/
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|
#define USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)
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/*! @} */
|
|
|
|
/*! @name WTMK_LVL - Watermark Level */
|
|
/*! @{ */
|
|
#define USDHC_WTMK_LVL_RD_WML_MASK (0xFFU)
|
|
#define USDHC_WTMK_LVL_RD_WML_SHIFT (0U)
|
|
#define USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK)
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|
#define USDHC_WTMK_LVL_RD_BRST_LEN_MASK (0x1F00U)
|
|
#define USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT (8U)
|
|
#define USDHC_WTMK_LVL_RD_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_RD_BRST_LEN_MASK)
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|
#define USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U)
|
|
#define USDHC_WTMK_LVL_WR_WML_SHIFT (16U)
|
|
#define USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK)
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|
#define USDHC_WTMK_LVL_WR_BRST_LEN_MASK (0x1F000000U)
|
|
#define USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT (24U)
|
|
#define USDHC_WTMK_LVL_WR_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK)
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|
/*! @} */
|
|
|
|
/*! @name MIX_CTRL - Mixer Control */
|
|
/*! @{ */
|
|
#define USDHC_MIX_CTRL_DMAEN_MASK (0x1U)
|
|
#define USDHC_MIX_CTRL_DMAEN_SHIFT (0U)
|
|
/*! DMAEN - DMA Enable
|
|
* 0b1..Enable
|
|
* 0b0..Disable
|
|
*/
|
|
#define USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)
|
|
#define USDHC_MIX_CTRL_BCEN_MASK (0x2U)
|
|
#define USDHC_MIX_CTRL_BCEN_SHIFT (1U)
|
|
/*! BCEN - Block Count Enable
|
|
* 0b1..Enable
|
|
* 0b0..Disable
|
|
*/
|
|
#define USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)
|
|
#define USDHC_MIX_CTRL_AC12EN_MASK (0x4U)
|
|
#define USDHC_MIX_CTRL_AC12EN_SHIFT (2U)
|
|
/*! AC12EN - Auto CMD12 Enable
|
|
* 0b1..Enable
|
|
* 0b0..Disable
|
|
*/
|
|
#define USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)
|
|
#define USDHC_MIX_CTRL_DDR_EN_MASK (0x8U)
|
|
#define USDHC_MIX_CTRL_DDR_EN_SHIFT (3U)
|
|
#define USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)
|
|
#define USDHC_MIX_CTRL_DTDSEL_MASK (0x10U)
|
|
#define USDHC_MIX_CTRL_DTDSEL_SHIFT (4U)
|
|
/*! DTDSEL - Data Transfer Direction Select
|
|
* 0b1..Read (Card to Host)
|
|
* 0b0..Write (Host to Card)
|
|
*/
|
|
#define USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)
|
|
#define USDHC_MIX_CTRL_MSBSEL_MASK (0x20U)
|
|
#define USDHC_MIX_CTRL_MSBSEL_SHIFT (5U)
|
|
/*! MSBSEL - Multi / Single Block Select
|
|
* 0b1..Multiple Blocks
|
|
* 0b0..Single Block
|
|
*/
|
|
#define USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)
|
|
#define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U)
|
|
#define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U)
|
|
#define USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
|
|
#define USDHC_MIX_CTRL_AC23EN_MASK (0x80U)
|
|
#define USDHC_MIX_CTRL_AC23EN_SHIFT (7U)
|
|
#define USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)
|
|
#define USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U)
|
|
#define USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U)
|
|
/*! EXE_TUNE - Execute Tuning: (Only used for SD3.0, SDR104 mode and EMMC HS200 mode)
|
|
* 0b1..Execute Tuning
|
|
* 0b0..Not Tuned or Tuning Completed
|
|
*/
|
|
#define USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK)
|
|
#define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U)
|
|
#define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U)
|
|
/*! SMP_CLK_SEL - SMP_CLK_SEL
|
|
* 0b1..Tuned clock is used to sample data / cmd
|
|
* 0b0..Fixed clock is used to sample data / cmd
|
|
*/
|
|
#define USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK)
|
|
#define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U)
|
|
#define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U)
|
|
/*! AUTO_TUNE_EN - Auto Tuning Enable (Only used for SD3.0, SDR104 mode and and EMMC HS200 mode)
|
|
* 0b1..Enable auto tuning
|
|
* 0b0..Disable auto tuning
|
|
*/
|
|
#define USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK)
|
|
#define USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U)
|
|
#define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U)
|
|
/*! FBCLK_SEL - Feedback Clock Source Selection (Only used for SD3.0, SDR104 mode and EMMC HS200 mode)
|
|
* 0b1..Feedback clock comes from the ipp_card_clk_out
|
|
* 0b0..Feedback clock comes from the loopback CLK
|
|
*/
|
|
#define USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name FORCE_EVENT - Force Event */
|
|
/*! @{ */
|
|
#define USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U)
|
|
#define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U)
|
|
#define USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK)
|
|
#define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U)
|
|
#define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U)
|
|
#define USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK)
|
|
#define USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U)
|
|
#define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U)
|
|
#define USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK)
|
|
#define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U)
|
|
#define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U)
|
|
#define USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK)
|
|
#define USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U)
|
|
#define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U)
|
|
#define USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK)
|
|
#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U)
|
|
#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U)
|
|
#define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK)
|
|
#define USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U)
|
|
#define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U)
|
|
#define USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK)
|
|
#define USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U)
|
|
#define USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U)
|
|
#define USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK)
|
|
#define USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U)
|
|
#define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U)
|
|
#define USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK)
|
|
#define USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U)
|
|
#define USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U)
|
|
#define USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK)
|
|
#define USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U)
|
|
#define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U)
|
|
#define USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK)
|
|
#define USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U)
|
|
#define USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U)
|
|
#define USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK)
|
|
#define USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U)
|
|
#define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U)
|
|
#define USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK)
|
|
#define USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U)
|
|
#define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U)
|
|
#define USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK)
|
|
#define USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U)
|
|
#define USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U)
|
|
#define USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK)
|
|
#define USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U)
|
|
#define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U)
|
|
#define USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK)
|
|
#define USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U)
|
|
#define USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U)
|
|
#define USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name ADMA_ERR_STATUS - ADMA Error Status Register */
|
|
/*! @{ */
|
|
#define USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U)
|
|
#define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U)
|
|
#define USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)
|
|
#define USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U)
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#define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U)
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/*! ADMALME - ADMA Length Mismatch Error
|
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* 0b1..Error
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* 0b0..No Error
|
|
*/
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#define USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)
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#define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U)
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#define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U)
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/*! ADMADCE - ADMA Descriptor Error
|
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* 0b1..Error
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* 0b0..No Error
|
|
*/
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#define USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)
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/*! @} */
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/*! @name ADMA_SYS_ADDR - ADMA System Address */
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/*! @{ */
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#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU)
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#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U)
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#define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)
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/*! @} */
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/*! @name DLL_CTRL - DLL (Delay Line) Control */
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|
/*! @{ */
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#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U)
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#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U)
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#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK)
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#define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U)
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#define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U)
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#define USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK)
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#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
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#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
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#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK)
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#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U)
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#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U)
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#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK)
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#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
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#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
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#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK)
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#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
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#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
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#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK)
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#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
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#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
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#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
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#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U)
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#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U)
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#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK)
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#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
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#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
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#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK)
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#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
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#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
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#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK)
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/*! @} */
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/*! @name DLL_STATUS - DLL Status */
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|
/*! @{ */
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#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U)
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#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U)
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#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK)
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#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U)
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#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U)
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#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK)
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#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU)
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#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U)
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#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK)
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#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U)
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#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U)
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#define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK)
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/*! @} */
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/*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */
|
|
/*! @{ */
|
|
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU)
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|
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U)
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|
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK)
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#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U)
|
|
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U)
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|
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK)
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#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U)
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#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U)
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#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK)
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#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U)
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#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U)
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#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)
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#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U)
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#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U)
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#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK)
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#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U)
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#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U)
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#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK)
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#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U)
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#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U)
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#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK)
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#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U)
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#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U)
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#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)
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/*! @} */
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/*! @name VEND_SPEC - Vendor Specific Register */
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/*! @{ */
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#define USDHC_VEND_SPEC_VSELECT_MASK (0x2U)
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#define USDHC_VEND_SPEC_VSELECT_SHIFT (1U)
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/*! VSELECT - Voltage Selection
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|
* 0b1..Change the voltage to low voltage range, around 1.8 V
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* 0b0..Change the voltage to high voltage range, around 3.0 V
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*/
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#define USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK)
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#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U)
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#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U)
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/*! CONFLICT_CHK_EN - Conflict check enable.
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* 0b0..Conflict check disable
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* 0b1..Conflict check enable
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*/
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#define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK)
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#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U)
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#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U)
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/*! AC12_WR_CHKBUSY_EN - AC12_WR_CHKBUSY_EN
|
|
* 0b0..Do not check busy after auto CMD12 for write data packet
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|
* 0b1..Check busy after auto CMD12 for write data packet
|
|
*/
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|
#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)
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#define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U)
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|
#define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U)
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/*! FRC_SDCLK_ON - FRC_SDCLK_ON
|
|
* 0b0..CLK active or inactive is fully controlled by the hardware.
|
|
* 0b1..Force CLK active.
|
|
*/
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|
#define USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)
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|
#define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U)
|
|
#define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U)
|
|
/*! CRC_CHK_DIS - CRC Check Disable
|
|
* 0b0..Check CRC16 for every read data packet and check CRC bits for every write data packet
|
|
* 0b1..Ignore CRC16 check for every read data packet and ignore CRC bits check for every write data packet
|
|
*/
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|
#define USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)
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|
#define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U)
|
|
#define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U)
|
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/*! CMD_BYTE_EN - CMD_BYTE_EN
|
|
* 0b0..Disable
|
|
* 0b1..Enable
|
|
*/
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|
#define USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)
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/*! @} */
|
|
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/*! @name MMC_BOOT - MMC Boot Register */
|
|
/*! @{ */
|
|
#define USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU)
|
|
#define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U)
|
|
/*! DTOCV_ACK - DTOCV_ACK
|
|
* 0b0000..SDCLK x 2^14
|
|
* 0b0001..SDCLK x 2^15
|
|
* 0b0010..SDCLK x 2^16
|
|
* 0b0011..SDCLK x 2^17
|
|
* 0b0100..SDCLK x 2^18
|
|
* 0b0101..SDCLK x 2^19
|
|
* 0b0110..SDCLK x 2^20
|
|
* 0b0111..SDCLK x 2^21
|
|
* 0b1110..SDCLK x 2^28
|
|
* 0b1111..SDCLK x 2^29
|
|
*/
|
|
#define USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)
|
|
#define USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U)
|
|
#define USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U)
|
|
/*! BOOT_ACK - BOOT_ACK
|
|
* 0b0..No ack
|
|
* 0b1..Ack
|
|
*/
|
|
#define USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)
|
|
#define USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U)
|
|
#define USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U)
|
|
/*! BOOT_MODE - BOOT_MODE
|
|
* 0b0..Normal boot
|
|
* 0b1..Alternative boot
|
|
*/
|
|
#define USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)
|
|
#define USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U)
|
|
#define USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U)
|
|
/*! BOOT_EN - BOOT_EN
|
|
* 0b0..Fast boot disable
|
|
* 0b1..Fast boot enable
|
|
*/
|
|
#define USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)
|
|
#define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U)
|
|
#define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U)
|
|
#define USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)
|
|
#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U)
|
|
#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U)
|
|
/*! DISABLE_TIME_OUT - Disable Time Out
|
|
* 0b0..Enable time out
|
|
* 0b1..Disable time out
|
|
*/
|
|
#define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)
|
|
#define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U)
|
|
#define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U)
|
|
#define USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name VEND_SPEC2 - Vendor Specific 2 Register */
|
|
/*! @{ */
|
|
#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U)
|
|
#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U)
|
|
/*! CARD_INT_D3_TEST - Card Interrupt Detection Test
|
|
* 0b0..Check the card interrupt only when DATA3 is high.
|
|
* 0b1..Check the card interrupt by ignoring the status of DATA3.
|
|
*/
|
|
#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)
|
|
#define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U)
|
|
#define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U)
|
|
#define USDHC_VEND_SPEC2_TUNING_8bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK)
|
|
#define USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U)
|
|
#define USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U)
|
|
#define USDHC_VEND_SPEC2_TUNING_1bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK)
|
|
#define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U)
|
|
#define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U)
|
|
/*! TUNING_CMD_EN - TUNING_CMD_EN
|
|
* 0b0..Auto tuning circuit does not check the CMD line.
|
|
* 0b1..Auto tuning circuit checks the CMD line.
|
|
*/
|
|
#define USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK)
|
|
#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U)
|
|
#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U)
|
|
/*! ACMD23_ARGU2_EN - Argument2 register enable for ACMD23
|
|
* 0b1..Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enable.
|
|
* 0b0..Disable
|
|
*/
|
|
#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK)
|
|
#define USDHC_VEND_SPEC2_PART_DLL_DEBUG_MASK (0x2000U)
|
|
#define USDHC_VEND_SPEC2_PART_DLL_DEBUG_SHIFT (13U)
|
|
#define USDHC_VEND_SPEC2_PART_DLL_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_PART_DLL_DEBUG_SHIFT)) & USDHC_VEND_SPEC2_PART_DLL_DEBUG_MASK)
|
|
#define USDHC_VEND_SPEC2_BUS_RST_MASK (0x4000U)
|
|
#define USDHC_VEND_SPEC2_BUS_RST_SHIFT (14U)
|
|
#define USDHC_VEND_SPEC2_BUS_RST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_BUS_RST_SHIFT)) & USDHC_VEND_SPEC2_BUS_RST_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name TUNING_CTRL - Tuning Control Register */
|
|
/*! @{ */
|
|
#define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0xFFU)
|
|
#define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U)
|
|
#define USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK)
|
|
#define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U)
|
|
#define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U)
|
|
#define USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK)
|
|
#define USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U)
|
|
#define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U)
|
|
#define USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK)
|
|
#define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U)
|
|
#define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U)
|
|
#define USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK)
|
|
#define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U)
|
|
#define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U)
|
|
#define USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group USDHC_Register_Masks */
|
|
|
|
|
|
/* USDHC - Peripheral instance base addresses */
|
|
/** Peripheral USDHC1 base address */
|
|
#define USDHC1_BASE (0x402C0000u)
|
|
/** Peripheral USDHC1 base pointer */
|
|
#define USDHC1 ((USDHC_Type *)USDHC1_BASE)
|
|
/** Peripheral USDHC2 base address */
|
|
#define USDHC2_BASE (0x402C4000u)
|
|
/** Peripheral USDHC2 base pointer */
|
|
#define USDHC2 ((USDHC_Type *)USDHC2_BASE)
|
|
/** Array initializer of USDHC peripheral base addresses */
|
|
#define USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE }
|
|
/** Array initializer of USDHC peripheral base pointers */
|
|
#define USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2 }
|
|
/** Interrupt vectors for the USDHC peripheral type */
|
|
#define USDHC_IRQS { NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group USDHC_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- WDOG Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** WDOG - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint16_t WCR; /**< Watchdog Control Register, offset: 0x0 */
|
|
__IO uint16_t WSR; /**< Watchdog Service Register, offset: 0x2 */
|
|
__I uint16_t WRSR; /**< Watchdog Reset Status Register, offset: 0x4 */
|
|
__IO uint16_t WICR; /**< Watchdog Interrupt Control Register, offset: 0x6 */
|
|
__IO uint16_t WMCR; /**< Watchdog Miscellaneous Control Register, offset: 0x8 */
|
|
} WDOG_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- WDOG Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup WDOG_Register_Masks WDOG Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name WCR - Watchdog Control Register */
|
|
/*! @{ */
|
|
#define WDOG_WCR_WDZST_MASK (0x1U)
|
|
#define WDOG_WCR_WDZST_SHIFT (0U)
|
|
/*! WDZST - WDZST
|
|
* 0b0..Continue timer operation (Default).
|
|
* 0b1..Suspend the watchdog timer.
|
|
*/
|
|
#define WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK)
|
|
#define WDOG_WCR_WDBG_MASK (0x2U)
|
|
#define WDOG_WCR_WDBG_SHIFT (1U)
|
|
/*! WDBG - WDBG
|
|
* 0b0..Continue WDOG timer operation (Default).
|
|
* 0b1..Suspend the watchdog timer.
|
|
*/
|
|
#define WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK)
|
|
#define WDOG_WCR_WDE_MASK (0x4U)
|
|
#define WDOG_WCR_WDE_SHIFT (2U)
|
|
/*! WDE - WDE
|
|
* 0b0..Disable the Watchdog (Default).
|
|
* 0b1..Enable the Watchdog.
|
|
*/
|
|
#define WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK)
|
|
#define WDOG_WCR_WDT_MASK (0x8U)
|
|
#define WDOG_WCR_WDT_SHIFT (3U)
|
|
/*! WDT - WDT
|
|
* 0b0..No effect on WDOG_B (Default).
|
|
* 0b1..Assert WDOG_B upon a Watchdog Time-out event.
|
|
*/
|
|
#define WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK)
|
|
#define WDOG_WCR_SRS_MASK (0x10U)
|
|
#define WDOG_WCR_SRS_SHIFT (4U)
|
|
/*! SRS - SRS
|
|
* 0b0..Assert system reset signal.
|
|
* 0b1..No effect on the system (Default).
|
|
*/
|
|
#define WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK)
|
|
#define WDOG_WCR_WDA_MASK (0x20U)
|
|
#define WDOG_WCR_WDA_SHIFT (5U)
|
|
/*! WDA - WDA
|
|
* 0b0..Assert WDOG_B output.
|
|
* 0b1..No effect on system (Default).
|
|
*/
|
|
#define WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK)
|
|
#define WDOG_WCR_SRE_MASK (0x40U)
|
|
#define WDOG_WCR_SRE_SHIFT (6U)
|
|
/*! SRE - software reset extension, an option way to generate software reset
|
|
* 0b0..using original way to generate software reset (default)
|
|
* 0b1..using new way to generate software reset.
|
|
*/
|
|
#define WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK)
|
|
#define WDOG_WCR_WDW_MASK (0x80U)
|
|
#define WDOG_WCR_WDW_SHIFT (7U)
|
|
/*! WDW - WDW
|
|
* 0b0..Continue WDOG timer operation (Default).
|
|
* 0b1..Suspend WDOG timer operation.
|
|
*/
|
|
#define WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK)
|
|
#define WDOG_WCR_WT_MASK (0xFF00U)
|
|
#define WDOG_WCR_WT_SHIFT (8U)
|
|
/*! WT - WT
|
|
* 0b00000000..- 0.5 Seconds (Default).
|
|
* 0b00000001..- 1.0 Seconds.
|
|
* 0b00000010..- 1.5 Seconds.
|
|
* 0b00000011..- 2.0 Seconds.
|
|
* 0b11111111..- 128 Seconds.
|
|
*/
|
|
#define WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name WSR - Watchdog Service Register */
|
|
/*! @{ */
|
|
#define WDOG_WSR_WSR_MASK (0xFFFFU)
|
|
#define WDOG_WSR_WSR_SHIFT (0U)
|
|
/*! WSR - WSR
|
|
* 0b0101010101010101..Write to the Watchdog Service Register (WDOG_WSR).
|
|
* 0b1010101010101010..Write to the Watchdog Service Register (WDOG_WSR).
|
|
*/
|
|
#define WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name WRSR - Watchdog Reset Status Register */
|
|
/*! @{ */
|
|
#define WDOG_WRSR_SFTW_MASK (0x1U)
|
|
#define WDOG_WRSR_SFTW_SHIFT (0U)
|
|
/*! SFTW - SFTW
|
|
* 0b0..Reset is not the result of a software reset.
|
|
* 0b1..Reset is the result of a software reset.
|
|
*/
|
|
#define WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK)
|
|
#define WDOG_WRSR_TOUT_MASK (0x2U)
|
|
#define WDOG_WRSR_TOUT_SHIFT (1U)
|
|
/*! TOUT - TOUT
|
|
* 0b0..Reset is not the result of a WDOG timeout.
|
|
* 0b1..Reset is the result of a WDOG timeout.
|
|
*/
|
|
#define WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK)
|
|
#define WDOG_WRSR_POR_MASK (0x10U)
|
|
#define WDOG_WRSR_POR_SHIFT (4U)
|
|
/*! POR - POR
|
|
* 0b0..Reset is not the result of a power on reset.
|
|
* 0b1..Reset is the result of a power on reset.
|
|
*/
|
|
#define WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name WICR - Watchdog Interrupt Control Register */
|
|
/*! @{ */
|
|
#define WDOG_WICR_WICT_MASK (0xFFU)
|
|
#define WDOG_WICR_WICT_SHIFT (0U)
|
|
/*! WICT - WICT
|
|
* 0b00000000..WICT[7:0] = Time duration between interrupt and time-out is 0 seconds.
|
|
* 0b00000001..WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds.
|
|
* 0b00000100..WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default).
|
|
* 0b11111111..WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds.
|
|
*/
|
|
#define WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK)
|
|
#define WDOG_WICR_WTIS_MASK (0x4000U)
|
|
#define WDOG_WICR_WTIS_SHIFT (14U)
|
|
/*! WTIS - WTIS
|
|
* 0b0..No interrupt has occurred (Default).
|
|
* 0b1..Interrupt has occurred
|
|
*/
|
|
#define WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK)
|
|
#define WDOG_WICR_WIE_MASK (0x8000U)
|
|
#define WDOG_WICR_WIE_SHIFT (15U)
|
|
/*! WIE - WIE
|
|
* 0b0..Disable Interrupt (Default).
|
|
* 0b1..Enable Interrupt.
|
|
*/
|
|
#define WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name WMCR - Watchdog Miscellaneous Control Register */
|
|
/*! @{ */
|
|
#define WDOG_WMCR_PDE_MASK (0x1U)
|
|
#define WDOG_WMCR_PDE_SHIFT (0U)
|
|
/*! PDE - PDE
|
|
* 0b0..Power Down Counter of WDOG is disabled.
|
|
* 0b1..Power Down Counter of WDOG is enabled (Default).
|
|
*/
|
|
#define WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group WDOG_Register_Masks */
|
|
|
|
|
|
/* WDOG - Peripheral instance base addresses */
|
|
/** Peripheral WDOG1 base address */
|
|
#define WDOG1_BASE (0x400B8000u)
|
|
/** Peripheral WDOG1 base pointer */
|
|
#define WDOG1 ((WDOG_Type *)WDOG1_BASE)
|
|
/** Peripheral WDOG2 base address */
|
|
#define WDOG2_BASE (0x400D0000u)
|
|
/** Peripheral WDOG2 base pointer */
|
|
#define WDOG2 ((WDOG_Type *)WDOG2_BASE)
|
|
/** Array initializer of WDOG peripheral base addresses */
|
|
#define WDOG_BASE_ADDRS { 0u, WDOG1_BASE, WDOG2_BASE }
|
|
/** Array initializer of WDOG peripheral base pointers */
|
|
#define WDOG_BASE_PTRS { (WDOG_Type *)0u, WDOG1, WDOG2 }
|
|
/** Interrupt vectors for the WDOG peripheral type */
|
|
#define WDOG_IRQS { NotAvail_IRQn, WDOG1_IRQn, WDOG2_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group WDOG_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- XBARA Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup XBARA_Peripheral_Access_Layer XBARA Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** XBARA - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint16_t SEL0; /**< Crossbar A Select Register 0, offset: 0x0 */
|
|
__IO uint16_t SEL1; /**< Crossbar A Select Register 1, offset: 0x2 */
|
|
__IO uint16_t SEL2; /**< Crossbar A Select Register 2, offset: 0x4 */
|
|
__IO uint16_t SEL3; /**< Crossbar A Select Register 3, offset: 0x6 */
|
|
__IO uint16_t SEL4; /**< Crossbar A Select Register 4, offset: 0x8 */
|
|
__IO uint16_t SEL5; /**< Crossbar A Select Register 5, offset: 0xA */
|
|
__IO uint16_t SEL6; /**< Crossbar A Select Register 6, offset: 0xC */
|
|
__IO uint16_t SEL7; /**< Crossbar A Select Register 7, offset: 0xE */
|
|
__IO uint16_t SEL8; /**< Crossbar A Select Register 8, offset: 0x10 */
|
|
__IO uint16_t SEL9; /**< Crossbar A Select Register 9, offset: 0x12 */
|
|
__IO uint16_t SEL10; /**< Crossbar A Select Register 10, offset: 0x14 */
|
|
__IO uint16_t SEL11; /**< Crossbar A Select Register 11, offset: 0x16 */
|
|
__IO uint16_t SEL12; /**< Crossbar A Select Register 12, offset: 0x18 */
|
|
__IO uint16_t SEL13; /**< Crossbar A Select Register 13, offset: 0x1A */
|
|
__IO uint16_t SEL14; /**< Crossbar A Select Register 14, offset: 0x1C */
|
|
__IO uint16_t SEL15; /**< Crossbar A Select Register 15, offset: 0x1E */
|
|
__IO uint16_t SEL16; /**< Crossbar A Select Register 16, offset: 0x20 */
|
|
__IO uint16_t SEL17; /**< Crossbar A Select Register 17, offset: 0x22 */
|
|
__IO uint16_t SEL18; /**< Crossbar A Select Register 18, offset: 0x24 */
|
|
__IO uint16_t SEL19; /**< Crossbar A Select Register 19, offset: 0x26 */
|
|
__IO uint16_t SEL20; /**< Crossbar A Select Register 20, offset: 0x28 */
|
|
__IO uint16_t SEL21; /**< Crossbar A Select Register 21, offset: 0x2A */
|
|
__IO uint16_t SEL22; /**< Crossbar A Select Register 22, offset: 0x2C */
|
|
__IO uint16_t SEL23; /**< Crossbar A Select Register 23, offset: 0x2E */
|
|
__IO uint16_t SEL24; /**< Crossbar A Select Register 24, offset: 0x30 */
|
|
__IO uint16_t SEL25; /**< Crossbar A Select Register 25, offset: 0x32 */
|
|
__IO uint16_t SEL26; /**< Crossbar A Select Register 26, offset: 0x34 */
|
|
__IO uint16_t SEL27; /**< Crossbar A Select Register 27, offset: 0x36 */
|
|
__IO uint16_t SEL28; /**< Crossbar A Select Register 28, offset: 0x38 */
|
|
__IO uint16_t SEL29; /**< Crossbar A Select Register 29, offset: 0x3A */
|
|
__IO uint16_t SEL30; /**< Crossbar A Select Register 30, offset: 0x3C */
|
|
__IO uint16_t SEL31; /**< Crossbar A Select Register 31, offset: 0x3E */
|
|
__IO uint16_t SEL32; /**< Crossbar A Select Register 32, offset: 0x40 */
|
|
__IO uint16_t SEL33; /**< Crossbar A Select Register 33, offset: 0x42 */
|
|
__IO uint16_t SEL34; /**< Crossbar A Select Register 34, offset: 0x44 */
|
|
__IO uint16_t SEL35; /**< Crossbar A Select Register 35, offset: 0x46 */
|
|
__IO uint16_t SEL36; /**< Crossbar A Select Register 36, offset: 0x48 */
|
|
__IO uint16_t SEL37; /**< Crossbar A Select Register 37, offset: 0x4A */
|
|
__IO uint16_t SEL38; /**< Crossbar A Select Register 38, offset: 0x4C */
|
|
__IO uint16_t SEL39; /**< Crossbar A Select Register 39, offset: 0x4E */
|
|
__IO uint16_t SEL40; /**< Crossbar A Select Register 40, offset: 0x50 */
|
|
__IO uint16_t SEL41; /**< Crossbar A Select Register 41, offset: 0x52 */
|
|
__IO uint16_t SEL42; /**< Crossbar A Select Register 42, offset: 0x54 */
|
|
__IO uint16_t SEL43; /**< Crossbar A Select Register 43, offset: 0x56 */
|
|
__IO uint16_t SEL44; /**< Crossbar A Select Register 44, offset: 0x58 */
|
|
__IO uint16_t SEL45; /**< Crossbar A Select Register 45, offset: 0x5A */
|
|
__IO uint16_t SEL46; /**< Crossbar A Select Register 46, offset: 0x5C */
|
|
__IO uint16_t SEL47; /**< Crossbar A Select Register 47, offset: 0x5E */
|
|
__IO uint16_t SEL48; /**< Crossbar A Select Register 48, offset: 0x60 */
|
|
__IO uint16_t SEL49; /**< Crossbar A Select Register 49, offset: 0x62 */
|
|
__IO uint16_t SEL50; /**< Crossbar A Select Register 50, offset: 0x64 */
|
|
__IO uint16_t SEL51; /**< Crossbar A Select Register 51, offset: 0x66 */
|
|
__IO uint16_t SEL52; /**< Crossbar A Select Register 52, offset: 0x68 */
|
|
__IO uint16_t SEL53; /**< Crossbar A Select Register 53, offset: 0x6A */
|
|
__IO uint16_t SEL54; /**< Crossbar A Select Register 54, offset: 0x6C */
|
|
__IO uint16_t SEL55; /**< Crossbar A Select Register 55, offset: 0x6E */
|
|
__IO uint16_t SEL56; /**< Crossbar A Select Register 56, offset: 0x70 */
|
|
__IO uint16_t SEL57; /**< Crossbar A Select Register 57, offset: 0x72 */
|
|
__IO uint16_t SEL58; /**< Crossbar A Select Register 58, offset: 0x74 */
|
|
__IO uint16_t SEL59; /**< Crossbar A Select Register 59, offset: 0x76 */
|
|
__IO uint16_t SEL60; /**< Crossbar A Select Register 60, offset: 0x78 */
|
|
__IO uint16_t SEL61; /**< Crossbar A Select Register 61, offset: 0x7A */
|
|
__IO uint16_t SEL62; /**< Crossbar A Select Register 62, offset: 0x7C */
|
|
__IO uint16_t SEL63; /**< Crossbar A Select Register 63, offset: 0x7E */
|
|
__IO uint16_t SEL64; /**< Crossbar A Select Register 64, offset: 0x80 */
|
|
__IO uint16_t SEL65; /**< Crossbar A Select Register 65, offset: 0x82 */
|
|
__IO uint16_t CTRL0; /**< Crossbar A Control Register 0, offset: 0x84 */
|
|
__IO uint16_t CTRL1; /**< Crossbar A Control Register 1, offset: 0x86 */
|
|
} XBARA_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- XBARA Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
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/*!
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* @addtogroup XBARA_Register_Masks XBARA Register Masks
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* @{
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*/
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/*! @name SEL0 - Crossbar A Select Register 0 */
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/*! @{ */
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#define XBARA_SEL0_SEL0_MASK (0x7FU)
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#define XBARA_SEL0_SEL0_SHIFT (0U)
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#define XBARA_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL0_SHIFT)) & XBARA_SEL0_SEL0_MASK)
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#define XBARA_SEL0_SEL1_MASK (0x7F00U)
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#define XBARA_SEL0_SEL1_SHIFT (8U)
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#define XBARA_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL1_SHIFT)) & XBARA_SEL0_SEL1_MASK)
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/*! @} */
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/*! @name SEL1 - Crossbar A Select Register 1 */
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/*! @{ */
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#define XBARA_SEL1_SEL2_MASK (0x7FU)
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#define XBARA_SEL1_SEL2_SHIFT (0U)
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#define XBARA_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL2_SHIFT)) & XBARA_SEL1_SEL2_MASK)
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#define XBARA_SEL1_SEL3_MASK (0x7F00U)
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#define XBARA_SEL1_SEL3_SHIFT (8U)
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#define XBARA_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL3_SHIFT)) & XBARA_SEL1_SEL3_MASK)
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/*! @} */
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/*! @name SEL2 - Crossbar A Select Register 2 */
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/*! @{ */
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#define XBARA_SEL2_SEL4_MASK (0x7FU)
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#define XBARA_SEL2_SEL4_SHIFT (0U)
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#define XBARA_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL4_SHIFT)) & XBARA_SEL2_SEL4_MASK)
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#define XBARA_SEL2_SEL5_MASK (0x7F00U)
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#define XBARA_SEL2_SEL5_SHIFT (8U)
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#define XBARA_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL5_SHIFT)) & XBARA_SEL2_SEL5_MASK)
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/*! @} */
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/*! @name SEL3 - Crossbar A Select Register 3 */
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/*! @{ */
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#define XBARA_SEL3_SEL6_MASK (0x7FU)
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#define XBARA_SEL3_SEL6_SHIFT (0U)
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#define XBARA_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL6_SHIFT)) & XBARA_SEL3_SEL6_MASK)
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#define XBARA_SEL3_SEL7_MASK (0x7F00U)
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#define XBARA_SEL3_SEL7_SHIFT (8U)
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#define XBARA_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL7_SHIFT)) & XBARA_SEL3_SEL7_MASK)
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/*! @} */
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/*! @name SEL4 - Crossbar A Select Register 4 */
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/*! @{ */
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#define XBARA_SEL4_SEL8_MASK (0x7FU)
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#define XBARA_SEL4_SEL8_SHIFT (0U)
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#define XBARA_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL8_SHIFT)) & XBARA_SEL4_SEL8_MASK)
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#define XBARA_SEL4_SEL9_MASK (0x7F00U)
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#define XBARA_SEL4_SEL9_SHIFT (8U)
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#define XBARA_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL9_SHIFT)) & XBARA_SEL4_SEL9_MASK)
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/*! @} */
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/*! @name SEL5 - Crossbar A Select Register 5 */
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/*! @{ */
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#define XBARA_SEL5_SEL10_MASK (0x7FU)
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#define XBARA_SEL5_SEL10_SHIFT (0U)
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#define XBARA_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL10_SHIFT)) & XBARA_SEL5_SEL10_MASK)
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#define XBARA_SEL5_SEL11_MASK (0x7F00U)
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#define XBARA_SEL5_SEL11_SHIFT (8U)
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#define XBARA_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL11_SHIFT)) & XBARA_SEL5_SEL11_MASK)
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/*! @} */
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/*! @name SEL6 - Crossbar A Select Register 6 */
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/*! @{ */
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#define XBARA_SEL6_SEL12_MASK (0x7FU)
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#define XBARA_SEL6_SEL12_SHIFT (0U)
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#define XBARA_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL12_SHIFT)) & XBARA_SEL6_SEL12_MASK)
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#define XBARA_SEL6_SEL13_MASK (0x7F00U)
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#define XBARA_SEL6_SEL13_SHIFT (8U)
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#define XBARA_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL13_SHIFT)) & XBARA_SEL6_SEL13_MASK)
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/*! @} */
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/*! @name SEL7 - Crossbar A Select Register 7 */
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/*! @{ */
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#define XBARA_SEL7_SEL14_MASK (0x7FU)
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#define XBARA_SEL7_SEL14_SHIFT (0U)
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#define XBARA_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL14_SHIFT)) & XBARA_SEL7_SEL14_MASK)
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#define XBARA_SEL7_SEL15_MASK (0x7F00U)
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#define XBARA_SEL7_SEL15_SHIFT (8U)
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#define XBARA_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL15_SHIFT)) & XBARA_SEL7_SEL15_MASK)
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/*! @} */
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/*! @name SEL8 - Crossbar A Select Register 8 */
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/*! @{ */
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#define XBARA_SEL8_SEL16_MASK (0x7FU)
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#define XBARA_SEL8_SEL16_SHIFT (0U)
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#define XBARA_SEL8_SEL16(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL16_SHIFT)) & XBARA_SEL8_SEL16_MASK)
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#define XBARA_SEL8_SEL17_MASK (0x7F00U)
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#define XBARA_SEL8_SEL17_SHIFT (8U)
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#define XBARA_SEL8_SEL17(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL17_SHIFT)) & XBARA_SEL8_SEL17_MASK)
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/*! @} */
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/*! @name SEL9 - Crossbar A Select Register 9 */
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/*! @{ */
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#define XBARA_SEL9_SEL18_MASK (0x7FU)
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#define XBARA_SEL9_SEL18_SHIFT (0U)
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#define XBARA_SEL9_SEL18(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL18_SHIFT)) & XBARA_SEL9_SEL18_MASK)
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#define XBARA_SEL9_SEL19_MASK (0x7F00U)
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#define XBARA_SEL9_SEL19_SHIFT (8U)
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#define XBARA_SEL9_SEL19(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL19_SHIFT)) & XBARA_SEL9_SEL19_MASK)
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/*! @} */
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/*! @name SEL10 - Crossbar A Select Register 10 */
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/*! @{ */
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#define XBARA_SEL10_SEL20_MASK (0x7FU)
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#define XBARA_SEL10_SEL20_SHIFT (0U)
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#define XBARA_SEL10_SEL20(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL20_SHIFT)) & XBARA_SEL10_SEL20_MASK)
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#define XBARA_SEL10_SEL21_MASK (0x7F00U)
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#define XBARA_SEL10_SEL21_SHIFT (8U)
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#define XBARA_SEL10_SEL21(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL21_SHIFT)) & XBARA_SEL10_SEL21_MASK)
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/*! @} */
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/*! @name SEL11 - Crossbar A Select Register 11 */
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/*! @{ */
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#define XBARA_SEL11_SEL22_MASK (0x7FU)
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#define XBARA_SEL11_SEL22_SHIFT (0U)
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#define XBARA_SEL11_SEL22(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL22_SHIFT)) & XBARA_SEL11_SEL22_MASK)
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#define XBARA_SEL11_SEL23_MASK (0x7F00U)
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#define XBARA_SEL11_SEL23_SHIFT (8U)
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#define XBARA_SEL11_SEL23(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL23_SHIFT)) & XBARA_SEL11_SEL23_MASK)
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/*! @} */
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/*! @name SEL12 - Crossbar A Select Register 12 */
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/*! @{ */
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#define XBARA_SEL12_SEL24_MASK (0x7FU)
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#define XBARA_SEL12_SEL24_SHIFT (0U)
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#define XBARA_SEL12_SEL24(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL24_SHIFT)) & XBARA_SEL12_SEL24_MASK)
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#define XBARA_SEL12_SEL25_MASK (0x7F00U)
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#define XBARA_SEL12_SEL25_SHIFT (8U)
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#define XBARA_SEL12_SEL25(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL25_SHIFT)) & XBARA_SEL12_SEL25_MASK)
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/*! @} */
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/*! @name SEL13 - Crossbar A Select Register 13 */
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/*! @{ */
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#define XBARA_SEL13_SEL26_MASK (0x7FU)
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#define XBARA_SEL13_SEL26_SHIFT (0U)
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#define XBARA_SEL13_SEL26(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL26_SHIFT)) & XBARA_SEL13_SEL26_MASK)
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#define XBARA_SEL13_SEL27_MASK (0x7F00U)
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#define XBARA_SEL13_SEL27_SHIFT (8U)
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#define XBARA_SEL13_SEL27(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL27_SHIFT)) & XBARA_SEL13_SEL27_MASK)
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/*! @} */
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/*! @name SEL14 - Crossbar A Select Register 14 */
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/*! @{ */
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#define XBARA_SEL14_SEL28_MASK (0x7FU)
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#define XBARA_SEL14_SEL28_SHIFT (0U)
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#define XBARA_SEL14_SEL28(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL28_SHIFT)) & XBARA_SEL14_SEL28_MASK)
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#define XBARA_SEL14_SEL29_MASK (0x7F00U)
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#define XBARA_SEL14_SEL29_SHIFT (8U)
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#define XBARA_SEL14_SEL29(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL29_SHIFT)) & XBARA_SEL14_SEL29_MASK)
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/*! @} */
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/*! @name SEL15 - Crossbar A Select Register 15 */
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/*! @{ */
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#define XBARA_SEL15_SEL30_MASK (0x7FU)
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#define XBARA_SEL15_SEL30_SHIFT (0U)
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#define XBARA_SEL15_SEL30(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL30_SHIFT)) & XBARA_SEL15_SEL30_MASK)
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#define XBARA_SEL15_SEL31_MASK (0x7F00U)
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#define XBARA_SEL15_SEL31_SHIFT (8U)
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#define XBARA_SEL15_SEL31(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL31_SHIFT)) & XBARA_SEL15_SEL31_MASK)
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/*! @} */
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/*! @name SEL16 - Crossbar A Select Register 16 */
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/*! @{ */
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#define XBARA_SEL16_SEL32_MASK (0x7FU)
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#define XBARA_SEL16_SEL32_SHIFT (0U)
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#define XBARA_SEL16_SEL32(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL32_SHIFT)) & XBARA_SEL16_SEL32_MASK)
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#define XBARA_SEL16_SEL33_MASK (0x7F00U)
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#define XBARA_SEL16_SEL33_SHIFT (8U)
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#define XBARA_SEL16_SEL33(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL33_SHIFT)) & XBARA_SEL16_SEL33_MASK)
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/*! @} */
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/*! @name SEL17 - Crossbar A Select Register 17 */
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/*! @{ */
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#define XBARA_SEL17_SEL34_MASK (0x7FU)
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#define XBARA_SEL17_SEL34_SHIFT (0U)
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#define XBARA_SEL17_SEL34(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL34_SHIFT)) & XBARA_SEL17_SEL34_MASK)
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#define XBARA_SEL17_SEL35_MASK (0x7F00U)
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#define XBARA_SEL17_SEL35_SHIFT (8U)
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#define XBARA_SEL17_SEL35(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL35_SHIFT)) & XBARA_SEL17_SEL35_MASK)
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/*! @} */
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/*! @name SEL18 - Crossbar A Select Register 18 */
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/*! @{ */
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#define XBARA_SEL18_SEL36_MASK (0x7FU)
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#define XBARA_SEL18_SEL36_SHIFT (0U)
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#define XBARA_SEL18_SEL36(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL36_SHIFT)) & XBARA_SEL18_SEL36_MASK)
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#define XBARA_SEL18_SEL37_MASK (0x7F00U)
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#define XBARA_SEL18_SEL37_SHIFT (8U)
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#define XBARA_SEL18_SEL37(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL37_SHIFT)) & XBARA_SEL18_SEL37_MASK)
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/*! @} */
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/*! @name SEL19 - Crossbar A Select Register 19 */
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/*! @{ */
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#define XBARA_SEL19_SEL38_MASK (0x7FU)
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#define XBARA_SEL19_SEL38_SHIFT (0U)
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#define XBARA_SEL19_SEL38(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL38_SHIFT)) & XBARA_SEL19_SEL38_MASK)
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#define XBARA_SEL19_SEL39_MASK (0x7F00U)
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#define XBARA_SEL19_SEL39_SHIFT (8U)
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#define XBARA_SEL19_SEL39(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL39_SHIFT)) & XBARA_SEL19_SEL39_MASK)
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/*! @} */
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/*! @name SEL20 - Crossbar A Select Register 20 */
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/*! @{ */
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#define XBARA_SEL20_SEL40_MASK (0x7FU)
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#define XBARA_SEL20_SEL40_SHIFT (0U)
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#define XBARA_SEL20_SEL40(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL40_SHIFT)) & XBARA_SEL20_SEL40_MASK)
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#define XBARA_SEL20_SEL41_MASK (0x7F00U)
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#define XBARA_SEL20_SEL41_SHIFT (8U)
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#define XBARA_SEL20_SEL41(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL41_SHIFT)) & XBARA_SEL20_SEL41_MASK)
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/*! @} */
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/*! @name SEL21 - Crossbar A Select Register 21 */
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/*! @{ */
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#define XBARA_SEL21_SEL42_MASK (0x7FU)
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#define XBARA_SEL21_SEL42_SHIFT (0U)
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#define XBARA_SEL21_SEL42(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL42_SHIFT)) & XBARA_SEL21_SEL42_MASK)
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#define XBARA_SEL21_SEL43_MASK (0x7F00U)
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#define XBARA_SEL21_SEL43_SHIFT (8U)
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#define XBARA_SEL21_SEL43(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL43_SHIFT)) & XBARA_SEL21_SEL43_MASK)
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/*! @} */
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/*! @name SEL22 - Crossbar A Select Register 22 */
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/*! @{ */
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#define XBARA_SEL22_SEL44_MASK (0x7FU)
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#define XBARA_SEL22_SEL44_SHIFT (0U)
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#define XBARA_SEL22_SEL44(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL44_SHIFT)) & XBARA_SEL22_SEL44_MASK)
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#define XBARA_SEL22_SEL45_MASK (0x7F00U)
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#define XBARA_SEL22_SEL45_SHIFT (8U)
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#define XBARA_SEL22_SEL45(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL45_SHIFT)) & XBARA_SEL22_SEL45_MASK)
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/*! @} */
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/*! @name SEL23 - Crossbar A Select Register 23 */
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/*! @{ */
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#define XBARA_SEL23_SEL46_MASK (0x7FU)
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#define XBARA_SEL23_SEL46_SHIFT (0U)
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#define XBARA_SEL23_SEL46(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL46_SHIFT)) & XBARA_SEL23_SEL46_MASK)
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#define XBARA_SEL23_SEL47_MASK (0x7F00U)
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#define XBARA_SEL23_SEL47_SHIFT (8U)
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#define XBARA_SEL23_SEL47(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL47_SHIFT)) & XBARA_SEL23_SEL47_MASK)
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/*! @} */
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/*! @name SEL24 - Crossbar A Select Register 24 */
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/*! @{ */
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#define XBARA_SEL24_SEL48_MASK (0x7FU)
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#define XBARA_SEL24_SEL48_SHIFT (0U)
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#define XBARA_SEL24_SEL48(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL48_SHIFT)) & XBARA_SEL24_SEL48_MASK)
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#define XBARA_SEL24_SEL49_MASK (0x7F00U)
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#define XBARA_SEL24_SEL49_SHIFT (8U)
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#define XBARA_SEL24_SEL49(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL49_SHIFT)) & XBARA_SEL24_SEL49_MASK)
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/*! @} */
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/*! @name SEL25 - Crossbar A Select Register 25 */
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/*! @{ */
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#define XBARA_SEL25_SEL50_MASK (0x7FU)
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#define XBARA_SEL25_SEL50_SHIFT (0U)
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#define XBARA_SEL25_SEL50(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL50_SHIFT)) & XBARA_SEL25_SEL50_MASK)
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#define XBARA_SEL25_SEL51_MASK (0x7F00U)
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#define XBARA_SEL25_SEL51_SHIFT (8U)
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#define XBARA_SEL25_SEL51(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL51_SHIFT)) & XBARA_SEL25_SEL51_MASK)
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/*! @} */
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/*! @name SEL26 - Crossbar A Select Register 26 */
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/*! @{ */
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#define XBARA_SEL26_SEL52_MASK (0x7FU)
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#define XBARA_SEL26_SEL52_SHIFT (0U)
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#define XBARA_SEL26_SEL52(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL52_SHIFT)) & XBARA_SEL26_SEL52_MASK)
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#define XBARA_SEL26_SEL53_MASK (0x7F00U)
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#define XBARA_SEL26_SEL53_SHIFT (8U)
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#define XBARA_SEL26_SEL53(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL53_SHIFT)) & XBARA_SEL26_SEL53_MASK)
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/*! @} */
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/*! @name SEL27 - Crossbar A Select Register 27 */
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/*! @{ */
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#define XBARA_SEL27_SEL54_MASK (0x7FU)
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#define XBARA_SEL27_SEL54_SHIFT (0U)
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#define XBARA_SEL27_SEL54(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL54_SHIFT)) & XBARA_SEL27_SEL54_MASK)
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#define XBARA_SEL27_SEL55_MASK (0x7F00U)
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#define XBARA_SEL27_SEL55_SHIFT (8U)
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#define XBARA_SEL27_SEL55(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL55_SHIFT)) & XBARA_SEL27_SEL55_MASK)
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/*! @} */
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/*! @name SEL28 - Crossbar A Select Register 28 */
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/*! @{ */
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#define XBARA_SEL28_SEL56_MASK (0x7FU)
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#define XBARA_SEL28_SEL56_SHIFT (0U)
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#define XBARA_SEL28_SEL56(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL56_SHIFT)) & XBARA_SEL28_SEL56_MASK)
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#define XBARA_SEL28_SEL57_MASK (0x7F00U)
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#define XBARA_SEL28_SEL57_SHIFT (8U)
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#define XBARA_SEL28_SEL57(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL57_SHIFT)) & XBARA_SEL28_SEL57_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL29 - Crossbar A Select Register 29 */
|
|
/*! @{ */
|
|
#define XBARA_SEL29_SEL58_MASK (0x7FU)
|
|
#define XBARA_SEL29_SEL58_SHIFT (0U)
|
|
#define XBARA_SEL29_SEL58(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL58_SHIFT)) & XBARA_SEL29_SEL58_MASK)
|
|
#define XBARA_SEL29_SEL59_MASK (0x7F00U)
|
|
#define XBARA_SEL29_SEL59_SHIFT (8U)
|
|
#define XBARA_SEL29_SEL59(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL59_SHIFT)) & XBARA_SEL29_SEL59_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL30 - Crossbar A Select Register 30 */
|
|
/*! @{ */
|
|
#define XBARA_SEL30_SEL60_MASK (0x7FU)
|
|
#define XBARA_SEL30_SEL60_SHIFT (0U)
|
|
#define XBARA_SEL30_SEL60(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL60_SHIFT)) & XBARA_SEL30_SEL60_MASK)
|
|
#define XBARA_SEL30_SEL61_MASK (0x7F00U)
|
|
#define XBARA_SEL30_SEL61_SHIFT (8U)
|
|
#define XBARA_SEL30_SEL61(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL61_SHIFT)) & XBARA_SEL30_SEL61_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL31 - Crossbar A Select Register 31 */
|
|
/*! @{ */
|
|
#define XBARA_SEL31_SEL62_MASK (0x7FU)
|
|
#define XBARA_SEL31_SEL62_SHIFT (0U)
|
|
#define XBARA_SEL31_SEL62(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL62_SHIFT)) & XBARA_SEL31_SEL62_MASK)
|
|
#define XBARA_SEL31_SEL63_MASK (0x7F00U)
|
|
#define XBARA_SEL31_SEL63_SHIFT (8U)
|
|
#define XBARA_SEL31_SEL63(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL63_SHIFT)) & XBARA_SEL31_SEL63_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL32 - Crossbar A Select Register 32 */
|
|
/*! @{ */
|
|
#define XBARA_SEL32_SEL64_MASK (0x7FU)
|
|
#define XBARA_SEL32_SEL64_SHIFT (0U)
|
|
#define XBARA_SEL32_SEL64(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL64_SHIFT)) & XBARA_SEL32_SEL64_MASK)
|
|
#define XBARA_SEL32_SEL65_MASK (0x7F00U)
|
|
#define XBARA_SEL32_SEL65_SHIFT (8U)
|
|
#define XBARA_SEL32_SEL65(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL65_SHIFT)) & XBARA_SEL32_SEL65_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL33 - Crossbar A Select Register 33 */
|
|
/*! @{ */
|
|
#define XBARA_SEL33_SEL66_MASK (0x7FU)
|
|
#define XBARA_SEL33_SEL66_SHIFT (0U)
|
|
#define XBARA_SEL33_SEL66(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL66_SHIFT)) & XBARA_SEL33_SEL66_MASK)
|
|
#define XBARA_SEL33_SEL67_MASK (0x7F00U)
|
|
#define XBARA_SEL33_SEL67_SHIFT (8U)
|
|
#define XBARA_SEL33_SEL67(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL67_SHIFT)) & XBARA_SEL33_SEL67_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL34 - Crossbar A Select Register 34 */
|
|
/*! @{ */
|
|
#define XBARA_SEL34_SEL68_MASK (0x7FU)
|
|
#define XBARA_SEL34_SEL68_SHIFT (0U)
|
|
#define XBARA_SEL34_SEL68(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL68_SHIFT)) & XBARA_SEL34_SEL68_MASK)
|
|
#define XBARA_SEL34_SEL69_MASK (0x7F00U)
|
|
#define XBARA_SEL34_SEL69_SHIFT (8U)
|
|
#define XBARA_SEL34_SEL69(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL69_SHIFT)) & XBARA_SEL34_SEL69_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL35 - Crossbar A Select Register 35 */
|
|
/*! @{ */
|
|
#define XBARA_SEL35_SEL70_MASK (0x7FU)
|
|
#define XBARA_SEL35_SEL70_SHIFT (0U)
|
|
#define XBARA_SEL35_SEL70(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL70_SHIFT)) & XBARA_SEL35_SEL70_MASK)
|
|
#define XBARA_SEL35_SEL71_MASK (0x7F00U)
|
|
#define XBARA_SEL35_SEL71_SHIFT (8U)
|
|
#define XBARA_SEL35_SEL71(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL71_SHIFT)) & XBARA_SEL35_SEL71_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL36 - Crossbar A Select Register 36 */
|
|
/*! @{ */
|
|
#define XBARA_SEL36_SEL72_MASK (0x7FU)
|
|
#define XBARA_SEL36_SEL72_SHIFT (0U)
|
|
#define XBARA_SEL36_SEL72(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL72_SHIFT)) & XBARA_SEL36_SEL72_MASK)
|
|
#define XBARA_SEL36_SEL73_MASK (0x7F00U)
|
|
#define XBARA_SEL36_SEL73_SHIFT (8U)
|
|
#define XBARA_SEL36_SEL73(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL73_SHIFT)) & XBARA_SEL36_SEL73_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL37 - Crossbar A Select Register 37 */
|
|
/*! @{ */
|
|
#define XBARA_SEL37_SEL74_MASK (0x7FU)
|
|
#define XBARA_SEL37_SEL74_SHIFT (0U)
|
|
#define XBARA_SEL37_SEL74(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL74_SHIFT)) & XBARA_SEL37_SEL74_MASK)
|
|
#define XBARA_SEL37_SEL75_MASK (0x7F00U)
|
|
#define XBARA_SEL37_SEL75_SHIFT (8U)
|
|
#define XBARA_SEL37_SEL75(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL75_SHIFT)) & XBARA_SEL37_SEL75_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL38 - Crossbar A Select Register 38 */
|
|
/*! @{ */
|
|
#define XBARA_SEL38_SEL76_MASK (0x7FU)
|
|
#define XBARA_SEL38_SEL76_SHIFT (0U)
|
|
#define XBARA_SEL38_SEL76(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL76_SHIFT)) & XBARA_SEL38_SEL76_MASK)
|
|
#define XBARA_SEL38_SEL77_MASK (0x7F00U)
|
|
#define XBARA_SEL38_SEL77_SHIFT (8U)
|
|
#define XBARA_SEL38_SEL77(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL77_SHIFT)) & XBARA_SEL38_SEL77_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL39 - Crossbar A Select Register 39 */
|
|
/*! @{ */
|
|
#define XBARA_SEL39_SEL78_MASK (0x7FU)
|
|
#define XBARA_SEL39_SEL78_SHIFT (0U)
|
|
#define XBARA_SEL39_SEL78(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL78_SHIFT)) & XBARA_SEL39_SEL78_MASK)
|
|
#define XBARA_SEL39_SEL79_MASK (0x7F00U)
|
|
#define XBARA_SEL39_SEL79_SHIFT (8U)
|
|
#define XBARA_SEL39_SEL79(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL79_SHIFT)) & XBARA_SEL39_SEL79_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL40 - Crossbar A Select Register 40 */
|
|
/*! @{ */
|
|
#define XBARA_SEL40_SEL80_MASK (0x7FU)
|
|
#define XBARA_SEL40_SEL80_SHIFT (0U)
|
|
#define XBARA_SEL40_SEL80(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL80_SHIFT)) & XBARA_SEL40_SEL80_MASK)
|
|
#define XBARA_SEL40_SEL81_MASK (0x7F00U)
|
|
#define XBARA_SEL40_SEL81_SHIFT (8U)
|
|
#define XBARA_SEL40_SEL81(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL81_SHIFT)) & XBARA_SEL40_SEL81_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL41 - Crossbar A Select Register 41 */
|
|
/*! @{ */
|
|
#define XBARA_SEL41_SEL82_MASK (0x7FU)
|
|
#define XBARA_SEL41_SEL82_SHIFT (0U)
|
|
#define XBARA_SEL41_SEL82(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL82_SHIFT)) & XBARA_SEL41_SEL82_MASK)
|
|
#define XBARA_SEL41_SEL83_MASK (0x7F00U)
|
|
#define XBARA_SEL41_SEL83_SHIFT (8U)
|
|
#define XBARA_SEL41_SEL83(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL83_SHIFT)) & XBARA_SEL41_SEL83_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL42 - Crossbar A Select Register 42 */
|
|
/*! @{ */
|
|
#define XBARA_SEL42_SEL84_MASK (0x7FU)
|
|
#define XBARA_SEL42_SEL84_SHIFT (0U)
|
|
#define XBARA_SEL42_SEL84(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL84_SHIFT)) & XBARA_SEL42_SEL84_MASK)
|
|
#define XBARA_SEL42_SEL85_MASK (0x7F00U)
|
|
#define XBARA_SEL42_SEL85_SHIFT (8U)
|
|
#define XBARA_SEL42_SEL85(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL85_SHIFT)) & XBARA_SEL42_SEL85_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL43 - Crossbar A Select Register 43 */
|
|
/*! @{ */
|
|
#define XBARA_SEL43_SEL86_MASK (0x7FU)
|
|
#define XBARA_SEL43_SEL86_SHIFT (0U)
|
|
#define XBARA_SEL43_SEL86(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL86_SHIFT)) & XBARA_SEL43_SEL86_MASK)
|
|
#define XBARA_SEL43_SEL87_MASK (0x7F00U)
|
|
#define XBARA_SEL43_SEL87_SHIFT (8U)
|
|
#define XBARA_SEL43_SEL87(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL87_SHIFT)) & XBARA_SEL43_SEL87_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL44 - Crossbar A Select Register 44 */
|
|
/*! @{ */
|
|
#define XBARA_SEL44_SEL88_MASK (0x7FU)
|
|
#define XBARA_SEL44_SEL88_SHIFT (0U)
|
|
#define XBARA_SEL44_SEL88(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL88_SHIFT)) & XBARA_SEL44_SEL88_MASK)
|
|
#define XBARA_SEL44_SEL89_MASK (0x7F00U)
|
|
#define XBARA_SEL44_SEL89_SHIFT (8U)
|
|
#define XBARA_SEL44_SEL89(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL89_SHIFT)) & XBARA_SEL44_SEL89_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL45 - Crossbar A Select Register 45 */
|
|
/*! @{ */
|
|
#define XBARA_SEL45_SEL90_MASK (0x7FU)
|
|
#define XBARA_SEL45_SEL90_SHIFT (0U)
|
|
#define XBARA_SEL45_SEL90(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL90_SHIFT)) & XBARA_SEL45_SEL90_MASK)
|
|
#define XBARA_SEL45_SEL91_MASK (0x7F00U)
|
|
#define XBARA_SEL45_SEL91_SHIFT (8U)
|
|
#define XBARA_SEL45_SEL91(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL91_SHIFT)) & XBARA_SEL45_SEL91_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL46 - Crossbar A Select Register 46 */
|
|
/*! @{ */
|
|
#define XBARA_SEL46_SEL92_MASK (0x7FU)
|
|
#define XBARA_SEL46_SEL92_SHIFT (0U)
|
|
#define XBARA_SEL46_SEL92(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL92_SHIFT)) & XBARA_SEL46_SEL92_MASK)
|
|
#define XBARA_SEL46_SEL93_MASK (0x7F00U)
|
|
#define XBARA_SEL46_SEL93_SHIFT (8U)
|
|
#define XBARA_SEL46_SEL93(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL93_SHIFT)) & XBARA_SEL46_SEL93_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL47 - Crossbar A Select Register 47 */
|
|
/*! @{ */
|
|
#define XBARA_SEL47_SEL94_MASK (0x7FU)
|
|
#define XBARA_SEL47_SEL94_SHIFT (0U)
|
|
#define XBARA_SEL47_SEL94(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL94_SHIFT)) & XBARA_SEL47_SEL94_MASK)
|
|
#define XBARA_SEL47_SEL95_MASK (0x7F00U)
|
|
#define XBARA_SEL47_SEL95_SHIFT (8U)
|
|
#define XBARA_SEL47_SEL95(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL95_SHIFT)) & XBARA_SEL47_SEL95_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL48 - Crossbar A Select Register 48 */
|
|
/*! @{ */
|
|
#define XBARA_SEL48_SEL96_MASK (0x7FU)
|
|
#define XBARA_SEL48_SEL96_SHIFT (0U)
|
|
#define XBARA_SEL48_SEL96(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL96_SHIFT)) & XBARA_SEL48_SEL96_MASK)
|
|
#define XBARA_SEL48_SEL97_MASK (0x7F00U)
|
|
#define XBARA_SEL48_SEL97_SHIFT (8U)
|
|
#define XBARA_SEL48_SEL97(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL97_SHIFT)) & XBARA_SEL48_SEL97_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL49 - Crossbar A Select Register 49 */
|
|
/*! @{ */
|
|
#define XBARA_SEL49_SEL98_MASK (0x7FU)
|
|
#define XBARA_SEL49_SEL98_SHIFT (0U)
|
|
#define XBARA_SEL49_SEL98(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL98_SHIFT)) & XBARA_SEL49_SEL98_MASK)
|
|
#define XBARA_SEL49_SEL99_MASK (0x7F00U)
|
|
#define XBARA_SEL49_SEL99_SHIFT (8U)
|
|
#define XBARA_SEL49_SEL99(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL99_SHIFT)) & XBARA_SEL49_SEL99_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL50 - Crossbar A Select Register 50 */
|
|
/*! @{ */
|
|
#define XBARA_SEL50_SEL100_MASK (0x7FU)
|
|
#define XBARA_SEL50_SEL100_SHIFT (0U)
|
|
#define XBARA_SEL50_SEL100(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL100_SHIFT)) & XBARA_SEL50_SEL100_MASK)
|
|
#define XBARA_SEL50_SEL101_MASK (0x7F00U)
|
|
#define XBARA_SEL50_SEL101_SHIFT (8U)
|
|
#define XBARA_SEL50_SEL101(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL101_SHIFT)) & XBARA_SEL50_SEL101_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL51 - Crossbar A Select Register 51 */
|
|
/*! @{ */
|
|
#define XBARA_SEL51_SEL102_MASK (0x7FU)
|
|
#define XBARA_SEL51_SEL102_SHIFT (0U)
|
|
#define XBARA_SEL51_SEL102(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL102_SHIFT)) & XBARA_SEL51_SEL102_MASK)
|
|
#define XBARA_SEL51_SEL103_MASK (0x7F00U)
|
|
#define XBARA_SEL51_SEL103_SHIFT (8U)
|
|
#define XBARA_SEL51_SEL103(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL103_SHIFT)) & XBARA_SEL51_SEL103_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL52 - Crossbar A Select Register 52 */
|
|
/*! @{ */
|
|
#define XBARA_SEL52_SEL104_MASK (0x7FU)
|
|
#define XBARA_SEL52_SEL104_SHIFT (0U)
|
|
#define XBARA_SEL52_SEL104(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL104_SHIFT)) & XBARA_SEL52_SEL104_MASK)
|
|
#define XBARA_SEL52_SEL105_MASK (0x7F00U)
|
|
#define XBARA_SEL52_SEL105_SHIFT (8U)
|
|
#define XBARA_SEL52_SEL105(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL105_SHIFT)) & XBARA_SEL52_SEL105_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL53 - Crossbar A Select Register 53 */
|
|
/*! @{ */
|
|
#define XBARA_SEL53_SEL106_MASK (0x7FU)
|
|
#define XBARA_SEL53_SEL106_SHIFT (0U)
|
|
#define XBARA_SEL53_SEL106(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL106_SHIFT)) & XBARA_SEL53_SEL106_MASK)
|
|
#define XBARA_SEL53_SEL107_MASK (0x7F00U)
|
|
#define XBARA_SEL53_SEL107_SHIFT (8U)
|
|
#define XBARA_SEL53_SEL107(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL107_SHIFT)) & XBARA_SEL53_SEL107_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL54 - Crossbar A Select Register 54 */
|
|
/*! @{ */
|
|
#define XBARA_SEL54_SEL108_MASK (0x7FU)
|
|
#define XBARA_SEL54_SEL108_SHIFT (0U)
|
|
#define XBARA_SEL54_SEL108(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL108_SHIFT)) & XBARA_SEL54_SEL108_MASK)
|
|
#define XBARA_SEL54_SEL109_MASK (0x7F00U)
|
|
#define XBARA_SEL54_SEL109_SHIFT (8U)
|
|
#define XBARA_SEL54_SEL109(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL109_SHIFT)) & XBARA_SEL54_SEL109_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL55 - Crossbar A Select Register 55 */
|
|
/*! @{ */
|
|
#define XBARA_SEL55_SEL110_MASK (0x7FU)
|
|
#define XBARA_SEL55_SEL110_SHIFT (0U)
|
|
#define XBARA_SEL55_SEL110(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL110_SHIFT)) & XBARA_SEL55_SEL110_MASK)
|
|
#define XBARA_SEL55_SEL111_MASK (0x7F00U)
|
|
#define XBARA_SEL55_SEL111_SHIFT (8U)
|
|
#define XBARA_SEL55_SEL111(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL111_SHIFT)) & XBARA_SEL55_SEL111_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL56 - Crossbar A Select Register 56 */
|
|
/*! @{ */
|
|
#define XBARA_SEL56_SEL112_MASK (0x7FU)
|
|
#define XBARA_SEL56_SEL112_SHIFT (0U)
|
|
#define XBARA_SEL56_SEL112(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL112_SHIFT)) & XBARA_SEL56_SEL112_MASK)
|
|
#define XBARA_SEL56_SEL113_MASK (0x7F00U)
|
|
#define XBARA_SEL56_SEL113_SHIFT (8U)
|
|
#define XBARA_SEL56_SEL113(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL113_SHIFT)) & XBARA_SEL56_SEL113_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL57 - Crossbar A Select Register 57 */
|
|
/*! @{ */
|
|
#define XBARA_SEL57_SEL114_MASK (0x7FU)
|
|
#define XBARA_SEL57_SEL114_SHIFT (0U)
|
|
#define XBARA_SEL57_SEL114(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL114_SHIFT)) & XBARA_SEL57_SEL114_MASK)
|
|
#define XBARA_SEL57_SEL115_MASK (0x7F00U)
|
|
#define XBARA_SEL57_SEL115_SHIFT (8U)
|
|
#define XBARA_SEL57_SEL115(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL115_SHIFT)) & XBARA_SEL57_SEL115_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL58 - Crossbar A Select Register 58 */
|
|
/*! @{ */
|
|
#define XBARA_SEL58_SEL116_MASK (0x7FU)
|
|
#define XBARA_SEL58_SEL116_SHIFT (0U)
|
|
#define XBARA_SEL58_SEL116(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL116_SHIFT)) & XBARA_SEL58_SEL116_MASK)
|
|
#define XBARA_SEL58_SEL117_MASK (0x7F00U)
|
|
#define XBARA_SEL58_SEL117_SHIFT (8U)
|
|
#define XBARA_SEL58_SEL117(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL117_SHIFT)) & XBARA_SEL58_SEL117_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL59 - Crossbar A Select Register 59 */
|
|
/*! @{ */
|
|
#define XBARA_SEL59_SEL118_MASK (0x7FU)
|
|
#define XBARA_SEL59_SEL118_SHIFT (0U)
|
|
#define XBARA_SEL59_SEL118(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL118_SHIFT)) & XBARA_SEL59_SEL118_MASK)
|
|
#define XBARA_SEL59_SEL119_MASK (0x7F00U)
|
|
#define XBARA_SEL59_SEL119_SHIFT (8U)
|
|
#define XBARA_SEL59_SEL119(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL119_SHIFT)) & XBARA_SEL59_SEL119_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL60 - Crossbar A Select Register 60 */
|
|
/*! @{ */
|
|
#define XBARA_SEL60_SEL120_MASK (0x7FU)
|
|
#define XBARA_SEL60_SEL120_SHIFT (0U)
|
|
#define XBARA_SEL60_SEL120(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL120_SHIFT)) & XBARA_SEL60_SEL120_MASK)
|
|
#define XBARA_SEL60_SEL121_MASK (0x7F00U)
|
|
#define XBARA_SEL60_SEL121_SHIFT (8U)
|
|
#define XBARA_SEL60_SEL121(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL121_SHIFT)) & XBARA_SEL60_SEL121_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL61 - Crossbar A Select Register 61 */
|
|
/*! @{ */
|
|
#define XBARA_SEL61_SEL122_MASK (0x7FU)
|
|
#define XBARA_SEL61_SEL122_SHIFT (0U)
|
|
#define XBARA_SEL61_SEL122(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL122_SHIFT)) & XBARA_SEL61_SEL122_MASK)
|
|
#define XBARA_SEL61_SEL123_MASK (0x7F00U)
|
|
#define XBARA_SEL61_SEL123_SHIFT (8U)
|
|
#define XBARA_SEL61_SEL123(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL123_SHIFT)) & XBARA_SEL61_SEL123_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL62 - Crossbar A Select Register 62 */
|
|
/*! @{ */
|
|
#define XBARA_SEL62_SEL124_MASK (0x7FU)
|
|
#define XBARA_SEL62_SEL124_SHIFT (0U)
|
|
#define XBARA_SEL62_SEL124(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL124_SHIFT)) & XBARA_SEL62_SEL124_MASK)
|
|
#define XBARA_SEL62_SEL125_MASK (0x7F00U)
|
|
#define XBARA_SEL62_SEL125_SHIFT (8U)
|
|
#define XBARA_SEL62_SEL125(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL125_SHIFT)) & XBARA_SEL62_SEL125_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL63 - Crossbar A Select Register 63 */
|
|
/*! @{ */
|
|
#define XBARA_SEL63_SEL126_MASK (0x7FU)
|
|
#define XBARA_SEL63_SEL126_SHIFT (0U)
|
|
#define XBARA_SEL63_SEL126(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL126_SHIFT)) & XBARA_SEL63_SEL126_MASK)
|
|
#define XBARA_SEL63_SEL127_MASK (0x7F00U)
|
|
#define XBARA_SEL63_SEL127_SHIFT (8U)
|
|
#define XBARA_SEL63_SEL127(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL127_SHIFT)) & XBARA_SEL63_SEL127_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL64 - Crossbar A Select Register 64 */
|
|
/*! @{ */
|
|
#define XBARA_SEL64_SEL128_MASK (0x7FU)
|
|
#define XBARA_SEL64_SEL128_SHIFT (0U)
|
|
#define XBARA_SEL64_SEL128(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL128_SHIFT)) & XBARA_SEL64_SEL128_MASK)
|
|
#define XBARA_SEL64_SEL129_MASK (0x7F00U)
|
|
#define XBARA_SEL64_SEL129_SHIFT (8U)
|
|
#define XBARA_SEL64_SEL129(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL129_SHIFT)) & XBARA_SEL64_SEL129_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL65 - Crossbar A Select Register 65 */
|
|
/*! @{ */
|
|
#define XBARA_SEL65_SEL130_MASK (0x7FU)
|
|
#define XBARA_SEL65_SEL130_SHIFT (0U)
|
|
#define XBARA_SEL65_SEL130(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL130_SHIFT)) & XBARA_SEL65_SEL130_MASK)
|
|
#define XBARA_SEL65_SEL131_MASK (0x7F00U)
|
|
#define XBARA_SEL65_SEL131_SHIFT (8U)
|
|
#define XBARA_SEL65_SEL131(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL131_SHIFT)) & XBARA_SEL65_SEL131_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CTRL0 - Crossbar A Control Register 0 */
|
|
/*! @{ */
|
|
#define XBARA_CTRL0_DEN0_MASK (0x1U)
|
|
#define XBARA_CTRL0_DEN0_SHIFT (0U)
|
|
/*! DEN0 - DMA Enable for XBAR_OUT0
|
|
* 0b0..DMA disabled
|
|
* 0b1..DMA enabled
|
|
*/
|
|
#define XBARA_CTRL0_DEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN0_SHIFT)) & XBARA_CTRL0_DEN0_MASK)
|
|
#define XBARA_CTRL0_IEN0_MASK (0x2U)
|
|
#define XBARA_CTRL0_IEN0_SHIFT (1U)
|
|
/*! IEN0 - Interrupt Enable for XBAR_OUT0
|
|
* 0b0..Interrupt disabled
|
|
* 0b1..Interrupt enabled
|
|
*/
|
|
#define XBARA_CTRL0_IEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN0_SHIFT)) & XBARA_CTRL0_IEN0_MASK)
|
|
#define XBARA_CTRL0_EDGE0_MASK (0xCU)
|
|
#define XBARA_CTRL0_EDGE0_SHIFT (2U)
|
|
/*! EDGE0 - Active edge for edge detection on XBAR_OUT0
|
|
* 0b00..STS0 never asserts
|
|
* 0b01..STS0 asserts on rising edges of XBAR_OUT0
|
|
* 0b10..STS0 asserts on falling edges of XBAR_OUT0
|
|
* 0b11..STS0 asserts on rising and falling edges of XBAR_OUT0
|
|
*/
|
|
#define XBARA_CTRL0_EDGE0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE0_SHIFT)) & XBARA_CTRL0_EDGE0_MASK)
|
|
#define XBARA_CTRL0_STS0_MASK (0x10U)
|
|
#define XBARA_CTRL0_STS0_SHIFT (4U)
|
|
/*! STS0 - Edge detection status for XBAR_OUT0
|
|
* 0b0..Active edge not yet detected on XBAR_OUT0
|
|
* 0b1..Active edge detected on XBAR_OUT0
|
|
*/
|
|
#define XBARA_CTRL0_STS0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS0_SHIFT)) & XBARA_CTRL0_STS0_MASK)
|
|
#define XBARA_CTRL0_DEN1_MASK (0x100U)
|
|
#define XBARA_CTRL0_DEN1_SHIFT (8U)
|
|
/*! DEN1 - DMA Enable for XBAR_OUT1
|
|
* 0b0..DMA disabled
|
|
* 0b1..DMA enabled
|
|
*/
|
|
#define XBARA_CTRL0_DEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN1_SHIFT)) & XBARA_CTRL0_DEN1_MASK)
|
|
#define XBARA_CTRL0_IEN1_MASK (0x200U)
|
|
#define XBARA_CTRL0_IEN1_SHIFT (9U)
|
|
/*! IEN1 - Interrupt Enable for XBAR_OUT1
|
|
* 0b0..Interrupt disabled
|
|
* 0b1..Interrupt enabled
|
|
*/
|
|
#define XBARA_CTRL0_IEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN1_SHIFT)) & XBARA_CTRL0_IEN1_MASK)
|
|
#define XBARA_CTRL0_EDGE1_MASK (0xC00U)
|
|
#define XBARA_CTRL0_EDGE1_SHIFT (10U)
|
|
/*! EDGE1 - Active edge for edge detection on XBAR_OUT1
|
|
* 0b00..STS1 never asserts
|
|
* 0b01..STS1 asserts on rising edges of XBAR_OUT1
|
|
* 0b10..STS1 asserts on falling edges of XBAR_OUT1
|
|
* 0b11..STS1 asserts on rising and falling edges of XBAR_OUT1
|
|
*/
|
|
#define XBARA_CTRL0_EDGE1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE1_SHIFT)) & XBARA_CTRL0_EDGE1_MASK)
|
|
#define XBARA_CTRL0_STS1_MASK (0x1000U)
|
|
#define XBARA_CTRL0_STS1_SHIFT (12U)
|
|
/*! STS1 - Edge detection status for XBAR_OUT1
|
|
* 0b0..Active edge not yet detected on XBAR_OUT1
|
|
* 0b1..Active edge detected on XBAR_OUT1
|
|
*/
|
|
#define XBARA_CTRL0_STS1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS1_SHIFT)) & XBARA_CTRL0_STS1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name CTRL1 - Crossbar A Control Register 1 */
|
|
/*! @{ */
|
|
#define XBARA_CTRL1_DEN2_MASK (0x1U)
|
|
#define XBARA_CTRL1_DEN2_SHIFT (0U)
|
|
/*! DEN2 - DMA Enable for XBAR_OUT2
|
|
* 0b0..DMA disabled
|
|
* 0b1..DMA enabled
|
|
*/
|
|
#define XBARA_CTRL1_DEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN2_SHIFT)) & XBARA_CTRL1_DEN2_MASK)
|
|
#define XBARA_CTRL1_IEN2_MASK (0x2U)
|
|
#define XBARA_CTRL1_IEN2_SHIFT (1U)
|
|
/*! IEN2 - Interrupt Enable for XBAR_OUT2
|
|
* 0b0..Interrupt disabled
|
|
* 0b1..Interrupt enabled
|
|
*/
|
|
#define XBARA_CTRL1_IEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN2_SHIFT)) & XBARA_CTRL1_IEN2_MASK)
|
|
#define XBARA_CTRL1_EDGE2_MASK (0xCU)
|
|
#define XBARA_CTRL1_EDGE2_SHIFT (2U)
|
|
/*! EDGE2 - Active edge for edge detection on XBAR_OUT2
|
|
* 0b00..STS2 never asserts
|
|
* 0b01..STS2 asserts on rising edges of XBAR_OUT2
|
|
* 0b10..STS2 asserts on falling edges of XBAR_OUT2
|
|
* 0b11..STS2 asserts on rising and falling edges of XBAR_OUT2
|
|
*/
|
|
#define XBARA_CTRL1_EDGE2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE2_SHIFT)) & XBARA_CTRL1_EDGE2_MASK)
|
|
#define XBARA_CTRL1_STS2_MASK (0x10U)
|
|
#define XBARA_CTRL1_STS2_SHIFT (4U)
|
|
/*! STS2 - Edge detection status for XBAR_OUT2
|
|
* 0b0..Active edge not yet detected on XBAR_OUT2
|
|
* 0b1..Active edge detected on XBAR_OUT2
|
|
*/
|
|
#define XBARA_CTRL1_STS2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS2_SHIFT)) & XBARA_CTRL1_STS2_MASK)
|
|
#define XBARA_CTRL1_DEN3_MASK (0x100U)
|
|
#define XBARA_CTRL1_DEN3_SHIFT (8U)
|
|
/*! DEN3 - DMA Enable for XBAR_OUT3
|
|
* 0b0..DMA disabled
|
|
* 0b1..DMA enabled
|
|
*/
|
|
#define XBARA_CTRL1_DEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN3_SHIFT)) & XBARA_CTRL1_DEN3_MASK)
|
|
#define XBARA_CTRL1_IEN3_MASK (0x200U)
|
|
#define XBARA_CTRL1_IEN3_SHIFT (9U)
|
|
/*! IEN3 - Interrupt Enable for XBAR_OUT3
|
|
* 0b0..Interrupt disabled
|
|
* 0b1..Interrupt enabled
|
|
*/
|
|
#define XBARA_CTRL1_IEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN3_SHIFT)) & XBARA_CTRL1_IEN3_MASK)
|
|
#define XBARA_CTRL1_EDGE3_MASK (0xC00U)
|
|
#define XBARA_CTRL1_EDGE3_SHIFT (10U)
|
|
/*! EDGE3 - Active edge for edge detection on XBAR_OUT3
|
|
* 0b00..STS3 never asserts
|
|
* 0b01..STS3 asserts on rising edges of XBAR_OUT3
|
|
* 0b10..STS3 asserts on falling edges of XBAR_OUT3
|
|
* 0b11..STS3 asserts on rising and falling edges of XBAR_OUT3
|
|
*/
|
|
#define XBARA_CTRL1_EDGE3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE3_SHIFT)) & XBARA_CTRL1_EDGE3_MASK)
|
|
#define XBARA_CTRL1_STS3_MASK (0x1000U)
|
|
#define XBARA_CTRL1_STS3_SHIFT (12U)
|
|
/*! STS3 - Edge detection status for XBAR_OUT3
|
|
* 0b0..Active edge not yet detected on XBAR_OUT3
|
|
* 0b1..Active edge detected on XBAR_OUT3
|
|
*/
|
|
#define XBARA_CTRL1_STS3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS3_SHIFT)) & XBARA_CTRL1_STS3_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group XBARA_Register_Masks */
|
|
|
|
|
|
/* XBARA - Peripheral instance base addresses */
|
|
/** Peripheral XBARA1 base address */
|
|
#define XBARA1_BASE (0x403BC000u)
|
|
/** Peripheral XBARA1 base pointer */
|
|
#define XBARA1 ((XBARA_Type *)XBARA1_BASE)
|
|
/** Array initializer of XBARA peripheral base addresses */
|
|
#define XBARA_BASE_ADDRS { XBARA1_BASE }
|
|
/** Array initializer of XBARA peripheral base pointers */
|
|
#define XBARA_BASE_PTRS { XBARA1 }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group XBARA_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- XBARB Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup XBARB_Peripheral_Access_Layer XBARB Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** XBARB - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint16_t SEL0; /**< Crossbar B Select Register 0, offset: 0x0 */
|
|
__IO uint16_t SEL1; /**< Crossbar B Select Register 1, offset: 0x2 */
|
|
__IO uint16_t SEL2; /**< Crossbar B Select Register 2, offset: 0x4 */
|
|
__IO uint16_t SEL3; /**< Crossbar B Select Register 3, offset: 0x6 */
|
|
__IO uint16_t SEL4; /**< Crossbar B Select Register 4, offset: 0x8 */
|
|
__IO uint16_t SEL5; /**< Crossbar B Select Register 5, offset: 0xA */
|
|
__IO uint16_t SEL6; /**< Crossbar B Select Register 6, offset: 0xC */
|
|
__IO uint16_t SEL7; /**< Crossbar B Select Register 7, offset: 0xE */
|
|
} XBARB_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- XBARB Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup XBARB_Register_Masks XBARB Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name SEL0 - Crossbar B Select Register 0 */
|
|
/*! @{ */
|
|
#define XBARB_SEL0_SEL0_MASK (0x3FU)
|
|
#define XBARB_SEL0_SEL0_SHIFT (0U)
|
|
#define XBARB_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL0_SHIFT)) & XBARB_SEL0_SEL0_MASK)
|
|
#define XBARB_SEL0_SEL1_MASK (0x3F00U)
|
|
#define XBARB_SEL0_SEL1_SHIFT (8U)
|
|
#define XBARB_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL1_SHIFT)) & XBARB_SEL0_SEL1_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL1 - Crossbar B Select Register 1 */
|
|
/*! @{ */
|
|
#define XBARB_SEL1_SEL2_MASK (0x3FU)
|
|
#define XBARB_SEL1_SEL2_SHIFT (0U)
|
|
#define XBARB_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL2_SHIFT)) & XBARB_SEL1_SEL2_MASK)
|
|
#define XBARB_SEL1_SEL3_MASK (0x3F00U)
|
|
#define XBARB_SEL1_SEL3_SHIFT (8U)
|
|
#define XBARB_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL3_SHIFT)) & XBARB_SEL1_SEL3_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL2 - Crossbar B Select Register 2 */
|
|
/*! @{ */
|
|
#define XBARB_SEL2_SEL4_MASK (0x3FU)
|
|
#define XBARB_SEL2_SEL4_SHIFT (0U)
|
|
#define XBARB_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL4_SHIFT)) & XBARB_SEL2_SEL4_MASK)
|
|
#define XBARB_SEL2_SEL5_MASK (0x3F00U)
|
|
#define XBARB_SEL2_SEL5_SHIFT (8U)
|
|
#define XBARB_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL5_SHIFT)) & XBARB_SEL2_SEL5_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL3 - Crossbar B Select Register 3 */
|
|
/*! @{ */
|
|
#define XBARB_SEL3_SEL6_MASK (0x3FU)
|
|
#define XBARB_SEL3_SEL6_SHIFT (0U)
|
|
#define XBARB_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL6_SHIFT)) & XBARB_SEL3_SEL6_MASK)
|
|
#define XBARB_SEL3_SEL7_MASK (0x3F00U)
|
|
#define XBARB_SEL3_SEL7_SHIFT (8U)
|
|
#define XBARB_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL7_SHIFT)) & XBARB_SEL3_SEL7_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL4 - Crossbar B Select Register 4 */
|
|
/*! @{ */
|
|
#define XBARB_SEL4_SEL8_MASK (0x3FU)
|
|
#define XBARB_SEL4_SEL8_SHIFT (0U)
|
|
#define XBARB_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL8_SHIFT)) & XBARB_SEL4_SEL8_MASK)
|
|
#define XBARB_SEL4_SEL9_MASK (0x3F00U)
|
|
#define XBARB_SEL4_SEL9_SHIFT (8U)
|
|
#define XBARB_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL9_SHIFT)) & XBARB_SEL4_SEL9_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL5 - Crossbar B Select Register 5 */
|
|
/*! @{ */
|
|
#define XBARB_SEL5_SEL10_MASK (0x3FU)
|
|
#define XBARB_SEL5_SEL10_SHIFT (0U)
|
|
#define XBARB_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL10_SHIFT)) & XBARB_SEL5_SEL10_MASK)
|
|
#define XBARB_SEL5_SEL11_MASK (0x3F00U)
|
|
#define XBARB_SEL5_SEL11_SHIFT (8U)
|
|
#define XBARB_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL11_SHIFT)) & XBARB_SEL5_SEL11_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL6 - Crossbar B Select Register 6 */
|
|
/*! @{ */
|
|
#define XBARB_SEL6_SEL12_MASK (0x3FU)
|
|
#define XBARB_SEL6_SEL12_SHIFT (0U)
|
|
#define XBARB_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL12_SHIFT)) & XBARB_SEL6_SEL12_MASK)
|
|
#define XBARB_SEL6_SEL13_MASK (0x3F00U)
|
|
#define XBARB_SEL6_SEL13_SHIFT (8U)
|
|
#define XBARB_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL13_SHIFT)) & XBARB_SEL6_SEL13_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name SEL7 - Crossbar B Select Register 7 */
|
|
/*! @{ */
|
|
#define XBARB_SEL7_SEL14_MASK (0x3FU)
|
|
#define XBARB_SEL7_SEL14_SHIFT (0U)
|
|
#define XBARB_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL14_SHIFT)) & XBARB_SEL7_SEL14_MASK)
|
|
#define XBARB_SEL7_SEL15_MASK (0x3F00U)
|
|
#define XBARB_SEL7_SEL15_SHIFT (8U)
|
|
#define XBARB_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL15_SHIFT)) & XBARB_SEL7_SEL15_MASK)
|
|
/*! @} */
|
|
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group XBARB_Register_Masks */
|
|
|
|
|
|
/* XBARB - Peripheral instance base addresses */
|
|
/** Peripheral XBARB2 base address */
|
|
#define XBARB2_BASE (0x403C0000u)
|
|
/** Peripheral XBARB2 base pointer */
|
|
#define XBARB2 ((XBARB_Type *)XBARB2_BASE)
|
|
/** Peripheral XBARB3 base address */
|
|
#define XBARB3_BASE (0x403C4000u)
|
|
/** Peripheral XBARB3 base pointer */
|
|
#define XBARB3 ((XBARB_Type *)XBARB3_BASE)
|
|
/** Array initializer of XBARB peripheral base addresses */
|
|
#define XBARB_BASE_ADDRS { 0u, 0u, XBARB2_BASE, XBARB3_BASE }
|
|
/** Array initializer of XBARB peripheral base pointers */
|
|
#define XBARB_BASE_PTRS { (XBARB_Type *)0u, (XBARB_Type *)0u, XBARB2, XBARB3 }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group XBARB_Peripheral_Access_Layer */
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- XTALOSC24M Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup XTALOSC24M_Peripheral_Access_Layer XTALOSC24M Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** XTALOSC24M - Register Layout Typedef */
|
|
typedef struct {
|
|
uint8_t RESERVED_0[336];
|
|
__IO uint32_t MISC0; /**< Miscellaneous Register 0, offset: 0x150 */
|
|
__IO uint32_t MISC0_SET; /**< Miscellaneous Register 0, offset: 0x154 */
|
|
__IO uint32_t MISC0_CLR; /**< Miscellaneous Register 0, offset: 0x158 */
|
|
__IO uint32_t MISC0_TOG; /**< Miscellaneous Register 0, offset: 0x15C */
|
|
uint8_t RESERVED_1[272];
|
|
__IO uint32_t LOWPWR_CTRL; /**< XTAL OSC (LP) Control Register, offset: 0x270 */
|
|
__IO uint32_t LOWPWR_CTRL_SET; /**< XTAL OSC (LP) Control Register, offset: 0x274 */
|
|
__IO uint32_t LOWPWR_CTRL_CLR; /**< XTAL OSC (LP) Control Register, offset: 0x278 */
|
|
__IO uint32_t LOWPWR_CTRL_TOG; /**< XTAL OSC (LP) Control Register, offset: 0x27C */
|
|
uint8_t RESERVED_2[32];
|
|
__IO uint32_t OSC_CONFIG0; /**< XTAL OSC Configuration 0 Register, offset: 0x2A0 */
|
|
__IO uint32_t OSC_CONFIG0_SET; /**< XTAL OSC Configuration 0 Register, offset: 0x2A4 */
|
|
__IO uint32_t OSC_CONFIG0_CLR; /**< XTAL OSC Configuration 0 Register, offset: 0x2A8 */
|
|
__IO uint32_t OSC_CONFIG0_TOG; /**< XTAL OSC Configuration 0 Register, offset: 0x2AC */
|
|
__IO uint32_t OSC_CONFIG1; /**< XTAL OSC Configuration 1 Register, offset: 0x2B0 */
|
|
__IO uint32_t OSC_CONFIG1_SET; /**< XTAL OSC Configuration 1 Register, offset: 0x2B4 */
|
|
__IO uint32_t OSC_CONFIG1_CLR; /**< XTAL OSC Configuration 1 Register, offset: 0x2B8 */
|
|
__IO uint32_t OSC_CONFIG1_TOG; /**< XTAL OSC Configuration 1 Register, offset: 0x2BC */
|
|
__IO uint32_t OSC_CONFIG2; /**< XTAL OSC Configuration 2 Register, offset: 0x2C0 */
|
|
__IO uint32_t OSC_CONFIG2_SET; /**< XTAL OSC Configuration 2 Register, offset: 0x2C4 */
|
|
__IO uint32_t OSC_CONFIG2_CLR; /**< XTAL OSC Configuration 2 Register, offset: 0x2C8 */
|
|
__IO uint32_t OSC_CONFIG2_TOG; /**< XTAL OSC Configuration 2 Register, offset: 0x2CC */
|
|
} XTALOSC24M_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- XTALOSC24M Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup XTALOSC24M_Register_Masks XTALOSC24M Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name MISC0 - Miscellaneous Register 0 */
|
|
/*! @{ */
|
|
#define XTALOSC24M_MISC0_REFTOP_PWD_MASK (0x1U)
|
|
#define XTALOSC24M_MISC0_REFTOP_PWD_SHIFT (0U)
|
|
#define XTALOSC24M_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_REFTOP_PWD_MASK)
|
|
#define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)
|
|
#define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)
|
|
/*! REFTOP_SELFBIASOFF
|
|
* 0b0..Uses coarse bias currents for startup
|
|
* 0b1..Uses bandgap-based bias currents for best performance.
|
|
*/
|
|
#define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK)
|
|
#define XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK (0x70U)
|
|
#define XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT (4U)
|
|
/*! REFTOP_VBGADJ
|
|
* 0b000..Nominal VBG
|
|
* 0b001..VBG+0.78%
|
|
* 0b010..VBG+1.56%
|
|
* 0b011..VBG+2.34%
|
|
* 0b100..VBG-0.78%
|
|
* 0b101..VBG-1.56%
|
|
* 0b110..VBG-2.34%
|
|
* 0b111..VBG-3.12%
|
|
*/
|
|
#define XTALOSC24M_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK)
|
|
#define XTALOSC24M_MISC0_REFTOP_VBGUP_MASK (0x80U)
|
|
#define XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT (7U)
|
|
#define XTALOSC24M_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGUP_MASK)
|
|
#define XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)
|
|
#define XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT (10U)
|
|
/*! STOP_MODE_CONFIG
|
|
* 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off;
|
|
* 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off;
|
|
* 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off.
|
|
* 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.
|
|
*/
|
|
#define XTALOSC24M_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK)
|
|
#define XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)
|
|
#define XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)
|
|
/*! DISCON_HIGH_SNVS
|
|
* 0b0..Turn on the switch
|
|
* 0b1..Turn off the switch
|
|
*/
|
|
#define XTALOSC24M_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK)
|
|
#define XTALOSC24M_MISC0_OSC_I_MASK (0x6000U)
|
|
#define XTALOSC24M_MISC0_OSC_I_SHIFT (13U)
|
|
/*! OSC_I
|
|
* 0b00..Nominal
|
|
* 0b01..Decrease current by 12.5%
|
|
* 0b10..Decrease current by 25.0%
|
|
* 0b11..Decrease current by 37.5%
|
|
*/
|
|
#define XTALOSC24M_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_I_SHIFT)) & XTALOSC24M_MISC0_OSC_I_MASK)
|
|
#define XTALOSC24M_MISC0_OSC_XTALOK_MASK (0x8000U)
|
|
#define XTALOSC24M_MISC0_OSC_XTALOK_SHIFT (15U)
|
|
#define XTALOSC24M_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_MASK)
|
|
#define XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK (0x10000U)
|
|
#define XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT (16U)
|
|
#define XTALOSC24M_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK)
|
|
#define XTALOSC24M_MISC0_CLKGATE_CTRL_MASK (0x2000000U)
|
|
#define XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT (25U)
|
|
/*! CLKGATE_CTRL
|
|
* 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
|
|
* 0b1..Prevent the logic from ever gating off the clock.
|
|
*/
|
|
#define XTALOSC24M_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_CTRL_MASK)
|
|
#define XTALOSC24M_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)
|
|
#define XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT (26U)
|
|
/*! CLKGATE_DELAY
|
|
* 0b000..0.5ms
|
|
* 0b001..1.0ms
|
|
* 0b010..2.0ms
|
|
* 0b011..3.0ms
|
|
* 0b100..4.0ms
|
|
* 0b101..5.0ms
|
|
* 0b110..6.0ms
|
|
* 0b111..7.0ms
|
|
*/
|
|
#define XTALOSC24M_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_DELAY_MASK)
|
|
#define XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)
|
|
#define XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)
|
|
/*! RTC_XTAL_SOURCE
|
|
* 0b0..Internal ring oscillator
|
|
* 0b1..RTC_XTAL
|
|
*/
|
|
#define XTALOSC24M_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK)
|
|
#define XTALOSC24M_MISC0_XTAL_24M_PWD_MASK (0x40000000U)
|
|
#define XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT (30U)
|
|
#define XTALOSC24M_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_XTAL_24M_PWD_MASK)
|
|
#define XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK (0x80000000U)
|
|
#define XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT (31U)
|
|
/*! VID_PLL_PREDIV
|
|
* 0b0..Divide by 1
|
|
* 0b1..Divide by 2
|
|
*/
|
|
#define XTALOSC24M_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MISC0_SET - Miscellaneous Register 0 */
|
|
/*! @{ */
|
|
#define XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK (0x1U)
|
|
#define XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT (0U)
|
|
#define XTALOSC24M_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK)
|
|
#define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)
|
|
#define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)
|
|
/*! REFTOP_SELFBIASOFF
|
|
* 0b0..Uses coarse bias currents for startup
|
|
* 0b1..Uses bandgap-based bias currents for best performance.
|
|
*/
|
|
#define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK)
|
|
#define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)
|
|
#define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)
|
|
/*! REFTOP_VBGADJ
|
|
* 0b000..Nominal VBG
|
|
* 0b001..VBG+0.78%
|
|
* 0b010..VBG+1.56%
|
|
* 0b011..VBG+2.34%
|
|
* 0b100..VBG-0.78%
|
|
* 0b101..VBG-1.56%
|
|
* 0b110..VBG-2.34%
|
|
* 0b111..VBG-3.12%
|
|
*/
|
|
#define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK)
|
|
#define XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)
|
|
#define XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)
|
|
#define XTALOSC24M_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK)
|
|
#define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)
|
|
#define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)
|
|
/*! STOP_MODE_CONFIG
|
|
* 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off;
|
|
* 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off;
|
|
* 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off.
|
|
* 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.
|
|
*/
|
|
#define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK)
|
|
#define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)
|
|
#define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)
|
|
/*! DISCON_HIGH_SNVS
|
|
* 0b0..Turn on the switch
|
|
* 0b1..Turn off the switch
|
|
*/
|
|
#define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK)
|
|
#define XTALOSC24M_MISC0_SET_OSC_I_MASK (0x6000U)
|
|
#define XTALOSC24M_MISC0_SET_OSC_I_SHIFT (13U)
|
|
/*! OSC_I
|
|
* 0b00..Nominal
|
|
* 0b01..Decrease current by 12.5%
|
|
* 0b10..Decrease current by 25.0%
|
|
* 0b11..Decrease current by 37.5%
|
|
*/
|
|
#define XTALOSC24M_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_I_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_I_MASK)
|
|
#define XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK (0x8000U)
|
|
#define XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT (15U)
|
|
#define XTALOSC24M_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK)
|
|
#define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)
|
|
#define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)
|
|
#define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK)
|
|
#define XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)
|
|
#define XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)
|
|
/*! CLKGATE_CTRL
|
|
* 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
|
|
* 0b1..Prevent the logic from ever gating off the clock.
|
|
*/
|
|
#define XTALOSC24M_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK)
|
|
#define XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)
|
|
#define XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)
|
|
/*! CLKGATE_DELAY
|
|
* 0b000..0.5ms
|
|
* 0b001..1.0ms
|
|
* 0b010..2.0ms
|
|
* 0b011..3.0ms
|
|
* 0b100..4.0ms
|
|
* 0b101..5.0ms
|
|
* 0b110..6.0ms
|
|
* 0b111..7.0ms
|
|
*/
|
|
#define XTALOSC24M_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK)
|
|
#define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)
|
|
#define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)
|
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/*! RTC_XTAL_SOURCE
|
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* 0b0..Internal ring oscillator
|
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* 0b1..RTC_XTAL
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*/
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#define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK)
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#define XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)
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#define XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)
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#define XTALOSC24M_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK)
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#define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U)
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#define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U)
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/*! VID_PLL_PREDIV
|
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* 0b0..Divide by 1
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* 0b1..Divide by 2
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*/
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#define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK)
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/*! @} */
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/*! @name MISC0_CLR - Miscellaneous Register 0 */
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/*! @{ */
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#define XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK (0x1U)
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#define XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT (0U)
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#define XTALOSC24M_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK)
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#define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)
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#define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)
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/*! REFTOP_SELFBIASOFF
|
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* 0b0..Uses coarse bias currents for startup
|
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* 0b1..Uses bandgap-based bias currents for best performance.
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*/
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#define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)
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#define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)
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#define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)
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/*! REFTOP_VBGADJ
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* 0b000..Nominal VBG
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* 0b001..VBG+0.78%
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* 0b010..VBG+1.56%
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* 0b011..VBG+2.34%
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* 0b100..VBG-0.78%
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* 0b101..VBG-1.56%
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* 0b110..VBG-2.34%
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* 0b111..VBG-3.12%
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*/
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#define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK)
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#define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)
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#define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)
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#define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK)
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#define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)
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#define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)
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/*! STOP_MODE_CONFIG
|
|
* 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off;
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* 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off;
|
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* 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off.
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* 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.
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|
*/
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#define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK)
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#define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)
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#define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)
|
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/*! DISCON_HIGH_SNVS
|
|
* 0b0..Turn on the switch
|
|
* 0b1..Turn off the switch
|
|
*/
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|
#define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK)
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#define XTALOSC24M_MISC0_CLR_OSC_I_MASK (0x6000U)
|
|
#define XTALOSC24M_MISC0_CLR_OSC_I_SHIFT (13U)
|
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/*! OSC_I
|
|
* 0b00..Nominal
|
|
* 0b01..Decrease current by 12.5%
|
|
* 0b10..Decrease current by 25.0%
|
|
* 0b11..Decrease current by 37.5%
|
|
*/
|
|
#define XTALOSC24M_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_I_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_I_MASK)
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|
#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)
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|
#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT (15U)
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|
#define XTALOSC24M_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK)
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|
#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)
|
|
#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)
|
|
#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK)
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|
#define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)
|
|
#define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)
|
|
/*! CLKGATE_CTRL
|
|
* 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
|
|
* 0b1..Prevent the logic from ever gating off the clock.
|
|
*/
|
|
#define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK)
|
|
#define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)
|
|
#define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)
|
|
/*! CLKGATE_DELAY
|
|
* 0b000..0.5ms
|
|
* 0b001..1.0ms
|
|
* 0b010..2.0ms
|
|
* 0b011..3.0ms
|
|
* 0b100..4.0ms
|
|
* 0b101..5.0ms
|
|
* 0b110..6.0ms
|
|
* 0b111..7.0ms
|
|
*/
|
|
#define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK)
|
|
#define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)
|
|
#define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)
|
|
/*! RTC_XTAL_SOURCE
|
|
* 0b0..Internal ring oscillator
|
|
* 0b1..RTC_XTAL
|
|
*/
|
|
#define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK)
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|
#define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)
|
|
#define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)
|
|
#define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK)
|
|
#define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U)
|
|
#define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U)
|
|
/*! VID_PLL_PREDIV
|
|
* 0b0..Divide by 1
|
|
* 0b1..Divide by 2
|
|
*/
|
|
#define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name MISC0_TOG - Miscellaneous Register 0 */
|
|
/*! @{ */
|
|
#define XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK (0x1U)
|
|
#define XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT (0U)
|
|
#define XTALOSC24M_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK)
|
|
#define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)
|
|
#define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)
|
|
/*! REFTOP_SELFBIASOFF
|
|
* 0b0..Uses coarse bias currents for startup
|
|
* 0b1..Uses bandgap-based bias currents for best performance.
|
|
*/
|
|
#define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)
|
|
#define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)
|
|
#define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)
|
|
/*! REFTOP_VBGADJ
|
|
* 0b000..Nominal VBG
|
|
* 0b001..VBG+0.78%
|
|
* 0b010..VBG+1.56%
|
|
* 0b011..VBG+2.34%
|
|
* 0b100..VBG-0.78%
|
|
* 0b101..VBG-1.56%
|
|
* 0b110..VBG-2.34%
|
|
* 0b111..VBG-3.12%
|
|
*/
|
|
#define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK)
|
|
#define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)
|
|
#define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)
|
|
#define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK)
|
|
#define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)
|
|
#define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)
|
|
/*! STOP_MODE_CONFIG
|
|
* 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off;
|
|
* 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off;
|
|
* 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off.
|
|
* 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.
|
|
*/
|
|
#define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK)
|
|
#define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)
|
|
#define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)
|
|
/*! DISCON_HIGH_SNVS
|
|
* 0b0..Turn on the switch
|
|
* 0b1..Turn off the switch
|
|
*/
|
|
#define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK)
|
|
#define XTALOSC24M_MISC0_TOG_OSC_I_MASK (0x6000U)
|
|
#define XTALOSC24M_MISC0_TOG_OSC_I_SHIFT (13U)
|
|
/*! OSC_I
|
|
* 0b00..Nominal
|
|
* 0b01..Decrease current by 12.5%
|
|
* 0b10..Decrease current by 25.0%
|
|
* 0b11..Decrease current by 37.5%
|
|
*/
|
|
#define XTALOSC24M_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_I_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_I_MASK)
|
|
#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)
|
|
#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT (15U)
|
|
#define XTALOSC24M_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK)
|
|
#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)
|
|
#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)
|
|
#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK)
|
|
#define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)
|
|
#define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)
|
|
/*! CLKGATE_CTRL
|
|
* 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
|
|
* 0b1..Prevent the logic from ever gating off the clock.
|
|
*/
|
|
#define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK)
|
|
#define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)
|
|
#define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)
|
|
/*! CLKGATE_DELAY
|
|
* 0b000..0.5ms
|
|
* 0b001..1.0ms
|
|
* 0b010..2.0ms
|
|
* 0b011..3.0ms
|
|
* 0b100..4.0ms
|
|
* 0b101..5.0ms
|
|
* 0b110..6.0ms
|
|
* 0b111..7.0ms
|
|
*/
|
|
#define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK)
|
|
#define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)
|
|
#define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)
|
|
/*! RTC_XTAL_SOURCE
|
|
* 0b0..Internal ring oscillator
|
|
* 0b1..RTC_XTAL
|
|
*/
|
|
#define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK)
|
|
#define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)
|
|
#define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)
|
|
#define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK)
|
|
#define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U)
|
|
#define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U)
|
|
/*! VID_PLL_PREDIV
|
|
* 0b0..Divide by 1
|
|
* 0b1..Divide by 2
|
|
*/
|
|
#define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK)
|
|
/*! @} */
|
|
|
|
/*! @name LOWPWR_CTRL - XTAL OSC (LP) Control Register */
|
|
/*! @{ */
|
|
#define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK (0x1U)
|
|
#define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT (0U)
|
|
/*! RC_OSC_EN
|
|
* 0b0..Use XTAL OSC to source the 24MHz clock
|
|
* 0b1..Use RC OSC
|
|
*/
|
|
#define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK)
|
|
#define XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK (0x10U)
|
|
#define XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT (4U)
|
|
/*! OSC_SEL
|
|
* 0b0..XTAL OSC
|
|
* 0b1..RC OSC
|
|
*/
|
|
#define XTALOSC24M_LOWPWR_CTRL_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK)
|
|
#define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK (0x20U)
|
|
#define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT (5U)
|
|
/*! LPBG_SEL
|
|
* 0b0..Normal power bandgap
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* 0b1..Low power bandgap
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*/
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#define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK (0x40U)
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#define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT (6U)
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#define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK (0x80U)
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#define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT (7U)
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#define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK (0x100U)
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#define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT (8U)
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#define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK (0x200U)
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#define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT (9U)
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#define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK (0x400U)
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#define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT (10U)
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#define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK (0x800U)
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#define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT (11U)
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#define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK (0x2000U)
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#define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT (13U)
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#define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
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#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT (14U)
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/*! XTALOSC_PWRUP_DELAY
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* 0b00..0.25ms
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* 0b01..0.5ms
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* 0b10..1ms
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* 0b11..2ms
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*/
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#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK (0x10000U)
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#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT (16U)
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/*! XTALOSC_PWRUP_STAT
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* 0b0..Not stable
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* 0b1..Stable and ready to use
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*/
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#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK (0x20000U)
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#define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT (17U)
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#define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK (0x40000U)
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#define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT (18U)
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#define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK)
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/*! @} */
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/*! @name LOWPWR_CTRL_SET - XTAL OSC (LP) Control Register */
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/*! @{ */
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#define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK (0x1U)
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#define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT (0U)
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/*! RC_OSC_EN
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* 0b0..Use XTAL OSC to source the 24MHz clock
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* 0b1..Use RC OSC
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*/
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#define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK (0x10U)
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#define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT (4U)
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/*! OSC_SEL
|
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* 0b0..XTAL OSC
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* 0b1..RC OSC
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*/
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#define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK (0x20U)
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#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT (5U)
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/*! LPBG_SEL
|
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* 0b0..Normal power bandgap
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* 0b1..Low power bandgap
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*/
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#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK (0x40U)
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#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT (6U)
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#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK (0x80U)
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#define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT (7U)
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#define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK (0x100U)
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#define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT (8U)
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#define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK (0x200U)
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#define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT (9U)
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#define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK (0x400U)
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#define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT (10U)
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#define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK (0x800U)
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#define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT (11U)
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#define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK (0x2000U)
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#define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT (13U)
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#define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
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#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT (14U)
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/*! XTALOSC_PWRUP_DELAY
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* 0b00..0.25ms
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* 0b01..0.5ms
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* 0b10..1ms
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|
* 0b11..2ms
|
|
*/
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#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK (0x10000U)
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#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT (16U)
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/*! XTALOSC_PWRUP_STAT
|
|
* 0b0..Not stable
|
|
* 0b1..Stable and ready to use
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|
*/
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#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK (0x20000U)
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#define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT (17U)
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#define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK (0x40000U)
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#define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT (18U)
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#define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK)
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/*! @} */
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/*! @name LOWPWR_CTRL_CLR - XTAL OSC (LP) Control Register */
|
|
/*! @{ */
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|
#define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK (0x1U)
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#define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT (0U)
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/*! RC_OSC_EN
|
|
* 0b0..Use XTAL OSC to source the 24MHz clock
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|
* 0b1..Use RC OSC
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|
*/
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#define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK (0x10U)
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#define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT (4U)
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/*! OSC_SEL
|
|
* 0b0..XTAL OSC
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|
* 0b1..RC OSC
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*/
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#define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK (0x20U)
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#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT (5U)
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/*! LPBG_SEL
|
|
* 0b0..Normal power bandgap
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|
* 0b1..Low power bandgap
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*/
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#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK (0x40U)
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#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT (6U)
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#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK (0x80U)
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#define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT (7U)
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#define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK (0x100U)
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#define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT (8U)
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#define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK (0x200U)
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#define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT (9U)
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#define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK (0x400U)
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#define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT (10U)
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#define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK (0x800U)
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#define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT (11U)
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#define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK (0x2000U)
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#define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT (13U)
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#define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
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#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT (14U)
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/*! XTALOSC_PWRUP_DELAY
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|
* 0b00..0.25ms
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|
* 0b01..0.5ms
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|
* 0b10..1ms
|
|
* 0b11..2ms
|
|
*/
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|
#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK (0x10000U)
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#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT (16U)
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/*! XTALOSC_PWRUP_STAT
|
|
* 0b0..Not stable
|
|
* 0b1..Stable and ready to use
|
|
*/
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#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK (0x20000U)
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#define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT (17U)
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#define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK (0x40000U)
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#define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT (18U)
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#define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK)
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/*! @} */
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/*! @name LOWPWR_CTRL_TOG - XTAL OSC (LP) Control Register */
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/*! @{ */
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#define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK (0x1U)
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#define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT (0U)
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/*! RC_OSC_EN
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* 0b0..Use XTAL OSC to source the 24MHz clock
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* 0b1..Use RC OSC
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*/
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#define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK (0x10U)
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#define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT (4U)
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/*! OSC_SEL
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* 0b0..XTAL OSC
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* 0b1..RC OSC
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*/
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#define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK (0x20U)
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#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT (5U)
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/*! LPBG_SEL
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* 0b0..Normal power bandgap
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* 0b1..Low power bandgap
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*/
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#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK (0x40U)
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#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT (6U)
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#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK (0x80U)
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#define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT (7U)
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#define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK (0x100U)
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#define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT (8U)
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#define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK (0x200U)
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#define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT (9U)
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#define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK (0x400U)
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#define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT (10U)
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#define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK (0x800U)
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#define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT (11U)
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#define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK (0x2000U)
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#define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT (13U)
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#define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
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#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT (14U)
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/*! XTALOSC_PWRUP_DELAY
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* 0b00..0.25ms
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* 0b01..0.5ms
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* 0b10..1ms
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* 0b11..2ms
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*/
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#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK (0x10000U)
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#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT (16U)
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/*! XTALOSC_PWRUP_STAT
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* 0b0..Not stable
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* 0b1..Stable and ready to use
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*/
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#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK (0x20000U)
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#define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT (17U)
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#define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK)
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#define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK (0x40000U)
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#define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT (18U)
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#define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK)
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/*! @} */
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/*! @name OSC_CONFIG0 - XTAL OSC Configuration 0 Register */
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/*! @{ */
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#define XTALOSC24M_OSC_CONFIG0_START_MASK (0x1U)
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#define XTALOSC24M_OSC_CONFIG0_START_SHIFT (0U)
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#define XTALOSC24M_OSC_CONFIG0_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_START_MASK)
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#define XTALOSC24M_OSC_CONFIG0_ENABLE_MASK (0x2U)
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#define XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT (1U)
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#define XTALOSC24M_OSC_CONFIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_ENABLE_MASK)
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#define XTALOSC24M_OSC_CONFIG0_BYPASS_MASK (0x4U)
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#define XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT (2U)
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#define XTALOSC24M_OSC_CONFIG0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_BYPASS_MASK)
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#define XTALOSC24M_OSC_CONFIG0_INVERT_MASK (0x8U)
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#define XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT (3U)
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#define XTALOSC24M_OSC_CONFIG0_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_INVERT_MASK)
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#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK (0xFF0U)
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#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT (4U)
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#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK)
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#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK (0xF000U)
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#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT (12U)
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#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK)
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#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK (0xF0000U)
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#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT (16U)
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#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK)
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#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK (0xFF000000U)
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#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT (24U)
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#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK)
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/*! @} */
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/*! @name OSC_CONFIG0_SET - XTAL OSC Configuration 0 Register */
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/*! @{ */
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#define XTALOSC24M_OSC_CONFIG0_SET_START_MASK (0x1U)
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#define XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT (0U)
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#define XTALOSC24M_OSC_CONFIG0_SET_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_START_MASK)
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#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK (0x2U)
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#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT (1U)
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#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK)
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#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK (0x4U)
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#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT (2U)
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#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK)
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#define XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK (0x8U)
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#define XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT (3U)
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#define XTALOSC24M_OSC_CONFIG0_SET_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK)
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#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK (0xFF0U)
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#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT (4U)
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#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK)
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#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK (0xF000U)
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#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT (12U)
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#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK)
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#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK (0xF0000U)
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#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT (16U)
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#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK)
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#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK (0xFF000000U)
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#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT (24U)
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#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK)
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/*! @} */
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/*! @name OSC_CONFIG0_CLR - XTAL OSC Configuration 0 Register */
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/*! @{ */
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#define XTALOSC24M_OSC_CONFIG0_CLR_START_MASK (0x1U)
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#define XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT (0U)
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#define XTALOSC24M_OSC_CONFIG0_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_START_MASK)
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#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK (0x2U)
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#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT (1U)
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#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK)
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#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK (0x4U)
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#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT (2U)
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#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK)
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#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK (0x8U)
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#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT (3U)
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#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK)
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#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK (0xFF0U)
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#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT (4U)
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#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK)
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#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK (0xF000U)
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#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT (12U)
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#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK)
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#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK (0xF0000U)
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#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT (16U)
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#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK)
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#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK (0xFF000000U)
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#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT (24U)
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#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK)
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/*! @} */
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/*! @name OSC_CONFIG0_TOG - XTAL OSC Configuration 0 Register */
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/*! @{ */
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#define XTALOSC24M_OSC_CONFIG0_TOG_START_MASK (0x1U)
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#define XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT (0U)
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#define XTALOSC24M_OSC_CONFIG0_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_START_MASK)
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#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK (0x2U)
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#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT (1U)
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#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK)
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#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK (0x4U)
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#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT (2U)
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#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK)
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#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK (0x8U)
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#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT (3U)
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#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK)
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#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK (0xFF0U)
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#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT (4U)
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#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK)
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#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK (0xF000U)
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#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT (12U)
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#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK)
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#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK (0xF0000U)
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#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT (16U)
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#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK)
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#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK (0xFF000000U)
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#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT (24U)
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#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK)
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/*! @} */
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/*! @name OSC_CONFIG1 - XTAL OSC Configuration 1 Register */
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/*! @{ */
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#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK (0xFFFU)
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#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT (0U)
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#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK)
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#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK (0xFFF00000U)
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#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT (20U)
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#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK)
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/*! @} */
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/*! @name OSC_CONFIG1_SET - XTAL OSC Configuration 1 Register */
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/*! @{ */
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#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK (0xFFFU)
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#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT (0U)
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#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK)
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#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK (0xFFF00000U)
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#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT (20U)
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#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK)
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/*! @} */
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/*! @name OSC_CONFIG1_CLR - XTAL OSC Configuration 1 Register */
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/*! @{ */
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#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK (0xFFFU)
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#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT (0U)
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#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK)
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#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK (0xFFF00000U)
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#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT (20U)
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#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK)
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/*! @} */
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/*! @name OSC_CONFIG1_TOG - XTAL OSC Configuration 1 Register */
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/*! @{ */
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#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK (0xFFFU)
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#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT (0U)
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#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK)
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#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK (0xFFF00000U)
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#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT (20U)
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#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK)
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/*! @} */
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/*! @name OSC_CONFIG2 - XTAL OSC Configuration 2 Register */
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/*! @{ */
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#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK (0xFFFU)
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#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT (0U)
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#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK)
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#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK (0x10000U)
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#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT (16U)
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#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK)
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#define XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK (0x20000U)
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#define XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT (17U)
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#define XTALOSC24M_OSC_CONFIG2_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK)
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#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK (0x80000000U)
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#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT (31U)
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#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK)
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/*! @} */
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/*! @name OSC_CONFIG2_SET - XTAL OSC Configuration 2 Register */
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/*! @{ */
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#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK (0xFFFU)
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#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT (0U)
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#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK)
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#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK (0x10000U)
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#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT (16U)
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#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK)
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#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK (0x20000U)
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#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT (17U)
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#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK)
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#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK (0x80000000U)
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#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT (31U)
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#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK)
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/*! @} */
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/*! @name OSC_CONFIG2_CLR - XTAL OSC Configuration 2 Register */
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/*! @{ */
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#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK (0xFFFU)
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#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT (0U)
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#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK)
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#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK (0x10000U)
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#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT (16U)
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#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK)
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#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK (0x20000U)
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#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT (17U)
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#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK)
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#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK (0x80000000U)
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#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT (31U)
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#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK)
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/*! @} */
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/*! @name OSC_CONFIG2_TOG - XTAL OSC Configuration 2 Register */
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/*! @{ */
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#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK (0xFFFU)
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#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT (0U)
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#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK)
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#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK (0x10000U)
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#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT (16U)
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#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK)
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#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK (0x20000U)
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#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT (17U)
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#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK)
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#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK (0x80000000U)
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#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT (31U)
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#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK)
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/*! @} */
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/*!
|
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* @}
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*/ /* end of group XTALOSC24M_Register_Masks */
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/* XTALOSC24M - Peripheral instance base addresses */
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/** Peripheral XTALOSC24M base address */
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#define XTALOSC24M_BASE (0x400D8000u)
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/** Peripheral XTALOSC24M base pointer */
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#define XTALOSC24M ((XTALOSC24M_Type *)XTALOSC24M_BASE)
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/** Array initializer of XTALOSC24M peripheral base addresses */
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#define XTALOSC24M_BASE_ADDRS { XTALOSC24M_BASE }
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/** Array initializer of XTALOSC24M peripheral base pointers */
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#define XTALOSC24M_BASE_PTRS { XTALOSC24M }
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|
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/*!
|
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* @}
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*/ /* end of group XTALOSC24M_Peripheral_Access_Layer */
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|
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/*
|
|
** End of section using anonymous unions
|
|
*/
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|
|
#if defined(__ARMCC_VERSION)
|
|
#if (__ARMCC_VERSION >= 6010050)
|
|
#pragma clang diagnostic pop
|
|
#else
|
|
#pragma pop
|
|
#endif
|
|
#elif defined(__CWCC__)
|
|
#pragma pop
|
|
#elif defined(__GNUC__)
|
|
/* leave anonymous unions enabled */
|
|
#elif defined(__IAR_SYSTEMS_ICC__)
|
|
#pragma language=default
|
|
#else
|
|
#error Not supported compiler type
|
|
#endif
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|
|
/*!
|
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* @}
|
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*/ /* end of group Peripheral_access_layer */
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/* ----------------------------------------------------------------------------
|
|
-- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
|
|
---------------------------------------------------------------------------- */
|
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|
|
/*!
|
|
* @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
|
|
* @{
|
|
*/
|
|
|
|
#if defined(__ARMCC_VERSION)
|
|
#if (__ARMCC_VERSION >= 6010050)
|
|
#pragma clang system_header
|
|
#endif
|
|
#elif defined(__IAR_SYSTEMS_ICC__)
|
|
#pragma system_include
|
|
#endif
|
|
|
|
/**
|
|
* @brief Mask and left-shift a bit field value for use in a register bit range.
|
|
* @param field Name of the register bit field.
|
|
* @param value Value of the bit field.
|
|
* @return Masked and shifted value.
|
|
*/
|
|
#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK))
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|
/**
|
|
* @brief Mask and right-shift a register value to extract a bit field value.
|
|
* @param field Name of the register bit field.
|
|
* @param value Value of the register.
|
|
* @return Masked and shifted bit field value.
|
|
*/
|
|
#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT))
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|
|
/*!
|
|
* @}
|
|
*/ /* end of group Bit_Field_Generic_Macros */
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|
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|
|
/* ----------------------------------------------------------------------------
|
|
-- SDK Compatibility
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup SDK_Compatibility_Symbols SDK Compatibility
|
|
* @{
|
|
*/
|
|
|
|
/* No SDK compatibility issues. */
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group SDK_Compatibility_Symbols */
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#endif /* _MIMXRT1052_H_ */
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